4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
33 #include "intel_drv.h"
35 /* Limits for overlay size. According to intel doc, the real limits are:
36 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
37 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
38 * the mininum of both. */
39 #define IMAGE_MAX_WIDTH 2048
40 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
41 /* on 830 and 845 these large limits result in the card hanging */
42 #define IMAGE_MAX_WIDTH_LEGACY 1024
43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
45 /* overlay register definitions */
47 #define OCMD_TILED_SURFACE (0x1<<19)
48 #define OCMD_MIRROR_MASK (0x3<<17)
49 #define OCMD_MIRROR_MODE (0x3<<17)
50 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
51 #define OCMD_MIRROR_VERTICAL (0x2<<17)
52 #define OCMD_MIRROR_BOTH (0x3<<17)
53 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
54 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
55 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
56 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
58 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
60 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
61 #define OCMD_YUV_422_PACKED (0x8<<10)
62 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_420_PLANAR (0xc<<10)
64 #define OCMD_YUV_422_PLANAR (0xd<<10)
65 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
66 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
67 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
68 #define OCMD_BUF_TYPE_MASK (Ox1<<5)
69 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
70 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
71 #define OCMD_TEST_MODE (0x1<<4)
72 #define OCMD_BUFFER_SELECT (0x3<<2)
73 #define OCMD_BUFFER0 (0x0<<2)
74 #define OCMD_BUFFER1 (0x1<<2)
75 #define OCMD_FIELD_SELECT (0x1<<2)
76 #define OCMD_FIELD0 (0x0<<1)
77 #define OCMD_FIELD1 (0x1<<1)
78 #define OCMD_ENABLE (0x1<<0)
80 /* OCONFIG register */
81 #define OCONF_PIPE_MASK (0x1<<18)
82 #define OCONF_PIPE_A (0x0<<18)
83 #define OCONF_PIPE_B (0x1<<18)
84 #define OCONF_GAMMA2_ENABLE (0x1<<16)
85 #define OCONF_CSC_MODE_BT601 (0x0<<5)
86 #define OCONF_CSC_MODE_BT709 (0x1<<5)
87 #define OCONF_CSC_BYPASS (0x1<<4)
88 #define OCONF_CC_OUT_8BIT (0x1<<3)
89 #define OCONF_TEST_MODE (0x1<<2)
90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
91 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
93 /* DCLRKM (dst-key) register */
94 #define DST_KEY_ENABLE (0x1<<31)
95 #define CLK_RGB24_MASK 0x0
96 #define CLK_RGB16_MASK 0x070307
97 #define CLK_RGB15_MASK 0x070707
98 #define CLK_RGB8I_MASK 0xffffff
100 #define RGB16_TO_COLORKEY(c) \
101 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
102 #define RGB15_TO_COLORKEY(c) \
103 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
105 /* overlay flip addr flag */
106 #define OFC_UPDATE 0x1
108 /* polyphase filter coefficients */
109 #define N_HORIZ_Y_TAPS 5
110 #define N_VERT_Y_TAPS 3
111 #define N_HORIZ_UV_TAPS 3
112 #define N_VERT_UV_TAPS 3
116 /* memory bufferd overlay registers */
117 struct overlay_registers {
145 u32 RESERVED1; /* 0x6C */
158 u32 FASTHSCALE; /* 0xA0 */
159 u32 UVSCALEV; /* 0xA4 */
160 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
161 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
162 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
163 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
164 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
165 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
166 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
167 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
168 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171 /* overlay flip addr flag */
172 #define OFC_UPDATE 0x1
174 #define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
175 #define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
178 static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
180 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
181 struct overlay_registers *regs;
183 /* no recursive mappings */
184 BUG_ON(overlay->virt_addr);
186 if (OVERLAY_NONPHYSICAL(overlay->dev)) {
187 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
188 overlay->reg_bo->gtt_offset);
191 DRM_ERROR("failed to map overlay regs in GTT\n");
195 regs = overlay->reg_bo->phys_obj->handle->vaddr;
197 return overlay->virt_addr = regs;
200 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
202 if (OVERLAY_NONPHYSICAL(overlay->dev))
203 io_mapping_unmap_atomic(overlay->virt_addr);
205 overlay->virt_addr = NULL;
210 /* overlay needs to be disable in OCMD reg */
211 static int intel_overlay_on(struct intel_overlay *overlay)
213 struct drm_device *dev = overlay->dev;
216 BUG_ON(overlay->active);
219 overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
222 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
223 OUT_RING(overlay->flip_addr | OFC_UPDATE);
224 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
228 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
229 if (overlay->last_flip_req == 0)
232 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
236 overlay->hw_wedged = 0;
237 overlay->last_flip_req = 0;
241 /* overlay needs to be enabled in OCMD reg */
242 static void intel_overlay_continue(struct intel_overlay *overlay,
243 bool load_polyphase_filter)
245 struct drm_device *dev = overlay->dev;
246 drm_i915_private_t *dev_priv = dev->dev_private;
247 u32 flip_addr = overlay->flip_addr;
250 BUG_ON(!overlay->active);
252 if (load_polyphase_filter)
253 flip_addr |= OFC_UPDATE;
255 /* check for underruns */
256 tmp = I915_READ(DOVSTA);
258 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
261 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
265 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
268 static int intel_overlay_wait_flip(struct intel_overlay *overlay)
270 struct drm_device *dev = overlay->dev;
271 drm_i915_private_t *dev_priv = dev->dev_private;
275 if (overlay->last_flip_req != 0) {
276 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
278 overlay->last_flip_req = 0;
280 tmp = I915_READ(ISR);
282 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
287 /* synchronous slowpath */
288 overlay->hw_wedged = RELEASE_OLD_VID;
291 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
295 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
296 if (overlay->last_flip_req == 0)
299 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
303 overlay->hw_wedged = 0;
304 overlay->last_flip_req = 0;
308 /* overlay needs to be disabled in OCMD reg */
309 static int intel_overlay_off(struct intel_overlay *overlay)
311 u32 flip_addr = overlay->flip_addr;
312 struct drm_device *dev = overlay->dev;
315 BUG_ON(!overlay->active);
317 /* According to intel docs the overlay hw may hang (when switching
318 * off) without loading the filter coeffs. It is however unclear whether
319 * this applies to the disabling of the overlay or to the switching off
320 * of the hw. Do it in both cases */
321 flip_addr |= OFC_UPDATE;
323 /* wait for overlay to go idle */
324 overlay->hw_wedged = SWITCH_OFF_STAGE_1;
327 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
329 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
333 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
334 if (overlay->last_flip_req == 0)
337 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
341 /* turn overlay off */
342 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
345 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
347 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
351 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
352 if (overlay->last_flip_req == 0)
355 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
359 overlay->hw_wedged = 0;
360 overlay->last_flip_req = 0;
364 static void intel_overlay_off_tail(struct intel_overlay *overlay)
366 struct drm_gem_object *obj;
368 /* never have the overlay hw on without showing a frame */
369 BUG_ON(!overlay->vid_bo);
370 obj = &overlay->vid_bo->base;
372 i915_gem_object_unpin(obj);
373 drm_gem_object_unreference(obj);
374 overlay->vid_bo = NULL;
376 overlay->crtc->overlay = NULL;
377 overlay->crtc = NULL;
381 /* recover from an interruption due to a signal
382 * We have to be careful not to repeat work forever an make forward progess. */
383 int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
386 struct drm_device *dev = overlay->dev;
387 struct drm_gem_object *obj;
391 if (overlay->hw_wedged == HW_WEDGED)
394 if (overlay->last_flip_req == 0) {
395 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
396 if (overlay->last_flip_req == 0)
400 ret = i915_do_wait_request(dev, overlay->last_flip_req, interruptible);
404 switch (overlay->hw_wedged) {
405 case RELEASE_OLD_VID:
406 obj = &overlay->old_vid_bo->base;
407 i915_gem_object_unpin(obj);
408 drm_gem_object_unreference(obj);
409 overlay->old_vid_bo = NULL;
411 case SWITCH_OFF_STAGE_1:
412 flip_addr = overlay->flip_addr;
413 flip_addr |= OFC_UPDATE;
415 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
418 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
420 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
424 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
425 if (overlay->last_flip_req == 0)
428 ret = i915_do_wait_request(dev, overlay->last_flip_req,
433 case SWITCH_OFF_STAGE_2:
434 intel_overlay_off_tail(overlay);
437 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
440 overlay->hw_wedged = 0;
441 overlay->last_flip_req = 0;
445 /* Wait for pending overlay flip and release old frame.
446 * Needs to be called before the overlay register are changed
447 * via intel_overlay_(un)map_regs_atomic */
448 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
451 struct drm_gem_object *obj;
453 /* only wait if there is actually an old frame to release to
454 * guarantee forward progress */
455 if (!overlay->old_vid_bo)
458 ret = intel_overlay_wait_flip(overlay);
462 obj = &overlay->old_vid_bo->base;
463 i915_gem_object_unpin(obj);
464 drm_gem_object_unreference(obj);
465 overlay->old_vid_bo = NULL;
470 struct put_image_params {
487 static int packed_depth_bytes(u32 format)
489 switch (format & I915_OVERLAY_DEPTH_MASK) {
490 case I915_OVERLAY_YUV422:
492 case I915_OVERLAY_YUV411:
493 /* return 6; not implemented */
499 static int packed_width_bytes(u32 format, short width)
501 switch (format & I915_OVERLAY_DEPTH_MASK) {
502 case I915_OVERLAY_YUV422:
509 static int uv_hsubsampling(u32 format)
511 switch (format & I915_OVERLAY_DEPTH_MASK) {
512 case I915_OVERLAY_YUV422:
513 case I915_OVERLAY_YUV420:
515 case I915_OVERLAY_YUV411:
516 case I915_OVERLAY_YUV410:
523 static int uv_vsubsampling(u32 format)
525 switch (format & I915_OVERLAY_DEPTH_MASK) {
526 case I915_OVERLAY_YUV420:
527 case I915_OVERLAY_YUV410:
529 case I915_OVERLAY_YUV422:
530 case I915_OVERLAY_YUV411:
537 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
539 u32 mask, shift, ret;
547 ret = ((offset + width + mask) >> shift) - (offset >> shift);
554 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
555 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
556 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
557 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
558 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
559 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
560 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
561 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
562 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
563 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
564 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
565 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
566 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
567 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
568 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
569 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
570 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
571 0xb000, 0x3000, 0x0800, 0x3000, 0xb000};
572 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
573 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
574 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
575 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
576 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
577 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
578 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
579 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
580 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
581 0x3000, 0x0800, 0x3000};
583 static void update_polyphase_filter(struct overlay_registers *regs)
585 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
586 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
589 static bool update_scaling_factors(struct intel_overlay *overlay,
590 struct overlay_registers *regs,
591 struct put_image_params *params)
593 /* fixed point with a 12 bit shift */
594 u32 xscale, yscale, xscale_UV, yscale_UV;
596 #define FRACT_MASK 0xfff
597 bool scale_changed = false;
598 int uv_hscale = uv_hsubsampling(params->format);
599 int uv_vscale = uv_vsubsampling(params->format);
601 if (params->dst_w > 1)
602 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
605 xscale = 1 << FP_SHIFT;
607 if (params->dst_h > 1)
608 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
611 yscale = 1 << FP_SHIFT;
613 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
614 xscale_UV = xscale/uv_hscale;
615 yscale_UV = yscale/uv_vscale;
616 /* make the Y scale to UV scale ratio an exact multiply */
617 xscale = xscale_UV * uv_hscale;
618 yscale = yscale_UV * uv_vscale;
624 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
625 scale_changed = true;
626 overlay->old_xscale = xscale;
627 overlay->old_yscale = yscale;
629 regs->YRGBSCALE = ((yscale & FRACT_MASK) << 20)
630 | ((xscale >> FP_SHIFT) << 16)
631 | ((xscale & FRACT_MASK) << 3);
632 regs->UVSCALE = ((yscale_UV & FRACT_MASK) << 20)
633 | ((xscale_UV >> FP_SHIFT) << 16)
634 | ((xscale_UV & FRACT_MASK) << 3);
635 regs->UVSCALEV = ((yscale >> FP_SHIFT) << 16)
636 | ((yscale_UV >> FP_SHIFT) << 0);
639 update_polyphase_filter(regs);
641 return scale_changed;
644 static void update_colorkey(struct intel_overlay *overlay,
645 struct overlay_registers *regs)
647 u32 key = overlay->color_key;
648 switch (overlay->crtc->base.fb->bits_per_pixel) {
651 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
653 if (overlay->crtc->base.fb->depth == 15) {
654 regs->DCLRKV = RGB15_TO_COLORKEY(key);
655 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
657 regs->DCLRKV = RGB16_TO_COLORKEY(key);
658 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
663 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
667 static u32 overlay_cmd_reg(struct put_image_params *params)
669 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
671 if (params->format & I915_OVERLAY_YUV_PLANAR) {
672 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
673 case I915_OVERLAY_YUV422:
674 cmd |= OCMD_YUV_422_PLANAR;
676 case I915_OVERLAY_YUV420:
677 cmd |= OCMD_YUV_420_PLANAR;
679 case I915_OVERLAY_YUV411:
680 case I915_OVERLAY_YUV410:
681 cmd |= OCMD_YUV_410_PLANAR;
684 } else { /* YUV packed */
685 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
686 case I915_OVERLAY_YUV422:
687 cmd |= OCMD_YUV_422_PACKED;
689 case I915_OVERLAY_YUV411:
690 cmd |= OCMD_YUV_411_PACKED;
694 switch (params->format & I915_OVERLAY_SWAP_MASK) {
695 case I915_OVERLAY_NO_SWAP:
697 case I915_OVERLAY_UV_SWAP:
700 case I915_OVERLAY_Y_SWAP:
703 case I915_OVERLAY_Y_AND_UV_SWAP:
704 cmd |= OCMD_Y_AND_UV_SWAP;
712 int intel_overlay_do_put_image(struct intel_overlay *overlay,
713 struct drm_gem_object *new_bo,
714 struct put_image_params *params)
717 struct overlay_registers *regs;
718 bool scale_changed = false;
719 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
720 struct drm_device *dev = overlay->dev;
722 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
723 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
726 ret = intel_overlay_release_old_vid(overlay);
730 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
734 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
738 if (!overlay->active) {
739 regs = intel_overlay_map_regs_atomic(overlay);
744 regs->OCONFIG = OCONF_CC_OUT_8BIT;
745 if (IS_I965GM(overlay->dev))
746 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
747 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
748 OCONF_PIPE_A : OCONF_PIPE_B;
749 intel_overlay_unmap_regs_atomic(overlay);
751 ret = intel_overlay_on(overlay);
756 regs = intel_overlay_map_regs_atomic(overlay);
762 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
763 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
765 if (params->format & I915_OVERLAY_YUV_PACKED)
766 tmp_width = packed_width_bytes(params->format, params->src_w);
768 tmp_width = params->src_w;
770 regs->SWIDTH = params->src_w;
771 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
772 params->offset_Y, tmp_width);
773 regs->SHEIGHT = params->src_h;
774 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
775 regs->OSTRIDE = params->stride_Y;
777 if (params->format & I915_OVERLAY_YUV_PLANAR) {
778 int uv_hscale = uv_hsubsampling(params->format);
779 int uv_vscale = uv_vsubsampling(params->format);
781 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
782 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
783 params->src_w/uv_hscale);
784 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
785 params->src_w/uv_hscale);
786 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
787 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
788 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
789 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
790 regs->OSTRIDE |= params->stride_UV << 16;
793 scale_changed = update_scaling_factors(overlay, regs, params);
795 update_colorkey(overlay, regs);
797 regs->OCMD = overlay_cmd_reg(params);
799 intel_overlay_unmap_regs_atomic(overlay);
801 intel_overlay_continue(overlay, scale_changed);
803 overlay->old_vid_bo = overlay->vid_bo;
804 overlay->vid_bo = to_intel_bo(new_bo);
809 i915_gem_object_unpin(new_bo);
813 int intel_overlay_switch_off(struct intel_overlay *overlay)
816 struct overlay_registers *regs;
817 struct drm_device *dev = overlay->dev;
819 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
820 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
822 if (overlay->hw_wedged) {
823 ret = intel_overlay_recover_from_interrupt(overlay, 1);
828 if (!overlay->active)
831 ret = intel_overlay_release_old_vid(overlay);
835 regs = intel_overlay_map_regs_atomic(overlay);
837 intel_overlay_unmap_regs_atomic(overlay);
839 ret = intel_overlay_off(overlay);
843 intel_overlay_off_tail(overlay);
848 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
849 struct intel_crtc *crtc)
851 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
853 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
855 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
858 pipeconf = I915_READ(pipeconf_reg);
860 /* can't use the overlay with double wide pipe */
861 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
867 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
869 struct drm_device *dev = overlay->dev;
870 drm_i915_private_t *dev_priv = dev->dev_private;
872 u32 pfit_control = I915_READ(PFIT_CONTROL);
874 /* XXX: This is not the same logic as in the xorg driver, but more in
875 * line with the intel documentation for the i965 */
876 if (!IS_I965G(dev) && (pfit_control & VERT_AUTO_SCALE)) {
877 ratio = I915_READ(PFIT_AUTO_RATIOS) >> PFIT_VERT_SCALE_SHIFT;
878 } else { /* on i965 use the PGM reg to read out the autoscaler values */
879 ratio = I915_READ(PFIT_PGM_RATIOS);
881 ratio >>= PFIT_VERT_SCALE_SHIFT_965;
883 ratio >>= PFIT_VERT_SCALE_SHIFT;
886 overlay->pfit_vscale_ratio = ratio;
889 static int check_overlay_dst(struct intel_overlay *overlay,
890 struct drm_intel_overlay_put_image *rec)
892 struct drm_display_mode *mode = &overlay->crtc->base.mode;
894 if ((rec->dst_x < mode->crtc_hdisplay)
895 && (rec->dst_x + rec->dst_width
896 <= mode->crtc_hdisplay)
897 && (rec->dst_y < mode->crtc_vdisplay)
898 && (rec->dst_y + rec->dst_height
899 <= mode->crtc_vdisplay))
905 static int check_overlay_scaling(struct put_image_params *rec)
909 /* downscaling limit is 8.0 */
910 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
913 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
920 static int check_overlay_src(struct drm_device *dev,
921 struct drm_intel_overlay_put_image *rec,
922 struct drm_gem_object *new_bo)
926 int uv_hscale = uv_hsubsampling(rec->flags);
927 int uv_vscale = uv_vsubsampling(rec->flags);
930 /* check src dimensions */
931 if (IS_845G(dev) || IS_I830(dev)) {
932 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY
933 || rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
936 if (rec->src_height > IMAGE_MAX_HEIGHT
937 || rec->src_width > IMAGE_MAX_WIDTH)
940 /* better safe than sorry, use 4 as the maximal subsampling ratio */
941 if (rec->src_height < N_VERT_Y_TAPS*4
942 || rec->src_width < N_HORIZ_Y_TAPS*4)
945 /* check alingment constrains */
946 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
947 case I915_OVERLAY_RGB:
948 /* not implemented */
950 case I915_OVERLAY_YUV_PACKED:
951 depth = packed_depth_bytes(rec->flags);
956 /* ignore UV planes */
960 /* check pixel alignment */
961 if (rec->offset_Y % depth)
964 case I915_OVERLAY_YUV_PLANAR:
965 if (uv_vscale < 0 || uv_hscale < 0)
967 /* no offset restrictions for planar formats */
973 if (rec->src_width % uv_hscale)
976 /* stride checking */
979 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
981 if (IS_I965G(dev) && rec->stride_Y < 512)
984 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
986 if (rec->stride_Y > tmp*1024 || rec->stride_UV > 2*1024)
989 /* check buffer dimensions */
990 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
991 case I915_OVERLAY_RGB:
992 case I915_OVERLAY_YUV_PACKED:
993 /* always 4 Y values per depth pixels */
994 if (packed_width_bytes(rec->flags, rec->src_width)
998 tmp = rec->stride_Y*rec->src_height;
999 if (rec->offset_Y + tmp > new_bo->size)
1002 case I915_OVERLAY_YUV_PLANAR:
1003 if (rec->src_width > rec->stride_Y)
1005 if (rec->src_width/uv_hscale > rec->stride_UV)
1008 tmp = rec->stride_Y*rec->src_height;
1009 if (rec->offset_Y + tmp > new_bo->size)
1011 tmp = rec->stride_UV*rec->src_height;
1013 if (rec->offset_U + tmp > new_bo->size
1014 || rec->offset_V + tmp > new_bo->size)
1022 int intel_overlay_put_image(struct drm_device *dev, void *data,
1023 struct drm_file *file_priv)
1025 struct drm_intel_overlay_put_image *put_image_rec = data;
1026 drm_i915_private_t *dev_priv = dev->dev_private;
1027 struct intel_overlay *overlay;
1028 struct drm_mode_object *drmmode_obj;
1029 struct intel_crtc *crtc;
1030 struct drm_gem_object *new_bo;
1031 struct put_image_params *params;
1035 DRM_ERROR("called with no initialization\n");
1039 overlay = dev_priv->overlay;
1041 DRM_DEBUG("userspace bug: no overlay\n");
1045 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1046 mutex_lock(&dev->mode_config.mutex);
1047 mutex_lock(&dev->struct_mutex);
1049 ret = intel_overlay_switch_off(overlay);
1051 mutex_unlock(&dev->struct_mutex);
1052 mutex_unlock(&dev->mode_config.mutex);
1057 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1061 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1062 DRM_MODE_OBJECT_CRTC);
1067 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1069 new_bo = drm_gem_object_lookup(dev, file_priv,
1070 put_image_rec->bo_handle);
1076 mutex_lock(&dev->mode_config.mutex);
1077 mutex_lock(&dev->struct_mutex);
1079 if (overlay->hw_wedged) {
1080 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1085 if (overlay->crtc != crtc) {
1086 struct drm_display_mode *mode = &crtc->base.mode;
1087 ret = intel_overlay_switch_off(overlay);
1091 ret = check_overlay_possible_on_crtc(overlay, crtc);
1095 overlay->crtc = crtc;
1096 crtc->overlay = overlay;
1098 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1099 /* and line to wide, i.e. one-line-mode */
1100 && mode->hdisplay > 1024) {
1101 overlay->pfit_active = 1;
1102 update_pfit_vscale_ratio(overlay);
1104 overlay->pfit_active = 0;
1107 ret = check_overlay_dst(overlay, put_image_rec);
1111 if (overlay->pfit_active) {
1112 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1113 overlay->pfit_vscale_ratio);
1114 /* shifting right rounds downwards, so add 1 */
1115 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1116 overlay->pfit_vscale_ratio) + 1;
1118 params->dst_y = put_image_rec->dst_y;
1119 params->dst_h = put_image_rec->dst_height;
1121 params->dst_x = put_image_rec->dst_x;
1122 params->dst_w = put_image_rec->dst_width;
1124 params->src_w = put_image_rec->src_width;
1125 params->src_h = put_image_rec->src_height;
1126 params->src_scan_w = put_image_rec->src_scan_width;
1127 params->src_scan_h = put_image_rec->src_scan_height;
1128 if (params->src_scan_h > params->src_h
1129 || params->src_scan_w > params->src_w) {
1134 ret = check_overlay_src(dev, put_image_rec, new_bo);
1137 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1138 params->stride_Y = put_image_rec->stride_Y;
1139 params->stride_UV = put_image_rec->stride_UV;
1140 params->offset_Y = put_image_rec->offset_Y;
1141 params->offset_U = put_image_rec->offset_U;
1142 params->offset_V = put_image_rec->offset_V;
1144 /* Check scaling after src size to prevent a divide-by-zero. */
1145 ret = check_overlay_scaling(params);
1149 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1153 mutex_unlock(&dev->struct_mutex);
1154 mutex_unlock(&dev->mode_config.mutex);
1161 mutex_unlock(&dev->struct_mutex);
1162 mutex_unlock(&dev->mode_config.mutex);
1163 drm_gem_object_unreference_unlocked(new_bo);
1170 static void update_reg_attrs(struct intel_overlay *overlay,
1171 struct overlay_registers *regs)
1173 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1174 regs->OCLRC1 = overlay->saturation;
1177 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1181 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1184 for (i = 0; i < 3; i++) {
1185 if (((gamma1 >> i * 8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1192 static bool check_gamma5_errata(u32 gamma5)
1196 for (i = 0; i < 3; i++) {
1197 if (((gamma5 >> i*8) & 0xff) == 0x80)
1204 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1206 if (!check_gamma_bounds(0, attrs->gamma0)
1207 || !check_gamma_bounds(attrs->gamma0, attrs->gamma1)
1208 || !check_gamma_bounds(attrs->gamma1, attrs->gamma2)
1209 || !check_gamma_bounds(attrs->gamma2, attrs->gamma3)
1210 || !check_gamma_bounds(attrs->gamma3, attrs->gamma4)
1211 || !check_gamma_bounds(attrs->gamma4, attrs->gamma5)
1212 || !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1214 if (!check_gamma5_errata(attrs->gamma5))
1219 int intel_overlay_attrs(struct drm_device *dev, void *data,
1220 struct drm_file *file_priv)
1222 struct drm_intel_overlay_attrs *attrs = data;
1223 drm_i915_private_t *dev_priv = dev->dev_private;
1224 struct intel_overlay *overlay;
1225 struct overlay_registers *regs;
1229 DRM_ERROR("called with no initialization\n");
1233 overlay = dev_priv->overlay;
1235 DRM_DEBUG("userspace bug: no overlay\n");
1239 mutex_lock(&dev->mode_config.mutex);
1240 mutex_lock(&dev->struct_mutex);
1242 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1243 attrs->color_key = overlay->color_key;
1244 attrs->brightness = overlay->brightness;
1245 attrs->contrast = overlay->contrast;
1246 attrs->saturation = overlay->saturation;
1249 attrs->gamma0 = I915_READ(OGAMC0);
1250 attrs->gamma1 = I915_READ(OGAMC1);
1251 attrs->gamma2 = I915_READ(OGAMC2);
1252 attrs->gamma3 = I915_READ(OGAMC3);
1253 attrs->gamma4 = I915_READ(OGAMC4);
1254 attrs->gamma5 = I915_READ(OGAMC5);
1258 overlay->color_key = attrs->color_key;
1259 if (attrs->brightness >= -128 && attrs->brightness <= 127) {
1260 overlay->brightness = attrs->brightness;
1265 if (attrs->contrast <= 255) {
1266 overlay->contrast = attrs->contrast;
1271 if (attrs->saturation <= 1023) {
1272 overlay->saturation = attrs->saturation;
1278 regs = intel_overlay_map_regs_atomic(overlay);
1284 update_reg_attrs(overlay, regs);
1286 intel_overlay_unmap_regs_atomic(overlay);
1288 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1289 if (!IS_I9XX(dev)) {
1294 if (overlay->active) {
1299 ret = check_gamma(attrs);
1303 I915_WRITE(OGAMC0, attrs->gamma0);
1304 I915_WRITE(OGAMC1, attrs->gamma1);
1305 I915_WRITE(OGAMC2, attrs->gamma2);
1306 I915_WRITE(OGAMC3, attrs->gamma3);
1307 I915_WRITE(OGAMC4, attrs->gamma4);
1308 I915_WRITE(OGAMC5, attrs->gamma5);
1314 mutex_unlock(&dev->struct_mutex);
1315 mutex_unlock(&dev->mode_config.mutex);
1320 void intel_setup_overlay(struct drm_device *dev)
1322 drm_i915_private_t *dev_priv = dev->dev_private;
1323 struct intel_overlay *overlay;
1324 struct drm_gem_object *reg_bo;
1325 struct overlay_registers *regs;
1328 if (!OVERLAY_EXISTS(dev))
1331 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1336 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1339 overlay->reg_bo = to_intel_bo(reg_bo);
1341 if (OVERLAY_NONPHYSICAL(dev)) {
1342 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1344 DRM_ERROR("failed to pin overlay register bo\n");
1347 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1349 ret = i915_gem_attach_phys_object(dev, reg_bo,
1350 I915_GEM_PHYS_OVERLAY_REGS);
1352 DRM_ERROR("failed to attach phys overlay regs\n");
1355 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1358 /* init all values */
1359 overlay->color_key = 0x0101fe;
1360 overlay->brightness = -19;
1361 overlay->contrast = 75;
1362 overlay->saturation = 146;
1364 regs = intel_overlay_map_regs_atomic(overlay);
1368 memset(regs, 0, sizeof(struct overlay_registers));
1369 update_polyphase_filter(regs);
1371 update_reg_attrs(overlay, regs);
1373 intel_overlay_unmap_regs_atomic(overlay);
1375 dev_priv->overlay = overlay;
1376 DRM_INFO("initialized overlay support\n");
1380 drm_gem_object_unreference(reg_bo);
1386 void intel_cleanup_overlay(struct drm_device *dev)
1388 drm_i915_private_t *dev_priv = dev->dev_private;
1390 if (dev_priv->overlay) {
1391 /* The bo's should be free'd by the generic code already.
1392 * Furthermore modesetting teardown happens beforehand so the
1393 * hardware should be off already */
1394 BUG_ON(dev_priv->overlay->active);
1396 kfree(dev_priv->overlay);