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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 710                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711                      clock.m1++) {
 712                         for (clock.m2 = limit->m2.min;
 713                              clock.m2 <= limit->m2.max; clock.m2++) {
 714                                 /* m1 is always 0 in IGD */
 715                                 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 716                                         break;
 717                                 for (clock.n = limit->n.min;
 718                                      clock.n <= limit->n.max; clock.n++) {
 719                                         int this_err;
 720
 721                                         intel_clock(dev, refclk, &clock);
 722
 723                                         if (!intel_PLL_is_valid(crtc, &clock))
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739
 740 static bool
 741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                             int target, int refclk, intel_clock_t *best_clock)
 743
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         intel_clock_t clock;
 747         int err = target;
 748         bool found = false;
 749
 750         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 751
 752         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 753                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 754                         /* m1 is always 0 in IGD */
 755                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 756                                 break;
 757                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 758                              clock.n++) {
 759                                 int this_err;
 760
 761                                 intel_clock(dev, refclk, &clock);
 762
 763                                 if (!intel_PLL_is_valid(crtc, &clock))
 764                                         continue;
 765
 766                                 this_err = abs(clock.dot - target);
 767                                 if (this_err < err) {
 768                                         *best_clock = clock;
 769                                         err = this_err;
 770                                         found = true;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return found;
 777 }
 778
 779 static bool
 780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 781                         int target, int refclk, intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found;
 788         /* approximately equals target * 0.00488 */
 789         int err_most = (target >> 8) + (target >> 10);
 790         found = false;
 791
 792         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 793                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 794                     LVDS_CLKB_POWER_UP)
 795                         clock.p2 = limit->p2.p2_fast;
 796                 else
 797                         clock.p2 = limit->p2.p2_slow;
 798         } else {
 799                 if (target < limit->p2.dot_limit)
 800                         clock.p2 = limit->p2.p2_slow;
 801                 else
 802                         clock.p2 = limit->p2.p2_fast;
 803         }
 804
 805         memset(best_clock, 0, sizeof(*best_clock));
 806         max_n = limit->n.max;
 807         /* based on hardware requriment prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirment prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         intel_clock(dev, refclk, &clock);
 819                                         if (!intel_PLL_is_valid(crtc, &clock))
 820                                                 continue;
 821                                         this_err = abs(clock.dot - target) ;
 822                                         if (this_err < err_most) {
 823                                                 *best_clock = clock;
 824                                                 err_most = this_err;
 825                                                 max_n = clock.n;
 826                                                 found = true;
 827                                         }
 828                                 }
 829                         }
 830                 }
 831         }
 832         return found;
 833 }
 834
 835 static bool
 836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *best_clock)
 838 {
 839         struct drm_device *dev = crtc->dev;
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.n = 1;
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.m1 = 12;
 846                 clock.m2 = 9;
 847         } else {
 848                 clock.n = 2;
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.m1 = 14;
 852                 clock.m2 = 8;
 853         }
 854         intel_clock(dev, refclk, &clock);
 855         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 856         return true;
 857 }
 858
 859 static bool
 860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found;
 868         int err_most = 47;
 869         found = false;
 870
 871         /* eDP has only 2 clock choice, no n/m/p setting */
 872         if (HAS_eDP)
 873                 return true;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 876                 return intel_find_pll_igdng_dp(limit, crtc, target,
 877                                                refclk, best_clock);
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 895                 /* based on hardware requriment prefer smaller n to precision */
 896                 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                         /* based on hardware requirment prefere larger m1,m2 */
 898                         for (clock.m1 = limit->m1.max;
 899                              clock.m1 >= limit->m1.min; clock.m1--) {
 900                                 for (clock.m2 = limit->m2.max;
 901                                      clock.m2 >= limit->m2.min; clock.m2--) {
 902                                         int this_err;
 903
 904                                         intel_clock(dev, refclk, &clock);
 905                                         if (!intel_PLL_is_valid(crtc, &clock))
 906                                                 continue;
 907                                         this_err = abs((10000 - (target*10000/clock.dot)));
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                                 /* found on first matching */
 914                                                 goto out;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920 out:
 921         return found;
 922 }
 923
 924 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 925 static bool
 926 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 927                       int target, int refclk, intel_clock_t *best_clock)
 928 {
 929     intel_clock_t clock;
 930     if (target < 200000) {
 931         clock.p1 = 2;
 932         clock.p2 = 10;
 933         clock.n = 2;
 934         clock.m1 = 23;
 935         clock.m2 = 8;
 936     } else {
 937         clock.p1 = 1;
 938         clock.p2 = 10;
 939         clock.n = 1;
 940         clock.m1 = 14;
 941         clock.m2 = 2;
 942     }
 943     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 944     clock.p = (clock.p1 * clock.p2);
 945     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 946     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 947     return true;
 948 }
 949
 950 void
 951 intel_wait_for_vblank(struct drm_device *dev)
 952 {
 953         /* Wait for 20ms, i.e. one cycle at 50hz. */
 954         mdelay(20);
 955 }
 956
 957 /* Parameters have changed, update FBC info */
 958 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 959 {
 960         struct drm_device *dev = crtc->dev;
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         struct drm_framebuffer *fb = crtc->fb;
 963         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 964         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 966         int plane, i;
 967         u32 fbc_ctl, fbc_ctl2;
 968
 969         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 970
 971         if (fb->pitch < dev_priv->cfb_pitch)
 972                 dev_priv->cfb_pitch = fb->pitch;
 973
 974         /* FBC_CTL wants 64B units */
 975         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 976         dev_priv->cfb_fence = obj_priv->fence_reg;
 977         dev_priv->cfb_plane = intel_crtc->plane;
 978         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 979
 980         /* Clear old tags */
 981         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 982                 I915_WRITE(FBC_TAG + (i * 4), 0);
 983
 984         /* Set it up... */
 985         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 986         if (obj_priv->tiling_mode != I915_TILING_NONE)
 987                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 988         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 989         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 990
 991         /* enable it... */
 992         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 993         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 994         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 995         if (obj_priv->tiling_mode != I915_TILING_NONE)
 996                 fbc_ctl |= dev_priv->cfb_fence;
 997         I915_WRITE(FBC_CONTROL, fbc_ctl);
 998
 999         DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1000                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1001 }
1002
1003 void i8xx_disable_fbc(struct drm_device *dev)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         u32 fbc_ctl;
1007
1008         if (!I915_HAS_FBC(dev))
1009                 return;
1010
1011         /* Disable compression */
1012         fbc_ctl = I915_READ(FBC_CONTROL);
1013         fbc_ctl &= ~FBC_CTL_EN;
1014         I915_WRITE(FBC_CONTROL, fbc_ctl);
1015
1016         /* Wait for compressing bit to clear */
1017         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1018                 ; /* nothing */
1019
1020         intel_wait_for_vblank(dev);
1021
1022         DRM_DEBUG("disabled FBC\n");
1023 }
1024
1025 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1026 {
1027         struct drm_device *dev = crtc->dev;
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029
1030         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1031 }
1032
1033 /**
1034  * intel_update_fbc - enable/disable FBC as needed
1035  * @crtc: CRTC to point the compressor at
1036  * @mode: mode in use
1037  *
1038  * Set up the framebuffer compression hardware at mode set time.  We
1039  * enable it if possible:
1040  *   - plane A only (on pre-965)
1041  *   - no pixel mulitply/line duplication
1042  *   - no alpha buffer discard
1043  *   - no dual wide
1044  *   - framebuffer <= 2048 in width, 1536 in height
1045  *
1046  * We can't assume that any compression will take place (worst case),
1047  * so the compressed buffer has to be the same size as the uncompressed
1048  * one.  It also must reside (along with the line length buffer) in
1049  * stolen memory.
1050  *
1051  * We need to enable/disable FBC on a global basis.
1052  */
1053 static void intel_update_fbc(struct drm_crtc *crtc,
1054                              struct drm_display_mode *mode)
1055 {
1056         struct drm_device *dev = crtc->dev;
1057         struct drm_i915_private *dev_priv = dev->dev_private;
1058         struct drm_framebuffer *fb = crtc->fb;
1059         struct intel_framebuffer *intel_fb;
1060         struct drm_i915_gem_object *obj_priv;
1061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1062         int plane = intel_crtc->plane;
1063
1064         if (!i915_powersave)
1065                 return;
1066
1067         if (!crtc->fb)
1068                 return;
1069
1070         intel_fb = to_intel_framebuffer(fb);
1071         obj_priv = intel_fb->obj->driver_private;
1072
1073         /*
1074          * If FBC is already on, we just have to verify that we can
1075          * keep it that way...
1076          * Need to disable if:
1077          *   - changing FBC params (stride, fence, mode)
1078          *   - new fb is too large to fit in compressed buffer
1079          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1080          */
1081         if (intel_fb->obj->size > dev_priv->cfb_size) {
1082                 DRM_DEBUG("framebuffer too large, disabling compression\n");
1083                 goto out_disable;
1084         }
1085         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1086             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1087                 DRM_DEBUG("mode incompatible with compression, disabling\n");
1088                 goto out_disable;
1089         }
1090         if ((mode->hdisplay > 2048) ||
1091             (mode->vdisplay > 1536)) {
1092                 DRM_DEBUG("mode too large for compression, disabling\n");
1093                 goto out_disable;
1094         }
1095         if (IS_I9XX(dev) && plane != 0) {
1096                 DRM_DEBUG("plane not 0, disabling compression\n");
1097                 goto out_disable;
1098         }
1099         if (obj_priv->tiling_mode != I915_TILING_X) {
1100                 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1101                 goto out_disable;
1102         }
1103
1104         if (i8xx_fbc_enabled(crtc)) {
1105                 /* We can re-enable it in this case, but need to update pitch */
1106                 if (fb->pitch > dev_priv->cfb_pitch)
1107                         i8xx_disable_fbc(dev);
1108                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1109                         i8xx_disable_fbc(dev);
1110                 if (plane != dev_priv->cfb_plane)
1111                         i8xx_disable_fbc(dev);
1112         }
1113
1114         if (!i8xx_fbc_enabled(crtc)) {
1115                 /* Now try to turn it back on if possible */
1116                 i8xx_enable_fbc(crtc, 500);
1117         }
1118
1119         return;
1120
1121 out_disable:
1122         DRM_DEBUG("unsupported config, disabling FBC\n");
1123         /* Multiple disables should be harmless */
1124         if (i8xx_fbc_enabled(crtc))
1125                 i8xx_disable_fbc(dev);
1126 }
1127
1128 static int
1129 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1130                     struct drm_framebuffer *old_fb)
1131 {
1132         struct drm_device *dev = crtc->dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         struct drm_i915_master_private *master_priv;
1135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1136         struct intel_framebuffer *intel_fb;
1137         struct drm_i915_gem_object *obj_priv;
1138         struct drm_gem_object *obj;
1139         int pipe = intel_crtc->pipe;
1140         int plane = intel_crtc->plane;
1141         unsigned long Start, Offset;
1142         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1143         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1144         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1145         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1146         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1147         u32 dspcntr, alignment;
1148         int ret;
1149
1150         /* no fb bound */
1151         if (!crtc->fb) {
1152                 DRM_DEBUG("No FB bound\n");
1153                 return 0;
1154         }
1155
1156         switch (plane) {
1157         case 0:
1158         case 1:
1159                 break;
1160         default:
1161                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1162                 return -EINVAL;
1163         }
1164
1165         intel_fb = to_intel_framebuffer(crtc->fb);
1166         obj = intel_fb->obj;
1167         obj_priv = obj->driver_private;
1168
1169         switch (obj_priv->tiling_mode) {
1170         case I915_TILING_NONE:
1171                 alignment = 64 * 1024;
1172                 break;
1173         case I915_TILING_X:
1174                 /* pin() will align the object as required by fence */
1175                 alignment = 0;
1176                 break;
1177         case I915_TILING_Y:
1178                 /* FIXME: Is this true? */
1179                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1180                 return -EINVAL;
1181         default:
1182                 BUG();
1183         }
1184
1185         mutex_lock(&dev->struct_mutex);
1186         ret = i915_gem_object_pin(obj, alignment);
1187         if (ret != 0) {
1188                 mutex_unlock(&dev->struct_mutex);
1189                 return ret;
1190         }
1191
1192         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1193         if (ret != 0) {
1194                 i915_gem_object_unpin(obj);
1195                 mutex_unlock(&dev->struct_mutex);
1196                 return ret;
1197         }
1198
1199         /* Pre-i965 needs to install a fence for tiled scan-out */
1200         if (!IS_I965G(dev) &&
1201             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1202             obj_priv->tiling_mode != I915_TILING_NONE) {
1203                 ret = i915_gem_object_get_fence_reg(obj);
1204                 if (ret != 0) {
1205                         i915_gem_object_unpin(obj);
1206                         mutex_unlock(&dev->struct_mutex);
1207                         return ret;
1208                 }
1209         }
1210
1211         dspcntr = I915_READ(dspcntr_reg);
1212         /* Mask out pixel format bits in case we change it */
1213         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1214         switch (crtc->fb->bits_per_pixel) {
1215         case 8:
1216                 dspcntr |= DISPPLANE_8BPP;
1217                 break;
1218         case 16:
1219                 if (crtc->fb->depth == 15)
1220                         dspcntr |= DISPPLANE_15_16BPP;
1221                 else
1222                         dspcntr |= DISPPLANE_16BPP;
1223                 break;
1224         case 24:
1225         case 32:
1226                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1227                 break;
1228         default:
1229                 DRM_ERROR("Unknown color depth\n");
1230                 i915_gem_object_unpin(obj);
1231                 mutex_unlock(&dev->struct_mutex);
1232                 return -EINVAL;
1233         }
1234         if (IS_I965G(dev)) {
1235                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1236                         dspcntr |= DISPPLANE_TILED;
1237                 else
1238                         dspcntr &= ~DISPPLANE_TILED;
1239         }
1240
1241         if (IS_IGDNG(dev))
1242                 /* must disable */
1243                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1244
1245         I915_WRITE(dspcntr_reg, dspcntr);
1246
1247         Start = obj_priv->gtt_offset;
1248         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1249
1250         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1251         I915_WRITE(dspstride, crtc->fb->pitch);
1252         if (IS_I965G(dev)) {
1253                 I915_WRITE(dspbase, Offset);
1254                 I915_READ(dspbase);
1255                 I915_WRITE(dspsurf, Start);
1256                 I915_READ(dspsurf);
1257                 I915_WRITE(dsptileoff, (y << 16) | x);
1258         } else {
1259                 I915_WRITE(dspbase, Start + Offset);
1260                 I915_READ(dspbase);
1261         }
1262
1263         intel_wait_for_vblank(dev);
1264
1265         if (old_fb) {
1266                 intel_fb = to_intel_framebuffer(old_fb);
1267                 obj_priv = intel_fb->obj->driver_private;
1268                 i915_gem_object_unpin(intel_fb->obj);
1269         }
1270         intel_increase_pllclock(crtc, true);
1271
1272         mutex_unlock(&dev->struct_mutex);
1273
1274         if (!dev->primary->master)
1275                 return 0;
1276
1277         master_priv = dev->primary->master->driver_priv;
1278         if (!master_priv->sarea_priv)
1279                 return 0;
1280
1281         if (pipe) {
1282                 master_priv->sarea_priv->pipeB_x = x;
1283                 master_priv->sarea_priv->pipeB_y = y;
1284         } else {
1285                 master_priv->sarea_priv->pipeA_x = x;
1286                 master_priv->sarea_priv->pipeA_y = y;
1287         }
1288
1289         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
1290                 intel_update_fbc(crtc, &crtc->mode);
1291
1292         return 0;
1293 }
1294
1295 /* Disable the VGA plane that we never use */
1296 static void i915_disable_vga (struct drm_device *dev)
1297 {
1298         struct drm_i915_private *dev_priv = dev->dev_private;
1299         u8 sr1;
1300         u32 vga_reg;
1301
1302         if (IS_IGDNG(dev))
1303                 vga_reg = CPU_VGACNTRL;
1304         else
1305                 vga_reg = VGACNTRL;
1306
1307         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1308                 return;
1309
1310         I915_WRITE8(VGA_SR_INDEX, 1);
1311         sr1 = I915_READ8(VGA_SR_DATA);
1312         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1313         udelay(100);
1314
1315         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1316 }
1317
1318 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1319 {
1320         struct drm_device *dev = crtc->dev;
1321         struct drm_i915_private *dev_priv = dev->dev_private;
1322         u32 dpa_ctl;
1323
1324         DRM_DEBUG("\n");
1325         dpa_ctl = I915_READ(DP_A);
1326         dpa_ctl &= ~DP_PLL_ENABLE;
1327         I915_WRITE(DP_A, dpa_ctl);
1328 }
1329
1330 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1331 {
1332         struct drm_device *dev = crtc->dev;
1333         struct drm_i915_private *dev_priv = dev->dev_private;
1334         u32 dpa_ctl;
1335
1336         dpa_ctl = I915_READ(DP_A);
1337         dpa_ctl |= DP_PLL_ENABLE;
1338         I915_WRITE(DP_A, dpa_ctl);
1339         udelay(200);
1340 }
1341
1342
1343 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1344 {
1345         struct drm_device *dev = crtc->dev;
1346         struct drm_i915_private *dev_priv = dev->dev_private;
1347         u32 dpa_ctl;
1348
1349         DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1350         dpa_ctl = I915_READ(DP_A);
1351         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1352
1353         if (clock < 200000) {
1354                 u32 temp;
1355                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1356                 /* workaround for 160Mhz:
1357                    1) program 0x4600c bits 15:0 = 0x8124
1358                    2) program 0x46010 bit 0 = 1
1359                    3) program 0x46034 bit 24 = 1
1360                    4) program 0x64000 bit 14 = 1
1361                    */
1362                 temp = I915_READ(0x4600c);
1363                 temp &= 0xffff0000;
1364                 I915_WRITE(0x4600c, temp | 0x8124);
1365
1366                 temp = I915_READ(0x46010);
1367                 I915_WRITE(0x46010, temp | 1);
1368
1369                 temp = I915_READ(0x46034);
1370                 I915_WRITE(0x46034, temp | (1 << 24));
1371         } else {
1372                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1373         }
1374         I915_WRITE(DP_A, dpa_ctl);
1375
1376         udelay(500);
1377 }
1378
1379 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1380 {
1381         struct drm_device *dev = crtc->dev;
1382         struct drm_i915_private *dev_priv = dev->dev_private;
1383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1384         int pipe = intel_crtc->pipe;
1385         int plane = intel_crtc->plane;
1386         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1387         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1388         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1389         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1390         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1391         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1392         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1393         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1394         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1395         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1396         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1397         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1398         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1399         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1400         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1401         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1402         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1403         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1404         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1405         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1406         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1407         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1408         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1409         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1410         u32 temp;
1411         int tries = 5, j, n;
1412
1413         /* XXX: When our outputs are all unaware of DPMS modes other than off
1414          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1415          */
1416         switch (mode) {
1417         case DRM_MODE_DPMS_ON:
1418         case DRM_MODE_DPMS_STANDBY:
1419         case DRM_MODE_DPMS_SUSPEND:
1420                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1421                 if (HAS_eDP) {
1422                         /* enable eDP PLL */
1423                         igdng_enable_pll_edp(crtc);
1424                 } else {
1425                         /* enable PCH DPLL */
1426                         temp = I915_READ(pch_dpll_reg);
1427                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1428                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1429                                 I915_READ(pch_dpll_reg);
1430                         }
1431
1432                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1433                         temp = I915_READ(fdi_rx_reg);
1434                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1435                                         FDI_SEL_PCDCLK |
1436                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1437                         I915_READ(fdi_rx_reg);
1438                         udelay(200);
1439
1440                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1441                         temp = I915_READ(fdi_tx_reg);
1442                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1443                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1444                                 I915_READ(fdi_tx_reg);
1445                                 udelay(100);
1446                         }
1447                 }
1448
1449                 /* Enable panel fitting for LVDS */
1450                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1451                         temp = I915_READ(pf_ctl_reg);
1452                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
1453
1454                         /* currently full aspect */
1455                         I915_WRITE(pf_win_pos, 0);
1456
1457                         I915_WRITE(pf_win_size,
1458                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1459                                    (dev_priv->panel_fixed_mode->vdisplay));
1460                 }
1461
1462                 /* Enable CPU pipe */
1463                 temp = I915_READ(pipeconf_reg);
1464                 if ((temp & PIPEACONF_ENABLE) == 0) {
1465                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1466                         I915_READ(pipeconf_reg);
1467                         udelay(100);
1468                 }
1469
1470                 /* configure and enable CPU plane */
1471                 temp = I915_READ(dspcntr_reg);
1472                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1473                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1474                         /* Flush the plane changes */
1475                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1476                 }
1477
1478                 if (!HAS_eDP) {
1479                         /* enable CPU FDI TX and PCH FDI RX */
1480                         temp = I915_READ(fdi_tx_reg);
1481                         temp |= FDI_TX_ENABLE;
1482                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1483                         temp &= ~FDI_LINK_TRAIN_NONE;
1484                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1485                         I915_WRITE(fdi_tx_reg, temp);
1486                         I915_READ(fdi_tx_reg);
1487
1488                         temp = I915_READ(fdi_rx_reg);
1489                         temp &= ~FDI_LINK_TRAIN_NONE;
1490                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1491                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1492                         I915_READ(fdi_rx_reg);
1493
1494                         udelay(150);
1495
1496                         /* Train FDI. */
1497                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1498                            for train result */
1499                         temp = I915_READ(fdi_rx_imr_reg);
1500                         temp &= ~FDI_RX_SYMBOL_LOCK;
1501                         temp &= ~FDI_RX_BIT_LOCK;
1502                         I915_WRITE(fdi_rx_imr_reg, temp);
1503                         I915_READ(fdi_rx_imr_reg);
1504                         udelay(150);
1505
1506                         temp = I915_READ(fdi_rx_iir_reg);
1507                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1508
1509                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1510                                 for (j = 0; j < tries; j++) {
1511                                         temp = I915_READ(fdi_rx_iir_reg);
1512                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1513                                         if (temp & FDI_RX_BIT_LOCK)
1514                                                 break;
1515                                         udelay(200);
1516                                 }
1517                                 if (j != tries)
1518                                         I915_WRITE(fdi_rx_iir_reg,
1519                                                         temp | FDI_RX_BIT_LOCK);
1520                                 else
1521                                         DRM_DEBUG("train 1 fail\n");
1522                         } else {
1523                                 I915_WRITE(fdi_rx_iir_reg,
1524                                                 temp | FDI_RX_BIT_LOCK);
1525                                 DRM_DEBUG("train 1 ok 2!\n");
1526                         }
1527                         temp = I915_READ(fdi_tx_reg);
1528                         temp &= ~FDI_LINK_TRAIN_NONE;
1529                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1530                         I915_WRITE(fdi_tx_reg, temp);
1531
1532                         temp = I915_READ(fdi_rx_reg);
1533                         temp &= ~FDI_LINK_TRAIN_NONE;
1534                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1535                         I915_WRITE(fdi_rx_reg, temp);
1536
1537                         udelay(150);
1538
1539                         temp = I915_READ(fdi_rx_iir_reg);
1540                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1541
1542                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1543                                 for (j = 0; j < tries; j++) {
1544                                         temp = I915_READ(fdi_rx_iir_reg);
1545                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1546                                         if (temp & FDI_RX_SYMBOL_LOCK)
1547                                                 break;
1548                                         udelay(200);
1549                                 }
1550                                 if (j != tries) {
1551                                         I915_WRITE(fdi_rx_iir_reg,
1552                                                         temp | FDI_RX_SYMBOL_LOCK);
1553                                         DRM_DEBUG("train 2 ok 1!\n");
1554                                 } else
1555                                         DRM_DEBUG("train 2 fail\n");
1556                         } else {
1557                                 I915_WRITE(fdi_rx_iir_reg,
1558                                                 temp | FDI_RX_SYMBOL_LOCK);
1559                                 DRM_DEBUG("train 2 ok 2!\n");
1560                         }
1561                         DRM_DEBUG("train done\n");
1562
1563                         /* set transcoder timing */
1564                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1565                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1566                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1567
1568                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1569                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1570                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1571
1572                         /* enable PCH transcoder */
1573                         temp = I915_READ(transconf_reg);
1574                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1575                         I915_READ(transconf_reg);
1576
1577                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1578                                 ;
1579
1580                         /* enable normal */
1581
1582                         temp = I915_READ(fdi_tx_reg);
1583                         temp &= ~FDI_LINK_TRAIN_NONE;
1584                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1585                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1586                         I915_READ(fdi_tx_reg);
1587
1588                         temp = I915_READ(fdi_rx_reg);
1589                         temp &= ~FDI_LINK_TRAIN_NONE;
1590                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1591                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1592                         I915_READ(fdi_rx_reg);
1593
1594                         /* wait one idle pattern time */
1595                         udelay(100);
1596
1597                 }
1598
1599                 intel_crtc_load_lut(crtc);
1600
1601         break;
1602         case DRM_MODE_DPMS_OFF:
1603                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1604
1605                 i915_disable_vga(dev);
1606
1607                 /* Disable display plane */
1608                 temp = I915_READ(dspcntr_reg);
1609                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1610                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1611                         /* Flush the plane changes */
1612                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1613                         I915_READ(dspbase_reg);
1614                 }
1615
1616                 /* disable cpu pipe, disable after all planes disabled */
1617                 temp = I915_READ(pipeconf_reg);
1618                 if ((temp & PIPEACONF_ENABLE) != 0) {
1619                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1620                         I915_READ(pipeconf_reg);
1621                         n = 0;
1622                         /* wait for cpu pipe off, pipe state */
1623                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1624                                 n++;
1625                                 if (n < 60) {
1626                                         udelay(500);
1627                                         continue;
1628                                 } else {
1629                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1630                                         break;
1631                                 }
1632                         }
1633                 } else
1634                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1635
1636                 if (HAS_eDP) {
1637                         igdng_disable_pll_edp(crtc);
1638                 }
1639
1640                 /* disable CPU FDI tx and PCH FDI rx */
1641                 temp = I915_READ(fdi_tx_reg);
1642                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1643                 I915_READ(fdi_tx_reg);
1644
1645                 temp = I915_READ(fdi_rx_reg);
1646                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1647                 I915_READ(fdi_rx_reg);
1648
1649                 udelay(100);
1650
1651                 /* still set train pattern 1 */
1652                 temp = I915_READ(fdi_tx_reg);
1653                 temp &= ~FDI_LINK_TRAIN_NONE;
1654                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1655                 I915_WRITE(fdi_tx_reg, temp);
1656
1657                 temp = I915_READ(fdi_rx_reg);
1658                 temp &= ~FDI_LINK_TRAIN_NONE;
1659                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1660                 I915_WRITE(fdi_rx_reg, temp);
1661
1662                 udelay(100);
1663
1664                 /* disable PCH transcoder */
1665                 temp = I915_READ(transconf_reg);
1666                 if ((temp & TRANS_ENABLE) != 0) {
1667                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1668                         I915_READ(transconf_reg);
1669                         n = 0;
1670                         /* wait for PCH transcoder off, transcoder state */
1671                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1672                                 n++;
1673                                 if (n < 60) {
1674                                         udelay(500);
1675                                         continue;
1676                                 } else {
1677                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1678                                         break;
1679                                 }
1680                         }
1681                 }
1682
1683                 /* disable PCH DPLL */
1684                 temp = I915_READ(pch_dpll_reg);
1685                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1686                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1687                         I915_READ(pch_dpll_reg);
1688                 }
1689
1690                 temp = I915_READ(fdi_rx_reg);
1691                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1692                         temp &= ~FDI_SEL_PCDCLK;
1693                         temp &= ~FDI_RX_PLL_ENABLE;
1694                         I915_WRITE(fdi_rx_reg, temp);
1695                         I915_READ(fdi_rx_reg);
1696                 }
1697
1698                 /* Disable CPU FDI TX PLL */
1699                 temp = I915_READ(fdi_tx_reg);
1700                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1701                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1702                         I915_READ(fdi_tx_reg);
1703                         udelay(100);
1704                 }
1705
1706                 /* Disable PF */
1707                 temp = I915_READ(pf_ctl_reg);
1708                 if ((temp & PF_ENABLE) != 0) {
1709                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1710                         I915_READ(pf_ctl_reg);
1711                 }
1712                 I915_WRITE(pf_win_size, 0);
1713
1714                 /* Wait for the clocks to turn off. */
1715                 udelay(150);
1716                 break;
1717         }
1718 }
1719
1720 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1721 {
1722         struct drm_device *dev = crtc->dev;
1723         struct drm_i915_private *dev_priv = dev->dev_private;
1724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1725         int pipe = intel_crtc->pipe;
1726         int plane = intel_crtc->plane;
1727         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1728         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1729         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1730         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1731         u32 temp;
1732
1733         /* XXX: When our outputs are all unaware of DPMS modes other than off
1734          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1735          */
1736         switch (mode) {
1737         case DRM_MODE_DPMS_ON:
1738         case DRM_MODE_DPMS_STANDBY:
1739         case DRM_MODE_DPMS_SUSPEND:
1740                 /* Enable the DPLL */
1741                 temp = I915_READ(dpll_reg);
1742                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1743                         I915_WRITE(dpll_reg, temp);
1744                         I915_READ(dpll_reg);
1745                         /* Wait for the clocks to stabilize. */
1746                         udelay(150);
1747                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1748                         I915_READ(dpll_reg);
1749                         /* Wait for the clocks to stabilize. */
1750                         udelay(150);
1751                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1752                         I915_READ(dpll_reg);
1753                         /* Wait for the clocks to stabilize. */
1754                         udelay(150);
1755                 }
1756
1757                 /* Enable the pipe */
1758                 temp = I915_READ(pipeconf_reg);
1759                 if ((temp & PIPEACONF_ENABLE) == 0)
1760                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1761
1762                 /* Enable the plane */
1763                 temp = I915_READ(dspcntr_reg);
1764                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1765                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1766                         /* Flush the plane changes */
1767                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1768                 }
1769
1770                 intel_crtc_load_lut(crtc);
1771
1772                 if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
1773                         intel_update_fbc(crtc, &crtc->mode);
1774
1775                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1776                 //intel_crtc_dpms_video(crtc, true); TODO
1777                 intel_update_watermarks(dev);
1778         break;
1779         case DRM_MODE_DPMS_OFF:
1780                 intel_update_watermarks(dev);
1781                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1782                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1783
1784                 if (dev_priv->cfb_plane == plane)
1785                         i8xx_disable_fbc(dev);
1786
1787                 /* Disable the VGA plane that we never use */
1788                 i915_disable_vga(dev);
1789
1790                 /* Disable display plane */
1791                 temp = I915_READ(dspcntr_reg);
1792                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1793                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1794                         /* Flush the plane changes */
1795                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1796                         I915_READ(dspbase_reg);
1797                 }
1798
1799                 if (!IS_I9XX(dev)) {
1800                         /* Wait for vblank for the disable to take effect */
1801                         intel_wait_for_vblank(dev);
1802                 }
1803
1804                 /* Next, disable display pipes */
1805                 temp = I915_READ(pipeconf_reg);
1806                 if ((temp & PIPEACONF_ENABLE) != 0) {
1807                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1808                         I915_READ(pipeconf_reg);
1809                 }
1810
1811                 /* Wait for vblank for the disable to take effect. */
1812                 intel_wait_for_vblank(dev);
1813
1814                 temp = I915_READ(dpll_reg);
1815                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1816                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1817                         I915_READ(dpll_reg);
1818                 }
1819
1820                 /* Wait for the clocks to turn off. */
1821                 udelay(150);
1822                 break;
1823         }
1824 }
1825
1826 /**
1827  * Sets the power management mode of the pipe and plane.
1828  *
1829  * This code should probably grow support for turning the cursor off and back
1830  * on appropriately at the same time as we're turning the pipe off/on.
1831  */
1832 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1833 {
1834         struct drm_device *dev = crtc->dev;
1835         struct drm_i915_master_private *master_priv;
1836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1837         int pipe = intel_crtc->pipe;
1838         bool enabled;
1839
1840         if (IS_IGDNG(dev))
1841                 igdng_crtc_dpms(crtc, mode);
1842         else
1843                 i9xx_crtc_dpms(crtc, mode);
1844
1845         intel_crtc->dpms_mode = mode;
1846
1847         if (!dev->primary->master)
1848                 return;
1849
1850         master_priv = dev->primary->master->driver_priv;
1851         if (!master_priv->sarea_priv)
1852                 return;
1853
1854         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1855
1856         switch (pipe) {
1857         case 0:
1858                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1859                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1860                 break;
1861         case 1:
1862                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1863                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1864                 break;
1865         default:
1866                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1867                 break;
1868         }
1869 }
1870
1871 static void intel_crtc_prepare (struct drm_crtc *crtc)
1872 {
1873         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1874         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1875 }
1876
1877 static void intel_crtc_commit (struct drm_crtc *crtc)
1878 {
1879         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1880         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1881 }
1882
1883 void intel_encoder_prepare (struct drm_encoder *encoder)
1884 {
1885         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1886         /* lvds has its own version of prepare see intel_lvds_prepare */
1887         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1888 }
1889
1890 void intel_encoder_commit (struct drm_encoder *encoder)
1891 {
1892         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1893         /* lvds has its own version of commit see intel_lvds_commit */
1894         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1895 }
1896
1897 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1898                                   struct drm_display_mode *mode,
1899                                   struct drm_display_mode *adjusted_mode)
1900 {
1901         struct drm_device *dev = crtc->dev;
1902         if (IS_IGDNG(dev)) {
1903                 /* FDI link clock is fixed at 2.7G */
1904                 if (mode->clock * 3 > 27000 * 4)
1905                         return MODE_CLOCK_HIGH;
1906         }
1907         return true;
1908 }
1909
1910
1911 /** Returns the core display clock speed for i830 - i945 */
1912 static int intel_get_core_clock_speed(struct drm_device *dev)
1913 {
1914
1915         /* Core clock values taken from the published datasheets.
1916          * The 830 may go up to 166 Mhz, which we should check.
1917          */
1918         if (IS_I945G(dev))
1919                 return 400000;
1920         else if (IS_I915G(dev))
1921                 return 333000;
1922         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1923                 return 200000;
1924         else if (IS_I915GM(dev)) {
1925                 u16 gcfgc = 0;
1926
1927                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1928
1929                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1930                         return 133000;
1931                 else {
1932                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1933                         case GC_DISPLAY_CLOCK_333_MHZ:
1934                                 return 333000;
1935                         default:
1936                         case GC_DISPLAY_CLOCK_190_200_MHZ:
1937                                 return 190000;
1938                         }
1939                 }
1940         } else if (IS_I865G(dev))
1941                 return 266000;
1942         else if (IS_I855(dev)) {
1943                 u16 hpllcc = 0;
1944                 /* Assume that the hardware is in the high speed state.  This
1945                  * should be the default.
1946                  */
1947                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1948                 case GC_CLOCK_133_200:
1949                 case GC_CLOCK_100_200:
1950                         return 200000;
1951                 case GC_CLOCK_166_250:
1952                         return 250000;
1953                 case GC_CLOCK_100_133:
1954                         return 133000;
1955                 }
1956         } else /* 852, 830 */
1957                 return 133000;
1958
1959         return 0; /* Silence gcc warning */
1960 }
1961
1962 /**
1963  * Return the pipe currently connected to the panel fitter,
1964  * or -1 if the panel fitter is not present or not in use
1965  */
1966 static int intel_panel_fitter_pipe (struct drm_device *dev)
1967 {
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         u32  pfit_control;
1970
1971         /* i830 doesn't have a panel fitter */
1972         if (IS_I830(dev))
1973                 return -1;
1974
1975         pfit_control = I915_READ(PFIT_CONTROL);
1976
1977         /* See if the panel fitter is in use */
1978         if ((pfit_control & PFIT_ENABLE) == 0)
1979                 return -1;
1980
1981         /* 965 can place panel fitter on either pipe */
1982         if (IS_I965G(dev))
1983                 return (pfit_control >> 29) & 0x3;
1984
1985         /* older chips can only use pipe 1 */
1986         return 1;
1987 }
1988
1989 struct fdi_m_n {
1990         u32        tu;
1991         u32        gmch_m;
1992         u32        gmch_n;
1993         u32        link_m;
1994         u32        link_n;
1995 };
1996
1997 static void
1998 fdi_reduce_ratio(u32 *num, u32 *den)
1999 {
2000         while (*num > 0xffffff || *den > 0xffffff) {
2001                 *num >>= 1;
2002                 *den >>= 1;
2003         }
2004 }
2005
2006 #define DATA_N 0x800000
2007 #define LINK_N 0x80000
2008
2009 static void
2010 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
2011                 int pixel_clock, int link_clock,
2012                 struct fdi_m_n *m_n)
2013 {
2014         u64 temp;
2015
2016         m_n->tu = 64; /* default size */
2017
2018         temp = (u64) DATA_N * pixel_clock;
2019         temp = div_u64(temp, link_clock);
2020         m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
2021         m_n->gmch_n = DATA_N;
2022         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2023
2024         temp = (u64) LINK_N * pixel_clock;
2025         m_n->link_m = div_u64(temp, link_clock);
2026         m_n->link_n = LINK_N;
2027         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2028 }
2029
2030
2031 struct intel_watermark_params {
2032         unsigned long fifo_size;
2033         unsigned long max_wm;
2034         unsigned long default_wm;
2035         unsigned long guard_size;
2036         unsigned long cacheline_size;
2037 };
2038
2039 /* IGD has different values for various configs */
2040 static struct intel_watermark_params igd_display_wm = {
2041         IGD_DISPLAY_FIFO,
2042         IGD_MAX_WM,
2043         IGD_DFT_WM,
2044         IGD_GUARD_WM,
2045         IGD_FIFO_LINE_SIZE
2046 };
2047 static struct intel_watermark_params igd_display_hplloff_wm = {
2048         IGD_DISPLAY_FIFO,
2049         IGD_MAX_WM,
2050         IGD_DFT_HPLLOFF_WM,
2051         IGD_GUARD_WM,
2052         IGD_FIFO_LINE_SIZE
2053 };
2054 static struct intel_watermark_params igd_cursor_wm = {
2055         IGD_CURSOR_FIFO,
2056         IGD_CURSOR_MAX_WM,
2057         IGD_CURSOR_DFT_WM,
2058         IGD_CURSOR_GUARD_WM,
2059         IGD_FIFO_LINE_SIZE,
2060 };
2061 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2062         IGD_CURSOR_FIFO,
2063         IGD_CURSOR_MAX_WM,
2064         IGD_CURSOR_DFT_WM,
2065         IGD_CURSOR_GUARD_WM,
2066         IGD_FIFO_LINE_SIZE
2067 };
2068 static struct intel_watermark_params i945_wm_info = {
2069         I945_FIFO_SIZE,
2070         I915_MAX_WM,
2071         1,
2072         2,
2073         I915_FIFO_LINE_SIZE
2074 };
2075 static struct intel_watermark_params i915_wm_info = {
2076         I915_FIFO_SIZE,
2077         I915_MAX_WM,
2078         1,
2079         2,
2080         I915_FIFO_LINE_SIZE
2081 };
2082 static struct intel_watermark_params i855_wm_info = {
2083         I855GM_FIFO_SIZE,
2084         I915_MAX_WM,
2085         1,
2086         2,
2087         I830_FIFO_LINE_SIZE
2088 };
2089 static struct intel_watermark_params i830_wm_info = {
2090         I830_FIFO_SIZE,
2091         I915_MAX_WM,
2092         1,
2093         2,
2094         I830_FIFO_LINE_SIZE
2095 };
2096
2097 /**
2098  * intel_calculate_wm - calculate watermark level
2099  * @clock_in_khz: pixel clock
2100  * @wm: chip FIFO params
2101  * @pixel_size: display pixel size
2102  * @latency_ns: memory latency for the platform
2103  *
2104  * Calculate the watermark level (the level at which the display plane will
2105  * start fetching from memory again).  Each chip has a different display
2106  * FIFO size and allocation, so the caller needs to figure that out and pass
2107  * in the correct intel_watermark_params structure.
2108  *
2109  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2110  * on the pixel size.  When it reaches the watermark level, it'll start
2111  * fetching FIFO line sized based chunks from memory until the FIFO fills
2112  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2113  * will occur, and a display engine hang could result.
2114  */
2115 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2116                                         struct intel_watermark_params *wm,
2117                                         int pixel_size,
2118                                         unsigned long latency_ns)
2119 {
2120         long entries_required, wm_size;
2121
2122         /*
2123          * Note: we need to make sure we don't overflow for various clock &
2124          * latency values.
2125          * clocks go from a few thousand to several hundred thousand.
2126          * latency is usually a few thousand
2127          */
2128         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2129                 1000;
2130         entries_required /= wm->cacheline_size;
2131
2132         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2133
2134         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2135
2136         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2137
2138         /* Don't promote wm_size to unsigned... */
2139         if (wm_size > (long)wm->max_wm)
2140                 wm_size = wm->max_wm;
2141         if (wm_size <= 0)
2142                 wm_size = wm->default_wm;
2143         return wm_size;
2144 }
2145
2146 struct cxsr_latency {
2147         int is_desktop;
2148         unsigned long fsb_freq;
2149         unsigned long mem_freq;
2150         unsigned long display_sr;
2151         unsigned long display_hpll_disable;
2152         unsigned long cursor_sr;
2153         unsigned long cursor_hpll_disable;
2154 };
2155
2156 static struct cxsr_latency cxsr_latency_table[] = {
2157         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2158         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2159         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2160
2161         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2162         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2163         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2164
2165         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2166         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2167         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2168
2169         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2170         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2171         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2172
2173         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2174         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2175         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2176
2177         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2178         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2179         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2180 };
2181
2182 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2183                                                    int mem)
2184 {
2185         int i;
2186         struct cxsr_latency *latency;
2187
2188         if (fsb == 0 || mem == 0)
2189                 return NULL;
2190
2191         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2192                 latency = &cxsr_latency_table[i];
2193                 if (is_desktop == latency->is_desktop &&
2194                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2195                         return latency;
2196         }
2197
2198         DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2199
2200         return NULL;
2201 }
2202
2203 static void igd_disable_cxsr(struct drm_device *dev)
2204 {
2205         struct drm_i915_private *dev_priv = dev->dev_private;
2206         u32 reg;
2207
2208         /* deactivate cxsr */
2209         reg = I915_READ(DSPFW3);
2210         reg &= ~(IGD_SELF_REFRESH_EN);
2211         I915_WRITE(DSPFW3, reg);
2212         DRM_INFO("Big FIFO is disabled\n");
2213 }
2214
2215 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2216                             int pixel_size)
2217 {
2218         struct drm_i915_private *dev_priv = dev->dev_private;
2219         u32 reg;
2220         unsigned long wm;
2221         struct cxsr_latency *latency;
2222
2223         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2224                 dev_priv->mem_freq);
2225         if (!latency) {
2226                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2227                 igd_disable_cxsr(dev);
2228                 return;
2229         }
2230
2231         /* Display SR */
2232         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2233                                 latency->display_sr);
2234         reg = I915_READ(DSPFW1);
2235         reg &= 0x7fffff;
2236         reg |= wm << 23;
2237         I915_WRITE(DSPFW1, reg);
2238         DRM_DEBUG("DSPFW1 register is %x\n", reg);
2239
2240         /* cursor SR */
2241         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2242                                 latency->cursor_sr);
2243         reg = I915_READ(DSPFW3);
2244         reg &= ~(0x3f << 24);
2245         reg |= (wm & 0x3f) << 24;
2246         I915_WRITE(DSPFW3, reg);
2247
2248         /* Display HPLL off SR */
2249         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2250                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2251         reg = I915_READ(DSPFW3);
2252         reg &= 0xfffffe00;
2253         reg |= wm & 0x1ff;
2254         I915_WRITE(DSPFW3, reg);
2255
2256         /* cursor HPLL off SR */
2257         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2258                                 latency->cursor_hpll_disable);
2259         reg = I915_READ(DSPFW3);
2260         reg &= ~(0x3f << 16);
2261         reg |= (wm & 0x3f) << 16;
2262         I915_WRITE(DSPFW3, reg);
2263         DRM_DEBUG("DSPFW3 register is %x\n", reg);
2264
2265         /* activate cxsr */
2266         reg = I915_READ(DSPFW3);
2267         reg |= IGD_SELF_REFRESH_EN;
2268         I915_WRITE(DSPFW3, reg);
2269
2270         DRM_INFO("Big FIFO is enabled\n");
2271
2272         return;
2273 }
2274
2275 /*
2276  * Latency for FIFO fetches is dependent on several factors:
2277  *   - memory configuration (speed, channels)
2278  *   - chipset
2279  *   - current MCH state
2280  * It can be fairly high in some situations, so here we assume a fairly
2281  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2282  * set this value too high, the FIFO will fetch frequently to stay full)
2283  * and power consumption (set it too low to save power and we might see
2284  * FIFO underruns and display "flicker").
2285  *
2286  * A value of 5us seems to be a good balance; safe for very low end
2287  * platforms but not overly aggressive on lower latency configs.
2288  */
2289 const static int latency_ns = 5000;
2290
2291 static int intel_get_fifo_size(struct drm_device *dev, int plane)
2292 {
2293         struct drm_i915_private *dev_priv = dev->dev_private;
2294         uint32_t dsparb = I915_READ(DSPARB);
2295         int size;
2296
2297         if (IS_I9XX(dev)) {
2298                 if (plane == 0)
2299                         size = dsparb & 0x7f;
2300                 else
2301                         size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2302                                 (dsparb & 0x7f);
2303         } else if (IS_I85X(dev)) {
2304                 if (plane == 0)
2305                         size = dsparb & 0x1ff;
2306                 else
2307                         size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2308                                 (dsparb & 0x1ff);
2309                 size >>= 1; /* Convert to cachelines */
2310         } else if (IS_845G(dev)) {
2311                 size = dsparb & 0x7f;
2312                 size >>= 2; /* Convert to cachelines */
2313         } else {
2314                 size = dsparb & 0x7f;
2315                 size >>= 1; /* Convert to cachelines */
2316         }
2317
2318         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2319                   size);
2320
2321         return size;
2322 }
2323
2324 static void g4x_update_wm(struct drm_device *dev)
2325 {
2326         struct drm_i915_private *dev_priv = dev->dev_private;
2327         u32 fw_blc_self = I915_READ(FW_BLC_SELF);
2328
2329         if (i915_powersave)
2330                 fw_blc_self |= FW_BLC_SELF_EN;
2331         else
2332                 fw_blc_self &= ~FW_BLC_SELF_EN;
2333         I915_WRITE(FW_BLC_SELF, fw_blc_self);
2334 }
2335
2336 static void i965_update_wm(struct drm_device *dev)
2337 {
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339
2340         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2341
2342         /* 965 has limitations... */
2343         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2344         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2345 }
2346
2347 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2348                            int planeb_clock, int sr_hdisplay, int pixel_size)
2349 {
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351         uint32_t fwater_lo;
2352         uint32_t fwater_hi;
2353         int total_size, cacheline_size, cwm, srwm = 1;
2354         int planea_wm, planeb_wm;
2355         struct intel_watermark_params planea_params, planeb_params;
2356         unsigned long line_time_us;
2357         int sr_clock, sr_entries = 0;
2358
2359         /* Create copies of the base settings for each pipe */
2360         if (IS_I965GM(dev) || IS_I945GM(dev))
2361                 planea_params = planeb_params = i945_wm_info;
2362         else if (IS_I9XX(dev))
2363                 planea_params = planeb_params = i915_wm_info;
2364         else
2365                 planea_params = planeb_params = i855_wm_info;
2366
2367         /* Grab a couple of global values before we overwrite them */
2368         total_size = planea_params.fifo_size;
2369         cacheline_size = planea_params.cacheline_size;
2370
2371         /* Update per-plane FIFO sizes */
2372         planea_params.fifo_size = intel_get_fifo_size(dev, 0);
2373         planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
2374
2375         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2376                                        pixel_size, latency_ns);
2377         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2378                                        pixel_size, latency_ns);
2379         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2380
2381         /*
2382          * Overlay gets an aggressive default since video jitter is bad.
2383          */
2384         cwm = 2;
2385
2386         /* Calc sr entries for one plane configs */
2387         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2388             (!planea_clock || !planeb_clock)) {
2389                 /* self-refresh has much higher latency */
2390                 const static int sr_latency_ns = 6000;
2391
2392                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2393                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2394
2395                 /* Use ns/us then divide to preserve precision */
2396                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2397                               pixel_size * sr_hdisplay) / 1000;
2398                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2399                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2400                 srwm = total_size - sr_entries;
2401                 if (srwm < 0)
2402                         srwm = 1;
2403                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2404         }
2405
2406         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2407                   planea_wm, planeb_wm, cwm, srwm);
2408
2409         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2410         fwater_hi = (cwm & 0x1f);
2411
2412         /* Set request length to 8 cachelines per fetch */
2413         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2414         fwater_hi = fwater_hi | (1 << 8);
2415
2416         I915_WRITE(FW_BLC, fwater_lo);
2417         I915_WRITE(FW_BLC2, fwater_hi);
2418 }
2419
2420 static void i830_update_wm(struct drm_device *dev, int planea_clock,
2421                            int pixel_size)
2422 {
2423         struct drm_i915_private *dev_priv = dev->dev_private;
2424         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2425         int planea_wm;
2426
2427         i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
2428
2429         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2430                                        pixel_size, latency_ns);
2431         fwater_lo |= (3<<8) | planea_wm;
2432
2433         DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2434
2435         I915_WRITE(FW_BLC, fwater_lo);
2436 }
2437
2438 /**
2439  * intel_update_watermarks - update FIFO watermark values based on current modes
2440  *
2441  * Calculate watermark values for the various WM regs based on current mode
2442  * and plane configuration.
2443  *
2444  * There are several cases to deal with here:
2445  *   - normal (i.e. non-self-refresh)
2446  *   - self-refresh (SR) mode
2447  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2448  *   - lines are small relative to FIFO size (buffer can hold more than 2
2449  *     lines), so need to account for TLB latency
2450  *
2451  *   The normal calculation is:
2452  *     watermark = dotclock * bytes per pixel * latency
2453  *   where latency is platform & configuration dependent (we assume pessimal
2454  *   values here).
2455  *
2456  *   The SR calculation is:
2457  *     watermark = (trunc(latency/line time)+1) * surface width *
2458  *       bytes per pixel
2459  *   where
2460  *     line time = htotal / dotclock
2461  *   and latency is assumed to be high, as above.
2462  *
2463  * The final value programmed to the register should always be rounded up,
2464  * and include an extra 2 entries to account for clock crossings.
2465  *
2466  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2467  * to set the non-SR watermarks to 8.
2468   */
2469 static void intel_update_watermarks(struct drm_device *dev)
2470 {
2471         struct drm_crtc *crtc;
2472         struct intel_crtc *intel_crtc;
2473         int sr_hdisplay = 0;
2474         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2475         int enabled = 0, pixel_size = 0;
2476
2477         /* Get the clock config from both planes */
2478         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2479                 intel_crtc = to_intel_crtc(crtc);
2480                 if (crtc->enabled) {
2481                         enabled++;
2482                         if (intel_crtc->plane == 0) {
2483                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2484                                           intel_crtc->pipe, crtc->mode.clock);
2485                                 planea_clock = crtc->mode.clock;
2486                         } else {
2487                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2488                                           intel_crtc->pipe, crtc->mode.clock);
2489                                 planeb_clock = crtc->mode.clock;
2490                         }
2491                         sr_hdisplay = crtc->mode.hdisplay;
2492                         sr_clock = crtc->mode.clock;
2493                         if (crtc->fb)
2494                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2495                         else
2496                                 pixel_size = 4; /* by default */
2497                 }
2498         }
2499
2500         if (enabled <= 0)
2501                 return;
2502
2503         /* Single plane configs can enable self refresh */
2504         if (enabled == 1 && IS_IGD(dev))
2505                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2506         else if (IS_IGD(dev))
2507                 igd_disable_cxsr(dev);
2508
2509         if (IS_G4X(dev))
2510                 g4x_update_wm(dev);
2511         else if (IS_I965G(dev))
2512                 i965_update_wm(dev);
2513         else if (IS_I9XX(dev) || IS_MOBILE(dev))
2514                 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
2515                                pixel_size);
2516         else
2517                 i830_update_wm(dev, planea_clock, pixel_size);
2518 }
2519
2520 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2521                                struct drm_display_mode *mode,
2522                                struct drm_display_mode *adjusted_mode,
2523                                int x, int y,
2524                                struct drm_framebuffer *old_fb)
2525 {
2526         struct drm_device *dev = crtc->dev;
2527         struct drm_i915_private *dev_priv = dev->dev_private;
2528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2529         int pipe = intel_crtc->pipe;
2530         int plane = intel_crtc->plane;
2531         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2532         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2533         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2534         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2535         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2536         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2537         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2538         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2539         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2540         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2541         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2542         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2543         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2544         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2545         int refclk, num_outputs = 0;
2546         intel_clock_t clock, reduced_clock;
2547         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2548         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2549         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2550         bool is_edp = false;
2551         struct drm_mode_config *mode_config = &dev->mode_config;
2552         struct drm_connector *connector;
2553         const intel_limit_t *limit;
2554         int ret;
2555         struct fdi_m_n m_n = {0};
2556         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2557         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2558         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2559         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2560         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2561         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2562         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2563         int lvds_reg = LVDS;
2564         u32 temp;
2565         int sdvo_pixel_multiply;
2566         int target_clock;
2567
2568         drm_vblank_pre_modeset(dev, pipe);
2569
2570         list_for_each_entry(connector, &mode_config->connector_list, head) {
2571                 struct intel_output *intel_output = to_intel_output(connector);
2572
2573                 if (!connector->encoder || connector->encoder->crtc != crtc)
2574                         continue;
2575
2576                 switch (intel_output->type) {
2577                 case INTEL_OUTPUT_LVDS:
2578                         is_lvds = true;
2579                         break;
2580                 case INTEL_OUTPUT_SDVO:
2581                 case INTEL_OUTPUT_HDMI:
2582                         is_sdvo = true;
2583                         if (intel_output->needs_tv_clock)
2584                                 is_tv = true;
2585                         break;
2586                 case INTEL_OUTPUT_DVO:
2587                         is_dvo = true;
2588                         break;
2589                 case INTEL_OUTPUT_TVOUT:
2590                         is_tv = true;
2591                         break;
2592                 case INTEL_OUTPUT_ANALOG:
2593                         is_crt = true;
2594                         break;
2595                 case INTEL_OUTPUT_DISPLAYPORT:
2596                         is_dp = true;
2597                         break;
2598                 case INTEL_OUTPUT_EDP:
2599                         is_edp = true;
2600                         break;
2601                 }
2602
2603                 num_outputs++;
2604         }
2605
2606         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2607                 refclk = dev_priv->lvds_ssc_freq * 1000;
2608                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2609         } else if (IS_I9XX(dev)) {
2610                 refclk = 96000;
2611                 if (IS_IGDNG(dev))
2612                         refclk = 120000; /* 120Mhz refclk */
2613         } else {
2614                 refclk = 48000;
2615         }
2616
2617
2618         /*
2619          * Returns a set of divisors for the desired target clock with the given
2620          * refclk, or FALSE.  The returned values represent the clock equation:
2621          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2622          */
2623         limit = intel_limit(crtc);
2624         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2625         if (!ok) {
2626                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2627                 drm_vblank_post_modeset(dev, pipe);
2628                 return -EINVAL;
2629         }
2630
2631         if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2632                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2633                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2634                                                             (adjusted_mode->clock*3/4),
2635                                                             refclk,
2636                                                             &reduced_clock);
2637         }
2638
2639         /* SDVO TV has fixed PLL values depend on its clock range,
2640            this mirrors vbios setting. */
2641         if (is_sdvo && is_tv) {
2642                 if (adjusted_mode->clock >= 100000
2643                                 && adjusted_mode->clock < 140500) {
2644                         clock.p1 = 2;
2645                         clock.p2 = 10;
2646                         clock.n = 3;
2647                         clock.m1 = 16;
2648                         clock.m2 = 8;
2649                 } else if (adjusted_mode->clock >= 140500
2650                                 && adjusted_mode->clock <= 200000) {
2651                         clock.p1 = 1;
2652                         clock.p2 = 10;
2653                         clock.n = 6;
2654                         clock.m1 = 12;
2655                         clock.m2 = 8;
2656                 }
2657         }
2658
2659         /* FDI link */
2660         if (IS_IGDNG(dev)) {
2661                 int lane, link_bw;
2662                 /* eDP doesn't require FDI link, so just set DP M/N
2663                    according to current link config */
2664                 if (is_edp) {
2665                         struct drm_connector *edp;
2666                         target_clock = mode->clock;
2667                         edp = intel_pipe_get_output(crtc);
2668                         intel_edp_link_config(to_intel_output(edp),
2669                                         &lane, &link_bw);
2670                 } else {
2671                         /* DP over FDI requires target mode clock
2672                            instead of link clock */
2673                         if (is_dp)
2674                                 target_clock = mode->clock;
2675                         else
2676                                 target_clock = adjusted_mode->clock;
2677                         lane = 4;
2678                         link_bw = 270000;
2679                 }
2680                 igdng_compute_m_n(3, lane, target_clock,
2681                                   link_bw, &m_n);
2682         }
2683
2684         if (IS_IGD(dev)) {
2685                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2686                 if (has_reduced_clock)
2687                         fp2 = (1 << reduced_clock.n) << 16 |
2688                                 reduced_clock.m1 << 8 | reduced_clock.m2;
2689         } else {
2690                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2691                 if (has_reduced_clock)
2692                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2693                                 reduced_clock.m2;
2694         }
2695
2696         if (!IS_IGDNG(dev))
2697                 dpll = DPLL_VGA_MODE_DIS;
2698
2699         if (IS_I9XX(dev)) {
2700                 if (is_lvds)
2701                         dpll |= DPLLB_MODE_LVDS;
2702                 else
2703                         dpll |= DPLLB_MODE_DAC_SERIAL;
2704                 if (is_sdvo) {
2705                         dpll |= DPLL_DVO_HIGH_SPEED;
2706                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2707                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2708                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2709                         else if (IS_IGDNG(dev))
2710                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2711                 }
2712                 if (is_dp)
2713                         dpll |= DPLL_DVO_HIGH_SPEED;
2714
2715                 /* compute bitmask from p1 value */
2716                 if (IS_IGD(dev))
2717                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2718                 else {
2719                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2720                         /* also FPA1 */
2721                         if (IS_IGDNG(dev))
2722                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2723                         if (IS_G4X(dev) && has_reduced_clock)
2724                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2725                 }
2726                 switch (clock.p2) {
2727                 case 5:
2728                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2729                         break;
2730                 case 7:
2731                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2732                         break;
2733                 case 10:
2734                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2735                         break;
2736                 case 14:
2737                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2738                         break;
2739                 }
2740                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2741                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2742         } else {
2743                 if (is_lvds) {
2744                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2745                 } else {
2746                         if (clock.p1 == 2)
2747                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2748                         else
2749                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2750                         if (clock.p2 == 4)
2751                                 dpll |= PLL_P2_DIVIDE_BY_4;
2752                 }
2753         }
2754
2755         if (is_sdvo && is_tv)
2756                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2757         else if (is_tv)
2758                 /* XXX: just matching BIOS for now */
2759                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2760                 dpll |= 3;
2761         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2762                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2763         else
2764                 dpll |= PLL_REF_INPUT_DREFCLK;
2765
2766         /* setup pipeconf */
2767         pipeconf = I915_READ(pipeconf_reg);
2768
2769         /* Set up the display plane register */
2770         dspcntr = DISPPLANE_GAMMA_ENABLE;
2771
2772         /* IGDNG's plane is forced to pipe, bit 24 is to
2773            enable color space conversion */
2774         if (!IS_IGDNG(dev)) {
2775                 if (pipe == 0)
2776                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
2777                 else
2778                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2779         }
2780
2781         if (pipe == 0 && !IS_I965G(dev)) {
2782                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2783                  * core speed.
2784                  *
2785                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2786                  * pipe == 0 check?
2787                  */
2788                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2789                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
2790                 else
2791                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2792         }
2793
2794         dspcntr |= DISPLAY_PLANE_ENABLE;
2795         pipeconf |= PIPEACONF_ENABLE;
2796         dpll |= DPLL_VCO_ENABLE;
2797
2798
2799         /* Disable the panel fitter if it was on our pipe */
2800         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2801                 I915_WRITE(PFIT_CONTROL, 0);
2802
2803         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2804         drm_mode_debug_printmodeline(mode);
2805
2806         /* assign to IGDNG registers */
2807         if (IS_IGDNG(dev)) {
2808                 fp_reg = pch_fp_reg;
2809                 dpll_reg = pch_dpll_reg;
2810         }
2811
2812         if (is_edp) {
2813                 igdng_disable_pll_edp(crtc);
2814         } else if ((dpll & DPLL_VCO_ENABLE)) {
2815                 I915_WRITE(fp_reg, fp);
2816                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2817                 I915_READ(dpll_reg);
2818                 udelay(150);
2819         }
2820
2821         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2822          * This is an exception to the general rule that mode_set doesn't turn
2823          * things on.
2824          */
2825         if (is_lvds) {
2826                 u32 lvds;
2827
2828                 if (IS_IGDNG(dev))
2829                         lvds_reg = PCH_LVDS;
2830
2831                 lvds = I915_READ(lvds_reg);
2832                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2833                 /* Set the B0-B3 data pairs corresponding to whether we're going to
2834                  * set the DPLLs for dual-channel mode or not.
2835                  */
2836                 if (clock.p2 == 7)
2837                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2838                 else
2839                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2840
2841                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2842                  * appropriately here, but we need to look more thoroughly into how
2843                  * panels behave in the two modes.
2844                  */
2845
2846                 I915_WRITE(lvds_reg, lvds);
2847                 I915_READ(lvds_reg);
2848         }
2849         if (is_dp)
2850                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2851
2852         if (!is_edp) {
2853                 I915_WRITE(fp_reg, fp);
2854                 I915_WRITE(dpll_reg, dpll);
2855                 I915_READ(dpll_reg);
2856                 /* Wait for the clocks to stabilize. */
2857                 udelay(150);
2858
2859                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2860                         if (is_sdvo) {
2861                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2862                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2863                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2864                         } else
2865                                 I915_WRITE(dpll_md_reg, 0);
2866                 } else {
2867                         /* write it again -- the BIOS does, after all */
2868                         I915_WRITE(dpll_reg, dpll);
2869                 }
2870                 I915_READ(dpll_reg);
2871                 /* Wait for the clocks to stabilize. */
2872                 udelay(150);
2873         }
2874
2875         if (is_lvds && has_reduced_clock && i915_powersave) {
2876                 I915_WRITE(fp_reg + 4, fp2);
2877                 intel_crtc->lowfreq_avail = true;
2878                 if (HAS_PIPE_CXSR(dev)) {
2879                         DRM_DEBUG("enabling CxSR downclocking\n");
2880                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
2881                 }
2882         } else {
2883                 I915_WRITE(fp_reg + 4, fp);
2884                 intel_crtc->lowfreq_avail = false;
2885                 if (HAS_PIPE_CXSR(dev)) {
2886                         DRM_DEBUG("disabling CxSR downclocking\n");
2887                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
2888                 }
2889         }
2890
2891         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2892                    ((adjusted_mode->crtc_htotal - 1) << 16));
2893         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2894                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
2895         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2896                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
2897         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2898                    ((adjusted_mode->crtc_vtotal - 1) << 16));
2899         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2900                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
2901         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2902                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
2903         /* pipesrc and dspsize control the size that is scaled from, which should
2904          * always be the user's requested size.
2905          */
2906         if (!IS_IGDNG(dev)) {
2907                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2908                                 (mode->hdisplay - 1));
2909                 I915_WRITE(dsppos_reg, 0);
2910         }
2911         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2912
2913         if (IS_IGDNG(dev)) {
2914                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2915                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2916                 I915_WRITE(link_m1_reg, m_n.link_m);
2917                 I915_WRITE(link_n1_reg, m_n.link_n);
2918
2919                 if (is_edp) {
2920                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
2921                 } else {
2922                         /* enable FDI RX PLL too */
2923                         temp = I915_READ(fdi_rx_reg);
2924                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2925                         udelay(200);
2926                 }
2927         }
2928
2929         I915_WRITE(pipeconf_reg, pipeconf);
2930         I915_READ(pipeconf_reg);
2931
2932         intel_wait_for_vblank(dev);
2933
2934         if (IS_IGDNG(dev)) {
2935                 /* enable address swizzle for tiling buffer */
2936                 temp = I915_READ(DISP_ARB_CTL);
2937                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
2938         }
2939
2940         I915_WRITE(dspcntr_reg, dspcntr);
2941
2942         /* Flush the plane changes */
2943         ret = intel_pipe_set_base(crtc, x, y, old_fb);
2944
2945         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
2946                 intel_update_fbc(crtc, &crtc->mode);
2947         intel_update_watermarks(dev);
2948
2949         drm_vblank_post_modeset(dev, pipe);
2950
2951         return ret;
2952 }
2953
2954 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2955 void intel_crtc_load_lut(struct drm_crtc *crtc)
2956 {
2957         struct drm_device *dev = crtc->dev;
2958         struct drm_i915_private *dev_priv = dev->dev_private;
2959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2960         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2961         int i;
2962
2963         /* The clocks have to be on to load the palette. */
2964         if (!crtc->enabled)
2965                 return;
2966
2967         /* use legacy palette for IGDNG */
2968         if (IS_IGDNG(dev))
2969                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2970                                                    LGC_PALETTE_B;
2971
2972         for (i = 0; i < 256; i++) {
2973                 I915_WRITE(palreg + 4 * i,
2974                            (intel_crtc->lut_r[i] << 16) |
2975                            (intel_crtc->lut_g[i] << 8) |
2976                            intel_crtc->lut_b[i]);
2977         }
2978 }
2979
2980 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2981                                  struct drm_file *file_priv,
2982                                  uint32_t handle,
2983                                  uint32_t width, uint32_t height)
2984 {
2985         struct drm_device *dev = crtc->dev;
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2988         struct drm_gem_object *bo;
2989         struct drm_i915_gem_object *obj_priv;
2990         int pipe = intel_crtc->pipe;
2991         int plane = intel_crtc->plane;
2992         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2993         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2994         uint32_t temp = I915_READ(control);
2995         size_t addr;
2996         int ret;
2997
2998         DRM_DEBUG("\n");
2999
3000         /* if we want to turn off the cursor ignore width and height */
3001         if (!handle) {
3002                 DRM_DEBUG("cursor off\n");
3003                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3004                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3005                         temp |= CURSOR_MODE_DISABLE;
3006                 } else {
3007                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3008                 }
3009                 addr = 0;
3010                 bo = NULL;
3011                 mutex_lock(&dev->struct_mutex);
3012                 goto finish;
3013         }
3014
3015         /* Currently we only support 64x64 cursors */
3016         if (width != 64 || height != 64) {
3017                 DRM_ERROR("we currently only support 64x64 cursors\n");
3018                 return -EINVAL;
3019         }
3020
3021         bo = drm_gem_object_lookup(dev, file_priv, handle);
3022         if (!bo)
3023                 return -ENOENT;
3024
3025         obj_priv = bo->driver_private;
3026
3027         if (bo->size < width * height * 4) {
3028                 DRM_ERROR("buffer is to small\n");
3029                 ret = -ENOMEM;
3030                 goto fail;
3031         }
3032
3033         /* we only need to pin inside GTT if cursor is non-phy */
3034         mutex_lock(&dev->struct_mutex);
3035         if (!dev_priv->cursor_needs_physical) {
3036                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3037                 if (ret) {
3038                         DRM_ERROR("failed to pin cursor bo\n");
3039                         goto fail_locked;
3040                 }
3041                 addr = obj_priv->gtt_offset;
3042         } else {
3043                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3044                 if (ret) {
3045                         DRM_ERROR("failed to attach phys object\n");
3046                         goto fail_locked;
3047                 }
3048                 addr = obj_priv->phys_obj->handle->busaddr;
3049         }
3050
3051         if (!IS_I9XX(dev))
3052                 I915_WRITE(CURSIZE, (height << 12) | width);
3053
3054         /* Hooray for CUR*CNTR differences */
3055         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3056                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3057                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3058                 temp |= (pipe << 28); /* Connect to correct pipe */
3059         } else {
3060                 temp &= ~(CURSOR_FORMAT_MASK);
3061                 temp |= CURSOR_ENABLE;
3062                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3063         }
3064
3065  finish:
3066         I915_WRITE(control, temp);
3067         I915_WRITE(base, addr);
3068
3069         if (intel_crtc->cursor_bo) {
3070                 if (dev_priv->cursor_needs_physical) {
3071                         if (intel_crtc->cursor_bo != bo)
3072                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3073                 } else
3074                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3075                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3076         }
3077
3078         if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
3079                 intel_update_fbc(crtc, &crtc->mode);
3080
3081         mutex_unlock(&dev->struct_mutex);
3082
3083         intel_crtc->cursor_addr = addr;
3084         intel_crtc->cursor_bo = bo;
3085
3086         return 0;
3087 fail:
3088         mutex_lock(&dev->struct_mutex);
3089 fail_locked:
3090         drm_gem_object_unreference(bo);
3091         mutex_unlock(&dev->struct_mutex);
3092         return ret;
3093 }
3094
3095 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3096 {
3097         struct drm_device *dev = crtc->dev;
3098         struct drm_i915_private *dev_priv = dev->dev_private;
3099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3100         struct intel_framebuffer *intel_fb;
3101         int pipe = intel_crtc->pipe;
3102         uint32_t temp = 0;
3103         uint32_t adder;
3104
3105         if (crtc->fb) {
3106                 intel_fb = to_intel_framebuffer(crtc->fb);
3107                 intel_mark_busy(dev, intel_fb->obj);
3108         }
3109
3110         if (x < 0) {
3111                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3112                 x = -x;
3113         }
3114         if (y < 0) {
3115                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3116                 y = -y;
3117         }
3118
3119         temp |= x << CURSOR_X_SHIFT;
3120         temp |= y << CURSOR_Y_SHIFT;
3121
3122         adder = intel_crtc->cursor_addr;
3123         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3124         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3125
3126         return 0;
3127 }
3128
3129 /** Sets the color ramps on behalf of RandR */
3130 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3131                                  u16 blue, int regno)
3132 {
3133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3134
3135         intel_crtc->lut_r[regno] = red >> 8;
3136         intel_crtc->lut_g[regno] = green >> 8;
3137         intel_crtc->lut_b[regno] = blue >> 8;
3138 }
3139
3140 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3141                                  u16 *blue, uint32_t size)
3142 {
3143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3144         int i;
3145
3146         if (size != 256)
3147                 return;
3148
3149         for (i = 0; i < 256; i++) {
3150                 intel_crtc->lut_r[i] = red[i] >> 8;
3151                 intel_crtc->lut_g[i] = green[i] >> 8;
3152                 intel_crtc->lut_b[i] = blue[i] >> 8;
3153         }
3154
3155         intel_crtc_load_lut(crtc);
3156 }
3157
3158 /**
3159  * Get a pipe with a simple mode set on it for doing load-based monitor
3160  * detection.
3161  *
3162  * It will be up to the load-detect code to adjust the pipe as appropriate for
3163  * its requirements.  The pipe will be connected to no other outputs.
3164  *
3165  * Currently this code will only succeed if there is a pipe with no outputs
3166  * configured for it.  In the future, it could choose to temporarily disable
3167  * some outputs to free up a pipe for its use.
3168  *
3169  * \return crtc, or NULL if no pipes are available.
3170  */
3171
3172 /* VESA 640x480x72Hz mode to set on the pipe */
3173 static struct drm_display_mode load_detect_mode = {
3174         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3175                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3176 };
3177
3178 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3179                                             struct drm_display_mode *mode,
3180                                             int *dpms_mode)
3181 {
3182         struct intel_crtc *intel_crtc;
3183         struct drm_crtc *possible_crtc;
3184         struct drm_crtc *supported_crtc =NULL;
3185         struct drm_encoder *encoder = &intel_output->enc;
3186         struct drm_crtc *crtc = NULL;
3187         struct drm_device *dev = encoder->dev;
3188         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3189         struct drm_crtc_helper_funcs *crtc_funcs;
3190         int i = -1;
3191
3192         /*
3193          * Algorithm gets a little messy:
3194          *   - if the connector already has an assigned crtc, use it (but make
3195          *     sure it's on first)
3196          *   - try to find the first unused crtc that can drive this connector,
3197          *     and use that if we find one
3198          *   - if there are no unused crtcs available, try to use the first
3199          *     one we found that supports the connector
3200          */
3201
3202         /* See if we already have a CRTC for this connector */
3203         if (encoder->crtc) {
3204                 crtc = encoder->crtc;
3205                 /* Make sure the crtc and connector are running */
3206                 intel_crtc = to_intel_crtc(crtc);
3207                 *dpms_mode = intel_crtc->dpms_mode;
3208                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3209                         crtc_funcs = crtc->helper_private;
3210                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3211                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3212                 }
3213                 return crtc;
3214         }
3215
3216         /* Find an unused one (if possible) */
3217         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3218                 i++;
3219                 if (!(encoder->possible_crtcs & (1 << i)))
3220                         continue;
3221                 if (!possible_crtc->enabled) {
3222                         crtc = possible_crtc;
3223                         break;
3224                 }
3225                 if (!supported_crtc)
3226                         supported_crtc = possible_crtc;
3227         }
3228
3229         /*
3230          * If we didn't find an unused CRTC, don't use any.
3231          */
3232         if (!crtc) {
3233                 return NULL;
3234         }
3235
3236         encoder->crtc = crtc;
3237         intel_output->base.encoder = encoder;
3238         intel_output->load_detect_temp = true;
3239
3240         intel_crtc = to_intel_crtc(crtc);
3241         *dpms_mode = intel_crtc->dpms_mode;
3242
3243         if (!crtc->enabled) {
3244                 if (!mode)
3245                         mode = &load_detect_mode;
3246                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3247         } else {
3248                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3249                         crtc_funcs = crtc->helper_private;
3250                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3251                 }
3252
3253                 /* Add this connector to the crtc */
3254                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3255                 encoder_funcs->commit(encoder);
3256         }
3257         /* let the connector get through one full cycle before testing */
3258         intel_wait_for_vblank(dev);
3259
3260         return crtc;
3261 }
3262
3263 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3264 {
3265         struct drm_encoder *encoder = &intel_output->enc;
3266         struct drm_device *dev = encoder->dev;
3267         struct drm_crtc *crtc = encoder->crtc;
3268         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3269         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3270
3271         if (intel_output->load_detect_temp) {
3272                 encoder->crtc = NULL;
3273                 intel_output->base.encoder = NULL;
3274                 intel_output->load_detect_temp = false;
3275                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3276                 drm_helper_disable_unused_functions(dev);
3277         }
3278
3279         /* Switch crtc and output back off if necessary */
3280         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3281                 if (encoder->crtc == crtc)
3282                         encoder_funcs->dpms(encoder, dpms_mode);
3283                 crtc_funcs->dpms(crtc, dpms_mode);
3284         }
3285 }
3286
3287 /* Returns the clock of the currently programmed mode of the given pipe. */
3288 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3289 {
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292         int pipe = intel_crtc->pipe;
3293         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3294         u32 fp;
3295         intel_clock_t clock;
3296
3297         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3298                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3299         else
3300                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3301
3302         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3303         if (IS_IGD(dev)) {
3304                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3305                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3306         } else {
3307                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3308                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3309         }
3310
3311         if (IS_I9XX(dev)) {
3312                 if (IS_IGD(dev))
3313                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3314                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3315                 else
3316                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3317                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3318
3319                 switch (dpll & DPLL_MODE_MASK) {
3320                 case DPLLB_MODE_DAC_SERIAL:
3321                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3322                                 5 : 10;
3323                         break;
3324                 case DPLLB_MODE_LVDS:
3325                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3326                                 7 : 14;
3327                         break;
3328                 default:
3329                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3330                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3331                         return 0;
3332                 }
3333
3334                 /* XXX: Handle the 100Mhz refclk */
3335                 intel_clock(dev, 96000, &clock);
3336         } else {
3337                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3338
3339                 if (is_lvds) {
3340                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3341                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3342                         clock.p2 = 14;
3343
3344                         if ((dpll & PLL_REF_INPUT_MASK) ==
3345                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3346                                 /* XXX: might not be 66MHz */
3347                                 intel_clock(dev, 66000, &clock);
3348                         } else
3349                                 intel_clock(dev, 48000, &clock);
3350                 } else {
3351                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3352                                 clock.p1 = 2;
3353                         else {
3354                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3355                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3356                         }
3357                         if (dpll & PLL_P2_DIVIDE_BY_4)
3358                                 clock.p2 = 4;
3359                         else
3360                                 clock.p2 = 2;
3361
3362                         intel_clock(dev, 48000, &clock);
3363                 }
3364         }
3365
3366         /* XXX: It would be nice to validate the clocks, but we can't reuse
3367          * i830PllIsValid() because it relies on the xf86_config connector
3368          * configuration being accurate, which it isn't necessarily.
3369          */
3370
3371         return clock.dot;
3372 }
3373
3374 /** Returns the currently programmed mode of the given pipe. */
3375 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3376                                              struct drm_crtc *crtc)
3377 {
3378         struct drm_i915_private *dev_priv = dev->dev_private;
3379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3380         int pipe = intel_crtc->pipe;
3381         struct drm_display_mode *mode;
3382         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3383         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3384         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3385         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3386
3387         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3388         if (!mode)
3389                 return NULL;
3390
3391         mode->clock = intel_crtc_clock_get(dev, crtc);
3392         mode->hdisplay = (htot & 0xffff) + 1;
3393         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3394         mode->hsync_start = (hsync & 0xffff) + 1;
3395         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3396         mode->vdisplay = (vtot & 0xffff) + 1;
3397         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3398         mode->vsync_start = (vsync & 0xffff) + 1;
3399         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3400
3401         drm_mode_set_name(mode);
3402         drm_mode_set_crtcinfo(mode, 0);
3403
3404         return mode;
3405 }
3406
3407 #define GPU_IDLE_TIMEOUT 500 /* ms */
3408
3409 /* When this timer fires, we've been idle for awhile */
3410 static void intel_gpu_idle_timer(unsigned long arg)
3411 {
3412         struct drm_device *dev = (struct drm_device *)arg;
3413         drm_i915_private_t *dev_priv = dev->dev_private;
3414
3415         DRM_DEBUG("idle timer fired, downclocking\n");
3416
3417         dev_priv->busy = false;
3418
3419         queue_work(dev_priv->wq, &dev_priv->idle_work);
3420 }
3421
3422 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3423 {
3424         drm_i915_private_t *dev_priv = dev->dev_private;
3425
3426         if (IS_IGDNG(dev))
3427                 return;
3428
3429         if (!dev_priv->render_reclock_avail) {
3430                 DRM_DEBUG("not reclocking render clock\n");
3431                 return;
3432         }
3433
3434         /* Restore render clock frequency to original value */
3435         if (IS_G4X(dev) || IS_I9XX(dev))
3436                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3437         else if (IS_I85X(dev))
3438                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3439         DRM_DEBUG("increasing render clock frequency\n");
3440
3441         /* Schedule downclock */
3442         if (schedule)
3443                 mod_timer(&dev_priv->idle_timer, jiffies +
3444                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3445 }
3446
3447 void intel_decrease_renderclock(struct drm_device *dev)
3448 {
3449         drm_i915_private_t *dev_priv = dev->dev_private;
3450
3451         if (IS_IGDNG(dev))
3452                 return;
3453
3454         if (!dev_priv->render_reclock_avail) {
3455                 DRM_DEBUG("not reclocking render clock\n");
3456                 return;
3457         }
3458
3459         if (IS_G4X(dev)) {
3460                 u16 gcfgc;
3461
3462                 /* Adjust render clock... */
3463                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3464
3465                 /* Down to minimum... */
3466                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3467                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3468
3469                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3470         } else if (IS_I965G(dev)) {
3471                 u16 gcfgc;
3472
3473                 /* Adjust render clock... */
3474                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3475
3476                 /* Down to minimum... */
3477                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3478                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3479
3480                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3481         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3482                 u16 gcfgc;
3483
3484                 /* Adjust render clock... */
3485                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3486
3487                 /* Down to minimum... */
3488                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3489                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3490
3491                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3492         } else if (IS_I915G(dev)) {
3493                 u16 gcfgc;
3494
3495                 /* Adjust render clock... */
3496                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3497
3498                 /* Down to minimum... */
3499                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3500                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3501
3502                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3503         } else if (IS_I85X(dev)) {
3504                 u16 hpllcc;
3505
3506                 /* Adjust render clock... */
3507                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3508
3509                 /* Up to maximum... */
3510                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3511                 hpllcc |= GC_CLOCK_133_200;
3512
3513                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3514         }
3515         DRM_DEBUG("decreasing render clock frequency\n");
3516 }
3517
3518 /* Note that no increase function is needed for this - increase_renderclock()
3519  *  will also rewrite these bits
3520  */
3521 void intel_decrease_displayclock(struct drm_device *dev)
3522 {
3523         if (IS_IGDNG(dev))
3524                 return;
3525
3526         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3527             IS_I915GM(dev)) {
3528                 u16 gcfgc;
3529
3530                 /* Adjust render clock... */
3531                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3532
3533                 /* Down to minimum... */
3534                 gcfgc &= ~0xf0;
3535                 gcfgc |= 0x80;
3536
3537                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3538         }
3539 }
3540
3541 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3542
3543 static void intel_crtc_idle_timer(unsigned long arg)
3544 {
3545         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3546         struct drm_crtc *crtc = &intel_crtc->base;
3547         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3548
3549         DRM_DEBUG("idle timer fired, downclocking\n");
3550
3551         intel_crtc->busy = false;
3552
3553         queue_work(dev_priv->wq, &dev_priv->idle_work);
3554 }
3555
3556 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3557 {
3558         struct drm_device *dev = crtc->dev;
3559         drm_i915_private_t *dev_priv = dev->dev_private;
3560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3561         int pipe = intel_crtc->pipe;
3562         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3563         int dpll = I915_READ(dpll_reg);
3564
3565         if (IS_IGDNG(dev))
3566                 return;
3567
3568         if (!dev_priv->lvds_downclock_avail)
3569                 return;
3570
3571         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3572                 DRM_DEBUG("upclocking LVDS\n");
3573
3574                 /* Unlock panel regs */
3575                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3576
3577                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3578                 I915_WRITE(dpll_reg, dpll);
3579                 dpll = I915_READ(dpll_reg);
3580                 intel_wait_for_vblank(dev);
3581                 dpll = I915_READ(dpll_reg);
3582                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3583                         DRM_DEBUG("failed to upclock LVDS!\n");
3584
3585                 /* ...and lock them again */
3586                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3587         }
3588
3589         /* Schedule downclock */
3590         if (schedule)
3591                 mod_timer(&intel_crtc->idle_timer, jiffies +
3592                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3593 }
3594
3595 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3596 {
3597         struct drm_device *dev = crtc->dev;
3598         drm_i915_private_t *dev_priv = dev->dev_private;
3599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3600         int pipe = intel_crtc->pipe;
3601         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3602         int dpll = I915_READ(dpll_reg);
3603
3604         if (IS_IGDNG(dev))
3605                 return;
3606
3607         if (!dev_priv->lvds_downclock_avail)
3608                 return;
3609
3610         /*
3611          * Since this is called by a timer, we should never get here in
3612          * the manual case.
3613          */
3614         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3615                 DRM_DEBUG("downclocking LVDS\n");
3616
3617                 /* Unlock panel regs */
3618                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3619
3620                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3621                 I915_WRITE(dpll_reg, dpll);
3622                 dpll = I915_READ(dpll_reg);
3623                 intel_wait_for_vblank(dev);
3624                 dpll = I915_READ(dpll_reg);
3625                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3626                         DRM_DEBUG("failed to downclock LVDS!\n");
3627
3628                 /* ...and lock them again */
3629                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3630         }
3631
3632 }
3633
3634 /**
3635  * intel_idle_update - adjust clocks for idleness
3636  * @work: work struct
3637  *
3638  * Either the GPU or display (or both) went idle.  Check the busy status
3639  * here and adjust the CRTC and GPU clocks as necessary.
3640  */
3641 static void intel_idle_update(struct work_struct *work)
3642 {
3643         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3644                                                     idle_work);
3645         struct drm_device *dev = dev_priv->dev;
3646         struct drm_crtc *crtc;
3647         struct intel_crtc *intel_crtc;
3648
3649         if (!i915_powersave)
3650                 return;
3651
3652         mutex_lock(&dev->struct_mutex);
3653
3654         /* GPU isn't processing, downclock it. */
3655         if (!dev_priv->busy) {
3656                 intel_decrease_renderclock(dev);
3657                 intel_decrease_displayclock(dev);
3658         }
3659
3660         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3661                 /* Skip inactive CRTCs */
3662                 if (!crtc->fb)
3663                         continue;
3664
3665                 intel_crtc = to_intel_crtc(crtc);
3666                 if (!intel_crtc->busy)
3667                         intel_decrease_pllclock(crtc);
3668         }
3669
3670         mutex_unlock(&dev->struct_mutex);
3671 }
3672
3673 /**
3674  * intel_mark_busy - mark the GPU and possibly the display busy
3675  * @dev: drm device
3676  * @obj: object we're operating on
3677  *
3678  * Callers can use this function to indicate that the GPU is busy processing
3679  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3680  * buffer), we'll also mark the display as busy, so we know to increase its
3681  * clock frequency.
3682  */
3683 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3684 {
3685         drm_i915_private_t *dev_priv = dev->dev_private;
3686         struct drm_crtc *crtc = NULL;
3687         struct intel_framebuffer *intel_fb;
3688         struct intel_crtc *intel_crtc;
3689
3690         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3691                 return;
3692
3693         dev_priv->busy = true;
3694         intel_increase_renderclock(dev, true);
3695
3696         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3697                 if (!crtc->fb)
3698                         continue;
3699
3700                 intel_crtc = to_intel_crtc(crtc);
3701                 intel_fb = to_intel_framebuffer(crtc->fb);
3702                 if (intel_fb->obj == obj) {
3703                         if (!intel_crtc->busy) {
3704                                 /* Non-busy -> busy, upclock */
3705                                 intel_increase_pllclock(crtc, true);
3706                                 intel_crtc->busy = true;
3707                         } else {
3708                                 /* Busy -> busy, put off timer */
3709                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3710                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3711                         }
3712                 }
3713         }
3714 }
3715
3716 static void intel_crtc_destroy(struct drm_crtc *crtc)
3717 {
3718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3719
3720         drm_crtc_cleanup(crtc);
3721         kfree(intel_crtc);
3722 }
3723
3724 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3725         .dpms = intel_crtc_dpms,
3726         .mode_fixup = intel_crtc_mode_fixup,
3727         .mode_set = intel_crtc_mode_set,
3728         .mode_set_base = intel_pipe_set_base,
3729         .prepare = intel_crtc_prepare,
3730         .commit = intel_crtc_commit,
3731 };
3732
3733 static const struct drm_crtc_funcs intel_crtc_funcs = {
3734         .cursor_set = intel_crtc_cursor_set,
3735         .cursor_move = intel_crtc_cursor_move,
3736         .gamma_set = intel_crtc_gamma_set,
3737         .set_config = drm_crtc_helper_set_config,
3738         .destroy = intel_crtc_destroy,
3739 };
3740
3741
3742 static void intel_crtc_init(struct drm_device *dev, int pipe)
3743 {
3744         struct intel_crtc *intel_crtc;
3745         int i;
3746
3747         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3748         if (intel_crtc == NULL)
3749                 return;
3750
3751         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3752
3753         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
3754         intel_crtc->pipe = pipe;
3755         intel_crtc->plane = pipe;
3756         for (i = 0; i < 256; i++) {
3757                 intel_crtc->lut_r[i] = i;
3758                 intel_crtc->lut_g[i] = i;
3759                 intel_crtc->lut_b[i] = i;
3760         }
3761
3762         /* Swap pipes & planes for FBC on pre-965 */
3763         intel_crtc->pipe = pipe;
3764         intel_crtc->plane = pipe;
3765         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
3766                 DRM_DEBUG("swapping pipes & planes for FBC\n");
3767                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
3768         }
3769
3770         intel_crtc->cursor_addr = 0;
3771         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3772         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3773
3774         intel_crtc->busy = false;
3775
3776         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
3777                     (unsigned long)intel_crtc);
3778 }
3779
3780 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3781                                 struct drm_file *file_priv)
3782 {
3783         drm_i915_private_t *dev_priv = dev->dev_private;
3784         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
3785         struct drm_mode_object *drmmode_obj;
3786         struct intel_crtc *crtc;
3787
3788         if (!dev_priv) {
3789                 DRM_ERROR("called with no initialization\n");
3790                 return -EINVAL;
3791         }
3792
3793         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
3794                         DRM_MODE_OBJECT_CRTC);
3795
3796         if (!drmmode_obj) {
3797                 DRM_ERROR("no such CRTC id\n");
3798                 return -EINVAL;
3799         }
3800
3801         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
3802         pipe_from_crtc_id->pipe = crtc->pipe;
3803
3804         return 0;
3805 }
3806
3807 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3808 {
3809         struct drm_crtc *crtc = NULL;
3810
3811         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3812                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813                 if (intel_crtc->pipe == pipe)
3814                         break;
3815         }
3816         return crtc;
3817 }
3818
3819 static int intel_connector_clones(struct drm_device *dev, int type_mask)
3820 {
3821         int index_mask = 0;
3822         struct drm_connector *connector;
3823         int entry = 0;
3824
3825         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3826                 struct intel_output *intel_output = to_intel_output(connector);
3827                 if (type_mask & intel_output->clone_mask)
3828                         index_mask |= (1 << entry);
3829                 entry++;
3830         }
3831         return index_mask;
3832 }
3833
3834
3835 static void intel_setup_outputs(struct drm_device *dev)
3836 {
3837         struct drm_i915_private *dev_priv = dev->dev_private;
3838         struct drm_connector *connector;
3839
3840         intel_crt_init(dev);
3841
3842         /* Set up integrated LVDS */
3843         if (IS_MOBILE(dev) && !IS_I830(dev))
3844                 intel_lvds_init(dev);
3845
3846         if (IS_IGDNG(dev)) {
3847                 int found;
3848
3849                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3850                         intel_dp_init(dev, DP_A);
3851
3852                 if (I915_READ(HDMIB) & PORT_DETECTED) {
3853                         /* check SDVOB */
3854                         /* found = intel_sdvo_init(dev, HDMIB); */
3855                         found = 0;
3856                         if (!found)
3857                                 intel_hdmi_init(dev, HDMIB);
3858                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3859                                 intel_dp_init(dev, PCH_DP_B);
3860                 }
3861
3862                 if (I915_READ(HDMIC) & PORT_DETECTED)
3863                         intel_hdmi_init(dev, HDMIC);
3864
3865                 if (I915_READ(HDMID) & PORT_DETECTED)
3866                         intel_hdmi_init(dev, HDMID);
3867
3868                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
3869                         intel_dp_init(dev, PCH_DP_C);
3870
3871                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
3872                         intel_dp_init(dev, PCH_DP_D);
3873
3874         } else if (IS_I9XX(dev)) {
3875                 bool found = false;
3876
3877                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3878                         found = intel_sdvo_init(dev, SDVOB);
3879                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3880                                 intel_hdmi_init(dev, SDVOB);
3881
3882                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
3883                                 intel_dp_init(dev, DP_B);
3884                 }
3885
3886                 /* Before G4X SDVOC doesn't have its own detect register */
3887
3888                 if (I915_READ(SDVOB) & SDVO_DETECTED)
3889                         found = intel_sdvo_init(dev, SDVOC);
3890
3891                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
3892
3893                         if (SUPPORTS_INTEGRATED_HDMI(dev))
3894                                 intel_hdmi_init(dev, SDVOC);
3895                         if (SUPPORTS_INTEGRATED_DP(dev))
3896                                 intel_dp_init(dev, DP_C);
3897                 }
3898
3899                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3900                         intel_dp_init(dev, DP_D);
3901         } else
3902                 intel_dvo_init(dev);
3903
3904         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3905                 intel_tv_init(dev);
3906
3907         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3908                 struct intel_output *intel_output = to_intel_output(connector);
3909                 struct drm_encoder *encoder = &intel_output->enc;
3910
3911                 encoder->possible_crtcs = intel_output->crtc_mask;
3912                 encoder->possible_clones = intel_connector_clones(dev,
3913                                                 intel_output->clone_mask);
3914         }
3915 }
3916
3917 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3918 {
3919         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3920         struct drm_device *dev = fb->dev;
3921
3922         if (fb->fbdev)
3923                 intelfb_remove(dev, fb);
3924
3925         drm_framebuffer_cleanup(fb);
3926         mutex_lock(&dev->struct_mutex);
3927         drm_gem_object_unreference(intel_fb->obj);
3928         mutex_unlock(&dev->struct_mutex);
3929
3930         kfree(intel_fb);
3931 }
3932
3933 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3934                                                 struct drm_file *file_priv,
3935                                                 unsigned int *handle)
3936 {
3937         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3938         struct drm_gem_object *object = intel_fb->obj;
3939
3940         return drm_gem_handle_create(file_priv, object, handle);
3941 }
3942
3943 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3944         .destroy = intel_user_framebuffer_destroy,
3945         .create_handle = intel_user_framebuffer_create_handle,
3946 };
3947
3948 int intel_framebuffer_create(struct drm_device *dev,
3949                              struct drm_mode_fb_cmd *mode_cmd,
3950                              struct drm_framebuffer **fb,
3951                              struct drm_gem_object *obj)
3952 {
3953         struct intel_framebuffer *intel_fb;
3954         int ret;
3955
3956         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3957         if (!intel_fb)
3958                 return -ENOMEM;
3959
3960         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3961         if (ret) {
3962                 DRM_ERROR("framebuffer init failed %d\n", ret);
3963                 return ret;
3964         }
3965
3966         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3967
3968         intel_fb->obj = obj;
3969
3970         *fb = &intel_fb->base;
3971
3972         return 0;
3973 }
3974
3975
3976 static struct drm_framebuffer *
3977 intel_user_framebuffer_create(struct drm_device *dev,
3978                               struct drm_file *filp,
3979                               struct drm_mode_fb_cmd *mode_cmd)
3980 {
3981         struct drm_gem_object *obj;
3982         struct drm_framebuffer *fb;
3983         int ret;
3984
3985         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3986         if (!obj)
3987                 return NULL;
3988
3989         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3990         if (ret) {
3991                 mutex_lock(&dev->struct_mutex);
3992                 drm_gem_object_unreference(obj);
3993                 mutex_unlock(&dev->struct_mutex);
3994                 return NULL;
3995         }
3996
3997         return fb;
3998 }
3999
4000 static const struct drm_mode_config_funcs intel_mode_funcs = {
4001         .fb_create = intel_user_framebuffer_create,
4002         .fb_changed = intelfb_probe,
4003 };
4004
4005 void intel_init_clock_gating(struct drm_device *dev)
4006 {
4007         struct drm_i915_private *dev_priv = dev->dev_private;
4008
4009         /*
4010          * Disable clock gating reported to work incorrectly according to the
4011          * specs, but enable as much else as we can.
4012          */
4013         if (IS_G4X(dev)) {
4014                 uint32_t dspclk_gate;
4015                 I915_WRITE(RENCLK_GATE_D1, 0);
4016                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4017                        GS_UNIT_CLOCK_GATE_DISABLE |
4018                        CL_UNIT_CLOCK_GATE_DISABLE);
4019                 I915_WRITE(RAMCLK_GATE_D, 0);
4020                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4021                         OVRUNIT_CLOCK_GATE_DISABLE |
4022                         OVCUNIT_CLOCK_GATE_DISABLE;
4023                 if (IS_GM45(dev))
4024                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4025                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4026         } else if (IS_I965GM(dev)) {
4027                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4028                 I915_WRITE(RENCLK_GATE_D2, 0);
4029                 I915_WRITE(DSPCLK_GATE_D, 0);
4030                 I915_WRITE(RAMCLK_GATE_D, 0);
4031                 I915_WRITE16(DEUC, 0);
4032         } else if (IS_I965G(dev)) {
4033                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4034                        I965_RCC_CLOCK_GATE_DISABLE |
4035                        I965_RCPB_CLOCK_GATE_DISABLE |
4036                        I965_ISC_CLOCK_GATE_DISABLE |
4037                        I965_FBC_CLOCK_GATE_DISABLE);
4038                 I915_WRITE(RENCLK_GATE_D2, 0);
4039         } else if (IS_I9XX(dev)) {
4040                 u32 dstate = I915_READ(D_STATE);
4041
4042                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4043                         DSTATE_DOT_CLOCK_GATING;
4044                 I915_WRITE(D_STATE, dstate);
4045         } else if (IS_I855(dev) || IS_I865G(dev)) {
4046                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4047         } else if (IS_I830(dev)) {
4048                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4049         }
4050 }
4051
4052 void intel_modeset_init(struct drm_device *dev)
4053 {
4054         struct drm_i915_private *dev_priv = dev->dev_private;
4055         int num_pipe;
4056         int i;
4057
4058         drm_mode_config_init(dev);
4059
4060         dev->mode_config.min_width = 0;
4061         dev->mode_config.min_height = 0;
4062
4063         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4064
4065         if (IS_I965G(dev)) {
4066                 dev->mode_config.max_width = 8192;
4067                 dev->mode_config.max_height = 8192;
4068         } else if (IS_I9XX(dev)) {
4069                 dev->mode_config.max_width = 4096;
4070                 dev->mode_config.max_height = 4096;
4071         } else {
4072                 dev->mode_config.max_width = 2048;
4073                 dev->mode_config.max_height = 2048;
4074         }
4075
4076         /* set memory base */
4077         if (IS_I9XX(dev))
4078                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4079         else
4080                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4081
4082         if (IS_MOBILE(dev) || IS_I9XX(dev))
4083                 num_pipe = 2;
4084         else
4085                 num_pipe = 1;
4086         DRM_DEBUG("%d display pipe%s available.\n",
4087                   num_pipe, num_pipe > 1 ? "s" : "");
4088
4089         if (IS_I85X(dev))
4090                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4091         else if (IS_I9XX(dev) || IS_G4X(dev))
4092                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4093
4094         for (i = 0; i < num_pipe; i++) {
4095                 intel_crtc_init(dev, i);
4096         }
4097
4098         intel_setup_outputs(dev);
4099
4100         intel_init_clock_gating(dev);
4101
4102         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4103         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4104                     (unsigned long)dev);
4105 }
4106
4107 void intel_modeset_cleanup(struct drm_device *dev)
4108 {
4109         struct drm_i915_private *dev_priv = dev->dev_private;
4110         struct drm_crtc *crtc;
4111         struct intel_crtc *intel_crtc;
4112
4113         mutex_lock(&dev->struct_mutex);
4114
4115         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4116                 /* Skip inactive CRTCs */
4117                 if (!crtc->fb)
4118                         continue;
4119
4120                 intel_crtc = to_intel_crtc(crtc);
4121                 intel_increase_pllclock(crtc, false);
4122                 del_timer_sync(&intel_crtc->idle_timer);
4123         }
4124
4125         intel_increase_renderclock(dev, false);
4126         del_timer_sync(&dev_priv->idle_timer);
4127
4128         mutex_unlock(&dev->struct_mutex);
4129
4130         i8xx_disable_fbc(dev);
4131         drm_mode_config_cleanup(dev);
4132 }
4133
4134
4135 /* current intel driver doesn't take advantage of encoders
4136    always give back the encoder for the connector
4137 */
4138 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4139 {
4140         struct intel_output *intel_output = to_intel_output(connector);
4141
4142         return &intel_output->enc;
4143 }