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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include "drmP.h"
  29 #include "intel_drv.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32
  33 #include "drm_crtc_helper.h"
  34
  35 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  36
  37 typedef struct {
  38     /* given values */
  39     int n;
  40     int m1, m2;
  41     int p1, p2;
  42     /* derived values */
  43     int dot;
  44     int vco;
  45     int m;
  46     int p;
  47 } intel_clock_t;
  48
  49 typedef struct {
  50     int min, max;
  51 } intel_range_t;
  52
  53 typedef struct {
  54     int dot_limit;
  55     int p2_slow, p2_fast;
  56 } intel_p2_t;
  57
  58 #define INTEL_P2_NUM                  2
  59 typedef struct intel_limit intel_limit_t;
  60 struct intel_limit {
  61     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  62     intel_p2_t      p2;
  63     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  64                       int, int, intel_clock_t *);
  65 };
  66
  67 #define I8XX_DOT_MIN              25000
  68 #define I8XX_DOT_MAX             350000
  69 #define I8XX_VCO_MIN             930000
  70 #define I8XX_VCO_MAX            1400000
  71 #define I8XX_N_MIN                    3
  72 #define I8XX_N_MAX                   16
  73 #define I8XX_M_MIN                   96
  74 #define I8XX_M_MAX                  140
  75 #define I8XX_M1_MIN                  18
  76 #define I8XX_M1_MAX                  26
  77 #define I8XX_M2_MIN                   6
  78 #define I8XX_M2_MAX                  16
  79 #define I8XX_P_MIN                    4
  80 #define I8XX_P_MAX                  128
  81 #define I8XX_P1_MIN                   2
  82 #define I8XX_P1_MAX                  33
  83 #define I8XX_P1_LVDS_MIN              1
  84 #define I8XX_P1_LVDS_MAX              6
  85 #define I8XX_P2_SLOW                  4
  86 #define I8XX_P2_FAST                  2
  87 #define I8XX_P2_LVDS_SLOW             14
  88 #define I8XX_P2_LVDS_FAST             14 /* No fast option */
  89 #define I8XX_P2_SLOW_LIMIT       165000
  90
  91 #define I9XX_DOT_MIN              20000
  92 #define I9XX_DOT_MAX             400000
  93 #define I9XX_VCO_MIN            1400000
  94 #define I9XX_VCO_MAX            2800000
  95 #define I9XX_N_MIN                    1
  96 #define I9XX_N_MAX                    6
  97 #define I9XX_M_MIN                   70
  98 #define I9XX_M_MAX                  120
  99 #define I9XX_M1_MIN                  10
 100 #define I9XX_M1_MAX                  22
 101 #define I9XX_M2_MIN                   5
 102 #define I9XX_M2_MAX                   9
 103 #define I9XX_P_SDVO_DAC_MIN           5
 104 #define I9XX_P_SDVO_DAC_MAX          80
 105 #define I9XX_P_LVDS_MIN               7
 106 #define I9XX_P_LVDS_MAX              98
 107 #define I9XX_P1_MIN                   1
 108 #define I9XX_P1_MAX                   8
 109 #define I9XX_P2_SDVO_DAC_SLOW                10
 110 #define I9XX_P2_SDVO_DAC_FAST                 5
 111 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 112 #define I9XX_P2_LVDS_SLOW                    14
 113 #define I9XX_P2_LVDS_FAST                     7
 114 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 115
 116 #define INTEL_LIMIT_I8XX_DVO_DAC    0
 117 #define INTEL_LIMIT_I8XX_LVDS       1
 118 #define INTEL_LIMIT_I9XX_SDVO_DAC   2
 119 #define INTEL_LIMIT_I9XX_LVDS       3
 120 #define INTEL_LIMIT_G4X_SDVO        4
 121 #define INTEL_LIMIT_G4X_HDMI_DAC   5
 122 #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS   6
 123 #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS   7
 124
 125 /*The parameter is for SDVO on G4x platform*/
 126 #define G4X_DOT_SDVO_MIN           25000
 127 #define G4X_DOT_SDVO_MAX           270000
 128 #define G4X_VCO_MIN                1750000
 129 #define G4X_VCO_MAX                3500000
 130 #define G4X_N_SDVO_MIN             1
 131 #define G4X_N_SDVO_MAX             4
 132 #define G4X_M_SDVO_MIN             104
 133 #define G4X_M_SDVO_MAX             138
 134 #define G4X_M1_SDVO_MIN            17
 135 #define G4X_M1_SDVO_MAX            23
 136 #define G4X_M2_SDVO_MIN            5
 137 #define G4X_M2_SDVO_MAX            11
 138 #define G4X_P_SDVO_MIN             10
 139 #define G4X_P_SDVO_MAX             30
 140 #define G4X_P1_SDVO_MIN            1
 141 #define G4X_P1_SDVO_MAX            3
 142 #define G4X_P2_SDVO_SLOW           10
 143 #define G4X_P2_SDVO_FAST           10
 144 #define G4X_P2_SDVO_LIMIT          270000
 145
 146 /*The parameter is for HDMI_DAC on G4x platform*/
 147 #define G4X_DOT_HDMI_DAC_MIN           22000
 148 #define G4X_DOT_HDMI_DAC_MAX           400000
 149 #define G4X_N_HDMI_DAC_MIN             1
 150 #define G4X_N_HDMI_DAC_MAX             4
 151 #define G4X_M_HDMI_DAC_MIN             104
 152 #define G4X_M_HDMI_DAC_MAX             138
 153 #define G4X_M1_HDMI_DAC_MIN            16
 154 #define G4X_M1_HDMI_DAC_MAX            23
 155 #define G4X_M2_HDMI_DAC_MIN            5
 156 #define G4X_M2_HDMI_DAC_MAX            11
 157 #define G4X_P_HDMI_DAC_MIN             5
 158 #define G4X_P_HDMI_DAC_MAX             80
 159 #define G4X_P1_HDMI_DAC_MIN            1
 160 #define G4X_P1_HDMI_DAC_MAX            8
 161 #define G4X_P2_HDMI_DAC_SLOW           10
 162 #define G4X_P2_HDMI_DAC_FAST           5
 163 #define G4X_P2_HDMI_DAC_LIMIT          165000
 164
 165 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 166 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 167 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 168 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 169 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 170 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 171 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 172 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 173 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 174 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 175 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 176 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 177 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 178 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 179 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 180 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 181 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 182 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 183
 184 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 185 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 186 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 187 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 188 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 189 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 190 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 191 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 192 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 193 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 194 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 195 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 196 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 197 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 198 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 199 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 200 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 201 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 202
 203 static bool
 204 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 205                     int target, int refclk, intel_clock_t *best_clock);
 206 static bool
 207 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 208                         int target, int refclk, intel_clock_t *best_clock);
 209
 210 static const intel_limit_t intel_limits[] = {
 211     { /* INTEL_LIMIT_I8XX_DVO_DAC */
 212         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 213         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 214         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 215         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 216         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 217         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 218         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 219         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 220         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 221                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 222         .find_pll = intel_find_best_PLL,
 223     },
 224     { /* INTEL_LIMIT_I8XX_LVDS */
 225         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 226         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 227         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 228         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 229         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 230         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 231         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 232         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 233         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 234                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 235         .find_pll = intel_find_best_PLL,
 236     },
 237     { /* INTEL_LIMIT_I9XX_SDVO_DAC */
 238         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 239         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 240         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 241         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 242         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 243         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 244         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 245         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 246         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 247                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 248         .find_pll = intel_find_best_PLL,
 249     },
 250     { /* INTEL_LIMIT_I9XX_LVDS */
 251         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 252         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 253         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 254         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 255         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 256         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 257         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 258         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 259         /* The single-channel range is 25-112Mhz, and dual-channel
 260          * is 80-224Mhz.  Prefer single channel as much as possible.
 261          */
 262         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 263                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 264         .find_pll = intel_find_best_PLL,
 265     },
 266     /* below parameter and function is for G4X Chipset Family*/
 267     { /* INTEL_LIMIT_G4X_SDVO */
 268         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 269         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 270         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 271         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 272         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 273         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 274         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 275         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 276         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 277                  .p2_slow = G4X_P2_SDVO_SLOW,
 278                  .p2_fast = G4X_P2_SDVO_FAST
 279         },
 280         .find_pll = intel_g4x_find_best_PLL,
 281     },
 282     { /* INTEL_LIMIT_G4X_HDMI_DAC */
 283         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 284         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 285         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 286         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 287         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 288         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 289         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 290         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 291         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 292                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 293                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 294         },
 295         .find_pll = intel_g4x_find_best_PLL,
 296     },
 297     { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
 298         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 299                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 300         .vco = { .min = G4X_VCO_MIN,
 301                  .max = G4X_VCO_MAX },
 302         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 303                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 304         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 305                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 306         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 307                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 308         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 309                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 310         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 311                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 312         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 313                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 314         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 315                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 316                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 317         },
 318         .find_pll = intel_g4x_find_best_PLL,
 319     },
 320     { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
 321         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 322                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 323         .vco = { .min = G4X_VCO_MIN,
 324                  .max = G4X_VCO_MAX },
 325         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 326                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 327         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 328                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 329         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 330                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 331         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 332                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 333         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 334                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 335         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 336                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 337         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 338                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 339                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 340         },
 341         .find_pll = intel_g4x_find_best_PLL,
 342     },
 343 };
 344
 345 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 346 {
 347         struct drm_device *dev = crtc->dev;
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         const intel_limit_t *limit;
 350
 351         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 352                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 353                     LVDS_CLKB_POWER_UP)
 354                         /* LVDS with dual channel */
 355                         limit = &intel_limits
 356                                         [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS];
 357                 else
 358                         /* LVDS with dual channel */
 359                         limit = &intel_limits
 360                                         [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS];
 361         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 362                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 363                 limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
 364         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 365                 limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
 366         } else /* The option is for other outputs */
 367                 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 368
 369         return limit;
 370 }
 371
 372 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 373 {
 374         struct drm_device *dev = crtc->dev;
 375         const intel_limit_t *limit;
 376
 377         if (IS_G4X(dev)) {
 378                 limit = intel_g4x_limit(crtc);
 379         } else if (IS_I9XX(dev)) {
 380                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 381                         limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
 382                 else
 383                         limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 384         } else {
 385                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 386                         limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
 387                 else
 388                         limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
 389         }
 390         return limit;
 391 }
 392
 393 static void intel_clock(int refclk, intel_clock_t *clock)
 394 {
 395         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 396         clock->p = clock->p1 * clock->p2;
 397         clock->vco = refclk * clock->m / (clock->n + 2);
 398         clock->dot = clock->vco / clock->p;
 399 }
 400
 401 /**
 402  * Returns whether any output on the specified pipe is of the specified type
 403  */
 404 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 405 {
 406     struct drm_device *dev = crtc->dev;
 407     struct drm_mode_config *mode_config = &dev->mode_config;
 408     struct drm_connector *l_entry;
 409
 410     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 411             if (l_entry->encoder &&
 412                 l_entry->encoder->crtc == crtc) {
 413                     struct intel_output *intel_output = to_intel_output(l_entry);
 414                     if (intel_output->type == type)
 415                             return true;
 416             }
 417     }
 418     return false;
 419 }
 420
 421 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 422 /**
 423  * Returns whether the given set of divisors are valid for a given refclk with
 424  * the given connectors.
 425  */
 426
 427 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 428 {
 429         const intel_limit_t *limit = intel_limit (crtc);
 430
 431         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 432                 INTELPllInvalid ("p1 out of range\n");
 433         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 434                 INTELPllInvalid ("p out of range\n");
 435         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 436                 INTELPllInvalid ("m2 out of range\n");
 437         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 438                 INTELPllInvalid ("m1 out of range\n");
 439         if (clock->m1 <= clock->m2)
 440                 INTELPllInvalid ("m1 <= m2\n");
 441         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 442                 INTELPllInvalid ("m out of range\n");
 443         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 444                 INTELPllInvalid ("n out of range\n");
 445         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 446                 INTELPllInvalid ("vco out of range\n");
 447         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 448          * connector, etc., rather than just a single range.
 449          */
 450         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 451                 INTELPllInvalid ("dot out of range\n");
 452
 453         return true;
 454 }
 455
 456 static bool
 457 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 458                     int target, int refclk, intel_clock_t *best_clock)
 459
 460 {
 461         struct drm_device *dev = crtc->dev;
 462         struct drm_i915_private *dev_priv = dev->dev_private;
 463         intel_clock_t clock;
 464         int err = target;
 465
 466         if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 467             (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
 468                 /*
 469                  * For LVDS, if the panel is on, just rely on its current
 470                  * settings for dual-channel.  We haven't figured out how to
 471                  * reliably set up different single/dual channel state, if we
 472                  * even can.
 473                  */
 474                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 475                     LVDS_CLKB_POWER_UP)
 476                         clock.p2 = limit->p2.p2_fast;
 477                 else
 478                         clock.p2 = limit->p2.p2_slow;
 479         } else {
 480                 if (target < limit->p2.dot_limit)
 481                         clock.p2 = limit->p2.p2_slow;
 482                 else
 483                         clock.p2 = limit->p2.p2_fast;
 484         }
 485
 486         memset (best_clock, 0, sizeof (*best_clock));
 487
 488         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 489                 for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 &&
 490                              clock.m2 <= limit->m2.max; clock.m2++) {
 491                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 492                              clock.n++) {
 493                                 for (clock.p1 = limit->p1.min;
 494                                      clock.p1 <= limit->p1.max; clock.p1++) {
 495                                         int this_err;
 496
 497                                         intel_clock(refclk, &clock);
 498
 499                                         if (!intel_PLL_is_valid(crtc, &clock))
 500                                                 continue;
 501
 502                                         this_err = abs(clock.dot - target);
 503                                         if (this_err < err) {
 504                                                 *best_clock = clock;
 505                                                 err = this_err;
 506                                         }
 507                                 }
 508                         }
 509                 }
 510         }
 511
 512         return (err != target);
 513 }
 514
 515 static bool
 516 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 517                         int target, int refclk, intel_clock_t *best_clock)
 518 {
 519         struct drm_device *dev = crtc->dev;
 520         struct drm_i915_private *dev_priv = dev->dev_private;
 521         intel_clock_t clock;
 522         int max_n;
 523         bool found;
 524         /* approximately equals target * 0.00488 */
 525         int err_most = (target >> 8) + (target >> 10);
 526         found = false;
 527
 528         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 529                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 530                     LVDS_CLKB_POWER_UP)
 531                         clock.p2 = limit->p2.p2_fast;
 532                 else
 533                         clock.p2 = limit->p2.p2_slow;
 534         } else {
 535                 if (target < limit->p2.dot_limit)
 536                         clock.p2 = limit->p2.p2_slow;
 537                 else
 538                         clock.p2 = limit->p2.p2_fast;
 539         }
 540
 541         memset(best_clock, 0, sizeof(*best_clock));
 542         max_n = limit->n.max;
 543         /* based on hardware requriment prefer smaller n to precision */
 544         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 545                 /* based on hardware requirment prefere larger m1,m2, p1 */
 546                 for (clock.m1 = limit->m1.max;
 547                      clock.m1 >= limit->m1.min; clock.m1--) {
 548                         for (clock.m2 = limit->m2.max;
 549                              clock.m2 >= limit->m2.min; clock.m2--) {
 550                                 for (clock.p1 = limit->p1.max;
 551                                      clock.p1 >= limit->p1.min; clock.p1--) {
 552                                         int this_err;
 553
 554                                         intel_clock(refclk, &clock);
 555                                         if (!intel_PLL_is_valid(crtc, &clock))
 556                                                 continue;
 557                                         this_err = abs(clock.dot - target) ;
 558                                         if (this_err < err_most) {
 559                                                 *best_clock = clock;
 560                                                 err_most = this_err;
 561                                                 max_n = clock.n;
 562                                                 found = true;
 563                                         }
 564                                 }
 565                         }
 566                 }
 567         }
 568
 569         return found;
 570 }
 571
 572 void
 573 intel_wait_for_vblank(struct drm_device *dev)
 574 {
 575         /* Wait for 20ms, i.e. one cycle at 50hz. */
 576         udelay(20000);
 577 }
 578
 579 static int
 580 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 581                     struct drm_framebuffer *old_fb)
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         struct drm_i915_private *dev_priv = dev->dev_private;
 585         struct drm_i915_master_private *master_priv;
 586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 587         struct intel_framebuffer *intel_fb;
 588         struct drm_i915_gem_object *obj_priv;
 589         struct drm_gem_object *obj;
 590         int pipe = intel_crtc->pipe;
 591         unsigned long Start, Offset;
 592         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 593         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 594         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 595         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 596         u32 dspcntr, alignment;
 597         int ret;
 598
 599         /* no fb bound */
 600         if (!crtc->fb) {
 601                 DRM_DEBUG("No FB bound\n");
 602                 return 0;
 603         }
 604
 605         switch (pipe) {
 606         case 0:
 607         case 1:
 608                 break;
 609         default:
 610                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 611                 return -EINVAL;
 612         }
 613
 614         intel_fb = to_intel_framebuffer(crtc->fb);
 615         obj = intel_fb->obj;
 616         obj_priv = obj->driver_private;
 617
 618         switch (obj_priv->tiling_mode) {
 619         case I915_TILING_NONE:
 620                 alignment = 64 * 1024;
 621                 break;
 622         case I915_TILING_X:
 623                 /* pin() will align the object as required by fence */
 624                 alignment = 0;
 625                 break;
 626         case I915_TILING_Y:
 627                 /* FIXME: Is this true? */
 628                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 629                 return -EINVAL;
 630         default:
 631                 BUG();
 632         }
 633
 634         mutex_lock(&dev->struct_mutex);
 635         ret = i915_gem_object_pin(intel_fb->obj, alignment);
 636         if (ret != 0) {
 637                 mutex_unlock(&dev->struct_mutex);
 638                 return ret;
 639         }
 640
 641         ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
 642         if (ret != 0) {
 643                 i915_gem_object_unpin(intel_fb->obj);
 644                 mutex_unlock(&dev->struct_mutex);
 645                 return ret;
 646         }
 647
 648         dspcntr = I915_READ(dspcntr_reg);
 649         /* Mask out pixel format bits in case we change it */
 650         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 651         switch (crtc->fb->bits_per_pixel) {
 652         case 8:
 653                 dspcntr |= DISPPLANE_8BPP;
 654                 break;
 655         case 16:
 656                 if (crtc->fb->depth == 15)
 657                         dspcntr |= DISPPLANE_15_16BPP;
 658                 else
 659                         dspcntr |= DISPPLANE_16BPP;
 660                 break;
 661         case 24:
 662         case 32:
 663                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 664                 break;
 665         default:
 666                 DRM_ERROR("Unknown color depth\n");
 667                 i915_gem_object_unpin(intel_fb->obj);
 668                 mutex_unlock(&dev->struct_mutex);
 669                 return -EINVAL;
 670         }
 671         I915_WRITE(dspcntr_reg, dspcntr);
 672
 673         Start = obj_priv->gtt_offset;
 674         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 675
 676         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 677         I915_WRITE(dspstride, crtc->fb->pitch);
 678         if (IS_I965G(dev)) {
 679                 I915_WRITE(dspbase, Offset);
 680                 I915_READ(dspbase);
 681                 I915_WRITE(dspsurf, Start);
 682                 I915_READ(dspsurf);
 683         } else {
 684                 I915_WRITE(dspbase, Start + Offset);
 685                 I915_READ(dspbase);
 686         }
 687
 688         intel_wait_for_vblank(dev);
 689
 690         if (old_fb) {
 691                 intel_fb = to_intel_framebuffer(old_fb);
 692                 i915_gem_object_unpin(intel_fb->obj);
 693         }
 694         mutex_unlock(&dev->struct_mutex);
 695
 696         if (!dev->primary->master)
 697                 return 0;
 698
 699         master_priv = dev->primary->master->driver_priv;
 700         if (!master_priv->sarea_priv)
 701                 return 0;
 702
 703         if (pipe) {
 704                 master_priv->sarea_priv->pipeB_x = x;
 705                 master_priv->sarea_priv->pipeB_y = y;
 706         } else {
 707                 master_priv->sarea_priv->pipeA_x = x;
 708                 master_priv->sarea_priv->pipeA_y = y;
 709         }
 710
 711         return 0;
 712 }
 713
 714
 715
 716 /**
 717  * Sets the power management mode of the pipe and plane.
 718  *
 719  * This code should probably grow support for turning the cursor off and back
 720  * on appropriately at the same time as we're turning the pipe off/on.
 721  */
 722 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 723 {
 724         struct drm_device *dev = crtc->dev;
 725         struct drm_i915_master_private *master_priv;
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728         int pipe = intel_crtc->pipe;
 729         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
 730         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 731         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
 732         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 733         u32 temp;
 734         bool enabled;
 735
 736         /* XXX: When our outputs are all unaware of DPMS modes other than off
 737          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 738          */
 739         switch (mode) {
 740         case DRM_MODE_DPMS_ON:
 741         case DRM_MODE_DPMS_STANDBY:
 742         case DRM_MODE_DPMS_SUSPEND:
 743                 /* Enable the DPLL */
 744                 temp = I915_READ(dpll_reg);
 745                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 746                         I915_WRITE(dpll_reg, temp);
 747                         I915_READ(dpll_reg);
 748                         /* Wait for the clocks to stabilize. */
 749                         udelay(150);
 750                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 751                         I915_READ(dpll_reg);
 752                         /* Wait for the clocks to stabilize. */
 753                         udelay(150);
 754                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 755                         I915_READ(dpll_reg);
 756                         /* Wait for the clocks to stabilize. */
 757                         udelay(150);
 758                 }
 759
 760                 /* Enable the pipe */
 761                 temp = I915_READ(pipeconf_reg);
 762                 if ((temp & PIPEACONF_ENABLE) == 0)
 763                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
 764
 765                 /* Enable the plane */
 766                 temp = I915_READ(dspcntr_reg);
 767                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 768                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
 769                         /* Flush the plane changes */
 770                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
 771                 }
 772
 773                 intel_crtc_load_lut(crtc);
 774
 775                 /* Give the overlay scaler a chance to enable if it's on this pipe */
 776                 //intel_crtc_dpms_video(crtc, true); TODO
 777         break;
 778         case DRM_MODE_DPMS_OFF:
 779                 /* Give the overlay scaler a chance to disable if it's on this pipe */
 780                 //intel_crtc_dpms_video(crtc, FALSE); TODO
 781
 782                 /* Disable the VGA plane that we never use */
 783                 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 784
 785                 /* Disable display plane */
 786                 temp = I915_READ(dspcntr_reg);
 787                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 788                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
 789                         /* Flush the plane changes */
 790                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
 791                         I915_READ(dspbase_reg);
 792                 }
 793
 794                 if (!IS_I9XX(dev)) {
 795                         /* Wait for vblank for the disable to take effect */
 796                         intel_wait_for_vblank(dev);
 797                 }
 798
 799                 /* Next, disable display pipes */
 800                 temp = I915_READ(pipeconf_reg);
 801                 if ((temp & PIPEACONF_ENABLE) != 0) {
 802                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
 803                         I915_READ(pipeconf_reg);
 804                 }
 805
 806                 /* Wait for vblank for the disable to take effect. */
 807                 intel_wait_for_vblank(dev);
 808
 809                 temp = I915_READ(dpll_reg);
 810                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 811                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
 812                         I915_READ(dpll_reg);
 813                 }
 814
 815                 /* Wait for the clocks to turn off. */
 816                 udelay(150);
 817                 break;
 818         }
 819
 820         if (!dev->primary->master)
 821                 return;
 822
 823         master_priv = dev->primary->master->driver_priv;
 824         if (!master_priv->sarea_priv)
 825                 return;
 826
 827         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
 828
 829         switch (pipe) {
 830         case 0:
 831                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
 832                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
 833                 break;
 834         case 1:
 835                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
 836                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
 837                 break;
 838         default:
 839                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 840                 break;
 841         }
 842
 843         intel_crtc->dpms_mode = mode;
 844 }
 845
 846 static void intel_crtc_prepare (struct drm_crtc *crtc)
 847 {
 848         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 849         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 850 }
 851
 852 static void intel_crtc_commit (struct drm_crtc *crtc)
 853 {
 854         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 855         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 856 }
 857
 858 void intel_encoder_prepare (struct drm_encoder *encoder)
 859 {
 860         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 861         /* lvds has its own version of prepare see intel_lvds_prepare */
 862         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
 863 }
 864
 865 void intel_encoder_commit (struct drm_encoder *encoder)
 866 {
 867         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 868         /* lvds has its own version of commit see intel_lvds_commit */
 869         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 870 }
 871
 872 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
 873                                   struct drm_display_mode *mode,
 874                                   struct drm_display_mode *adjusted_mode)
 875 {
 876         return true;
 877 }
 878
 879
 880 /** Returns the core display clock speed for i830 - i945 */
 881 static int intel_get_core_clock_speed(struct drm_device *dev)
 882 {
 883
 884         /* Core clock values taken from the published datasheets.
 885          * The 830 may go up to 166 Mhz, which we should check.
 886          */
 887         if (IS_I945G(dev))
 888                 return 400000;
 889         else if (IS_I915G(dev))
 890                 return 333000;
 891         else if (IS_I945GM(dev) || IS_845G(dev))
 892                 return 200000;
 893         else if (IS_I915GM(dev)) {
 894                 u16 gcfgc = 0;
 895
 896                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
 897
 898                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
 899                         return 133000;
 900                 else {
 901                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 902                         case GC_DISPLAY_CLOCK_333_MHZ:
 903                                 return 333000;
 904                         default:
 905                         case GC_DISPLAY_CLOCK_190_200_MHZ:
 906                                 return 190000;
 907                         }
 908                 }
 909         } else if (IS_I865G(dev))
 910                 return 266000;
 911         else if (IS_I855(dev)) {
 912                 u16 hpllcc = 0;
 913                 /* Assume that the hardware is in the high speed state.  This
 914                  * should be the default.
 915                  */
 916                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 917                 case GC_CLOCK_133_200:
 918                 case GC_CLOCK_100_200:
 919                         return 200000;
 920                 case GC_CLOCK_166_250:
 921                         return 250000;
 922                 case GC_CLOCK_100_133:
 923                         return 133000;
 924                 }
 925         } else /* 852, 830 */
 926                 return 133000;
 927
 928         return 0; /* Silence gcc warning */
 929 }
 930
 931
 932 /**
 933  * Return the pipe currently connected to the panel fitter,
 934  * or -1 if the panel fitter is not present or not in use
 935  */
 936 static int intel_panel_fitter_pipe (struct drm_device *dev)
 937 {
 938         struct drm_i915_private *dev_priv = dev->dev_private;
 939         u32  pfit_control;
 940
 941         /* i830 doesn't have a panel fitter */
 942         if (IS_I830(dev))
 943                 return -1;
 944
 945         pfit_control = I915_READ(PFIT_CONTROL);
 946
 947         /* See if the panel fitter is in use */
 948         if ((pfit_control & PFIT_ENABLE) == 0)
 949                 return -1;
 950
 951         /* 965 can place panel fitter on either pipe */
 952         if (IS_I965G(dev))
 953                 return (pfit_control >> 29) & 0x3;
 954
 955         /* older chips can only use pipe 1 */
 956         return 1;
 957 }
 958
 959 static int intel_crtc_mode_set(struct drm_crtc *crtc,
 960                                struct drm_display_mode *mode,
 961                                struct drm_display_mode *adjusted_mode,
 962                                int x, int y,
 963                                struct drm_framebuffer *old_fb)
 964 {
 965         struct drm_device *dev = crtc->dev;
 966         struct drm_i915_private *dev_priv = dev->dev_private;
 967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 968         int pipe = intel_crtc->pipe;
 969         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
 970         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
 971         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
 972         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 973         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 974         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
 975         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
 976         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
 977         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
 978         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
 979         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
 980         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
 981         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
 982         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
 983         int refclk, num_outputs = 0;
 984         intel_clock_t clock;
 985         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
 986         bool ok, is_sdvo = false, is_dvo = false;
 987         bool is_crt = false, is_lvds = false, is_tv = false;
 988         struct drm_mode_config *mode_config = &dev->mode_config;
 989         struct drm_connector *connector;
 990         const intel_limit_t *limit;
 991         int ret;
 992
 993         drm_vblank_pre_modeset(dev, pipe);
 994
 995         list_for_each_entry(connector, &mode_config->connector_list, head) {
 996                 struct intel_output *intel_output = to_intel_output(connector);
 997
 998                 if (!connector->encoder || connector->encoder->crtc != crtc)
 999                         continue;
1000
1001                 switch (intel_output->type) {
1002                 case INTEL_OUTPUT_LVDS:
1003                         is_lvds = true;
1004                         break;
1005                 case INTEL_OUTPUT_SDVO:
1006                 case INTEL_OUTPUT_HDMI:
1007                         is_sdvo = true;
1008                         if (intel_output->needs_tv_clock)
1009                                 is_tv = true;
1010                         break;
1011                 case INTEL_OUTPUT_DVO:
1012                         is_dvo = true;
1013                         break;
1014                 case INTEL_OUTPUT_TVOUT:
1015                         is_tv = true;
1016                         break;
1017                 case INTEL_OUTPUT_ANALOG:
1018                         is_crt = true;
1019                         break;
1020                 }
1021
1022                 num_outputs++;
1023         }
1024
1025         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
1026                 refclk = dev_priv->lvds_ssc_freq * 1000;
1027                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
1028         } else if (IS_I9XX(dev)) {
1029                 refclk = 96000;
1030         } else {
1031                 refclk = 48000;
1032         }
1033
1034         /*
1035          * Returns a set of divisors for the desired target clock with the given
1036          * refclk, or FALSE.  The returned values represent the clock equation:
1037          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
1038          */
1039         limit = intel_limit(crtc);
1040         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
1041         if (!ok) {
1042                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
1043                 return -EINVAL;
1044         }
1045
1046         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
1047
1048         dpll = DPLL_VGA_MODE_DIS;
1049         if (IS_I9XX(dev)) {
1050                 if (is_lvds)
1051                         dpll |= DPLLB_MODE_LVDS;
1052                 else
1053                         dpll |= DPLLB_MODE_DAC_SERIAL;
1054                 if (is_sdvo) {
1055                         dpll |= DPLL_DVO_HIGH_SPEED;
1056                         if (IS_I945G(dev) || IS_I945GM(dev)) {
1057                                 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1058                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1059                         }
1060                 }
1061
1062                 /* compute bitmask from p1 value */
1063                 dpll |= (1 << (clock.p1 - 1)) << 16;
1064                 switch (clock.p2) {
1065                 case 5:
1066                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1067                         break;
1068                 case 7:
1069                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1070                         break;
1071                 case 10:
1072                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1073                         break;
1074                 case 14:
1075                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1076                         break;
1077                 }
1078                 if (IS_I965G(dev))
1079                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1080         } else {
1081                 if (is_lvds) {
1082                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1083                 } else {
1084                         if (clock.p1 == 2)
1085                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
1086                         else
1087                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1088                         if (clock.p2 == 4)
1089                                 dpll |= PLL_P2_DIVIDE_BY_4;
1090                 }
1091         }
1092
1093         if (is_sdvo && is_tv)
1094                 dpll |= PLL_REF_INPUT_TVCLKINBC;
1095         else if (is_tv)
1096                 /* XXX: just matching BIOS for now */
1097                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
1098                 dpll |= 3;
1099         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
1100                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1101         else
1102                 dpll |= PLL_REF_INPUT_DREFCLK;
1103
1104         /* setup pipeconf */
1105         pipeconf = I915_READ(pipeconf_reg);
1106
1107         /* Set up the display plane register */
1108         dspcntr = DISPPLANE_GAMMA_ENABLE;
1109
1110         if (pipe == 0)
1111                 dspcntr |= DISPPLANE_SEL_PIPE_A;
1112         else
1113                 dspcntr |= DISPPLANE_SEL_PIPE_B;
1114
1115         if (pipe == 0 && !IS_I965G(dev)) {
1116                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
1117                  * core speed.
1118                  *
1119                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
1120                  * pipe == 0 check?
1121                  */
1122                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
1123                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
1124                 else
1125                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
1126         }
1127
1128         dspcntr |= DISPLAY_PLANE_ENABLE;
1129         pipeconf |= PIPEACONF_ENABLE;
1130         dpll |= DPLL_VCO_ENABLE;
1131
1132
1133         /* Disable the panel fitter if it was on our pipe */
1134         if (intel_panel_fitter_pipe(dev) == pipe)
1135                 I915_WRITE(PFIT_CONTROL, 0);
1136
1137         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1138         drm_mode_debug_printmodeline(mode);
1139
1140
1141         if (dpll & DPLL_VCO_ENABLE) {
1142                 I915_WRITE(fp_reg, fp);
1143                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
1144                 I915_READ(dpll_reg);
1145                 udelay(150);
1146         }
1147
1148         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1149          * This is an exception to the general rule that mode_set doesn't turn
1150          * things on.
1151          */
1152         if (is_lvds) {
1153                 u32 lvds = I915_READ(LVDS);
1154
1155                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
1156                 /* Set the B0-B3 data pairs corresponding to whether we're going to
1157                  * set the DPLLs for dual-channel mode or not.
1158                  */
1159                 if (clock.p2 == 7)
1160                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1161                 else
1162                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1163
1164                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1165                  * appropriately here, but we need to look more thoroughly into how
1166                  * panels behave in the two modes.
1167                  */
1168
1169                 I915_WRITE(LVDS, lvds);
1170                 I915_READ(LVDS);
1171         }
1172
1173         I915_WRITE(fp_reg, fp);
1174         I915_WRITE(dpll_reg, dpll);
1175         I915_READ(dpll_reg);
1176         /* Wait for the clocks to stabilize. */
1177         udelay(150);
1178
1179         if (IS_I965G(dev)) {
1180                 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1181                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
1182                            ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1183         } else {
1184                 /* write it again -- the BIOS does, after all */
1185                 I915_WRITE(dpll_reg, dpll);
1186         }
1187         I915_READ(dpll_reg);
1188         /* Wait for the clocks to stabilize. */
1189         udelay(150);
1190
1191         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
1192                    ((adjusted_mode->crtc_htotal - 1) << 16));
1193         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
1194                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
1195         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
1196                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
1197         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
1198                    ((adjusted_mode->crtc_vtotal - 1) << 16));
1199         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
1200                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
1201         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
1202                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
1203         /* pipesrc and dspsize control the size that is scaled from, which should
1204          * always be the user's requested size.
1205          */
1206         I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
1207         I915_WRITE(dsppos_reg, 0);
1208         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1209         I915_WRITE(pipeconf_reg, pipeconf);
1210         I915_READ(pipeconf_reg);
1211
1212         intel_wait_for_vblank(dev);
1213
1214         I915_WRITE(dspcntr_reg, dspcntr);
1215
1216         /* Flush the plane changes */
1217         ret = intel_pipe_set_base(crtc, x, y, old_fb);
1218         if (ret != 0)
1219             return ret;
1220
1221         drm_vblank_post_modeset(dev, pipe);
1222
1223         return 0;
1224 }
1225
1226 /** Loads the palette/gamma unit for the CRTC with the prepared values */
1227 void intel_crtc_load_lut(struct drm_crtc *crtc)
1228 {
1229         struct drm_device *dev = crtc->dev;
1230         struct drm_i915_private *dev_priv = dev->dev_private;
1231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1232         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
1233         int i;
1234
1235         /* The clocks have to be on to load the palette. */
1236         if (!crtc->enabled)
1237                 return;
1238
1239         for (i = 0; i < 256; i++) {
1240                 I915_WRITE(palreg + 4 * i,
1241                            (intel_crtc->lut_r[i] << 16) |
1242                            (intel_crtc->lut_g[i] << 8) |
1243                            intel_crtc->lut_b[i]);
1244         }
1245 }
1246
1247 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
1248                                  struct drm_file *file_priv,
1249                                  uint32_t handle,
1250                                  uint32_t width, uint32_t height)
1251 {
1252         struct drm_device *dev = crtc->dev;
1253         struct drm_i915_private *dev_priv = dev->dev_private;
1254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1255         struct drm_gem_object *bo;
1256         struct drm_i915_gem_object *obj_priv;
1257         int pipe = intel_crtc->pipe;
1258         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1259         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1260         uint32_t temp;
1261         size_t addr;
1262         int ret;
1263
1264         DRM_DEBUG("\n");
1265
1266         /* if we want to turn off the cursor ignore width and height */
1267         if (!handle) {
1268                 DRM_DEBUG("cursor off\n");
1269                 temp = CURSOR_MODE_DISABLE;
1270                 addr = 0;
1271                 bo = NULL;
1272                 mutex_lock(&dev->struct_mutex);
1273                 goto finish;
1274         }
1275
1276         /* Currently we only support 64x64 cursors */
1277         if (width != 64 || height != 64) {
1278                 DRM_ERROR("we currently only support 64x64 cursors\n");
1279                 return -EINVAL;
1280         }
1281
1282         bo = drm_gem_object_lookup(dev, file_priv, handle);
1283         if (!bo)
1284                 return -ENOENT;
1285
1286         obj_priv = bo->driver_private;
1287
1288         if (bo->size < width * height * 4) {
1289                 DRM_ERROR("buffer is to small\n");
1290                 ret = -ENOMEM;
1291                 goto fail;
1292         }
1293
1294         /* we only need to pin inside GTT if cursor is non-phy */
1295         mutex_lock(&dev->struct_mutex);
1296         if (!dev_priv->cursor_needs_physical) {
1297                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
1298                 if (ret) {
1299                         DRM_ERROR("failed to pin cursor bo\n");
1300                         goto fail_locked;
1301                 }
1302                 addr = obj_priv->gtt_offset;
1303         } else {
1304                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
1305                 if (ret) {
1306                         DRM_ERROR("failed to attach phys object\n");
1307                         goto fail_locked;
1308                 }
1309                 addr = obj_priv->phys_obj->handle->busaddr;
1310         }
1311
1312         temp = 0;
1313         /* set the pipe for the cursor */
1314         temp |= (pipe << 28);
1315         temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1316
1317  finish:
1318         I915_WRITE(control, temp);
1319         I915_WRITE(base, addr);
1320
1321         if (intel_crtc->cursor_bo) {
1322                 if (dev_priv->cursor_needs_physical) {
1323                         if (intel_crtc->cursor_bo != bo)
1324                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
1325                 } else
1326                         i915_gem_object_unpin(intel_crtc->cursor_bo);
1327                 drm_gem_object_unreference(intel_crtc->cursor_bo);
1328         }
1329         mutex_unlock(&dev->struct_mutex);
1330
1331         intel_crtc->cursor_addr = addr;
1332         intel_crtc->cursor_bo = bo;
1333
1334         return 0;
1335 fail:
1336         mutex_lock(&dev->struct_mutex);
1337 fail_locked:
1338         drm_gem_object_unreference(bo);
1339         mutex_unlock(&dev->struct_mutex);
1340         return ret;
1341 }
1342
1343 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1344 {
1345         struct drm_device *dev = crtc->dev;
1346         struct drm_i915_private *dev_priv = dev->dev_private;
1347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1348         int pipe = intel_crtc->pipe;
1349         uint32_t temp = 0;
1350         uint32_t adder;
1351
1352         if (x < 0) {
1353                 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1354                 x = -x;
1355         }
1356         if (y < 0) {
1357                 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1358                 y = -y;
1359         }
1360
1361         temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1362         temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1363
1364         adder = intel_crtc->cursor_addr;
1365         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1366         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1367
1368         return 0;
1369 }
1370
1371 /** Sets the color ramps on behalf of RandR */
1372 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1373                                  u16 blue, int regno)
1374 {
1375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1376
1377         intel_crtc->lut_r[regno] = red >> 8;
1378         intel_crtc->lut_g[regno] = green >> 8;
1379         intel_crtc->lut_b[regno] = blue >> 8;
1380 }
1381
1382 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1383                                  u16 *blue, uint32_t size)
1384 {
1385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1386         int i;
1387
1388         if (size != 256)
1389                 return;
1390
1391         for (i = 0; i < 256; i++) {
1392                 intel_crtc->lut_r[i] = red[i] >> 8;
1393                 intel_crtc->lut_g[i] = green[i] >> 8;
1394                 intel_crtc->lut_b[i] = blue[i] >> 8;
1395         }
1396
1397         intel_crtc_load_lut(crtc);
1398 }
1399
1400 /**
1401  * Get a pipe with a simple mode set on it for doing load-based monitor
1402  * detection.
1403  *
1404  * It will be up to the load-detect code to adjust the pipe as appropriate for
1405  * its requirements.  The pipe will be connected to no other outputs.
1406  *
1407  * Currently this code will only succeed if there is a pipe with no outputs
1408  * configured for it.  In the future, it could choose to temporarily disable
1409  * some outputs to free up a pipe for its use.
1410  *
1411  * \return crtc, or NULL if no pipes are available.
1412  */
1413
1414 /* VESA 640x480x72Hz mode to set on the pipe */
1415 static struct drm_display_mode load_detect_mode = {
1416         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
1417                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1418 };
1419
1420 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
1421                                             struct drm_display_mode *mode,
1422                                             int *dpms_mode)
1423 {
1424         struct intel_crtc *intel_crtc;
1425         struct drm_crtc *possible_crtc;
1426         struct drm_crtc *supported_crtc =NULL;
1427         struct drm_encoder *encoder = &intel_output->enc;
1428         struct drm_crtc *crtc = NULL;
1429         struct drm_device *dev = encoder->dev;
1430         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1431         struct drm_crtc_helper_funcs *crtc_funcs;
1432         int i = -1;
1433
1434         /*
1435          * Algorithm gets a little messy:
1436          *   - if the connector already has an assigned crtc, use it (but make
1437          *     sure it's on first)
1438          *   - try to find the first unused crtc that can drive this connector,
1439          *     and use that if we find one
1440          *   - if there are no unused crtcs available, try to use the first
1441          *     one we found that supports the connector
1442          */
1443
1444         /* See if we already have a CRTC for this connector */
1445         if (encoder->crtc) {
1446                 crtc = encoder->crtc;
1447                 /* Make sure the crtc and connector are running */
1448                 intel_crtc = to_intel_crtc(crtc);
1449                 *dpms_mode = intel_crtc->dpms_mode;
1450                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1451                         crtc_funcs = crtc->helper_private;
1452                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1453                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1454                 }
1455                 return crtc;
1456         }
1457
1458         /* Find an unused one (if possible) */
1459         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
1460                 i++;
1461                 if (!(encoder->possible_crtcs & (1 << i)))
1462                         continue;
1463                 if (!possible_crtc->enabled) {
1464                         crtc = possible_crtc;
1465                         break;
1466                 }
1467                 if (!supported_crtc)
1468                         supported_crtc = possible_crtc;
1469         }
1470
1471         /*
1472          * If we didn't find an unused CRTC, don't use any.
1473          */
1474         if (!crtc) {
1475                 return NULL;
1476         }
1477
1478         encoder->crtc = crtc;
1479         intel_output->load_detect_temp = true;
1480
1481         intel_crtc = to_intel_crtc(crtc);
1482         *dpms_mode = intel_crtc->dpms_mode;
1483
1484         if (!crtc->enabled) {
1485                 if (!mode)
1486                         mode = &load_detect_mode;
1487                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
1488         } else {
1489                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1490                         crtc_funcs = crtc->helper_private;
1491                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1492                 }
1493
1494                 /* Add this connector to the crtc */
1495                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
1496                 encoder_funcs->commit(encoder);
1497         }
1498         /* let the connector get through one full cycle before testing */
1499         intel_wait_for_vblank(dev);
1500
1501         return crtc;
1502 }
1503
1504 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
1505 {
1506         struct drm_encoder *encoder = &intel_output->enc;
1507         struct drm_device *dev = encoder->dev;
1508         struct drm_crtc *crtc = encoder->crtc;
1509         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1510         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1511
1512         if (intel_output->load_detect_temp) {
1513                 encoder->crtc = NULL;
1514                 intel_output->load_detect_temp = false;
1515                 crtc->enabled = drm_helper_crtc_in_use(crtc);
1516                 drm_helper_disable_unused_functions(dev);
1517         }
1518
1519         /* Switch crtc and output back off if necessary */
1520         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
1521                 if (encoder->crtc == crtc)
1522                         encoder_funcs->dpms(encoder, dpms_mode);
1523                 crtc_funcs->dpms(crtc, dpms_mode);
1524         }
1525 }
1526
1527 /* Returns the clock of the currently programmed mode of the given pipe. */
1528 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1529 {
1530         struct drm_i915_private *dev_priv = dev->dev_private;
1531         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1532         int pipe = intel_crtc->pipe;
1533         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
1534         u32 fp;
1535         intel_clock_t clock;
1536
1537         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1538                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
1539         else
1540                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
1541
1542         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1543         clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1544         clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1545         if (IS_I9XX(dev)) {
1546                 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
1547                                DPLL_FPA01_P1_POST_DIV_SHIFT);
1548
1549                 switch (dpll & DPLL_MODE_MASK) {
1550                 case DPLLB_MODE_DAC_SERIAL:
1551                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
1552                                 5 : 10;
1553                         break;
1554                 case DPLLB_MODE_LVDS:
1555                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
1556                                 7 : 14;
1557                         break;
1558                 default:
1559                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1560                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
1561                         return 0;
1562                 }
1563
1564                 /* XXX: Handle the 100Mhz refclk */
1565                 intel_clock(96000, &clock);
1566         } else {
1567                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
1568
1569                 if (is_lvds) {
1570                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1571                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
1572                         clock.p2 = 14;
1573
1574                         if ((dpll & PLL_REF_INPUT_MASK) ==
1575                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1576                                 /* XXX: might not be 66MHz */
1577                                 intel_clock(66000, &clock);
1578                         } else
1579                                 intel_clock(48000, &clock);
1580                 } else {
1581                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
1582                                 clock.p1 = 2;
1583                         else {
1584                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1585                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1586                         }
1587                         if (dpll & PLL_P2_DIVIDE_BY_4)
1588                                 clock.p2 = 4;
1589                         else
1590                                 clock.p2 = 2;
1591
1592                         intel_clock(48000, &clock);
1593                 }
1594         }
1595
1596         /* XXX: It would be nice to validate the clocks, but we can't reuse
1597          * i830PllIsValid() because it relies on the xf86_config connector
1598          * configuration being accurate, which it isn't necessarily.
1599          */
1600
1601         return clock.dot;
1602 }
1603
1604 /** Returns the currently programmed mode of the given pipe. */
1605 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1606                                              struct drm_crtc *crtc)
1607 {
1608         struct drm_i915_private *dev_priv = dev->dev_private;
1609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1610         int pipe = intel_crtc->pipe;
1611         struct drm_display_mode *mode;
1612         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1613         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1614         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1615         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1616
1617         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1618         if (!mode)
1619                 return NULL;
1620
1621         mode->clock = intel_crtc_clock_get(dev, crtc);
1622         mode->hdisplay = (htot & 0xffff) + 1;
1623         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1624         mode->hsync_start = (hsync & 0xffff) + 1;
1625         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1626         mode->vdisplay = (vtot & 0xffff) + 1;
1627         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1628         mode->vsync_start = (vsync & 0xffff) + 1;
1629         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1630
1631         drm_mode_set_name(mode);
1632         drm_mode_set_crtcinfo(mode, 0);
1633
1634         return mode;
1635 }
1636
1637 static void intel_crtc_destroy(struct drm_crtc *crtc)
1638 {
1639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1640
1641         drm_crtc_cleanup(crtc);
1642         kfree(intel_crtc);
1643 }
1644
1645 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
1646         .dpms = intel_crtc_dpms,
1647         .mode_fixup = intel_crtc_mode_fixup,
1648         .mode_set = intel_crtc_mode_set,
1649         .mode_set_base = intel_pipe_set_base,
1650         .prepare = intel_crtc_prepare,
1651         .commit = intel_crtc_commit,
1652 };
1653
1654 static const struct drm_crtc_funcs intel_crtc_funcs = {
1655         .cursor_set = intel_crtc_cursor_set,
1656         .cursor_move = intel_crtc_cursor_move,
1657         .gamma_set = intel_crtc_gamma_set,
1658         .set_config = drm_crtc_helper_set_config,
1659         .destroy = intel_crtc_destroy,
1660 };
1661
1662
1663 static void intel_crtc_init(struct drm_device *dev, int pipe)
1664 {
1665         struct intel_crtc *intel_crtc;
1666         int i;
1667
1668         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
1669         if (intel_crtc == NULL)
1670                 return;
1671
1672         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
1673
1674         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
1675         intel_crtc->pipe = pipe;
1676         for (i = 0; i < 256; i++) {
1677                 intel_crtc->lut_r[i] = i;
1678                 intel_crtc->lut_g[i] = i;
1679                 intel_crtc->lut_b[i] = i;
1680         }
1681
1682         intel_crtc->cursor_addr = 0;
1683         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
1684         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
1685
1686         intel_crtc->mode_set.crtc = &intel_crtc->base;
1687         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
1688         intel_crtc->mode_set.num_connectors = 0;
1689
1690         if (i915_fbpercrtc) {
1691
1692
1693
1694         }
1695 }
1696
1697 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1698 {
1699         struct drm_crtc *crtc = NULL;
1700
1701         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1702                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1703                 if (intel_crtc->pipe == pipe)
1704                         break;
1705         }
1706         return crtc;
1707 }
1708
1709 static int intel_connector_clones(struct drm_device *dev, int type_mask)
1710 {
1711         int index_mask = 0;
1712         struct drm_connector *connector;
1713         int entry = 0;
1714
1715         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1716                 struct intel_output *intel_output = to_intel_output(connector);
1717                 if (type_mask & (1 << intel_output->type))
1718                         index_mask |= (1 << entry);
1719                 entry++;
1720         }
1721         return index_mask;
1722 }
1723
1724
1725 static void intel_setup_outputs(struct drm_device *dev)
1726 {
1727         struct drm_i915_private *dev_priv = dev->dev_private;
1728         struct drm_connector *connector;
1729
1730         intel_crt_init(dev);
1731
1732         /* Set up integrated LVDS */
1733         if (IS_MOBILE(dev) && !IS_I830(dev))
1734                 intel_lvds_init(dev);
1735
1736         if (IS_I9XX(dev)) {
1737                 int found;
1738
1739                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
1740                         found = intel_sdvo_init(dev, SDVOB);
1741                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1742                                 intel_hdmi_init(dev, SDVOB);
1743                 }
1744                 if (!IS_G4X(dev) || (I915_READ(SDVOB) & SDVO_DETECTED)) {
1745                         found = intel_sdvo_init(dev, SDVOC);
1746                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1747                                 intel_hdmi_init(dev, SDVOC);
1748                 }
1749         } else
1750                 intel_dvo_init(dev);
1751
1752         if (IS_I9XX(dev) && IS_MOBILE(dev))
1753                 intel_tv_init(dev);
1754
1755         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1756                 struct intel_output *intel_output = to_intel_output(connector);
1757                 struct drm_encoder *encoder = &intel_output->enc;
1758                 int crtc_mask = 0, clone_mask = 0;
1759
1760                 /* valid crtcs */
1761                 switch(intel_output->type) {
1762                 case INTEL_OUTPUT_HDMI:
1763                         crtc_mask = ((1 << 0)|
1764                                      (1 << 1));
1765                         clone_mask = ((1 << INTEL_OUTPUT_HDMI));
1766                         break;
1767                 case INTEL_OUTPUT_DVO:
1768                 case INTEL_OUTPUT_SDVO:
1769                         crtc_mask = ((1 << 0)|
1770                                      (1 << 1));
1771                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1772                                       (1 << INTEL_OUTPUT_DVO) |
1773                                       (1 << INTEL_OUTPUT_SDVO));
1774                         break;
1775                 case INTEL_OUTPUT_ANALOG:
1776                         crtc_mask = ((1 << 0)|
1777                                      (1 << 1));
1778                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1779                                       (1 << INTEL_OUTPUT_DVO) |
1780                                       (1 << INTEL_OUTPUT_SDVO));
1781                         break;
1782                 case INTEL_OUTPUT_LVDS:
1783                         crtc_mask = (1 << 1);
1784                         clone_mask = (1 << INTEL_OUTPUT_LVDS);
1785                         break;
1786                 case INTEL_OUTPUT_TVOUT:
1787                         crtc_mask = ((1 << 0) |
1788                                      (1 << 1));
1789                         clone_mask = (1 << INTEL_OUTPUT_TVOUT);
1790                         break;
1791                 }
1792                 encoder->possible_crtcs = crtc_mask;
1793                 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
1794         }
1795 }
1796
1797 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1798 {
1799         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1800         struct drm_device *dev = fb->dev;
1801
1802         if (fb->fbdev)
1803                 intelfb_remove(dev, fb);
1804
1805         drm_framebuffer_cleanup(fb);
1806         mutex_lock(&dev->struct_mutex);
1807         drm_gem_object_unreference(intel_fb->obj);
1808         mutex_unlock(&dev->struct_mutex);
1809
1810         kfree(intel_fb);
1811 }
1812
1813 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1814                                                 struct drm_file *file_priv,
1815                                                 unsigned int *handle)
1816 {
1817         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1818         struct drm_gem_object *object = intel_fb->obj;
1819
1820         return drm_gem_handle_create(file_priv, object, handle);
1821 }
1822
1823 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1824         .destroy = intel_user_framebuffer_destroy,
1825         .create_handle = intel_user_framebuffer_create_handle,
1826 };
1827
1828 int intel_framebuffer_create(struct drm_device *dev,
1829                              struct drm_mode_fb_cmd *mode_cmd,
1830                              struct drm_framebuffer **fb,
1831                              struct drm_gem_object *obj)
1832 {
1833         struct intel_framebuffer *intel_fb;
1834         int ret;
1835
1836         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1837         if (!intel_fb)
1838                 return -ENOMEM;
1839
1840         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
1841         if (ret) {
1842                 DRM_ERROR("framebuffer init failed %d\n", ret);
1843                 return ret;
1844         }
1845
1846         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
1847
1848         intel_fb->obj = obj;
1849
1850         *fb = &intel_fb->base;
1851
1852         return 0;
1853 }
1854
1855
1856 static struct drm_framebuffer *
1857 intel_user_framebuffer_create(struct drm_device *dev,
1858                               struct drm_file *filp,
1859                               struct drm_mode_fb_cmd *mode_cmd)
1860 {
1861         struct drm_gem_object *obj;
1862         struct drm_framebuffer *fb;
1863         int ret;
1864
1865         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
1866         if (!obj)
1867                 return NULL;
1868
1869         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
1870         if (ret) {
1871                 mutex_lock(&dev->struct_mutex);
1872                 drm_gem_object_unreference(obj);
1873                 mutex_unlock(&dev->struct_mutex);
1874                 return NULL;
1875         }
1876
1877         return fb;
1878 }
1879
1880 static const struct drm_mode_config_funcs intel_mode_funcs = {
1881         .fb_create = intel_user_framebuffer_create,
1882         .fb_changed = intelfb_probe,
1883 };
1884
1885 void intel_modeset_init(struct drm_device *dev)
1886 {
1887         int num_pipe;
1888         int i;
1889
1890         drm_mode_config_init(dev);
1891
1892         dev->mode_config.min_width = 0;
1893         dev->mode_config.min_height = 0;
1894
1895         dev->mode_config.funcs = (void *)&intel_mode_funcs;
1896
1897         if (IS_I965G(dev)) {
1898                 dev->mode_config.max_width = 8192;
1899                 dev->mode_config.max_height = 8192;
1900         } else {
1901                 dev->mode_config.max_width = 2048;
1902                 dev->mode_config.max_height = 2048;
1903         }
1904
1905         /* set memory base */
1906         if (IS_I9XX(dev))
1907                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
1908         else
1909                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
1910
1911         if (IS_MOBILE(dev) || IS_I9XX(dev))
1912                 num_pipe = 2;
1913         else
1914                 num_pipe = 1;
1915         DRM_DEBUG("%d display pipe%s available.\n",
1916                   num_pipe, num_pipe > 1 ? "s" : "");
1917
1918         for (i = 0; i < num_pipe; i++) {
1919                 intel_crtc_init(dev, i);
1920         }
1921
1922         intel_setup_outputs(dev);
1923 }
1924
1925 void intel_modeset_cleanup(struct drm_device *dev)
1926 {
1927         drm_mode_config_cleanup(dev);
1928 }
1929
1930
1931 /* current intel driver doesn't take advantage of encoders
1932    always give back the encoder for the connector
1933 */
1934 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
1935 {
1936         struct intel_output *intel_output = to_intel_output(connector);
1937
1938         return &intel_output->enc;
1939 }