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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 710              clock.m1++) {
 711                 for (clock.m2 = limit->m2.min;
 712                      clock.m2 <= limit->m2.max; clock.m2++) {
 713                         /* m1 is always 0 in IGD */
 714                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 715                                 break;
 716                         for (clock.n = limit->n.min;
 717                              clock.n <= limit->n.max; clock.n++) {
 718                                 for (clock.p1 = limit->p1.min;
 719                                         clock.p1 <= limit->p1.max; clock.p1++) {
 720                                         int this_err;
 721
 722                                         intel_clock(dev, refclk, &clock);
 723
 724                                         if (!intel_PLL_is_valid(crtc, &clock))
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740
 741 static bool
 742 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 743                             int target, int refclk, intel_clock_t *best_clock)
 744
 745 {
 746         struct drm_device *dev = crtc->dev;
 747         intel_clock_t clock;
 748         int err = target;
 749         bool found = false;
 750
 751         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 752
 753         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 754                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 755                         /* m1 is always 0 in IGD */
 756                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 757                                 break;
 758                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 759                              clock.n++) {
 760                                 int this_err;
 761
 762                                 intel_clock(dev, refclk, &clock);
 763
 764                                 if (!intel_PLL_is_valid(crtc, &clock))
 765                                         continue;
 766
 767                                 this_err = abs(clock.dot - target);
 768                                 if (this_err < err) {
 769                                         *best_clock = clock;
 770                                         err = this_err;
 771                                         found = true;
 772                                 }
 773                         }
 774                 }
 775         }
 776
 777         return found;
 778 }
 779
 780 static bool
 781 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 782                         int target, int refclk, intel_clock_t *best_clock)
 783 {
 784         struct drm_device *dev = crtc->dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         intel_clock_t clock;
 787         int max_n;
 788         bool found;
 789         /* approximately equals target * 0.00488 */
 790         int err_most = (target >> 8) + (target >> 10);
 791         found = false;
 792
 793         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 794                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 795                     LVDS_CLKB_POWER_UP)
 796                         clock.p2 = limit->p2.p2_fast;
 797                 else
 798                         clock.p2 = limit->p2.p2_slow;
 799         } else {
 800                 if (target < limit->p2.dot_limit)
 801                         clock.p2 = limit->p2.p2_slow;
 802                 else
 803                         clock.p2 = limit->p2.p2_fast;
 804         }
 805
 806         memset(best_clock, 0, sizeof(*best_clock));
 807         max_n = limit->n.max;
 808         /* based on hardware requriment prefer smaller n to precision */
 809         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 810                 /* based on hardware requirment prefere larger m1,m2 */
 811                 for (clock.m1 = limit->m1.max;
 812                      clock.m1 >= limit->m1.min; clock.m1--) {
 813                         for (clock.m2 = limit->m2.max;
 814                              clock.m2 >= limit->m2.min; clock.m2--) {
 815                                 for (clock.p1 = limit->p1.max;
 816                                      clock.p1 >= limit->p1.min; clock.p1--) {
 817                                         int this_err;
 818
 819                                         intel_clock(dev, refclk, &clock);
 820                                         if (!intel_PLL_is_valid(crtc, &clock))
 821                                                 continue;
 822                                         this_err = abs(clock.dot - target) ;
 823                                         if (this_err < err_most) {
 824                                                 *best_clock = clock;
 825                                                 err_most = this_err;
 826                                                 max_n = clock.n;
 827                                                 found = true;
 828                                         }
 829                                 }
 830                         }
 831                 }
 832         }
 833         return found;
 834 }
 835
 836 static bool
 837 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 838                       int target, int refclk, intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->dev;
 841         intel_clock_t clock;
 842         if (target < 200000) {
 843                 clock.n = 1;
 844                 clock.p1 = 2;
 845                 clock.p2 = 10;
 846                 clock.m1 = 12;
 847                 clock.m2 = 9;
 848         } else {
 849                 clock.n = 2;
 850                 clock.p1 = 1;
 851                 clock.p2 = 10;
 852                 clock.m1 = 14;
 853                 clock.m2 = 8;
 854         }
 855         intel_clock(dev, refclk, &clock);
 856         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 857         return true;
 858 }
 859
 860 static bool
 861 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 862                         int target, int refclk, intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc->dev;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         intel_clock_t clock;
 867         int err_most = 47;
 868         int err_min = 10000;
 869
 870         /* eDP has only 2 clock choice, no n/m/p setting */
 871         if (HAS_eDP)
 872                 return true;
 873
 874         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 875                 return intel_find_pll_igdng_dp(limit, crtc, target,
 876                                                refclk, best_clock);
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 880                     LVDS_CLKB_POWER_UP)
 881                         clock.p2 = limit->p2.p2_fast;
 882                 else
 883                         clock.p2 = limit->p2.p2_slow;
 884         } else {
 885                 if (target < limit->p2.dot_limit)
 886                         clock.p2 = limit->p2.p2_slow;
 887                 else
 888                         clock.p2 = limit->p2.p2_fast;
 889         }
 890
 891         memset(best_clock, 0, sizeof(*best_clock));
 892         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 893                 /* based on hardware requriment prefer smaller n to precision */
 894                 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
 895                         /* based on hardware requirment prefere larger m1,m2 */
 896                         for (clock.m1 = limit->m1.max;
 897                              clock.m1 >= limit->m1.min; clock.m1--) {
 898                                 for (clock.m2 = limit->m2.max;
 899                                      clock.m2 >= limit->m2.min; clock.m2--) {
 900                                         int this_err;
 901
 902                                         intel_clock(dev, refclk, &clock);
 903                                         if (!intel_PLL_is_valid(crtc, &clock))
 904                                                 continue;
 905                                         this_err = abs((10000 - (target*10000/clock.dot)));
 906                                         if (this_err < err_most) {
 907                                                 *best_clock = clock;
 908                                                 /* found on first matching */
 909                                                 goto out;
 910                                         } else if (this_err < err_min) {
 911                                                 *best_clock = clock;
 912                                                 err_min = this_err;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918 out:
 919         return true;
 920 }
 921
 922 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 923 static bool
 924 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 925                       int target, int refclk, intel_clock_t *best_clock)
 926 {
 927     intel_clock_t clock;
 928     if (target < 200000) {
 929         clock.p1 = 2;
 930         clock.p2 = 10;
 931         clock.n = 2;
 932         clock.m1 = 23;
 933         clock.m2 = 8;
 934     } else {
 935         clock.p1 = 1;
 936         clock.p2 = 10;
 937         clock.n = 1;
 938         clock.m1 = 14;
 939         clock.m2 = 2;
 940     }
 941     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 942     clock.p = (clock.p1 * clock.p2);
 943     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 944     clock.vco = 0;
 945     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 946     return true;
 947 }
 948
 949 void
 950 intel_wait_for_vblank(struct drm_device *dev)
 951 {
 952         /* Wait for 20ms, i.e. one cycle at 50hz. */
 953         mdelay(20);
 954 }
 955
 956 /* Parameters have changed, update FBC info */
 957 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 958 {
 959         struct drm_device *dev = crtc->dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         struct drm_framebuffer *fb = crtc->fb;
 962         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 963         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 965         int plane, i;
 966         u32 fbc_ctl, fbc_ctl2;
 967
 968         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 969
 970         if (fb->pitch < dev_priv->cfb_pitch)
 971                 dev_priv->cfb_pitch = fb->pitch;
 972
 973         /* FBC_CTL wants 64B units */
 974         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 975         dev_priv->cfb_fence = obj_priv->fence_reg;
 976         dev_priv->cfb_plane = intel_crtc->plane;
 977         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 978
 979         /* Clear old tags */
 980         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 981                 I915_WRITE(FBC_TAG + (i * 4), 0);
 982
 983         /* Set it up... */
 984         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 985         if (obj_priv->tiling_mode != I915_TILING_NONE)
 986                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 987         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 988         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 989
 990         /* enable it... */
 991         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 992         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 993         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 994         if (obj_priv->tiling_mode != I915_TILING_NONE)
 995                 fbc_ctl |= dev_priv->cfb_fence;
 996         I915_WRITE(FBC_CONTROL, fbc_ctl);
 997
 998         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
 999                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1000 }
1001
1002 void i8xx_disable_fbc(struct drm_device *dev)
1003 {
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         u32 fbc_ctl;
1006
1007         if (!I915_HAS_FBC(dev))
1008                 return;
1009
1010         /* Disable compression */
1011         fbc_ctl = I915_READ(FBC_CONTROL);
1012         fbc_ctl &= ~FBC_CTL_EN;
1013         I915_WRITE(FBC_CONTROL, fbc_ctl);
1014
1015         /* Wait for compressing bit to clear */
1016         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1017                 ; /* nothing */
1018
1019         intel_wait_for_vblank(dev);
1020
1021         DRM_DEBUG_KMS("disabled FBC\n");
1022 }
1023
1024 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1025 {
1026         struct drm_device *dev = crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028
1029         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1030 }
1031
1032 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1033 {
1034         struct drm_device *dev = crtc->dev;
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         struct drm_framebuffer *fb = crtc->fb;
1037         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1038         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1040         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1041                      DPFC_CTL_PLANEB);
1042         unsigned long stall_watermark = 200;
1043         u32 dpfc_ctl;
1044
1045         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1046         dev_priv->cfb_fence = obj_priv->fence_reg;
1047         dev_priv->cfb_plane = intel_crtc->plane;
1048
1049         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1050         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1051                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1052                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1053         } else {
1054                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1055         }
1056
1057         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1058         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1059                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1060                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1061         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1062
1063         /* enable it... */
1064         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1065
1066         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1067 }
1068
1069 void g4x_disable_fbc(struct drm_device *dev)
1070 {
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         u32 dpfc_ctl;
1073
1074         /* Disable compression */
1075         dpfc_ctl = I915_READ(DPFC_CONTROL);
1076         dpfc_ctl &= ~DPFC_CTL_EN;
1077         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1078         intel_wait_for_vblank(dev);
1079
1080         DRM_DEBUG_KMS("disabled FBC\n");
1081 }
1082
1083 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1084 {
1085         struct drm_device *dev = crtc->dev;
1086         struct drm_i915_private *dev_priv = dev->dev_private;
1087
1088         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1089 }
1090
1091 /**
1092  * intel_update_fbc - enable/disable FBC as needed
1093  * @crtc: CRTC to point the compressor at
1094  * @mode: mode in use
1095  *
1096  * Set up the framebuffer compression hardware at mode set time.  We
1097  * enable it if possible:
1098  *   - plane A only (on pre-965)
1099  *   - no pixel mulitply/line duplication
1100  *   - no alpha buffer discard
1101  *   - no dual wide
1102  *   - framebuffer <= 2048 in width, 1536 in height
1103  *
1104  * We can't assume that any compression will take place (worst case),
1105  * so the compressed buffer has to be the same size as the uncompressed
1106  * one.  It also must reside (along with the line length buffer) in
1107  * stolen memory.
1108  *
1109  * We need to enable/disable FBC on a global basis.
1110  */
1111 static void intel_update_fbc(struct drm_crtc *crtc,
1112                              struct drm_display_mode *mode)
1113 {
1114         struct drm_device *dev = crtc->dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         struct drm_framebuffer *fb = crtc->fb;
1117         struct intel_framebuffer *intel_fb;
1118         struct drm_i915_gem_object *obj_priv;
1119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1120         int plane = intel_crtc->plane;
1121
1122         if (!i915_powersave)
1123                 return;
1124
1125         if (!dev_priv->display.fbc_enabled ||
1126             !dev_priv->display.enable_fbc ||
1127             !dev_priv->display.disable_fbc)
1128                 return;
1129
1130         if (!crtc->fb)
1131                 return;
1132
1133         intel_fb = to_intel_framebuffer(fb);
1134         obj_priv = intel_fb->obj->driver_private;
1135
1136         /*
1137          * If FBC is already on, we just have to verify that we can
1138          * keep it that way...
1139          * Need to disable if:
1140          *   - changing FBC params (stride, fence, mode)
1141          *   - new fb is too large to fit in compressed buffer
1142          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1143          */
1144         if (intel_fb->obj->size > dev_priv->cfb_size) {
1145                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1146                                 "compression\n");
1147                 goto out_disable;
1148         }
1149         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151                 DRM_DEBUG_KMS("mode incompatible with compression, "
1152                                 "disabling\n");
1153                 goto out_disable;
1154         }
1155         if ((mode->hdisplay > 2048) ||
1156             (mode->vdisplay > 1536)) {
1157                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1158                 goto out_disable;
1159         }
1160         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1161                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1162                 goto out_disable;
1163         }
1164         if (obj_priv->tiling_mode != I915_TILING_X) {
1165                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1166                 goto out_disable;
1167         }
1168
1169         if (dev_priv->display.fbc_enabled(crtc)) {
1170                 /* We can re-enable it in this case, but need to update pitch */
1171                 if (fb->pitch > dev_priv->cfb_pitch)
1172                         dev_priv->display.disable_fbc(dev);
1173                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1174                         dev_priv->display.disable_fbc(dev);
1175                 if (plane != dev_priv->cfb_plane)
1176                         dev_priv->display.disable_fbc(dev);
1177         }
1178
1179         if (!dev_priv->display.fbc_enabled(crtc)) {
1180                 /* Now try to turn it back on if possible */
1181                 dev_priv->display.enable_fbc(crtc, 500);
1182         }
1183
1184         return;
1185
1186 out_disable:
1187         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1188         /* Multiple disables should be harmless */
1189         if (dev_priv->display.fbc_enabled(crtc))
1190                 dev_priv->display.disable_fbc(dev);
1191 }
1192
1193 static int
1194 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1195                     struct drm_framebuffer *old_fb)
1196 {
1197         struct drm_device *dev = crtc->dev;
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         struct drm_i915_master_private *master_priv;
1200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1201         struct intel_framebuffer *intel_fb;
1202         struct drm_i915_gem_object *obj_priv;
1203         struct drm_gem_object *obj;
1204         int pipe = intel_crtc->pipe;
1205         int plane = intel_crtc->plane;
1206         unsigned long Start, Offset;
1207         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1208         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1209         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1210         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1211         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1212         u32 dspcntr, alignment;
1213         int ret;
1214
1215         /* no fb bound */
1216         if (!crtc->fb) {
1217                 DRM_DEBUG_KMS("No FB bound\n");
1218                 return 0;
1219         }
1220
1221         switch (plane) {
1222         case 0:
1223         case 1:
1224                 break;
1225         default:
1226                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1227                 return -EINVAL;
1228         }
1229
1230         intel_fb = to_intel_framebuffer(crtc->fb);
1231         obj = intel_fb->obj;
1232         obj_priv = obj->driver_private;
1233
1234         switch (obj_priv->tiling_mode) {
1235         case I915_TILING_NONE:
1236                 alignment = 64 * 1024;
1237                 break;
1238         case I915_TILING_X:
1239                 /* pin() will align the object as required by fence */
1240                 alignment = 0;
1241                 break;
1242         case I915_TILING_Y:
1243                 /* FIXME: Is this true? */
1244                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1245                 return -EINVAL;
1246         default:
1247                 BUG();
1248         }
1249
1250         mutex_lock(&dev->struct_mutex);
1251         ret = i915_gem_object_pin(obj, alignment);
1252         if (ret != 0) {
1253                 mutex_unlock(&dev->struct_mutex);
1254                 return ret;
1255         }
1256
1257         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1258         if (ret != 0) {
1259                 i915_gem_object_unpin(obj);
1260                 mutex_unlock(&dev->struct_mutex);
1261                 return ret;
1262         }
1263
1264         /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1265          * whereas 965+ only requires a fence if using framebuffer compression.
1266          * For simplicity, we always install a fence as the cost is not that onerous.
1267          */
1268         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1269             obj_priv->tiling_mode != I915_TILING_NONE) {
1270                 ret = i915_gem_object_get_fence_reg(obj);
1271                 if (ret != 0) {
1272                         i915_gem_object_unpin(obj);
1273                         mutex_unlock(&dev->struct_mutex);
1274                         return ret;
1275                 }
1276         }
1277
1278         dspcntr = I915_READ(dspcntr_reg);
1279         /* Mask out pixel format bits in case we change it */
1280         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1281         switch (crtc->fb->bits_per_pixel) {
1282         case 8:
1283                 dspcntr |= DISPPLANE_8BPP;
1284                 break;
1285         case 16:
1286                 if (crtc->fb->depth == 15)
1287                         dspcntr |= DISPPLANE_15_16BPP;
1288                 else
1289                         dspcntr |= DISPPLANE_16BPP;
1290                 break;
1291         case 24:
1292         case 32:
1293                 if (crtc->fb->depth == 30)
1294                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1295                 else
1296                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1297                 break;
1298         default:
1299                 DRM_ERROR("Unknown color depth\n");
1300                 i915_gem_object_unpin(obj);
1301                 mutex_unlock(&dev->struct_mutex);
1302                 return -EINVAL;
1303         }
1304         if (IS_I965G(dev)) {
1305                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1306                         dspcntr |= DISPPLANE_TILED;
1307                 else
1308                         dspcntr &= ~DISPPLANE_TILED;
1309         }
1310
1311         if (IS_IGDNG(dev))
1312                 /* must disable */
1313                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1314
1315         I915_WRITE(dspcntr_reg, dspcntr);
1316
1317         Start = obj_priv->gtt_offset;
1318         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1319
1320         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1321         I915_WRITE(dspstride, crtc->fb->pitch);
1322         if (IS_I965G(dev)) {
1323                 I915_WRITE(dspbase, Offset);
1324                 I915_READ(dspbase);
1325                 I915_WRITE(dspsurf, Start);
1326                 I915_READ(dspsurf);
1327                 I915_WRITE(dsptileoff, (y << 16) | x);
1328         } else {
1329                 I915_WRITE(dspbase, Start + Offset);
1330                 I915_READ(dspbase);
1331         }
1332
1333         if ((IS_I965G(dev) || plane == 0))
1334                 intel_update_fbc(crtc, &crtc->mode);
1335
1336         intel_wait_for_vblank(dev);
1337
1338         if (old_fb) {
1339                 intel_fb = to_intel_framebuffer(old_fb);
1340                 obj_priv = intel_fb->obj->driver_private;
1341                 i915_gem_object_unpin(intel_fb->obj);
1342         }
1343         intel_increase_pllclock(crtc, true);
1344
1345         mutex_unlock(&dev->struct_mutex);
1346
1347         if (!dev->primary->master)
1348                 return 0;
1349
1350         master_priv = dev->primary->master->driver_priv;
1351         if (!master_priv->sarea_priv)
1352                 return 0;
1353
1354         if (pipe) {
1355                 master_priv->sarea_priv->pipeB_x = x;
1356                 master_priv->sarea_priv->pipeB_y = y;
1357         } else {
1358                 master_priv->sarea_priv->pipeA_x = x;
1359                 master_priv->sarea_priv->pipeA_y = y;
1360         }
1361
1362         return 0;
1363 }
1364
1365 /* Disable the VGA plane that we never use */
1366 static void i915_disable_vga (struct drm_device *dev)
1367 {
1368         struct drm_i915_private *dev_priv = dev->dev_private;
1369         u8 sr1;
1370         u32 vga_reg;
1371
1372         if (IS_IGDNG(dev))
1373                 vga_reg = CPU_VGACNTRL;
1374         else
1375                 vga_reg = VGACNTRL;
1376
1377         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1378                 return;
1379
1380         I915_WRITE8(VGA_SR_INDEX, 1);
1381         sr1 = I915_READ8(VGA_SR_DATA);
1382         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1383         udelay(100);
1384
1385         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1386 }
1387
1388 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1389 {
1390         struct drm_device *dev = crtc->dev;
1391         struct drm_i915_private *dev_priv = dev->dev_private;
1392         u32 dpa_ctl;
1393
1394         DRM_DEBUG_KMS("\n");
1395         dpa_ctl = I915_READ(DP_A);
1396         dpa_ctl &= ~DP_PLL_ENABLE;
1397         I915_WRITE(DP_A, dpa_ctl);
1398 }
1399
1400 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1401 {
1402         struct drm_device *dev = crtc->dev;
1403         struct drm_i915_private *dev_priv = dev->dev_private;
1404         u32 dpa_ctl;
1405
1406         dpa_ctl = I915_READ(DP_A);
1407         dpa_ctl |= DP_PLL_ENABLE;
1408         I915_WRITE(DP_A, dpa_ctl);
1409         udelay(200);
1410 }
1411
1412
1413 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1414 {
1415         struct drm_device *dev = crtc->dev;
1416         struct drm_i915_private *dev_priv = dev->dev_private;
1417         u32 dpa_ctl;
1418
1419         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1420         dpa_ctl = I915_READ(DP_A);
1421         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1422
1423         if (clock < 200000) {
1424                 u32 temp;
1425                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1426                 /* workaround for 160Mhz:
1427                    1) program 0x4600c bits 15:0 = 0x8124
1428                    2) program 0x46010 bit 0 = 1
1429                    3) program 0x46034 bit 24 = 1
1430                    4) program 0x64000 bit 14 = 1
1431                    */
1432                 temp = I915_READ(0x4600c);
1433                 temp &= 0xffff0000;
1434                 I915_WRITE(0x4600c, temp | 0x8124);
1435
1436                 temp = I915_READ(0x46010);
1437                 I915_WRITE(0x46010, temp | 1);
1438
1439                 temp = I915_READ(0x46034);
1440                 I915_WRITE(0x46034, temp | (1 << 24));
1441         } else {
1442                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1443         }
1444         I915_WRITE(DP_A, dpa_ctl);
1445
1446         udelay(500);
1447 }
1448
1449 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1450 {
1451         struct drm_device *dev = crtc->dev;
1452         struct drm_i915_private *dev_priv = dev->dev_private;
1453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1454         int pipe = intel_crtc->pipe;
1455         int plane = intel_crtc->plane;
1456         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1457         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1458         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1459         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1460         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1461         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1462         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1463         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1464         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1465         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1466         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1467         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1468         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1469         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1470         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1471         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1472         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1473         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1474         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1475         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1476         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1477         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1478         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1479         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1480         u32 temp;
1481         int tries = 5, j, n;
1482
1483         /* XXX: When our outputs are all unaware of DPMS modes other than off
1484          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1485          */
1486         switch (mode) {
1487         case DRM_MODE_DPMS_ON:
1488         case DRM_MODE_DPMS_STANDBY:
1489         case DRM_MODE_DPMS_SUSPEND:
1490                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1491                 if (HAS_eDP) {
1492                         /* enable eDP PLL */
1493                         igdng_enable_pll_edp(crtc);
1494                 } else {
1495                         /* enable PCH DPLL */
1496                         temp = I915_READ(pch_dpll_reg);
1497                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1498                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1499                                 I915_READ(pch_dpll_reg);
1500                         }
1501
1502                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1503                         temp = I915_READ(fdi_rx_reg);
1504                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1505                                         FDI_SEL_PCDCLK |
1506                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1507                         I915_READ(fdi_rx_reg);
1508                         udelay(200);
1509
1510                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1511                         temp = I915_READ(fdi_tx_reg);
1512                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1513                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1514                                 I915_READ(fdi_tx_reg);
1515                                 udelay(100);
1516                         }
1517                 }
1518
1519                 /* Enable panel fitting for LVDS */
1520                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1521                         temp = I915_READ(pf_ctl_reg);
1522                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1523
1524                         /* currently full aspect */
1525                         I915_WRITE(pf_win_pos, 0);
1526
1527                         I915_WRITE(pf_win_size,
1528                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1529                                    (dev_priv->panel_fixed_mode->vdisplay));
1530                 }
1531
1532                 /* Enable CPU pipe */
1533                 temp = I915_READ(pipeconf_reg);
1534                 if ((temp & PIPEACONF_ENABLE) == 0) {
1535                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1536                         I915_READ(pipeconf_reg);
1537                         udelay(100);
1538                 }
1539
1540                 /* configure and enable CPU plane */
1541                 temp = I915_READ(dspcntr_reg);
1542                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1543                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1544                         /* Flush the plane changes */
1545                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1546                 }
1547
1548                 if (!HAS_eDP) {
1549                         /* enable CPU FDI TX and PCH FDI RX */
1550                         temp = I915_READ(fdi_tx_reg);
1551                         temp |= FDI_TX_ENABLE;
1552                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1553                         temp &= ~FDI_LINK_TRAIN_NONE;
1554                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1555                         I915_WRITE(fdi_tx_reg, temp);
1556                         I915_READ(fdi_tx_reg);
1557
1558                         temp = I915_READ(fdi_rx_reg);
1559                         temp &= ~FDI_LINK_TRAIN_NONE;
1560                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1561                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1562                         I915_READ(fdi_rx_reg);
1563
1564                         udelay(150);
1565
1566                         /* Train FDI. */
1567                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1568                            for train result */
1569                         temp = I915_READ(fdi_rx_imr_reg);
1570                         temp &= ~FDI_RX_SYMBOL_LOCK;
1571                         temp &= ~FDI_RX_BIT_LOCK;
1572                         I915_WRITE(fdi_rx_imr_reg, temp);
1573                         I915_READ(fdi_rx_imr_reg);
1574                         udelay(150);
1575
1576                         temp = I915_READ(fdi_rx_iir_reg);
1577                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1578
1579                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1580                                 for (j = 0; j < tries; j++) {
1581                                         temp = I915_READ(fdi_rx_iir_reg);
1582                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1583                                                                 temp);
1584                                         if (temp & FDI_RX_BIT_LOCK)
1585                                                 break;
1586                                         udelay(200);
1587                                 }
1588                                 if (j != tries)
1589                                         I915_WRITE(fdi_rx_iir_reg,
1590                                                         temp | FDI_RX_BIT_LOCK);
1591                                 else
1592                                         DRM_DEBUG_KMS("train 1 fail\n");
1593                         } else {
1594                                 I915_WRITE(fdi_rx_iir_reg,
1595                                                 temp | FDI_RX_BIT_LOCK);
1596                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1597                         }
1598                         temp = I915_READ(fdi_tx_reg);
1599                         temp &= ~FDI_LINK_TRAIN_NONE;
1600                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1601                         I915_WRITE(fdi_tx_reg, temp);
1602
1603                         temp = I915_READ(fdi_rx_reg);
1604                         temp &= ~FDI_LINK_TRAIN_NONE;
1605                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1606                         I915_WRITE(fdi_rx_reg, temp);
1607
1608                         udelay(150);
1609
1610                         temp = I915_READ(fdi_rx_iir_reg);
1611                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1612
1613                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1614                                 for (j = 0; j < tries; j++) {
1615                                         temp = I915_READ(fdi_rx_iir_reg);
1616                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1617                                                                 temp);
1618                                         if (temp & FDI_RX_SYMBOL_LOCK)
1619                                                 break;
1620                                         udelay(200);
1621                                 }
1622                                 if (j != tries) {
1623                                         I915_WRITE(fdi_rx_iir_reg,
1624                                                         temp | FDI_RX_SYMBOL_LOCK);
1625                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1626                                 } else
1627                                         DRM_DEBUG_KMS("train 2 fail\n");
1628                         } else {
1629                                 I915_WRITE(fdi_rx_iir_reg,
1630                                                 temp | FDI_RX_SYMBOL_LOCK);
1631                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1632                         }
1633                         DRM_DEBUG_KMS("train done\n");
1634
1635                         /* set transcoder timing */
1636                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1637                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1638                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1639
1640                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1641                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1642                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1643
1644                         /* enable PCH transcoder */
1645                         temp = I915_READ(transconf_reg);
1646                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1647                         I915_READ(transconf_reg);
1648
1649                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1650                                 ;
1651
1652                         /* enable normal */
1653
1654                         temp = I915_READ(fdi_tx_reg);
1655                         temp &= ~FDI_LINK_TRAIN_NONE;
1656                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1657                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1658                         I915_READ(fdi_tx_reg);
1659
1660                         temp = I915_READ(fdi_rx_reg);
1661                         temp &= ~FDI_LINK_TRAIN_NONE;
1662                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1663                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1664                         I915_READ(fdi_rx_reg);
1665
1666                         /* wait one idle pattern time */
1667                         udelay(100);
1668
1669                 }
1670
1671                 intel_crtc_load_lut(crtc);
1672
1673         break;
1674         case DRM_MODE_DPMS_OFF:
1675                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1676
1677                 i915_disable_vga(dev);
1678
1679                 /* Disable display plane */
1680                 temp = I915_READ(dspcntr_reg);
1681                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1682                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1683                         /* Flush the plane changes */
1684                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1685                         I915_READ(dspbase_reg);
1686                 }
1687
1688                 /* disable cpu pipe, disable after all planes disabled */
1689                 temp = I915_READ(pipeconf_reg);
1690                 if ((temp & PIPEACONF_ENABLE) != 0) {
1691                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1692                         I915_READ(pipeconf_reg);
1693                         n = 0;
1694                         /* wait for cpu pipe off, pipe state */
1695                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1696                                 n++;
1697                                 if (n < 60) {
1698                                         udelay(500);
1699                                         continue;
1700                                 } else {
1701                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1702                                                                 pipe);
1703                                         break;
1704                                 }
1705                         }
1706                 } else
1707                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1708
1709                 if (HAS_eDP) {
1710                         igdng_disable_pll_edp(crtc);
1711                 }
1712
1713                 /* disable CPU FDI tx and PCH FDI rx */
1714                 temp = I915_READ(fdi_tx_reg);
1715                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1716                 I915_READ(fdi_tx_reg);
1717
1718                 temp = I915_READ(fdi_rx_reg);
1719                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1720                 I915_READ(fdi_rx_reg);
1721
1722                 udelay(100);
1723
1724                 /* still set train pattern 1 */
1725                 temp = I915_READ(fdi_tx_reg);
1726                 temp &= ~FDI_LINK_TRAIN_NONE;
1727                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1728                 I915_WRITE(fdi_tx_reg, temp);
1729
1730                 temp = I915_READ(fdi_rx_reg);
1731                 temp &= ~FDI_LINK_TRAIN_NONE;
1732                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1733                 I915_WRITE(fdi_rx_reg, temp);
1734
1735                 udelay(100);
1736
1737                 /* disable PCH transcoder */
1738                 temp = I915_READ(transconf_reg);
1739                 if ((temp & TRANS_ENABLE) != 0) {
1740                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1741                         I915_READ(transconf_reg);
1742                         n = 0;
1743                         /* wait for PCH transcoder off, transcoder state */
1744                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1745                                 n++;
1746                                 if (n < 60) {
1747                                         udelay(500);
1748                                         continue;
1749                                 } else {
1750                                         DRM_DEBUG_KMS("transcoder %d off "
1751                                                         "delay\n", pipe);
1752                                         break;
1753                                 }
1754                         }
1755                 }
1756
1757                 /* disable PCH DPLL */
1758                 temp = I915_READ(pch_dpll_reg);
1759                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1760                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1761                         I915_READ(pch_dpll_reg);
1762                 }
1763
1764                 temp = I915_READ(fdi_rx_reg);
1765                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1766                         temp &= ~FDI_SEL_PCDCLK;
1767                         temp &= ~FDI_RX_PLL_ENABLE;
1768                         I915_WRITE(fdi_rx_reg, temp);
1769                         I915_READ(fdi_rx_reg);
1770                 }
1771
1772                 /* Disable CPU FDI TX PLL */
1773                 temp = I915_READ(fdi_tx_reg);
1774                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1775                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1776                         I915_READ(fdi_tx_reg);
1777                         udelay(100);
1778                 }
1779
1780                 /* Disable PF */
1781                 temp = I915_READ(pf_ctl_reg);
1782                 if ((temp & PF_ENABLE) != 0) {
1783                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1784                         I915_READ(pf_ctl_reg);
1785                 }
1786                 I915_WRITE(pf_win_size, 0);
1787
1788                 /* Wait for the clocks to turn off. */
1789                 udelay(150);
1790                 break;
1791         }
1792 }
1793
1794 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1795 {
1796         struct intel_overlay *overlay;
1797         int ret;
1798
1799         if (!enable && intel_crtc->overlay) {
1800                 overlay = intel_crtc->overlay;
1801                 mutex_lock(&overlay->dev->struct_mutex);
1802                 for (;;) {
1803                         ret = intel_overlay_switch_off(overlay);
1804                         if (ret == 0)
1805                                 break;
1806
1807                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1808                         if (ret != 0) {
1809                                 /* overlay doesn't react anymore. Usually
1810                                  * results in a black screen and an unkillable
1811                                  * X server. */
1812                                 BUG();
1813                                 overlay->hw_wedged = HW_WEDGED;
1814                                 break;
1815                         }
1816                 }
1817                 mutex_unlock(&overlay->dev->struct_mutex);
1818         }
1819         /* Let userspace switch the overlay on again. In most cases userspace
1820          * has to recompute where to put it anyway. */
1821
1822         return;
1823 }
1824
1825 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1826 {
1827         struct drm_device *dev = crtc->dev;
1828         struct drm_i915_private *dev_priv = dev->dev_private;
1829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1830         int pipe = intel_crtc->pipe;
1831         int plane = intel_crtc->plane;
1832         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1833         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1834         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1835         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1836         u32 temp;
1837
1838         /* XXX: When our outputs are all unaware of DPMS modes other than off
1839          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1840          */
1841         switch (mode) {
1842         case DRM_MODE_DPMS_ON:
1843         case DRM_MODE_DPMS_STANDBY:
1844         case DRM_MODE_DPMS_SUSPEND:
1845                 intel_update_watermarks(dev);
1846
1847                 /* Enable the DPLL */
1848                 temp = I915_READ(dpll_reg);
1849                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1850                         I915_WRITE(dpll_reg, temp);
1851                         I915_READ(dpll_reg);
1852                         /* Wait for the clocks to stabilize. */
1853                         udelay(150);
1854                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1855                         I915_READ(dpll_reg);
1856                         /* Wait for the clocks to stabilize. */
1857                         udelay(150);
1858                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1859                         I915_READ(dpll_reg);
1860                         /* Wait for the clocks to stabilize. */
1861                         udelay(150);
1862                 }
1863
1864                 /* Enable the pipe */
1865                 temp = I915_READ(pipeconf_reg);
1866                 if ((temp & PIPEACONF_ENABLE) == 0)
1867                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1868
1869                 /* Enable the plane */
1870                 temp = I915_READ(dspcntr_reg);
1871                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1872                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1873                         /* Flush the plane changes */
1874                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1875                 }
1876
1877                 intel_crtc_load_lut(crtc);
1878
1879                 if ((IS_I965G(dev) || plane == 0))
1880                         intel_update_fbc(crtc, &crtc->mode);
1881
1882                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1883                 intel_crtc_dpms_overlay(intel_crtc, true);
1884         break;
1885         case DRM_MODE_DPMS_OFF:
1886                 intel_update_watermarks(dev);
1887
1888                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1889                 intel_crtc_dpms_overlay(intel_crtc, false);
1890
1891                 if (dev_priv->cfb_plane == plane &&
1892                     dev_priv->display.disable_fbc)
1893                         dev_priv->display.disable_fbc(dev);
1894
1895                 /* Disable the VGA plane that we never use */
1896                 i915_disable_vga(dev);
1897
1898                 /* Disable display plane */
1899                 temp = I915_READ(dspcntr_reg);
1900                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1901                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1902                         /* Flush the plane changes */
1903                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1904                         I915_READ(dspbase_reg);
1905                 }
1906
1907                 if (!IS_I9XX(dev)) {
1908                         /* Wait for vblank for the disable to take effect */
1909                         intel_wait_for_vblank(dev);
1910                 }
1911
1912                 /* Next, disable display pipes */
1913                 temp = I915_READ(pipeconf_reg);
1914                 if ((temp & PIPEACONF_ENABLE) != 0) {
1915                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1916                         I915_READ(pipeconf_reg);
1917                 }
1918
1919                 /* Wait for vblank for the disable to take effect. */
1920                 intel_wait_for_vblank(dev);
1921
1922                 temp = I915_READ(dpll_reg);
1923                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1924                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1925                         I915_READ(dpll_reg);
1926                 }
1927
1928                 /* Wait for the clocks to turn off. */
1929                 udelay(150);
1930                 break;
1931         }
1932 }
1933
1934 /**
1935  * Sets the power management mode of the pipe and plane.
1936  *
1937  * This code should probably grow support for turning the cursor off and back
1938  * on appropriately at the same time as we're turning the pipe off/on.
1939  */
1940 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1941 {
1942         struct drm_device *dev = crtc->dev;
1943         struct drm_i915_private *dev_priv = dev->dev_private;
1944         struct drm_i915_master_private *master_priv;
1945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1946         int pipe = intel_crtc->pipe;
1947         bool enabled;
1948
1949         dev_priv->display.dpms(crtc, mode);
1950
1951         intel_crtc->dpms_mode = mode;
1952
1953         if (!dev->primary->master)
1954                 return;
1955
1956         master_priv = dev->primary->master->driver_priv;
1957         if (!master_priv->sarea_priv)
1958                 return;
1959
1960         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1961
1962         switch (pipe) {
1963         case 0:
1964                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1965                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1966                 break;
1967         case 1:
1968                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1969                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1970                 break;
1971         default:
1972                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1973                 break;
1974         }
1975 }
1976
1977 static void intel_crtc_prepare (struct drm_crtc *crtc)
1978 {
1979         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1980         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1981 }
1982
1983 static void intel_crtc_commit (struct drm_crtc *crtc)
1984 {
1985         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1986         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1987 }
1988
1989 void intel_encoder_prepare (struct drm_encoder *encoder)
1990 {
1991         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1992         /* lvds has its own version of prepare see intel_lvds_prepare */
1993         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1994 }
1995
1996 void intel_encoder_commit (struct drm_encoder *encoder)
1997 {
1998         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1999         /* lvds has its own version of commit see intel_lvds_commit */
2000         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2001 }
2002
2003 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2004                                   struct drm_display_mode *mode,
2005                                   struct drm_display_mode *adjusted_mode)
2006 {
2007         struct drm_device *dev = crtc->dev;
2008         if (IS_IGDNG(dev)) {
2009                 /* FDI link clock is fixed at 2.7G */
2010                 if (mode->clock * 3 > 27000 * 4)
2011                         return MODE_CLOCK_HIGH;
2012         }
2013         return true;
2014 }
2015
2016 static int i945_get_display_clock_speed(struct drm_device *dev)
2017 {
2018         return 400000;
2019 }
2020
2021 static int i915_get_display_clock_speed(struct drm_device *dev)
2022 {
2023         return 333000;
2024 }
2025
2026 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2027 {
2028         return 200000;
2029 }
2030
2031 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2032 {
2033         u16 gcfgc = 0;
2034
2035         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2036
2037         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2038                 return 133000;
2039         else {
2040                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2041                 case GC_DISPLAY_CLOCK_333_MHZ:
2042                         return 333000;
2043                 default:
2044                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2045                         return 190000;
2046                 }
2047         }
2048 }
2049
2050 static int i865_get_display_clock_speed(struct drm_device *dev)
2051 {
2052         return 266000;
2053 }
2054
2055 static int i855_get_display_clock_speed(struct drm_device *dev)
2056 {
2057         u16 hpllcc = 0;
2058         /* Assume that the hardware is in the high speed state.  This
2059          * should be the default.
2060          */
2061         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2062         case GC_CLOCK_133_200:
2063         case GC_CLOCK_100_200:
2064                 return 200000;
2065         case GC_CLOCK_166_250:
2066                 return 250000;
2067         case GC_CLOCK_100_133:
2068                 return 133000;
2069         }
2070
2071         /* Shouldn't happen */
2072         return 0;
2073 }
2074
2075 static int i830_get_display_clock_speed(struct drm_device *dev)
2076 {
2077         return 133000;
2078 }
2079
2080 /**
2081  * Return the pipe currently connected to the panel fitter,
2082  * or -1 if the panel fitter is not present or not in use
2083  */
2084 int intel_panel_fitter_pipe (struct drm_device *dev)
2085 {
2086         struct drm_i915_private *dev_priv = dev->dev_private;
2087         u32  pfit_control;
2088
2089         /* i830 doesn't have a panel fitter */
2090         if (IS_I830(dev))
2091                 return -1;
2092
2093         pfit_control = I915_READ(PFIT_CONTROL);
2094
2095         /* See if the panel fitter is in use */
2096         if ((pfit_control & PFIT_ENABLE) == 0)
2097                 return -1;
2098
2099         /* 965 can place panel fitter on either pipe */
2100         if (IS_I965G(dev))
2101                 return (pfit_control >> 29) & 0x3;
2102
2103         /* older chips can only use pipe 1 */
2104         return 1;
2105 }
2106
2107 struct fdi_m_n {
2108         u32        tu;
2109         u32        gmch_m;
2110         u32        gmch_n;
2111         u32        link_m;
2112         u32        link_n;
2113 };
2114
2115 static void
2116 fdi_reduce_ratio(u32 *num, u32 *den)
2117 {
2118         while (*num > 0xffffff || *den > 0xffffff) {
2119                 *num >>= 1;
2120                 *den >>= 1;
2121         }
2122 }
2123
2124 #define DATA_N 0x800000
2125 #define LINK_N 0x80000
2126
2127 static void
2128 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2129                 int pixel_clock, int link_clock,
2130                 struct fdi_m_n *m_n)
2131 {
2132         u64 temp;
2133
2134         m_n->tu = 64; /* default size */
2135
2136         temp = (u64) DATA_N * pixel_clock;
2137         temp = div_u64(temp, link_clock);
2138         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2139         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2140         m_n->gmch_n = DATA_N;
2141         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2142
2143         temp = (u64) LINK_N * pixel_clock;
2144         m_n->link_m = div_u64(temp, link_clock);
2145         m_n->link_n = LINK_N;
2146         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2147 }
2148
2149
2150 struct intel_watermark_params {
2151         unsigned long fifo_size;
2152         unsigned long max_wm;
2153         unsigned long default_wm;
2154         unsigned long guard_size;
2155         unsigned long cacheline_size;
2156 };
2157
2158 /* IGD has different values for various configs */
2159 static struct intel_watermark_params igd_display_wm = {
2160         IGD_DISPLAY_FIFO,
2161         IGD_MAX_WM,
2162         IGD_DFT_WM,
2163         IGD_GUARD_WM,
2164         IGD_FIFO_LINE_SIZE
2165 };
2166 static struct intel_watermark_params igd_display_hplloff_wm = {
2167         IGD_DISPLAY_FIFO,
2168         IGD_MAX_WM,
2169         IGD_DFT_HPLLOFF_WM,
2170         IGD_GUARD_WM,
2171         IGD_FIFO_LINE_SIZE
2172 };
2173 static struct intel_watermark_params igd_cursor_wm = {
2174         IGD_CURSOR_FIFO,
2175         IGD_CURSOR_MAX_WM,
2176         IGD_CURSOR_DFT_WM,
2177         IGD_CURSOR_GUARD_WM,
2178         IGD_FIFO_LINE_SIZE,
2179 };
2180 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2181         IGD_CURSOR_FIFO,
2182         IGD_CURSOR_MAX_WM,
2183         IGD_CURSOR_DFT_WM,
2184         IGD_CURSOR_GUARD_WM,
2185         IGD_FIFO_LINE_SIZE
2186 };
2187 static struct intel_watermark_params g4x_wm_info = {
2188         G4X_FIFO_SIZE,
2189         G4X_MAX_WM,
2190         G4X_MAX_WM,
2191         2,
2192         G4X_FIFO_LINE_SIZE,
2193 };
2194 static struct intel_watermark_params i945_wm_info = {
2195         I945_FIFO_SIZE,
2196         I915_MAX_WM,
2197         1,
2198         2,
2199         I915_FIFO_LINE_SIZE
2200 };
2201 static struct intel_watermark_params i915_wm_info = {
2202         I915_FIFO_SIZE,
2203         I915_MAX_WM,
2204         1,
2205         2,
2206         I915_FIFO_LINE_SIZE
2207 };
2208 static struct intel_watermark_params i855_wm_info = {
2209         I855GM_FIFO_SIZE,
2210         I915_MAX_WM,
2211         1,
2212         2,
2213         I830_FIFO_LINE_SIZE
2214 };
2215 static struct intel_watermark_params i830_wm_info = {
2216         I830_FIFO_SIZE,
2217         I915_MAX_WM,
2218         1,
2219         2,
2220         I830_FIFO_LINE_SIZE
2221 };
2222
2223 /**
2224  * intel_calculate_wm - calculate watermark level
2225  * @clock_in_khz: pixel clock
2226  * @wm: chip FIFO params
2227  * @pixel_size: display pixel size
2228  * @latency_ns: memory latency for the platform
2229  *
2230  * Calculate the watermark level (the level at which the display plane will
2231  * start fetching from memory again).  Each chip has a different display
2232  * FIFO size and allocation, so the caller needs to figure that out and pass
2233  * in the correct intel_watermark_params structure.
2234  *
2235  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2236  * on the pixel size.  When it reaches the watermark level, it'll start
2237  * fetching FIFO line sized based chunks from memory until the FIFO fills
2238  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2239  * will occur, and a display engine hang could result.
2240  */
2241 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2242                                         struct intel_watermark_params *wm,
2243                                         int pixel_size,
2244                                         unsigned long latency_ns)
2245 {
2246         long entries_required, wm_size;
2247
2248         /*
2249          * Note: we need to make sure we don't overflow for various clock &
2250          * latency values.
2251          * clocks go from a few thousand to several hundred thousand.
2252          * latency is usually a few thousand
2253          */
2254         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2255                 1000;
2256         entries_required /= wm->cacheline_size;
2257
2258         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2259
2260         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2261
2262         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2263
2264         /* Don't promote wm_size to unsigned... */
2265         if (wm_size > (long)wm->max_wm)
2266                 wm_size = wm->max_wm;
2267         if (wm_size <= 0)
2268                 wm_size = wm->default_wm;
2269         return wm_size;
2270 }
2271
2272 struct cxsr_latency {
2273         int is_desktop;
2274         unsigned long fsb_freq;
2275         unsigned long mem_freq;
2276         unsigned long display_sr;
2277         unsigned long display_hpll_disable;
2278         unsigned long cursor_sr;
2279         unsigned long cursor_hpll_disable;
2280 };
2281
2282 static struct cxsr_latency cxsr_latency_table[] = {
2283         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2284         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2285         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2286
2287         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2288         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2289         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2290
2291         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2292         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2293         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2294
2295         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2296         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2297         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2298
2299         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2300         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2301         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2302
2303         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2304         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2305         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2306 };
2307
2308 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2309                                                    int mem)
2310 {
2311         int i;
2312         struct cxsr_latency *latency;
2313
2314         if (fsb == 0 || mem == 0)
2315                 return NULL;
2316
2317         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2318                 latency = &cxsr_latency_table[i];
2319                 if (is_desktop == latency->is_desktop &&
2320                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2321                         return latency;
2322         }
2323
2324         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2325
2326         return NULL;
2327 }
2328
2329 static void igd_disable_cxsr(struct drm_device *dev)
2330 {
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         u32 reg;
2333
2334         /* deactivate cxsr */
2335         reg = I915_READ(DSPFW3);
2336         reg &= ~(IGD_SELF_REFRESH_EN);
2337         I915_WRITE(DSPFW3, reg);
2338         DRM_INFO("Big FIFO is disabled\n");
2339 }
2340
2341 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2342                             int pixel_size)
2343 {
2344         struct drm_i915_private *dev_priv = dev->dev_private;
2345         u32 reg;
2346         unsigned long wm;
2347         struct cxsr_latency *latency;
2348
2349         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2350                 dev_priv->mem_freq);
2351         if (!latency) {
2352                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2353                 igd_disable_cxsr(dev);
2354                 return;
2355         }
2356
2357         /* Display SR */
2358         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2359                                 latency->display_sr);
2360         reg = I915_READ(DSPFW1);
2361         reg &= 0x7fffff;
2362         reg |= wm << 23;
2363         I915_WRITE(DSPFW1, reg);
2364         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2365
2366         /* cursor SR */
2367         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2368                                 latency->cursor_sr);
2369         reg = I915_READ(DSPFW3);
2370         reg &= ~(0x3f << 24);
2371         reg |= (wm & 0x3f) << 24;
2372         I915_WRITE(DSPFW3, reg);
2373
2374         /* Display HPLL off SR */
2375         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2376                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2377         reg = I915_READ(DSPFW3);
2378         reg &= 0xfffffe00;
2379         reg |= wm & 0x1ff;
2380         I915_WRITE(DSPFW3, reg);
2381
2382         /* cursor HPLL off SR */
2383         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2384                                 latency->cursor_hpll_disable);
2385         reg = I915_READ(DSPFW3);
2386         reg &= ~(0x3f << 16);
2387         reg |= (wm & 0x3f) << 16;
2388         I915_WRITE(DSPFW3, reg);
2389         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2390
2391         /* activate cxsr */
2392         reg = I915_READ(DSPFW3);
2393         reg |= IGD_SELF_REFRESH_EN;
2394         I915_WRITE(DSPFW3, reg);
2395
2396         DRM_INFO("Big FIFO is enabled\n");
2397
2398         return;
2399 }
2400
2401 /*
2402  * Latency for FIFO fetches is dependent on several factors:
2403  *   - memory configuration (speed, channels)
2404  *   - chipset
2405  *   - current MCH state
2406  * It can be fairly high in some situations, so here we assume a fairly
2407  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2408  * set this value too high, the FIFO will fetch frequently to stay full)
2409  * and power consumption (set it too low to save power and we might see
2410  * FIFO underruns and display "flicker").
2411  *
2412  * A value of 5us seems to be a good balance; safe for very low end
2413  * platforms but not overly aggressive on lower latency configs.
2414  */
2415 const static int latency_ns = 5000;
2416
2417 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2418 {
2419         struct drm_i915_private *dev_priv = dev->dev_private;
2420         uint32_t dsparb = I915_READ(DSPARB);
2421         int size;
2422
2423         if (plane == 0)
2424                 size = dsparb & 0x7f;
2425         else
2426                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2427                         (dsparb & 0x7f);
2428
2429         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2430                         plane ? "B" : "A", size);
2431
2432         return size;
2433 }
2434
2435 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2436 {
2437         struct drm_i915_private *dev_priv = dev->dev_private;
2438         uint32_t dsparb = I915_READ(DSPARB);
2439         int size;
2440
2441         if (plane == 0)
2442                 size = dsparb & 0x1ff;
2443         else
2444                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2445                         (dsparb & 0x1ff);
2446         size >>= 1; /* Convert to cachelines */
2447
2448         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2449                         plane ? "B" : "A", size);
2450
2451         return size;
2452 }
2453
2454 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2455 {
2456         struct drm_i915_private *dev_priv = dev->dev_private;
2457         uint32_t dsparb = I915_READ(DSPARB);
2458         int size;
2459
2460         size = dsparb & 0x7f;
2461         size >>= 2; /* Convert to cachelines */
2462
2463         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2464                         plane ? "B" : "A",
2465                   size);
2466
2467         return size;
2468 }
2469
2470 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2471 {
2472         struct drm_i915_private *dev_priv = dev->dev_private;
2473         uint32_t dsparb = I915_READ(DSPARB);
2474         int size;
2475
2476         size = dsparb & 0x7f;
2477         size >>= 1; /* Convert to cachelines */
2478
2479         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2480                         plane ? "B" : "A", size);
2481
2482         return size;
2483 }
2484
2485 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2486                           int planeb_clock, int sr_hdisplay, int pixel_size)
2487 {
2488         struct drm_i915_private *dev_priv = dev->dev_private;
2489         int total_size, cacheline_size;
2490         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2491         struct intel_watermark_params planea_params, planeb_params;
2492         unsigned long line_time_us;
2493         int sr_clock, sr_entries = 0, entries_required;
2494
2495         /* Create copies of the base settings for each pipe */
2496         planea_params = planeb_params = g4x_wm_info;
2497
2498         /* Grab a couple of global values before we overwrite them */
2499         total_size = planea_params.fifo_size;
2500         cacheline_size = planea_params.cacheline_size;
2501
2502         /*
2503          * Note: we need to make sure we don't overflow for various clock &
2504          * latency values.
2505          * clocks go from a few thousand to several hundred thousand.
2506          * latency is usually a few thousand
2507          */
2508         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2509                 1000;
2510         entries_required /= G4X_FIFO_LINE_SIZE;
2511         planea_wm = entries_required + planea_params.guard_size;
2512
2513         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2514                 1000;
2515         entries_required /= G4X_FIFO_LINE_SIZE;
2516         planeb_wm = entries_required + planeb_params.guard_size;
2517
2518         cursora_wm = cursorb_wm = 16;
2519         cursor_sr = 32;
2520
2521         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2522
2523         /* Calc sr entries for one plane configs */
2524         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2525                 /* self-refresh has much higher latency */
2526                 const static int sr_latency_ns = 12000;
2527
2528                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2529                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2530
2531                 /* Use ns/us then divide to preserve precision */
2532                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2533                               pixel_size * sr_hdisplay) / 1000;
2534                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2535                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2536                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2537         }
2538
2539         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2540                   planea_wm, planeb_wm, sr_entries);
2541
2542         planea_wm &= 0x3f;
2543         planeb_wm &= 0x3f;
2544
2545         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2546                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2547                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2548         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2549                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2550         /* HPLL off in SR has some issues on G4x... disable it */
2551         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2552                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2553 }
2554
2555 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2556                            int planeb_clock, int sr_hdisplay, int pixel_size)
2557 {
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         unsigned long line_time_us;
2560         int sr_clock, sr_entries, srwm = 1;
2561
2562         /* Calc sr entries for one plane configs */
2563         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2564                 /* self-refresh has much higher latency */
2565                 const static int sr_latency_ns = 12000;
2566
2567                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2568                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2569
2570                 /* Use ns/us then divide to preserve precision */
2571                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2572                               pixel_size * sr_hdisplay) / 1000;
2573                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2574                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2575                 srwm = I945_FIFO_SIZE - sr_entries;
2576                 if (srwm < 0)
2577                         srwm = 1;
2578                 srwm &= 0x3f;
2579                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2580         }
2581
2582         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2583                       srwm);
2584
2585         /* 965 has limitations... */
2586         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2587                    (8 << 0));
2588         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2589 }
2590
2591 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2592                            int planeb_clock, int sr_hdisplay, int pixel_size)
2593 {
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         uint32_t fwater_lo;
2596         uint32_t fwater_hi;
2597         int total_size, cacheline_size, cwm, srwm = 1;
2598         int planea_wm, planeb_wm;
2599         struct intel_watermark_params planea_params, planeb_params;
2600         unsigned long line_time_us;
2601         int sr_clock, sr_entries = 0;
2602
2603         /* Create copies of the base settings for each pipe */
2604         if (IS_I965GM(dev) || IS_I945GM(dev))
2605                 planea_params = planeb_params = i945_wm_info;
2606         else if (IS_I9XX(dev))
2607                 planea_params = planeb_params = i915_wm_info;
2608         else
2609                 planea_params = planeb_params = i855_wm_info;
2610
2611         /* Grab a couple of global values before we overwrite them */
2612         total_size = planea_params.fifo_size;
2613         cacheline_size = planea_params.cacheline_size;
2614
2615         /* Update per-plane FIFO sizes */
2616         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2617         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2618
2619         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2620                                        pixel_size, latency_ns);
2621         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2622                                        pixel_size, latency_ns);
2623         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2624
2625         /*
2626          * Overlay gets an aggressive default since video jitter is bad.
2627          */
2628         cwm = 2;
2629
2630         /* Calc sr entries for one plane configs */
2631         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2632             (!planea_clock || !planeb_clock)) {
2633                 /* self-refresh has much higher latency */
2634                 const static int sr_latency_ns = 6000;
2635
2636                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2637                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2638
2639                 /* Use ns/us then divide to preserve precision */
2640                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2641                               pixel_size * sr_hdisplay) / 1000;
2642                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2643                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2644                 srwm = total_size - sr_entries;
2645                 if (srwm < 0)
2646                         srwm = 1;
2647                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2648         }
2649
2650         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2651                   planea_wm, planeb_wm, cwm, srwm);
2652
2653         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2654         fwater_hi = (cwm & 0x1f);
2655
2656         /* Set request length to 8 cachelines per fetch */
2657         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2658         fwater_hi = fwater_hi | (1 << 8);
2659
2660         I915_WRITE(FW_BLC, fwater_lo);
2661         I915_WRITE(FW_BLC2, fwater_hi);
2662 }
2663
2664 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2665                            int unused2, int pixel_size)
2666 {
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2669         int planea_wm;
2670
2671         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2672
2673         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2674                                        pixel_size, latency_ns);
2675         fwater_lo |= (3<<8) | planea_wm;
2676
2677         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2678
2679         I915_WRITE(FW_BLC, fwater_lo);
2680 }
2681
2682 /**
2683  * intel_update_watermarks - update FIFO watermark values based on current modes
2684  *
2685  * Calculate watermark values for the various WM regs based on current mode
2686  * and plane configuration.
2687  *
2688  * There are several cases to deal with here:
2689  *   - normal (i.e. non-self-refresh)
2690  *   - self-refresh (SR) mode
2691  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2692  *   - lines are small relative to FIFO size (buffer can hold more than 2
2693  *     lines), so need to account for TLB latency
2694  *
2695  *   The normal calculation is:
2696  *     watermark = dotclock * bytes per pixel * latency
2697  *   where latency is platform & configuration dependent (we assume pessimal
2698  *   values here).
2699  *
2700  *   The SR calculation is:
2701  *     watermark = (trunc(latency/line time)+1) * surface width *
2702  *       bytes per pixel
2703  *   where
2704  *     line time = htotal / dotclock
2705  *   and latency is assumed to be high, as above.
2706  *
2707  * The final value programmed to the register should always be rounded up,
2708  * and include an extra 2 entries to account for clock crossings.
2709  *
2710  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2711  * to set the non-SR watermarks to 8.
2712   */
2713 static void intel_update_watermarks(struct drm_device *dev)
2714 {
2715         struct drm_i915_private *dev_priv = dev->dev_private;
2716         struct drm_crtc *crtc;
2717         struct intel_crtc *intel_crtc;
2718         int sr_hdisplay = 0;
2719         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2720         int enabled = 0, pixel_size = 0;
2721
2722         if (!dev_priv->display.update_wm)
2723                 return;
2724
2725         /* Get the clock config from both planes */
2726         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2727                 intel_crtc = to_intel_crtc(crtc);
2728                 if (crtc->enabled) {
2729                         enabled++;
2730                         if (intel_crtc->plane == 0) {
2731                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2732                                           intel_crtc->pipe, crtc->mode.clock);
2733                                 planea_clock = crtc->mode.clock;
2734                         } else {
2735                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2736                                           intel_crtc->pipe, crtc->mode.clock);
2737                                 planeb_clock = crtc->mode.clock;
2738                         }
2739                         sr_hdisplay = crtc->mode.hdisplay;
2740                         sr_clock = crtc->mode.clock;
2741                         if (crtc->fb)
2742                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2743                         else
2744                                 pixel_size = 4; /* by default */
2745                 }
2746         }
2747
2748         if (enabled <= 0)
2749                 return;
2750
2751         /* Single plane configs can enable self refresh */
2752         if (enabled == 1 && IS_IGD(dev))
2753                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2754         else if (IS_IGD(dev))
2755                 igd_disable_cxsr(dev);
2756
2757         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2758                                     sr_hdisplay, pixel_size);
2759 }
2760
2761 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2762                                struct drm_display_mode *mode,
2763                                struct drm_display_mode *adjusted_mode,
2764                                int x, int y,
2765                                struct drm_framebuffer *old_fb)
2766 {
2767         struct drm_device *dev = crtc->dev;
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770         int pipe = intel_crtc->pipe;
2771         int plane = intel_crtc->plane;
2772         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2773         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2774         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2775         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2776         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2777         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2778         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2779         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2780         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2781         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2782         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2783         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2784         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2785         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2786         int refclk, num_outputs = 0;
2787         intel_clock_t clock, reduced_clock;
2788         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2789         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2790         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2791         bool is_edp = false;
2792         struct drm_mode_config *mode_config = &dev->mode_config;
2793         struct drm_connector *connector;
2794         const intel_limit_t *limit;
2795         int ret;
2796         struct fdi_m_n m_n = {0};
2797         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2798         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2799         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2800         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2801         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2802         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2803         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2804         int lvds_reg = LVDS;
2805         u32 temp;
2806         int sdvo_pixel_multiply;
2807         int target_clock;
2808
2809         drm_vblank_pre_modeset(dev, pipe);
2810
2811         list_for_each_entry(connector, &mode_config->connector_list, head) {
2812                 struct intel_output *intel_output = to_intel_output(connector);
2813
2814                 if (!connector->encoder || connector->encoder->crtc != crtc)
2815                         continue;
2816
2817                 switch (intel_output->type) {
2818                 case INTEL_OUTPUT_LVDS:
2819                         is_lvds = true;
2820                         break;
2821                 case INTEL_OUTPUT_SDVO:
2822                 case INTEL_OUTPUT_HDMI:
2823                         is_sdvo = true;
2824                         if (intel_output->needs_tv_clock)
2825                                 is_tv = true;
2826                         break;
2827                 case INTEL_OUTPUT_DVO:
2828                         is_dvo = true;
2829                         break;
2830                 case INTEL_OUTPUT_TVOUT:
2831                         is_tv = true;
2832                         break;
2833                 case INTEL_OUTPUT_ANALOG:
2834                         is_crt = true;
2835                         break;
2836                 case INTEL_OUTPUT_DISPLAYPORT:
2837                         is_dp = true;
2838                         break;
2839                 case INTEL_OUTPUT_EDP:
2840                         is_edp = true;
2841                         break;
2842                 }
2843
2844                 num_outputs++;
2845         }
2846
2847         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2848                 refclk = dev_priv->lvds_ssc_freq * 1000;
2849                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2850                                         refclk / 1000);
2851         } else if (IS_I9XX(dev)) {
2852                 refclk = 96000;
2853                 if (IS_IGDNG(dev))
2854                         refclk = 120000; /* 120Mhz refclk */
2855         } else {
2856                 refclk = 48000;
2857         }
2858
2859
2860         /*
2861          * Returns a set of divisors for the desired target clock with the given
2862          * refclk, or FALSE.  The returned values represent the clock equation:
2863          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2864          */
2865         limit = intel_limit(crtc);
2866         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2867         if (!ok) {
2868                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2869                 drm_vblank_post_modeset(dev, pipe);
2870                 return -EINVAL;
2871         }
2872
2873         if (is_lvds && limit->find_reduced_pll &&
2874                         dev_priv->lvds_downclock_avail) {
2875                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2876                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2877                                                             dev_priv->lvds_downclock,
2878                                                             refclk,
2879                                                             &reduced_clock);
2880                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2881                         /*
2882                          * If the different P is found, it means that we can't
2883                          * switch the display clock by using the FP0/FP1.
2884                          * In such case we will disable the LVDS downclock
2885                          * feature.
2886                          */
2887                         DRM_DEBUG_KMS("Different P is found for "
2888                                                 "LVDS clock/downclock\n");
2889                         has_reduced_clock = 0;
2890                 }
2891         }
2892         /* SDVO TV has fixed PLL values depend on its clock range,
2893            this mirrors vbios setting. */
2894         if (is_sdvo && is_tv) {
2895                 if (adjusted_mode->clock >= 100000
2896                                 && adjusted_mode->clock < 140500) {
2897                         clock.p1 = 2;
2898                         clock.p2 = 10;
2899                         clock.n = 3;
2900                         clock.m1 = 16;
2901                         clock.m2 = 8;
2902                 } else if (adjusted_mode->clock >= 140500
2903                                 && adjusted_mode->clock <= 200000) {
2904                         clock.p1 = 1;
2905                         clock.p2 = 10;
2906                         clock.n = 6;
2907                         clock.m1 = 12;
2908                         clock.m2 = 8;
2909                 }
2910         }
2911
2912         /* FDI link */
2913         if (IS_IGDNG(dev)) {
2914                 int lane, link_bw, bpp;
2915                 /* eDP doesn't require FDI link, so just set DP M/N
2916                    according to current link config */
2917                 if (is_edp) {
2918                         struct drm_connector *edp;
2919                         target_clock = mode->clock;
2920                         edp = intel_pipe_get_output(crtc);
2921                         intel_edp_link_config(to_intel_output(edp),
2922                                         &lane, &link_bw);
2923                 } else {
2924                         /* DP over FDI requires target mode clock
2925                            instead of link clock */
2926                         if (is_dp)
2927                                 target_clock = mode->clock;
2928                         else
2929                                 target_clock = adjusted_mode->clock;
2930                         lane = 4;
2931                         link_bw = 270000;
2932                 }
2933
2934                 /* determine panel color depth */
2935                 temp = I915_READ(pipeconf_reg);
2936
2937                 switch (temp & PIPE_BPC_MASK) {
2938                 case PIPE_8BPC:
2939                         bpp = 24;
2940                         break;
2941                 case PIPE_10BPC:
2942                         bpp = 30;
2943                         break;
2944                 case PIPE_6BPC:
2945                         bpp = 18;
2946                         break;
2947                 case PIPE_12BPC:
2948                         bpp = 36;
2949                         break;
2950                 default:
2951                         DRM_ERROR("unknown pipe bpc value\n");
2952                         bpp = 24;
2953                 }
2954
2955                 igdng_compute_m_n(bpp, lane, target_clock,
2956                                   link_bw, &m_n);
2957         }
2958
2959         /* Ironlake: try to setup display ref clock before DPLL
2960          * enabling. This is only under driver's control after
2961          * PCH B stepping, previous chipset stepping should be
2962          * ignoring this setting.
2963          */
2964         if (IS_IGDNG(dev)) {
2965                 temp = I915_READ(PCH_DREF_CONTROL);
2966                 /* Always enable nonspread source */
2967                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2968                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2969                 I915_WRITE(PCH_DREF_CONTROL, temp);
2970                 POSTING_READ(PCH_DREF_CONTROL);
2971
2972                 temp &= ~DREF_SSC_SOURCE_MASK;
2973                 temp |= DREF_SSC_SOURCE_ENABLE;
2974                 I915_WRITE(PCH_DREF_CONTROL, temp);
2975                 POSTING_READ(PCH_DREF_CONTROL);
2976
2977                 udelay(200);
2978
2979                 if (is_edp) {
2980                         if (dev_priv->lvds_use_ssc) {
2981                                 temp |= DREF_SSC1_ENABLE;
2982                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2983                                 POSTING_READ(PCH_DREF_CONTROL);
2984
2985                                 udelay(200);
2986
2987                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2988                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2989                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2990                                 POSTING_READ(PCH_DREF_CONTROL);
2991                         } else {
2992                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2993                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2994                                 POSTING_READ(PCH_DREF_CONTROL);
2995                         }
2996                 }
2997         }
2998
2999         if (IS_IGD(dev)) {
3000                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3001                 if (has_reduced_clock)
3002                         fp2 = (1 << reduced_clock.n) << 16 |
3003                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3004         } else {
3005                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3006                 if (has_reduced_clock)
3007                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3008                                 reduced_clock.m2;
3009         }
3010
3011         if (!IS_IGDNG(dev))
3012                 dpll = DPLL_VGA_MODE_DIS;
3013
3014         if (IS_I9XX(dev)) {
3015                 if (is_lvds)
3016                         dpll |= DPLLB_MODE_LVDS;
3017                 else
3018                         dpll |= DPLLB_MODE_DAC_SERIAL;
3019                 if (is_sdvo) {
3020                         dpll |= DPLL_DVO_HIGH_SPEED;
3021                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3022                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3023                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3024                         else if (IS_IGDNG(dev))
3025                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3026                 }
3027                 if (is_dp)
3028                         dpll |= DPLL_DVO_HIGH_SPEED;
3029
3030                 /* compute bitmask from p1 value */
3031                 if (IS_IGD(dev))
3032                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
3033                 else {
3034                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3035                         /* also FPA1 */
3036                         if (IS_IGDNG(dev))
3037                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3038                         if (IS_G4X(dev) && has_reduced_clock)
3039                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3040                 }
3041                 switch (clock.p2) {
3042                 case 5:
3043                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3044                         break;
3045                 case 7:
3046                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3047                         break;
3048                 case 10:
3049                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3050                         break;
3051                 case 14:
3052                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3053                         break;
3054                 }
3055                 if (IS_I965G(dev) && !IS_IGDNG(dev))
3056                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3057         } else {
3058                 if (is_lvds) {
3059                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3060                 } else {
3061                         if (clock.p1 == 2)
3062                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3063                         else
3064                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3065                         if (clock.p2 == 4)
3066                                 dpll |= PLL_P2_DIVIDE_BY_4;
3067                 }
3068         }
3069
3070         if (is_sdvo && is_tv)
3071                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3072         else if (is_tv)
3073                 /* XXX: just matching BIOS for now */
3074                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3075                 dpll |= 3;
3076         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3077                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3078         else
3079                 dpll |= PLL_REF_INPUT_DREFCLK;
3080
3081         /* setup pipeconf */
3082         pipeconf = I915_READ(pipeconf_reg);
3083
3084         /* Set up the display plane register */
3085         dspcntr = DISPPLANE_GAMMA_ENABLE;
3086
3087         /* IGDNG's plane is forced to pipe, bit 24 is to
3088            enable color space conversion */
3089         if (!IS_IGDNG(dev)) {
3090                 if (pipe == 0)
3091                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3092                 else
3093                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3094         }
3095
3096         if (pipe == 0 && !IS_I965G(dev)) {
3097                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3098                  * core speed.
3099                  *
3100                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3101                  * pipe == 0 check?
3102                  */
3103                 if (mode->clock >
3104                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3105                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3106                 else
3107                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3108         }
3109
3110         dspcntr |= DISPLAY_PLANE_ENABLE;
3111         pipeconf |= PIPEACONF_ENABLE;
3112         dpll |= DPLL_VCO_ENABLE;
3113
3114
3115         /* Disable the panel fitter if it was on our pipe */
3116         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3117                 I915_WRITE(PFIT_CONTROL, 0);
3118
3119         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3120         drm_mode_debug_printmodeline(mode);
3121
3122         /* assign to IGDNG registers */
3123         if (IS_IGDNG(dev)) {
3124                 fp_reg = pch_fp_reg;
3125                 dpll_reg = pch_dpll_reg;
3126         }
3127
3128         if (is_edp) {
3129                 igdng_disable_pll_edp(crtc);
3130         } else if ((dpll & DPLL_VCO_ENABLE)) {
3131                 I915_WRITE(fp_reg, fp);
3132                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3133                 I915_READ(dpll_reg);
3134                 udelay(150);
3135         }
3136
3137         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3138          * This is an exception to the general rule that mode_set doesn't turn
3139          * things on.
3140          */
3141         if (is_lvds) {
3142                 u32 lvds;
3143
3144                 if (IS_IGDNG(dev))
3145                         lvds_reg = PCH_LVDS;
3146
3147                 lvds = I915_READ(lvds_reg);
3148                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3149                 /* set the corresponsding LVDS_BORDER bit */
3150                 lvds |= dev_priv->lvds_border_bits;
3151                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3152                  * set the DPLLs for dual-channel mode or not.
3153                  */
3154                 if (clock.p2 == 7)
3155                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3156                 else
3157                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3158
3159                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3160                  * appropriately here, but we need to look more thoroughly into how
3161                  * panels behave in the two modes.
3162                  */
3163
3164                 I915_WRITE(lvds_reg, lvds);
3165                 I915_READ(lvds_reg);
3166         }
3167         if (is_dp)
3168                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3169
3170         if (!is_edp) {
3171                 I915_WRITE(fp_reg, fp);
3172                 I915_WRITE(dpll_reg, dpll);
3173                 I915_READ(dpll_reg);
3174                 /* Wait for the clocks to stabilize. */
3175                 udelay(150);
3176
3177                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3178                         if (is_sdvo) {
3179                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3180                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3181                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3182                         } else
3183                                 I915_WRITE(dpll_md_reg, 0);
3184                 } else {
3185                         /* write it again -- the BIOS does, after all */
3186                         I915_WRITE(dpll_reg, dpll);
3187                 }
3188                 I915_READ(dpll_reg);
3189                 /* Wait for the clocks to stabilize. */
3190                 udelay(150);
3191         }
3192
3193         if (is_lvds && has_reduced_clock && i915_powersave) {
3194                 I915_WRITE(fp_reg + 4, fp2);
3195                 intel_crtc->lowfreq_avail = true;
3196                 if (HAS_PIPE_CXSR(dev)) {
3197                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3198                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3199                 }
3200         } else {
3201                 I915_WRITE(fp_reg + 4, fp);
3202                 intel_crtc->lowfreq_avail = false;
3203                 if (HAS_PIPE_CXSR(dev)) {
3204                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3205                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3206                 }
3207         }
3208
3209         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3210                    ((adjusted_mode->crtc_htotal - 1) << 16));
3211         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3212                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3213         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3214                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3215         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3216                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3217         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3218                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3219         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3220                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3221         /* pipesrc and dspsize control the size that is scaled from, which should
3222          * always be the user's requested size.
3223          */
3224         if (!IS_IGDNG(dev)) {
3225                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3226                                 (mode->hdisplay - 1));
3227                 I915_WRITE(dsppos_reg, 0);
3228         }
3229         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3230
3231         if (IS_IGDNG(dev)) {
3232                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3233                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3234                 I915_WRITE(link_m1_reg, m_n.link_m);
3235                 I915_WRITE(link_n1_reg, m_n.link_n);
3236
3237                 if (is_edp) {
3238                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
3239                 } else {
3240                         /* enable FDI RX PLL too */
3241                         temp = I915_READ(fdi_rx_reg);
3242                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3243                         udelay(200);
3244                 }
3245         }
3246
3247         I915_WRITE(pipeconf_reg, pipeconf);
3248         I915_READ(pipeconf_reg);
3249
3250         intel_wait_for_vblank(dev);
3251
3252         if (IS_IGDNG(dev)) {
3253                 /* enable address swizzle for tiling buffer */
3254                 temp = I915_READ(DISP_ARB_CTL);
3255                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3256         }
3257
3258         I915_WRITE(dspcntr_reg, dspcntr);
3259
3260         /* Flush the plane changes */
3261         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3262
3263         if ((IS_I965G(dev) || plane == 0))
3264                 intel_update_fbc(crtc, &crtc->mode);
3265
3266         intel_update_watermarks(dev);
3267
3268         drm_vblank_post_modeset(dev, pipe);
3269
3270         return ret;
3271 }
3272
3273 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3274 void intel_crtc_load_lut(struct drm_crtc *crtc)
3275 {
3276         struct drm_device *dev = crtc->dev;
3277         struct drm_i915_private *dev_priv = dev->dev_private;
3278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3279         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3280         int i;
3281
3282         /* The clocks have to be on to load the palette. */
3283         if (!crtc->enabled)
3284                 return;
3285
3286         /* use legacy palette for IGDNG */
3287         if (IS_IGDNG(dev))
3288                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3289                                                    LGC_PALETTE_B;
3290
3291         for (i = 0; i < 256; i++) {
3292                 I915_WRITE(palreg + 4 * i,
3293                            (intel_crtc->lut_r[i] << 16) |
3294                            (intel_crtc->lut_g[i] << 8) |
3295                            intel_crtc->lut_b[i]);
3296         }
3297 }
3298
3299 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3300                                  struct drm_file *file_priv,
3301                                  uint32_t handle,
3302                                  uint32_t width, uint32_t height)
3303 {
3304         struct drm_device *dev = crtc->dev;
3305         struct drm_i915_private *dev_priv = dev->dev_private;
3306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3307         struct drm_gem_object *bo;
3308         struct drm_i915_gem_object *obj_priv;
3309         int pipe = intel_crtc->pipe;
3310         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3311         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3312         uint32_t temp = I915_READ(control);
3313         size_t addr;
3314         int ret;
3315
3316         DRM_DEBUG_KMS("\n");
3317
3318         /* if we want to turn off the cursor ignore width and height */
3319         if (!handle) {
3320                 DRM_DEBUG_KMS("cursor off\n");
3321                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3322                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3323                         temp |= CURSOR_MODE_DISABLE;
3324                 } else {
3325                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3326                 }
3327                 addr = 0;
3328                 bo = NULL;
3329                 mutex_lock(&dev->struct_mutex);
3330                 goto finish;
3331         }
3332
3333         /* Currently we only support 64x64 cursors */
3334         if (width != 64 || height != 64) {
3335                 DRM_ERROR("we currently only support 64x64 cursors\n");
3336                 return -EINVAL;
3337         }
3338
3339         bo = drm_gem_object_lookup(dev, file_priv, handle);
3340         if (!bo)
3341                 return -ENOENT;
3342
3343         obj_priv = bo->driver_private;
3344
3345         if (bo->size < width * height * 4) {
3346                 DRM_ERROR("buffer is to small\n");
3347                 ret = -ENOMEM;
3348                 goto fail;
3349         }
3350
3351         /* we only need to pin inside GTT if cursor is non-phy */
3352         mutex_lock(&dev->struct_mutex);
3353         if (!dev_priv->cursor_needs_physical) {
3354                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3355                 if (ret) {
3356                         DRM_ERROR("failed to pin cursor bo\n");
3357                         goto fail_locked;
3358                 }
3359                 addr = obj_priv->gtt_offset;
3360         } else {
3361                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3362                 if (ret) {
3363                         DRM_ERROR("failed to attach phys object\n");
3364                         goto fail_locked;
3365                 }
3366                 addr = obj_priv->phys_obj->handle->busaddr;
3367         }
3368
3369         if (!IS_I9XX(dev))
3370                 I915_WRITE(CURSIZE, (height << 12) | width);
3371
3372         /* Hooray for CUR*CNTR differences */
3373         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3374                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3375                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3376                 temp |= (pipe << 28); /* Connect to correct pipe */
3377         } else {
3378                 temp &= ~(CURSOR_FORMAT_MASK);
3379                 temp |= CURSOR_ENABLE;
3380                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3381         }
3382
3383  finish:
3384         I915_WRITE(control, temp);
3385         I915_WRITE(base, addr);
3386
3387         if (intel_crtc->cursor_bo) {
3388                 if (dev_priv->cursor_needs_physical) {
3389                         if (intel_crtc->cursor_bo != bo)
3390                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3391                 } else
3392                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3393                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3394         }
3395
3396         mutex_unlock(&dev->struct_mutex);
3397
3398         intel_crtc->cursor_addr = addr;
3399         intel_crtc->cursor_bo = bo;
3400
3401         return 0;
3402 fail:
3403         mutex_lock(&dev->struct_mutex);
3404 fail_locked:
3405         drm_gem_object_unreference(bo);
3406         mutex_unlock(&dev->struct_mutex);
3407         return ret;
3408 }
3409
3410 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3411 {
3412         struct drm_device *dev = crtc->dev;
3413         struct drm_i915_private *dev_priv = dev->dev_private;
3414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415         struct intel_framebuffer *intel_fb;
3416         int pipe = intel_crtc->pipe;
3417         uint32_t temp = 0;
3418         uint32_t adder;
3419
3420         if (crtc->fb) {
3421                 intel_fb = to_intel_framebuffer(crtc->fb);
3422                 intel_mark_busy(dev, intel_fb->obj);
3423         }
3424
3425         if (x < 0) {
3426                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3427                 x = -x;
3428         }
3429         if (y < 0) {
3430                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3431                 y = -y;
3432         }
3433
3434         temp |= x << CURSOR_X_SHIFT;
3435         temp |= y << CURSOR_Y_SHIFT;
3436
3437         adder = intel_crtc->cursor_addr;
3438         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3439         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3440
3441         return 0;
3442 }
3443
3444 /** Sets the color ramps on behalf of RandR */
3445 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3446                                  u16 blue, int regno)
3447 {
3448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3449
3450         intel_crtc->lut_r[regno] = red >> 8;
3451         intel_crtc->lut_g[regno] = green >> 8;
3452         intel_crtc->lut_b[regno] = blue >> 8;
3453 }
3454
3455 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3456                              u16 *blue, int regno)
3457 {
3458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3459
3460         *red = intel_crtc->lut_r[regno] << 8;
3461         *green = intel_crtc->lut_g[regno] << 8;
3462         *blue = intel_crtc->lut_b[regno] << 8;
3463 }
3464
3465 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3466                                  u16 *blue, uint32_t size)
3467 {
3468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3469         int i;
3470
3471         if (size != 256)
3472                 return;
3473
3474         for (i = 0; i < 256; i++) {
3475                 intel_crtc->lut_r[i] = red[i] >> 8;
3476                 intel_crtc->lut_g[i] = green[i] >> 8;
3477                 intel_crtc->lut_b[i] = blue[i] >> 8;
3478         }
3479
3480         intel_crtc_load_lut(crtc);
3481 }
3482
3483 /**
3484  * Get a pipe with a simple mode set on it for doing load-based monitor
3485  * detection.
3486  *
3487  * It will be up to the load-detect code to adjust the pipe as appropriate for
3488  * its requirements.  The pipe will be connected to no other outputs.
3489  *
3490  * Currently this code will only succeed if there is a pipe with no outputs
3491  * configured for it.  In the future, it could choose to temporarily disable
3492  * some outputs to free up a pipe for its use.
3493  *
3494  * \return crtc, or NULL if no pipes are available.
3495  */
3496
3497 /* VESA 640x480x72Hz mode to set on the pipe */
3498 static struct drm_display_mode load_detect_mode = {
3499         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3500                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3501 };
3502
3503 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3504                                             struct drm_display_mode *mode,
3505                                             int *dpms_mode)
3506 {
3507         struct intel_crtc *intel_crtc;
3508         struct drm_crtc *possible_crtc;
3509         struct drm_crtc *supported_crtc =NULL;
3510         struct drm_encoder *encoder = &intel_output->enc;
3511         struct drm_crtc *crtc = NULL;
3512         struct drm_device *dev = encoder->dev;
3513         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3514         struct drm_crtc_helper_funcs *crtc_funcs;
3515         int i = -1;
3516
3517         /*
3518          * Algorithm gets a little messy:
3519          *   - if the connector already has an assigned crtc, use it (but make
3520          *     sure it's on first)
3521          *   - try to find the first unused crtc that can drive this connector,
3522          *     and use that if we find one
3523          *   - if there are no unused crtcs available, try to use the first
3524          *     one we found that supports the connector
3525          */
3526
3527         /* See if we already have a CRTC for this connector */
3528         if (encoder->crtc) {
3529                 crtc = encoder->crtc;
3530                 /* Make sure the crtc and connector are running */
3531                 intel_crtc = to_intel_crtc(crtc);
3532                 *dpms_mode = intel_crtc->dpms_mode;
3533                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3534                         crtc_funcs = crtc->helper_private;
3535                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3536                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3537                 }
3538                 return crtc;
3539         }
3540
3541         /* Find an unused one (if possible) */
3542         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3543                 i++;
3544                 if (!(encoder->possible_crtcs & (1 << i)))
3545                         continue;
3546                 if (!possible_crtc->enabled) {
3547                         crtc = possible_crtc;
3548                         break;
3549                 }
3550                 if (!supported_crtc)
3551                         supported_crtc = possible_crtc;
3552         }
3553
3554         /*
3555          * If we didn't find an unused CRTC, don't use any.
3556          */
3557         if (!crtc) {
3558                 return NULL;
3559         }
3560
3561         encoder->crtc = crtc;
3562         intel_output->base.encoder = encoder;
3563         intel_output->load_detect_temp = true;
3564
3565         intel_crtc = to_intel_crtc(crtc);
3566         *dpms_mode = intel_crtc->dpms_mode;
3567
3568         if (!crtc->enabled) {
3569                 if (!mode)
3570                         mode = &load_detect_mode;
3571                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3572         } else {
3573                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3574                         crtc_funcs = crtc->helper_private;
3575                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3576                 }
3577
3578                 /* Add this connector to the crtc */
3579                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3580                 encoder_funcs->commit(encoder);
3581         }
3582         /* let the connector get through one full cycle before testing */
3583         intel_wait_for_vblank(dev);
3584
3585         return crtc;
3586 }
3587
3588 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3589 {
3590         struct drm_encoder *encoder = &intel_output->enc;
3591         struct drm_device *dev = encoder->dev;
3592         struct drm_crtc *crtc = encoder->crtc;
3593         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3594         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3595
3596         if (intel_output->load_detect_temp) {
3597                 encoder->crtc = NULL;
3598                 intel_output->base.encoder = NULL;
3599                 intel_output->load_detect_temp = false;
3600                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3601                 drm_helper_disable_unused_functions(dev);
3602         }
3603
3604         /* Switch crtc and output back off if necessary */
3605         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3606                 if (encoder->crtc == crtc)
3607                         encoder_funcs->dpms(encoder, dpms_mode);
3608                 crtc_funcs->dpms(crtc, dpms_mode);
3609         }
3610 }
3611
3612 /* Returns the clock of the currently programmed mode of the given pipe. */
3613 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3614 {
3615         struct drm_i915_private *dev_priv = dev->dev_private;
3616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617         int pipe = intel_crtc->pipe;
3618         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3619         u32 fp;
3620         intel_clock_t clock;
3621
3622         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3623                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3624         else
3625                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3626
3627         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3628         if (IS_IGD(dev)) {
3629                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3630                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3631         } else {
3632                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3633                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3634         }
3635
3636         if (IS_I9XX(dev)) {
3637                 if (IS_IGD(dev))
3638                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3639                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3640                 else
3641                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3642                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3643
3644                 switch (dpll & DPLL_MODE_MASK) {
3645                 case DPLLB_MODE_DAC_SERIAL:
3646                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3647                                 5 : 10;
3648                         break;
3649                 case DPLLB_MODE_LVDS:
3650                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3651                                 7 : 14;
3652                         break;
3653                 default:
3654                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3655                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3656                         return 0;
3657                 }
3658
3659                 /* XXX: Handle the 100Mhz refclk */
3660                 intel_clock(dev, 96000, &clock);
3661         } else {
3662                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3663
3664                 if (is_lvds) {
3665                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3666                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3667                         clock.p2 = 14;
3668
3669                         if ((dpll & PLL_REF_INPUT_MASK) ==
3670                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3671                                 /* XXX: might not be 66MHz */
3672                                 intel_clock(dev, 66000, &clock);
3673                         } else
3674                                 intel_clock(dev, 48000, &clock);
3675                 } else {
3676                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3677                                 clock.p1 = 2;
3678                         else {
3679                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3680                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3681                         }
3682                         if (dpll & PLL_P2_DIVIDE_BY_4)
3683                                 clock.p2 = 4;
3684                         else
3685                                 clock.p2 = 2;
3686
3687                         intel_clock(dev, 48000, &clock);
3688                 }
3689         }
3690
3691         /* XXX: It would be nice to validate the clocks, but we can't reuse
3692          * i830PllIsValid() because it relies on the xf86_config connector
3693          * configuration being accurate, which it isn't necessarily.
3694          */
3695
3696         return clock.dot;
3697 }
3698
3699 /** Returns the currently programmed mode of the given pipe. */
3700 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3701                                              struct drm_crtc *crtc)
3702 {
3703         struct drm_i915_private *dev_priv = dev->dev_private;
3704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705         int pipe = intel_crtc->pipe;
3706         struct drm_display_mode *mode;
3707         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3708         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3709         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3710         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3711
3712         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3713         if (!mode)
3714                 return NULL;
3715
3716         mode->clock = intel_crtc_clock_get(dev, crtc);
3717         mode->hdisplay = (htot & 0xffff) + 1;
3718         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3719         mode->hsync_start = (hsync & 0xffff) + 1;
3720         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3721         mode->vdisplay = (vtot & 0xffff) + 1;
3722         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3723         mode->vsync_start = (vsync & 0xffff) + 1;
3724         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3725
3726         drm_mode_set_name(mode);
3727         drm_mode_set_crtcinfo(mode, 0);
3728
3729         return mode;
3730 }
3731
3732 #define GPU_IDLE_TIMEOUT 500 /* ms */
3733
3734 /* When this timer fires, we've been idle for awhile */
3735 static void intel_gpu_idle_timer(unsigned long arg)
3736 {
3737         struct drm_device *dev = (struct drm_device *)arg;
3738         drm_i915_private_t *dev_priv = dev->dev_private;
3739
3740         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3741
3742         dev_priv->busy = false;
3743
3744         queue_work(dev_priv->wq, &dev_priv->idle_work);
3745 }
3746
3747 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3748 {
3749         drm_i915_private_t *dev_priv = dev->dev_private;
3750
3751         if (IS_IGDNG(dev))
3752                 return;
3753
3754         if (!dev_priv->render_reclock_avail) {
3755                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3756                 return;
3757         }
3758
3759         /* Restore render clock frequency to original value */
3760         if (IS_G4X(dev) || IS_I9XX(dev))
3761                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3762         else if (IS_I85X(dev))
3763                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3764         DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3765
3766         /* Schedule downclock */
3767         if (schedule)
3768                 mod_timer(&dev_priv->idle_timer, jiffies +
3769                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3770 }
3771
3772 void intel_decrease_renderclock(struct drm_device *dev)
3773 {
3774         drm_i915_private_t *dev_priv = dev->dev_private;
3775
3776         if (IS_IGDNG(dev))
3777                 return;
3778
3779         if (!dev_priv->render_reclock_avail) {
3780                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3781                 return;
3782         }
3783
3784         if (IS_G4X(dev)) {
3785                 u16 gcfgc;
3786
3787                 /* Adjust render clock... */
3788                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3789
3790                 /* Down to minimum... */
3791                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3792                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3793
3794                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3795         } else if (IS_I965G(dev)) {
3796                 u16 gcfgc;
3797
3798                 /* Adjust render clock... */
3799                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3800
3801                 /* Down to minimum... */
3802                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3803                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3804
3805                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3806         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3807                 u16 gcfgc;
3808
3809                 /* Adjust render clock... */
3810                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3811
3812                 /* Down to minimum... */
3813                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3814                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3815
3816                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3817         } else if (IS_I915G(dev)) {
3818                 u16 gcfgc;
3819
3820                 /* Adjust render clock... */
3821                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3822
3823                 /* Down to minimum... */
3824                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3825                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3826
3827                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3828         } else if (IS_I85X(dev)) {
3829                 u16 hpllcc;
3830
3831                 /* Adjust render clock... */
3832                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3833
3834                 /* Up to maximum... */
3835                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3836                 hpllcc |= GC_CLOCK_133_200;
3837
3838                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3839         }
3840         DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3841 }
3842
3843 /* Note that no increase function is needed for this - increase_renderclock()
3844  *  will also rewrite these bits
3845  */
3846 void intel_decrease_displayclock(struct drm_device *dev)
3847 {
3848         if (IS_IGDNG(dev))
3849                 return;
3850
3851         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3852             IS_I915GM(dev)) {
3853                 u16 gcfgc;
3854
3855                 /* Adjust render clock... */
3856                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3857
3858                 /* Down to minimum... */
3859                 gcfgc &= ~0xf0;
3860                 gcfgc |= 0x80;
3861
3862                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3863         }
3864 }
3865
3866 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3867
3868 static void intel_crtc_idle_timer(unsigned long arg)
3869 {
3870         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3871         struct drm_crtc *crtc = &intel_crtc->base;
3872         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3873
3874         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3875
3876         intel_crtc->busy = false;
3877
3878         queue_work(dev_priv->wq, &dev_priv->idle_work);
3879 }
3880
3881 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3882 {
3883         struct drm_device *dev = crtc->dev;
3884         drm_i915_private_t *dev_priv = dev->dev_private;
3885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3886         int pipe = intel_crtc->pipe;
3887         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3888         int dpll = I915_READ(dpll_reg);
3889
3890         if (IS_IGDNG(dev))
3891                 return;
3892
3893         if (!dev_priv->lvds_downclock_avail)
3894                 return;
3895
3896         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3897                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3898
3899                 /* Unlock panel regs */
3900                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3901
3902                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3903                 I915_WRITE(dpll_reg, dpll);
3904                 dpll = I915_READ(dpll_reg);
3905                 intel_wait_for_vblank(dev);
3906                 dpll = I915_READ(dpll_reg);
3907                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3908                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3909
3910                 /* ...and lock them again */
3911                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3912         }
3913
3914         /* Schedule downclock */
3915         if (schedule)
3916                 mod_timer(&intel_crtc->idle_timer, jiffies +
3917                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3918 }
3919
3920 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3921 {
3922         struct drm_device *dev = crtc->dev;
3923         drm_i915_private_t *dev_priv = dev->dev_private;
3924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3925         int pipe = intel_crtc->pipe;
3926         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3927         int dpll = I915_READ(dpll_reg);
3928
3929         if (IS_IGDNG(dev))
3930                 return;
3931
3932         if (!dev_priv->lvds_downclock_avail)
3933                 return;
3934
3935         /*
3936          * Since this is called by a timer, we should never get here in
3937          * the manual case.
3938          */
3939         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3940                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3941
3942                 /* Unlock panel regs */
3943                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3944
3945                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3946                 I915_WRITE(dpll_reg, dpll);
3947                 dpll = I915_READ(dpll_reg);
3948                 intel_wait_for_vblank(dev);
3949                 dpll = I915_READ(dpll_reg);
3950                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3951                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3952
3953                 /* ...and lock them again */
3954                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3955         }
3956
3957 }
3958
3959 /**
3960  * intel_idle_update - adjust clocks for idleness
3961  * @work: work struct
3962  *
3963  * Either the GPU or display (or both) went idle.  Check the busy status
3964  * here and adjust the CRTC and GPU clocks as necessary.
3965  */
3966 static void intel_idle_update(struct work_struct *work)
3967 {
3968         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3969                                                     idle_work);
3970         struct drm_device *dev = dev_priv->dev;
3971         struct drm_crtc *crtc;
3972         struct intel_crtc *intel_crtc;
3973
3974         if (!i915_powersave)
3975                 return;
3976
3977         mutex_lock(&dev->struct_mutex);
3978
3979         /* GPU isn't processing, downclock it. */
3980         if (!dev_priv->busy) {
3981                 intel_decrease_renderclock(dev);
3982                 intel_decrease_displayclock(dev);
3983         }
3984
3985         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3986                 /* Skip inactive CRTCs */
3987                 if (!crtc->fb)
3988                         continue;
3989
3990                 intel_crtc = to_intel_crtc(crtc);
3991                 if (!intel_crtc->busy)
3992                         intel_decrease_pllclock(crtc);
3993         }
3994
3995         mutex_unlock(&dev->struct_mutex);
3996 }
3997
3998 /**
3999  * intel_mark_busy - mark the GPU and possibly the display busy
4000  * @dev: drm device
4001  * @obj: object we're operating on
4002  *
4003  * Callers can use this function to indicate that the GPU is busy processing
4004  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4005  * buffer), we'll also mark the display as busy, so we know to increase its
4006  * clock frequency.
4007  */
4008 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4009 {
4010         drm_i915_private_t *dev_priv = dev->dev_private;
4011         struct drm_crtc *crtc = NULL;
4012         struct intel_framebuffer *intel_fb;
4013         struct intel_crtc *intel_crtc;
4014
4015         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4016                 return;
4017
4018         dev_priv->busy = true;
4019         intel_increase_renderclock(dev, true);
4020
4021         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4022                 if (!crtc->fb)
4023                         continue;
4024
4025                 intel_crtc = to_intel_crtc(crtc);
4026                 intel_fb = to_intel_framebuffer(crtc->fb);
4027                 if (intel_fb->obj == obj) {
4028                         if (!intel_crtc->busy) {
4029                                 /* Non-busy -> busy, upclock */
4030                                 intel_increase_pllclock(crtc, true);
4031                                 intel_crtc->busy = true;
4032                         } else {
4033                                 /* Busy -> busy, put off timer */
4034                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4035                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4036                         }
4037                 }
4038         }
4039 }
4040
4041 static void intel_crtc_destroy(struct drm_crtc *crtc)
4042 {
4043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4044
4045         drm_crtc_cleanup(crtc);
4046         kfree(intel_crtc);
4047 }
4048
4049 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4050         .dpms = intel_crtc_dpms,
4051         .mode_fixup = intel_crtc_mode_fixup,
4052         .mode_set = intel_crtc_mode_set,
4053         .mode_set_base = intel_pipe_set_base,
4054         .prepare = intel_crtc_prepare,
4055         .commit = intel_crtc_commit,
4056         .load_lut = intel_crtc_load_lut,
4057 };
4058
4059 static const struct drm_crtc_funcs intel_crtc_funcs = {
4060         .cursor_set = intel_crtc_cursor_set,
4061         .cursor_move = intel_crtc_cursor_move,
4062         .gamma_set = intel_crtc_gamma_set,
4063         .set_config = drm_crtc_helper_set_config,
4064         .destroy = intel_crtc_destroy,
4065 };
4066
4067
4068 static void intel_crtc_init(struct drm_device *dev, int pipe)
4069 {
4070         struct intel_crtc *intel_crtc;
4071         int i;
4072
4073         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4074         if (intel_crtc == NULL)
4075                 return;
4076
4077         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4078
4079         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4080         intel_crtc->pipe = pipe;
4081         intel_crtc->plane = pipe;
4082         for (i = 0; i < 256; i++) {
4083                 intel_crtc->lut_r[i] = i;
4084                 intel_crtc->lut_g[i] = i;
4085                 intel_crtc->lut_b[i] = i;
4086         }
4087
4088         /* Swap pipes & planes for FBC on pre-965 */
4089         intel_crtc->pipe = pipe;
4090         intel_crtc->plane = pipe;
4091         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4092                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4093                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4094         }
4095
4096         intel_crtc->cursor_addr = 0;
4097         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4098         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4099
4100         intel_crtc->busy = false;
4101
4102         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4103                     (unsigned long)intel_crtc);
4104 }
4105
4106 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4107                                 struct drm_file *file_priv)
4108 {
4109         drm_i915_private_t *dev_priv = dev->dev_private;
4110         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4111         struct drm_mode_object *drmmode_obj;
4112         struct intel_crtc *crtc;
4113
4114         if (!dev_priv) {
4115                 DRM_ERROR("called with no initialization\n");
4116                 return -EINVAL;
4117         }
4118
4119         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4120                         DRM_MODE_OBJECT_CRTC);
4121
4122         if (!drmmode_obj) {
4123                 DRM_ERROR("no such CRTC id\n");
4124                 return -EINVAL;
4125         }
4126
4127         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4128         pipe_from_crtc_id->pipe = crtc->pipe;
4129
4130         return 0;
4131 }
4132
4133 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4134 {
4135         struct drm_crtc *crtc = NULL;
4136
4137         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4138                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4139                 if (intel_crtc->pipe == pipe)
4140                         break;
4141         }
4142         return crtc;
4143 }
4144
4145 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4146 {
4147         int index_mask = 0;
4148         struct drm_connector *connector;
4149         int entry = 0;
4150
4151         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4152                 struct intel_output *intel_output = to_intel_output(connector);
4153                 if (type_mask & intel_output->clone_mask)
4154                         index_mask |= (1 << entry);
4155                 entry++;
4156         }
4157         return index_mask;
4158 }
4159
4160
4161 static void intel_setup_outputs(struct drm_device *dev)
4162 {
4163         struct drm_i915_private *dev_priv = dev->dev_private;
4164         struct drm_connector *connector;
4165
4166         intel_crt_init(dev);
4167
4168         /* Set up integrated LVDS */
4169         if (IS_MOBILE(dev) && !IS_I830(dev))
4170                 intel_lvds_init(dev);
4171
4172         if (IS_IGDNG(dev)) {
4173                 int found;
4174
4175                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4176                         intel_dp_init(dev, DP_A);
4177
4178                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4179                         /* check SDVOB */
4180                         /* found = intel_sdvo_init(dev, HDMIB); */
4181                         found = 0;
4182                         if (!found)
4183                                 intel_hdmi_init(dev, HDMIB);
4184                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4185                                 intel_dp_init(dev, PCH_DP_B);
4186                 }
4187
4188                 if (I915_READ(HDMIC) & PORT_DETECTED)
4189                         intel_hdmi_init(dev, HDMIC);
4190
4191                 if (I915_READ(HDMID) & PORT_DETECTED)
4192                         intel_hdmi_init(dev, HDMID);
4193
4194                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4195                         intel_dp_init(dev, PCH_DP_C);
4196
4197                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4198                         intel_dp_init(dev, PCH_DP_D);
4199
4200         } else if (IS_I9XX(dev)) {
4201                 bool found = false;
4202
4203                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4204                         found = intel_sdvo_init(dev, SDVOB);
4205                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4206                                 intel_hdmi_init(dev, SDVOB);
4207
4208                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
4209                                 intel_dp_init(dev, DP_B);
4210                 }
4211
4212                 /* Before G4X SDVOC doesn't have its own detect register */
4213
4214                 if (I915_READ(SDVOB) & SDVO_DETECTED)
4215                         found = intel_sdvo_init(dev, SDVOC);
4216
4217                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4218
4219                         if (SUPPORTS_INTEGRATED_HDMI(dev))
4220                                 intel_hdmi_init(dev, SDVOC);
4221                         if (SUPPORTS_INTEGRATED_DP(dev))
4222                                 intel_dp_init(dev, DP_C);
4223                 }
4224
4225                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4226                         intel_dp_init(dev, DP_D);
4227         } else
4228                 intel_dvo_init(dev);
4229
4230         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
4231                 intel_tv_init(dev);
4232
4233         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4234                 struct intel_output *intel_output = to_intel_output(connector);
4235                 struct drm_encoder *encoder = &intel_output->enc;
4236
4237                 encoder->possible_crtcs = intel_output->crtc_mask;
4238                 encoder->possible_clones = intel_connector_clones(dev,
4239                                                 intel_output->clone_mask);
4240         }
4241 }
4242
4243 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4244 {
4245         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4246         struct drm_device *dev = fb->dev;
4247
4248         if (fb->fbdev)
4249                 intelfb_remove(dev, fb);
4250
4251         drm_framebuffer_cleanup(fb);
4252         mutex_lock(&dev->struct_mutex);
4253         drm_gem_object_unreference(intel_fb->obj);
4254         mutex_unlock(&dev->struct_mutex);
4255
4256         kfree(intel_fb);
4257 }
4258
4259 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4260                                                 struct drm_file *file_priv,
4261                                                 unsigned int *handle)
4262 {
4263         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4264         struct drm_gem_object *object = intel_fb->obj;
4265
4266         return drm_gem_handle_create(file_priv, object, handle);
4267 }
4268
4269 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4270         .destroy = intel_user_framebuffer_destroy,
4271         .create_handle = intel_user_framebuffer_create_handle,
4272 };
4273
4274 int intel_framebuffer_create(struct drm_device *dev,
4275                              struct drm_mode_fb_cmd *mode_cmd,
4276                              struct drm_framebuffer **fb,
4277                              struct drm_gem_object *obj)
4278 {
4279         struct intel_framebuffer *intel_fb;
4280         int ret;
4281
4282         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4283         if (!intel_fb)
4284                 return -ENOMEM;
4285
4286         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4287         if (ret) {
4288                 DRM_ERROR("framebuffer init failed %d\n", ret);
4289                 return ret;
4290         }
4291
4292         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4293
4294         intel_fb->obj = obj;
4295
4296         *fb = &intel_fb->base;
4297
4298         return 0;
4299 }
4300
4301
4302 static struct drm_framebuffer *
4303 intel_user_framebuffer_create(struct drm_device *dev,
4304                               struct drm_file *filp,
4305                               struct drm_mode_fb_cmd *mode_cmd)
4306 {
4307         struct drm_gem_object *obj;
4308         struct drm_framebuffer *fb;
4309         int ret;
4310
4311         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4312         if (!obj)
4313                 return NULL;
4314
4315         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4316         if (ret) {
4317                 mutex_lock(&dev->struct_mutex);
4318                 drm_gem_object_unreference(obj);
4319                 mutex_unlock(&dev->struct_mutex);
4320                 return NULL;
4321         }
4322
4323         return fb;
4324 }
4325
4326 static const struct drm_mode_config_funcs intel_mode_funcs = {
4327         .fb_create = intel_user_framebuffer_create,
4328         .fb_changed = intelfb_probe,
4329 };
4330
4331 void intel_init_clock_gating(struct drm_device *dev)
4332 {
4333         struct drm_i915_private *dev_priv = dev->dev_private;
4334
4335         /*
4336          * Disable clock gating reported to work incorrectly according to the
4337          * specs, but enable as much else as we can.
4338          */
4339         if (IS_IGDNG(dev)) {
4340                 return;
4341         } else if (IS_G4X(dev)) {
4342                 uint32_t dspclk_gate;
4343                 I915_WRITE(RENCLK_GATE_D1, 0);
4344                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4345                        GS_UNIT_CLOCK_GATE_DISABLE |
4346                        CL_UNIT_CLOCK_GATE_DISABLE);
4347                 I915_WRITE(RAMCLK_GATE_D, 0);
4348                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4349                         OVRUNIT_CLOCK_GATE_DISABLE |
4350                         OVCUNIT_CLOCK_GATE_DISABLE;
4351                 if (IS_GM45(dev))
4352                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4353                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4354         } else if (IS_I965GM(dev)) {
4355                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4356                 I915_WRITE(RENCLK_GATE_D2, 0);
4357                 I915_WRITE(DSPCLK_GATE_D, 0);
4358                 I915_WRITE(RAMCLK_GATE_D, 0);
4359                 I915_WRITE16(DEUC, 0);
4360         } else if (IS_I965G(dev)) {
4361                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4362                        I965_RCC_CLOCK_GATE_DISABLE |
4363                        I965_RCPB_CLOCK_GATE_DISABLE |
4364                        I965_ISC_CLOCK_GATE_DISABLE |
4365                        I965_FBC_CLOCK_GATE_DISABLE);
4366                 I915_WRITE(RENCLK_GATE_D2, 0);
4367         } else if (IS_I9XX(dev)) {
4368                 u32 dstate = I915_READ(D_STATE);
4369
4370                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4371                         DSTATE_DOT_CLOCK_GATING;
4372                 I915_WRITE(D_STATE, dstate);
4373         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4374                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4375         } else if (IS_I830(dev)) {
4376                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4377         }
4378
4379         /*
4380          * GPU can automatically power down the render unit if given a page
4381          * to save state.
4382          */
4383         if (I915_HAS_RC6(dev)) {
4384                 struct drm_gem_object *pwrctx;
4385                 struct drm_i915_gem_object *obj_priv;
4386                 int ret;
4387
4388                 pwrctx = drm_gem_object_alloc(dev, 4096);
4389                 if (!pwrctx) {
4390                         DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4391                         goto out;
4392                 }
4393
4394                 ret = i915_gem_object_pin(pwrctx, 4096);
4395                 if (ret) {
4396                         DRM_ERROR("failed to pin power context: %d\n", ret);
4397                         drm_gem_object_unreference(pwrctx);
4398                         goto out;
4399                 }
4400
4401                 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4402
4403                 obj_priv = pwrctx->driver_private;
4404
4405                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4406                 I915_WRITE(MCHBAR_RENDER_STANDBY,
4407                            I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4408
4409                 dev_priv->pwrctx = pwrctx;
4410         }
4411
4412 out:
4413         return;
4414 }
4415
4416 /* Set up chip specific display functions */
4417 static void intel_init_display(struct drm_device *dev)
4418 {
4419         struct drm_i915_private *dev_priv = dev->dev_private;
4420
4421         /* We always want a DPMS function */
4422         if (IS_IGDNG(dev))
4423                 dev_priv->display.dpms = igdng_crtc_dpms;
4424         else
4425                 dev_priv->display.dpms = i9xx_crtc_dpms;
4426
4427         /* Only mobile has FBC, leave pointers NULL for other chips */
4428         if (IS_MOBILE(dev)) {
4429                 if (IS_GM45(dev)) {
4430                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4431                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4432                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4433                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4434                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4435                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4436                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4437                 }
4438                 /* 855GM needs testing */
4439         }
4440
4441         /* Returns the core display clock speed */
4442         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_IGDGM(dev)))
4443                 dev_priv->display.get_display_clock_speed =
4444                         i945_get_display_clock_speed;
4445         else if (IS_I915G(dev))
4446                 dev_priv->display.get_display_clock_speed =
4447                         i915_get_display_clock_speed;
4448         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4449                 dev_priv->display.get_display_clock_speed =
4450                         i9xx_misc_get_display_clock_speed;
4451         else if (IS_I915GM(dev))
4452                 dev_priv->display.get_display_clock_speed =
4453                         i915gm_get_display_clock_speed;
4454         else if (IS_I865G(dev))
4455                 dev_priv->display.get_display_clock_speed =
4456                         i865_get_display_clock_speed;
4457         else if (IS_I85X(dev))
4458                 dev_priv->display.get_display_clock_speed =
4459                         i855_get_display_clock_speed;
4460         else /* 852, 830 */
4461                 dev_priv->display.get_display_clock_speed =
4462                         i830_get_display_clock_speed;
4463
4464         /* For FIFO watermark updates */
4465         if (IS_IGDNG(dev))
4466                 dev_priv->display.update_wm = NULL;
4467         else if (IS_G4X(dev))
4468                 dev_priv->display.update_wm = g4x_update_wm;
4469         else if (IS_I965G(dev))
4470                 dev_priv->display.update_wm = i965_update_wm;
4471         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4472                 dev_priv->display.update_wm = i9xx_update_wm;
4473                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4474         } else {
4475                 if (IS_I85X(dev))
4476                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4477                 else if (IS_845G(dev))
4478                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4479                 else
4480                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4481                 dev_priv->display.update_wm = i830_update_wm;
4482         }
4483 }
4484
4485 void intel_modeset_init(struct drm_device *dev)
4486 {
4487         struct drm_i915_private *dev_priv = dev->dev_private;
4488         int num_pipe;
4489         int i;
4490
4491         drm_mode_config_init(dev);
4492
4493         dev->mode_config.min_width = 0;
4494         dev->mode_config.min_height = 0;
4495
4496         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4497
4498         intel_init_display(dev);
4499
4500         if (IS_I965G(dev)) {
4501                 dev->mode_config.max_width = 8192;
4502                 dev->mode_config.max_height = 8192;
4503         } else if (IS_I9XX(dev)) {
4504                 dev->mode_config.max_width = 4096;
4505                 dev->mode_config.max_height = 4096;
4506         } else {
4507                 dev->mode_config.max_width = 2048;
4508                 dev->mode_config.max_height = 2048;
4509         }
4510
4511         /* set memory base */
4512         if (IS_I9XX(dev))
4513                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4514         else
4515                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4516
4517         if (IS_MOBILE(dev) || IS_I9XX(dev))
4518                 num_pipe = 2;
4519         else
4520                 num_pipe = 1;
4521         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4522                   num_pipe, num_pipe > 1 ? "s" : "");
4523
4524         if (IS_I85X(dev))
4525                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4526         else if (IS_I9XX(dev) || IS_G4X(dev))
4527                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4528
4529         for (i = 0; i < num_pipe; i++) {
4530                 intel_crtc_init(dev, i);
4531         }
4532
4533         intel_setup_outputs(dev);
4534
4535         intel_init_clock_gating(dev);
4536
4537         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4538         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4539                     (unsigned long)dev);
4540
4541         intel_setup_overlay(dev);
4542 }
4543
4544 void intel_modeset_cleanup(struct drm_device *dev)
4545 {
4546         struct drm_i915_private *dev_priv = dev->dev_private;
4547         struct drm_crtc *crtc;
4548         struct intel_crtc *intel_crtc;
4549
4550         mutex_lock(&dev->struct_mutex);
4551
4552         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4553                 /* Skip inactive CRTCs */
4554                 if (!crtc->fb)
4555                         continue;
4556
4557                 intel_crtc = to_intel_crtc(crtc);
4558                 intel_increase_pllclock(crtc, false);
4559                 del_timer_sync(&intel_crtc->idle_timer);
4560         }
4561
4562         intel_increase_renderclock(dev, false);
4563         del_timer_sync(&dev_priv->idle_timer);
4564
4565         mutex_unlock(&dev->struct_mutex);
4566
4567         if (dev_priv->display.disable_fbc)
4568                 dev_priv->display.disable_fbc(dev);
4569
4570         if (dev_priv->pwrctx) {
4571                 i915_gem_object_unpin(dev_priv->pwrctx);
4572                 drm_gem_object_unreference(dev_priv->pwrctx);
4573         }
4574
4575         drm_mode_config_cleanup(dev);
4576 }
4577
4578
4579 /* current intel driver doesn't take advantage of encoders
4580    always give back the encoder for the connector
4581 */
4582 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4583 {
4584         struct intel_output *intel_output = to_intel_output(connector);
4585
4586         return &intel_output->enc;
4587 }
4588
4589 /*
4590  * set vga decode state - true == enable VGA decode
4591  */
4592 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4593 {
4594         struct drm_i915_private *dev_priv = dev->dev_private;
4595         u16 gmch_ctrl;
4596
4597         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4598         if (state)
4599                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4600         else
4601                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4602         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4603         return 0;
4604 }