SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/kernel.h>
  29 #include "drmP.h"
  30 #include "intel_drv.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "intel_dp.h"
  34
  35 #include "drm_crtc_helper.h"
  36
  37 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  38 static void intel_update_watermarks(struct drm_device *dev);
  39
  40 typedef struct {
  41     /* given values */
  42     int n;
  43     int m1, m2;
  44     int p1, p2;
  45     /* derived values */
  46     int dot;
  47     int vco;
  48     int m;
  49     int p;
  50 } intel_clock_t;
  51
  52 typedef struct {
  53     int min, max;
  54 } intel_range_t;
  55
  56 typedef struct {
  57     int dot_limit;
  58     int p2_slow, p2_fast;
  59 } intel_p2_t;
  60
  61 #define INTEL_P2_NUM                  2
  62 typedef struct intel_limit intel_limit_t;
  63 struct intel_limit {
  64     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  65     intel_p2_t      p2;
  66     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  67                       int, int, intel_clock_t *);
  68 };
  69
  70 #define I8XX_DOT_MIN              25000
  71 #define I8XX_DOT_MAX             350000
  72 #define I8XX_VCO_MIN             930000
  73 #define I8XX_VCO_MAX            1400000
  74 #define I8XX_N_MIN                    3
  75 #define I8XX_N_MAX                   16
  76 #define I8XX_M_MIN                   96
  77 #define I8XX_M_MAX                  140
  78 #define I8XX_M1_MIN                  18
  79 #define I8XX_M1_MAX                  26
  80 #define I8XX_M2_MIN                   6
  81 #define I8XX_M2_MAX                  16
  82 #define I8XX_P_MIN                    4
  83 #define I8XX_P_MAX                  128
  84 #define I8XX_P1_MIN                   2
  85 #define I8XX_P1_MAX                  33
  86 #define I8XX_P1_LVDS_MIN              1
  87 #define I8XX_P1_LVDS_MAX              6
  88 #define I8XX_P2_SLOW                  4
  89 #define I8XX_P2_FAST                  2
  90 #define I8XX_P2_LVDS_SLOW             14
  91 #define I8XX_P2_LVDS_FAST             14 /* No fast option */
  92 #define I8XX_P2_SLOW_LIMIT       165000
  93
  94 #define I9XX_DOT_MIN              20000
  95 #define I9XX_DOT_MAX             400000
  96 #define I9XX_VCO_MIN            1400000
  97 #define I9XX_VCO_MAX            2800000
  98 #define IGD_VCO_MIN             1700000
  99 #define IGD_VCO_MAX             3500000
 100 #define I9XX_N_MIN                    1
 101 #define I9XX_N_MAX                    6
 102 /* IGD's Ncounter is a ring counter */
 103 #define IGD_N_MIN                     3
 104 #define IGD_N_MAX                     6
 105 #define I9XX_M_MIN                   70
 106 #define I9XX_M_MAX                  120
 107 #define IGD_M_MIN                     2
 108 #define IGD_M_MAX                   256
 109 #define I9XX_M1_MIN                  10
 110 #define I9XX_M1_MAX                  22
 111 #define I9XX_M2_MIN                   5
 112 #define I9XX_M2_MAX                   9
 113 /* IGD M1 is reserved, and must be 0 */
 114 #define IGD_M1_MIN                    0
 115 #define IGD_M1_MAX                    0
 116 #define IGD_M2_MIN                    0
 117 #define IGD_M2_MAX                    254
 118 #define I9XX_P_SDVO_DAC_MIN           5
 119 #define I9XX_P_SDVO_DAC_MAX          80
 120 #define I9XX_P_LVDS_MIN               7
 121 #define I9XX_P_LVDS_MAX              98
 122 #define IGD_P_LVDS_MIN                7
 123 #define IGD_P_LVDS_MAX               112
 124 #define I9XX_P1_MIN                   1
 125 #define I9XX_P1_MAX                   8
 126 #define I9XX_P2_SDVO_DAC_SLOW                10
 127 #define I9XX_P2_SDVO_DAC_FAST                 5
 128 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 129 #define I9XX_P2_LVDS_SLOW                    14
 130 #define I9XX_P2_LVDS_FAST                     7
 131 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 132
 133 /*The parameter is for SDVO on G4x platform*/
 134 #define G4X_DOT_SDVO_MIN           25000
 135 #define G4X_DOT_SDVO_MAX           270000
 136 #define G4X_VCO_MIN                1750000
 137 #define G4X_VCO_MAX                3500000
 138 #define G4X_N_SDVO_MIN             1
 139 #define G4X_N_SDVO_MAX             4
 140 #define G4X_M_SDVO_MIN             104
 141 #define G4X_M_SDVO_MAX             138
 142 #define G4X_M1_SDVO_MIN            17
 143 #define G4X_M1_SDVO_MAX            23
 144 #define G4X_M2_SDVO_MIN            5
 145 #define G4X_M2_SDVO_MAX            11
 146 #define G4X_P_SDVO_MIN             10
 147 #define G4X_P_SDVO_MAX             30
 148 #define G4X_P1_SDVO_MIN            1
 149 #define G4X_P1_SDVO_MAX            3
 150 #define G4X_P2_SDVO_SLOW           10
 151 #define G4X_P2_SDVO_FAST           10
 152 #define G4X_P2_SDVO_LIMIT          270000
 153
 154 /*The parameter is for HDMI_DAC on G4x platform*/
 155 #define G4X_DOT_HDMI_DAC_MIN           22000
 156 #define G4X_DOT_HDMI_DAC_MAX           400000
 157 #define G4X_N_HDMI_DAC_MIN             1
 158 #define G4X_N_HDMI_DAC_MAX             4
 159 #define G4X_M_HDMI_DAC_MIN             104
 160 #define G4X_M_HDMI_DAC_MAX             138
 161 #define G4X_M1_HDMI_DAC_MIN            16
 162 #define G4X_M1_HDMI_DAC_MAX            23
 163 #define G4X_M2_HDMI_DAC_MIN            5
 164 #define G4X_M2_HDMI_DAC_MAX            11
 165 #define G4X_P_HDMI_DAC_MIN             5
 166 #define G4X_P_HDMI_DAC_MAX             80
 167 #define G4X_P1_HDMI_DAC_MIN            1
 168 #define G4X_P1_HDMI_DAC_MAX            8
 169 #define G4X_P2_HDMI_DAC_SLOW           10
 170 #define G4X_P2_HDMI_DAC_FAST           5
 171 #define G4X_P2_HDMI_DAC_LIMIT          165000
 172
 173 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 174 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 175 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 176 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 177 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 178 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 179 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 180 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 181 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 182 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 183 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 184 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 185 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 186 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 187 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 188 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 189 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 190 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 191
 192 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 193 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 194 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 195 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 196 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 197 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 198 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 199 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 200 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 201 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 202 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 203 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 204 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 205 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 206 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 207 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 208 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 209 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 210
 211 /*The parameter is for DISPLAY PORT on G4x platform*/
 212 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 213 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 214 #define G4X_N_DISPLAY_PORT_MIN             1
 215 #define G4X_N_DISPLAY_PORT_MAX             2
 216 #define G4X_M_DISPLAY_PORT_MIN             97
 217 #define G4X_M_DISPLAY_PORT_MAX             108
 218 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 219 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 220 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 221 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 222 #define G4X_P_DISPLAY_PORT_MIN             10
 223 #define G4X_P_DISPLAY_PORT_MAX             20
 224 #define G4X_P1_DISPLAY_PORT_MIN            1
 225 #define G4X_P1_DISPLAY_PORT_MAX            2
 226 #define G4X_P2_DISPLAY_PORT_SLOW           10
 227 #define G4X_P2_DISPLAY_PORT_FAST           10
 228 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 229
 230 /* IGDNG */
 231 /* as we calculate clock using (register_value + 2) for
 232    N/M1/M2, so here the range value for them is (actual_value-2).
 233  */
 234 #define IGDNG_DOT_MIN         25000
 235 #define IGDNG_DOT_MAX         350000
 236 #define IGDNG_VCO_MIN         1760000
 237 #define IGDNG_VCO_MAX         3510000
 238 #define IGDNG_N_MIN           1
 239 #define IGDNG_N_MAX           5
 240 #define IGDNG_M_MIN           79
 241 #define IGDNG_M_MAX           118
 242 #define IGDNG_M1_MIN          12
 243 #define IGDNG_M1_MAX          23
 244 #define IGDNG_M2_MIN          5
 245 #define IGDNG_M2_MAX          9
 246 #define IGDNG_P_SDVO_DAC_MIN  5
 247 #define IGDNG_P_SDVO_DAC_MAX  80
 248 #define IGDNG_P_LVDS_MIN      28
 249 #define IGDNG_P_LVDS_MAX      112
 250 #define IGDNG_P1_MIN          1
 251 #define IGDNG_P1_MAX          8
 252 #define IGDNG_P2_SDVO_DAC_SLOW 10
 253 #define IGDNG_P2_SDVO_DAC_FAST 5
 254 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 255 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 256 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 257
 258 static bool
 259 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 260                     int target, int refclk, intel_clock_t *best_clock);
 261 static bool
 262 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 263                         int target, int refclk, intel_clock_t *best_clock);
 264 static bool
 265 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 266                         int target, int refclk, intel_clock_t *best_clock);
 267
 268 static bool
 269 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 270                       int target, int refclk, intel_clock_t *best_clock);
 271
 272 static const intel_limit_t intel_limits_i8xx_dvo = {
 273         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 274         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 275         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 276         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 277         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 278         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 279         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 280         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 281         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 282                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 283         .find_pll = intel_find_best_PLL,
 284 };
 285
 286 static const intel_limit_t intel_limits_i8xx_lvds = {
 287         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 288         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 289         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 290         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 291         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 292         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 293         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 294         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 295         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 296                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 297         .find_pll = intel_find_best_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i9xx_sdvo = {
 301         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 302         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 303         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 304         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 305         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 306         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 307         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 308         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 309         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 310                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 311         .find_pll = intel_find_best_PLL,
 312 };
 313
 314 static const intel_limit_t intel_limits_i9xx_lvds = {
 315         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 316         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 317         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 318         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 319         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 320         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 321         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 322         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 323         /* The single-channel range is 25-112Mhz, and dual-channel
 324          * is 80-224Mhz.  Prefer single channel as much as possible.
 325          */
 326         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 327                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 328         .find_pll = intel_find_best_PLL,
 329 };
 330
 331     /* below parameter and function is for G4X Chipset Family*/
 332 static const intel_limit_t intel_limits_g4x_sdvo = {
 333         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 334         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 335         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 336         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 337         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 338         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 339         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 340         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 341         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 342                  .p2_slow = G4X_P2_SDVO_SLOW,
 343                  .p2_fast = G4X_P2_SDVO_FAST
 344         },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 static const intel_limit_t intel_limits_g4x_hdmi = {
 349         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 350         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 351         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 352         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 353         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 354         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 355         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 356         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 357         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 358                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 359                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 360         },
 361         .find_pll = intel_g4x_find_best_PLL,
 362 };
 363
 364 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 365         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 366                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 367         .vco = { .min = G4X_VCO_MIN,
 368                  .max = G4X_VCO_MAX },
 369         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 370                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 371         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 372                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 373         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 374                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 375         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 376                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 377         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 378                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 379         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 380                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 381         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 382                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 383                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 384         },
 385         .find_pll = intel_g4x_find_best_PLL,
 386 };
 387
 388 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 389         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 390                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 391         .vco = { .min = G4X_VCO_MIN,
 392                  .max = G4X_VCO_MAX },
 393         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 394                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 395         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 396                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 397         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 398                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 399         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 400                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 401         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 402                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 403         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 404                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 405         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 406                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 407                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 408         },
 409         .find_pll = intel_g4x_find_best_PLL,
 410 };
 411
 412 static const intel_limit_t intel_limits_g4x_display_port = {
 413         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 414                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 415         .vco = { .min = G4X_VCO_MIN,
 416                  .max = G4X_VCO_MAX},
 417         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 418                  .max = G4X_N_DISPLAY_PORT_MAX },
 419         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 420                  .max = G4X_M_DISPLAY_PORT_MAX },
 421         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 422                  .max = G4X_M1_DISPLAY_PORT_MAX },
 423         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 424                  .max = G4X_M2_DISPLAY_PORT_MAX },
 425         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 426                  .max = G4X_P_DISPLAY_PORT_MAX },
 427         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 428                  .max = G4X_P1_DISPLAY_PORT_MAX},
 429         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 430                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 431                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 432         .find_pll = intel_find_pll_g4x_dp,
 433 };
 434
 435 static const intel_limit_t intel_limits_igd_sdvo = {
 436         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 437         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 438         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 439         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 440         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 441         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 442         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 443         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 444         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 445                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 446         .find_pll = intel_find_best_PLL,
 447 };
 448
 449 static const intel_limit_t intel_limits_igd_lvds = {
 450         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 451         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 452         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 453         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 454         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 455         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 456         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 457         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 458         /* IGD only supports single-channel mode. */
 459         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 460                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 461         .find_pll = intel_find_best_PLL,
 462 };
 463
 464 static const intel_limit_t intel_limits_igdng_sdvo = {
 465         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 466         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 467         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 468         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 469         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 470         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 471         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 472         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 473         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 474                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 475                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 476         .find_pll = intel_igdng_find_best_PLL,
 477 };
 478
 479 static const intel_limit_t intel_limits_igdng_lvds = {
 480         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 481         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 482         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 483         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 484         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 485         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 486         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 487         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 488         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 489                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 490                  .p2_fast = IGDNG_P2_LVDS_FAST },
 491         .find_pll = intel_igdng_find_best_PLL,
 492 };
 493
 494 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 495 {
 496         const intel_limit_t *limit;
 497         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 498                 limit = &intel_limits_igdng_lvds;
 499         else
 500                 limit = &intel_limits_igdng_sdvo;
 501
 502         return limit;
 503 }
 504
 505 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 506 {
 507         struct drm_device *dev = crtc->dev;
 508         struct drm_i915_private *dev_priv = dev->dev_private;
 509         const intel_limit_t *limit;
 510
 511         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 512                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 513                     LVDS_CLKB_POWER_UP)
 514                         /* LVDS with dual channel */
 515                         limit = &intel_limits_g4x_dual_channel_lvds;
 516                 else
 517                         /* LVDS with dual channel */
 518                         limit = &intel_limits_g4x_single_channel_lvds;
 519         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 520                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 521                 limit = &intel_limits_g4x_hdmi;
 522         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 523                 limit = &intel_limits_g4x_sdvo;
 524         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 525                 limit = &intel_limits_g4x_display_port;
 526         } else /* The option is for other outputs */
 527                 limit = &intel_limits_i9xx_sdvo;
 528
 529         return limit;
 530 }
 531
 532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 533 {
 534         struct drm_device *dev = crtc->dev;
 535         const intel_limit_t *limit;
 536
 537         if (IS_IGDNG(dev))
 538                 limit = intel_igdng_limit(crtc);
 539         else if (IS_G4X(dev)) {
 540                 limit = intel_g4x_limit(crtc);
 541         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 542                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_i9xx_lvds;
 544                 else
 545                         limit = &intel_limits_i9xx_sdvo;
 546         } else if (IS_IGD(dev)) {
 547                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 548                         limit = &intel_limits_igd_lvds;
 549                 else
 550                         limit = &intel_limits_igd_sdvo;
 551         } else {
 552                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 553                         limit = &intel_limits_i8xx_lvds;
 554                 else
 555                         limit = &intel_limits_i8xx_dvo;
 556         }
 557         return limit;
 558 }
 559
 560 /* m1 is reserved as 0 in IGD, n is a ring counter */
 561 static void igd_clock(int refclk, intel_clock_t *clock)
 562 {
 563         clock->m = clock->m2 + 2;
 564         clock->p = clock->p1 * clock->p2;
 565         clock->vco = refclk * clock->m / clock->n;
 566         clock->dot = clock->vco / clock->p;
 567 }
 568
 569 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 570 {
 571         if (IS_IGD(dev)) {
 572                 igd_clock(refclk, clock);
 573                 return;
 574         }
 575         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 576         clock->p = clock->p1 * clock->p2;
 577         clock->vco = refclk * clock->m / (clock->n + 2);
 578         clock->dot = clock->vco / clock->p;
 579 }
 580
 581 /**
 582  * Returns whether any output on the specified pipe is of the specified type
 583  */
 584 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 585 {
 586     struct drm_device *dev = crtc->dev;
 587     struct drm_mode_config *mode_config = &dev->mode_config;
 588     struct drm_connector *l_entry;
 589
 590     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 591             if (l_entry->encoder &&
 592                 l_entry->encoder->crtc == crtc) {
 593                     struct intel_output *intel_output = to_intel_output(l_entry);
 594                     if (intel_output->type == type)
 595                             return true;
 596             }
 597     }
 598     return false;
 599 }
 600
 601 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 602 /**
 603  * Returns whether the given set of divisors are valid for a given refclk with
 604  * the given connectors.
 605  */
 606
 607 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 608 {
 609         const intel_limit_t *limit = intel_limit (crtc);
 610         struct drm_device *dev = crtc->dev;
 611
 612         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 613                 INTELPllInvalid ("p1 out of range\n");
 614         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 615                 INTELPllInvalid ("p out of range\n");
 616         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 617                 INTELPllInvalid ("m2 out of range\n");
 618         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 619                 INTELPllInvalid ("m1 out of range\n");
 620         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 621                 INTELPllInvalid ("m1 <= m2\n");
 622         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 623                 INTELPllInvalid ("m out of range\n");
 624         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 625                 INTELPllInvalid ("n out of range\n");
 626         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 627                 INTELPllInvalid ("vco out of range\n");
 628         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 629          * connector, etc., rather than just a single range.
 630          */
 631         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 632                 INTELPllInvalid ("dot out of range\n");
 633
 634         return true;
 635 }
 636
 637 static bool
 638 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 639                     int target, int refclk, intel_clock_t *best_clock)
 640
 641 {
 642         struct drm_device *dev = crtc->dev;
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         intel_clock_t clock;
 645         int err = target;
 646
 647         if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 648             (I915_READ(LVDS)) != 0) {
 649                 /*
 650                  * For LVDS, if the panel is on, just rely on its current
 651                  * settings for dual-channel.  We haven't figured out how to
 652                  * reliably set up different single/dual channel state, if we
 653                  * even can.
 654                  */
 655                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 656                     LVDS_CLKB_POWER_UP)
 657                         clock.p2 = limit->p2.p2_fast;
 658                 else
 659                         clock.p2 = limit->p2.p2_slow;
 660         } else {
 661                 if (target < limit->p2.dot_limit)
 662                         clock.p2 = limit->p2.p2_slow;
 663                 else
 664                         clock.p2 = limit->p2.p2_fast;
 665         }
 666
 667         memset (best_clock, 0, sizeof (*best_clock));
 668
 669         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 670                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 671                         /* m1 is always 0 in IGD */
 672                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 673                                 break;
 674                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 675                              clock.n++) {
 676                                 for (clock.p1 = limit->p1.min;
 677                                      clock.p1 <= limit->p1.max; clock.p1++) {
 678                                         int this_err;
 679
 680                                         intel_clock(dev, refclk, &clock);
 681
 682                                         if (!intel_PLL_is_valid(crtc, &clock))
 683                                                 continue;
 684
 685                                         this_err = abs(clock.dot - target);
 686                                         if (this_err < err) {
 687                                                 *best_clock = clock;
 688                                                 err = this_err;
 689                                         }
 690                                 }
 691                         }
 692                 }
 693         }
 694
 695         return (err != target);
 696 }
 697
 698 static bool
 699 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 700                         int target, int refclk, intel_clock_t *best_clock)
 701 {
 702         struct drm_device *dev = crtc->dev;
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         intel_clock_t clock;
 705         int max_n;
 706         bool found;
 707         /* approximately equals target * 0.00488 */
 708         int err_most = (target >> 8) + (target >> 10);
 709         found = false;
 710
 711         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 712                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 713                     LVDS_CLKB_POWER_UP)
 714                         clock.p2 = limit->p2.p2_fast;
 715                 else
 716                         clock.p2 = limit->p2.p2_slow;
 717         } else {
 718                 if (target < limit->p2.dot_limit)
 719                         clock.p2 = limit->p2.p2_slow;
 720                 else
 721                         clock.p2 = limit->p2.p2_fast;
 722         }
 723
 724         memset(best_clock, 0, sizeof(*best_clock));
 725         max_n = limit->n.max;
 726         /* based on hardware requriment prefer smaller n to precision */
 727         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 728                 /* based on hardware requirment prefere larger m1,m2, p1 */
 729                 for (clock.m1 = limit->m1.max;
 730                      clock.m1 >= limit->m1.min; clock.m1--) {
 731                         for (clock.m2 = limit->m2.max;
 732                              clock.m2 >= limit->m2.min; clock.m2--) {
 733                                 for (clock.p1 = limit->p1.max;
 734                                      clock.p1 >= limit->p1.min; clock.p1--) {
 735                                         int this_err;
 736
 737                                         intel_clock(dev, refclk, &clock);
 738                                         if (!intel_PLL_is_valid(crtc, &clock))
 739                                                 continue;
 740                                         this_err = abs(clock.dot - target) ;
 741                                         if (this_err < err_most) {
 742                                                 *best_clock = clock;
 743                                                 err_most = this_err;
 744                                                 max_n = clock.n;
 745                                                 found = true;
 746                                         }
 747                                 }
 748                         }
 749                 }
 750         }
 751         return found;
 752 }
 753
 754 static bool
 755 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 756                         int target, int refclk, intel_clock_t *best_clock)
 757 {
 758         struct drm_device *dev = crtc->dev;
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         intel_clock_t clock;
 761         int max_n;
 762         bool found;
 763         int err_most = 47;
 764         found = false;
 765
 766         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 767                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 768                     LVDS_CLKB_POWER_UP)
 769                         clock.p2 = limit->p2.p2_fast;
 770                 else
 771                         clock.p2 = limit->p2.p2_slow;
 772         } else {
 773                 if (target < limit->p2.dot_limit)
 774                         clock.p2 = limit->p2.p2_slow;
 775                 else
 776                         clock.p2 = limit->p2.p2_fast;
 777         }
 778
 779         memset(best_clock, 0, sizeof(*best_clock));
 780         max_n = limit->n.max;
 781         /* based on hardware requriment prefer smaller n to precision */
 782         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 783                 /* based on hardware requirment prefere larger m1,m2, p1 */
 784                 for (clock.m1 = limit->m1.max;
 785                      clock.m1 >= limit->m1.min; clock.m1--) {
 786                         for (clock.m2 = limit->m2.max;
 787                              clock.m2 >= limit->m2.min; clock.m2--) {
 788                                 for (clock.p1 = limit->p1.max;
 789                                      clock.p1 >= limit->p1.min; clock.p1--) {
 790                                         int this_err;
 791
 792                                         intel_clock(dev, refclk, &clock);
 793                                         if (!intel_PLL_is_valid(crtc, &clock))
 794                                                 continue;
 795                                         this_err = abs((10000 - (target*10000/clock.dot)));
 796                                         if (this_err < err_most) {
 797                                                 *best_clock = clock;
 798                                                 err_most = this_err;
 799                                                 max_n = clock.n;
 800                                                 found = true;
 801                                                 /* found on first matching */
 802                                                 goto out;
 803                                         }
 804                                 }
 805                         }
 806                 }
 807         }
 808 out:
 809         return found;
 810 }
 811
 812 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 813 static bool
 814 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 815                       int target, int refclk, intel_clock_t *best_clock)
 816 {
 817     intel_clock_t clock;
 818     if (target < 200000) {
 819         clock.p1 = 2;
 820         clock.p2 = 10;
 821         clock.n = 2;
 822         clock.m1 = 23;
 823         clock.m2 = 8;
 824     } else {
 825         clock.p1 = 1;
 826         clock.p2 = 10;
 827         clock.n = 1;
 828         clock.m1 = 14;
 829         clock.m2 = 2;
 830     }
 831     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 832     clock.p = (clock.p1 * clock.p2);
 833     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 834     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 835     return true;
 836 }
 837
 838 void
 839 intel_wait_for_vblank(struct drm_device *dev)
 840 {
 841         /* Wait for 20ms, i.e. one cycle at 50hz. */
 842         mdelay(20);
 843 }
 844
 845 static int
 846 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 847                     struct drm_framebuffer *old_fb)
 848 {
 849         struct drm_device *dev = crtc->dev;
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         struct drm_i915_master_private *master_priv;
 852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 853         struct intel_framebuffer *intel_fb;
 854         struct drm_i915_gem_object *obj_priv;
 855         struct drm_gem_object *obj;
 856         int pipe = intel_crtc->pipe;
 857         unsigned long Start, Offset;
 858         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 859         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 860         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 861         int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
 862         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 863         u32 dspcntr, alignment;
 864         int ret;
 865
 866         /* no fb bound */
 867         if (!crtc->fb) {
 868                 DRM_DEBUG("No FB bound\n");
 869                 return 0;
 870         }
 871
 872         switch (pipe) {
 873         case 0:
 874         case 1:
 875                 break;
 876         default:
 877                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 878                 return -EINVAL;
 879         }
 880
 881         intel_fb = to_intel_framebuffer(crtc->fb);
 882         obj = intel_fb->obj;
 883         obj_priv = obj->driver_private;
 884
 885         switch (obj_priv->tiling_mode) {
 886         case I915_TILING_NONE:
 887                 alignment = 64 * 1024;
 888                 break;
 889         case I915_TILING_X:
 890                 /* pin() will align the object as required by fence */
 891                 alignment = 0;
 892                 break;
 893         case I915_TILING_Y:
 894                 /* FIXME: Is this true? */
 895                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 896                 return -EINVAL;
 897         default:
 898                 BUG();
 899         }
 900
 901         mutex_lock(&dev->struct_mutex);
 902         ret = i915_gem_object_pin(obj, alignment);
 903         if (ret != 0) {
 904                 mutex_unlock(&dev->struct_mutex);
 905                 return ret;
 906         }
 907
 908         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 909         if (ret != 0) {
 910                 i915_gem_object_unpin(obj);
 911                 mutex_unlock(&dev->struct_mutex);
 912                 return ret;
 913         }
 914
 915         /* Pre-i965 needs to install a fence for tiled scan-out */
 916         if (!IS_I965G(dev) &&
 917             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
 918             obj_priv->tiling_mode != I915_TILING_NONE) {
 919                 ret = i915_gem_object_get_fence_reg(obj);
 920                 if (ret != 0) {
 921                         i915_gem_object_unpin(obj);
 922                         mutex_unlock(&dev->struct_mutex);
 923                         return ret;
 924                 }
 925         }
 926
 927         dspcntr = I915_READ(dspcntr_reg);
 928         /* Mask out pixel format bits in case we change it */
 929         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 930         switch (crtc->fb->bits_per_pixel) {
 931         case 8:
 932                 dspcntr |= DISPPLANE_8BPP;
 933                 break;
 934         case 16:
 935                 if (crtc->fb->depth == 15)
 936                         dspcntr |= DISPPLANE_15_16BPP;
 937                 else
 938                         dspcntr |= DISPPLANE_16BPP;
 939                 break;
 940         case 24:
 941         case 32:
 942                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 943                 break;
 944         default:
 945                 DRM_ERROR("Unknown color depth\n");
 946                 i915_gem_object_unpin(obj);
 947                 mutex_unlock(&dev->struct_mutex);
 948                 return -EINVAL;
 949         }
 950         if (IS_I965G(dev)) {
 951                 if (obj_priv->tiling_mode != I915_TILING_NONE)
 952                         dspcntr |= DISPPLANE_TILED;
 953                 else
 954                         dspcntr &= ~DISPPLANE_TILED;
 955         }
 956
 957         I915_WRITE(dspcntr_reg, dspcntr);
 958
 959         Start = obj_priv->gtt_offset;
 960         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 961
 962         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 963         I915_WRITE(dspstride, crtc->fb->pitch);
 964         if (IS_I965G(dev)) {
 965                 I915_WRITE(dspbase, Offset);
 966                 I915_READ(dspbase);
 967                 I915_WRITE(dspsurf, Start);
 968                 I915_READ(dspsurf);
 969                 I915_WRITE(dsptileoff, (y << 16) | x);
 970         } else {
 971                 I915_WRITE(dspbase, Start + Offset);
 972                 I915_READ(dspbase);
 973         }
 974
 975         intel_wait_for_vblank(dev);
 976
 977         if (old_fb) {
 978                 intel_fb = to_intel_framebuffer(old_fb);
 979                 i915_gem_object_unpin(intel_fb->obj);
 980         }
 981         mutex_unlock(&dev->struct_mutex);
 982
 983         if (!dev->primary->master)
 984                 return 0;
 985
 986         master_priv = dev->primary->master->driver_priv;
 987         if (!master_priv->sarea_priv)
 988                 return 0;
 989
 990         if (pipe) {
 991                 master_priv->sarea_priv->pipeB_x = x;
 992                 master_priv->sarea_priv->pipeB_y = y;
 993         } else {
 994                 master_priv->sarea_priv->pipeA_x = x;
 995                 master_priv->sarea_priv->pipeA_y = y;
 996         }
 997
 998         return 0;
 999 }
1000
1001 /* Disable the VGA plane that we never use */
1002 static void i915_disable_vga (struct drm_device *dev)
1003 {
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         u8 sr1;
1006         u32 vga_reg;
1007
1008         if (IS_IGDNG(dev))
1009                 vga_reg = CPU_VGACNTRL;
1010         else
1011                 vga_reg = VGACNTRL;
1012
1013         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1014                 return;
1015
1016         I915_WRITE8(VGA_SR_INDEX, 1);
1017         sr1 = I915_READ8(VGA_SR_DATA);
1018         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1019         udelay(100);
1020
1021         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1022 }
1023
1024 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1025 {
1026         struct drm_device *dev = crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1029         int pipe = intel_crtc->pipe;
1030         int plane = intel_crtc->plane;
1031         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1032         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1033         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1034         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1035         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1036         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1037         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1038         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1039         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1040         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1041         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1042         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1043         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1044         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1045         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1046         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1047         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1048         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1049         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1050         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1051         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1052         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1053         u32 temp;
1054         int tries = 5, j;
1055
1056         /* XXX: When our outputs are all unaware of DPMS modes other than off
1057          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1058          */
1059         switch (mode) {
1060         case DRM_MODE_DPMS_ON:
1061         case DRM_MODE_DPMS_STANDBY:
1062         case DRM_MODE_DPMS_SUSPEND:
1063                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1064                 /* enable PCH DPLL */
1065                 temp = I915_READ(pch_dpll_reg);
1066                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1067                         I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1068                         I915_READ(pch_dpll_reg);
1069                 }
1070
1071                 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1072                 temp = I915_READ(fdi_rx_reg);
1073                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1074                                 FDI_SEL_PCDCLK |
1075                                 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1076                 I915_READ(fdi_rx_reg);
1077                 udelay(200);
1078
1079                 /* Enable CPU FDI TX PLL, always on for IGDNG */
1080                 temp = I915_READ(fdi_tx_reg);
1081                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1082                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1083                         I915_READ(fdi_tx_reg);
1084                         udelay(100);
1085                 }
1086
1087                 /* Enable CPU pipe */
1088                 temp = I915_READ(pipeconf_reg);
1089                 if ((temp & PIPEACONF_ENABLE) == 0) {
1090                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1091                         I915_READ(pipeconf_reg);
1092                         udelay(100);
1093                 }
1094
1095                 /* configure and enable CPU plane */
1096                 temp = I915_READ(dspcntr_reg);
1097                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1098                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1099                         /* Flush the plane changes */
1100                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1101                 }
1102
1103                 /* enable CPU FDI TX and PCH FDI RX */
1104                 temp = I915_READ(fdi_tx_reg);
1105                 temp |= FDI_TX_ENABLE;
1106                 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1107                 temp &= ~FDI_LINK_TRAIN_NONE;
1108                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1109                 I915_WRITE(fdi_tx_reg, temp);
1110                 I915_READ(fdi_tx_reg);
1111
1112                 temp = I915_READ(fdi_rx_reg);
1113                 temp &= ~FDI_LINK_TRAIN_NONE;
1114                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1115                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1116                 I915_READ(fdi_rx_reg);
1117
1118                 udelay(150);
1119
1120                 /* Train FDI. */
1121                 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1122                    for train result */
1123                 temp = I915_READ(fdi_rx_imr_reg);
1124                 temp &= ~FDI_RX_SYMBOL_LOCK;
1125                 temp &= ~FDI_RX_BIT_LOCK;
1126                 I915_WRITE(fdi_rx_imr_reg, temp);
1127                 I915_READ(fdi_rx_imr_reg);
1128                 udelay(150);
1129
1130                 temp = I915_READ(fdi_rx_iir_reg);
1131                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1132
1133                 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1134                         for (j = 0; j < tries; j++) {
1135                                 temp = I915_READ(fdi_rx_iir_reg);
1136                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1137                                 if (temp & FDI_RX_BIT_LOCK)
1138                                         break;
1139                                 udelay(200);
1140                         }
1141                         if (j != tries)
1142                                 I915_WRITE(fdi_rx_iir_reg,
1143                                                 temp | FDI_RX_BIT_LOCK);
1144                         else
1145                                 DRM_DEBUG("train 1 fail\n");
1146                 } else {
1147                         I915_WRITE(fdi_rx_iir_reg,
1148                                         temp | FDI_RX_BIT_LOCK);
1149                         DRM_DEBUG("train 1 ok 2!\n");
1150                 }
1151                 temp = I915_READ(fdi_tx_reg);
1152                 temp &= ~FDI_LINK_TRAIN_NONE;
1153                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1154                 I915_WRITE(fdi_tx_reg, temp);
1155
1156                 temp = I915_READ(fdi_rx_reg);
1157                 temp &= ~FDI_LINK_TRAIN_NONE;
1158                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1159                 I915_WRITE(fdi_rx_reg, temp);
1160
1161                 udelay(150);
1162
1163                 temp = I915_READ(fdi_rx_iir_reg);
1164                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1165
1166                 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1167                         for (j = 0; j < tries; j++) {
1168                                 temp = I915_READ(fdi_rx_iir_reg);
1169                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1170                                 if (temp & FDI_RX_SYMBOL_LOCK)
1171                                         break;
1172                                 udelay(200);
1173                         }
1174                         if (j != tries) {
1175                                 I915_WRITE(fdi_rx_iir_reg,
1176                                                 temp | FDI_RX_SYMBOL_LOCK);
1177                                 DRM_DEBUG("train 2 ok 1!\n");
1178                         } else
1179                                 DRM_DEBUG("train 2 fail\n");
1180                 } else {
1181                         I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1182                         DRM_DEBUG("train 2 ok 2!\n");
1183                 }
1184                 DRM_DEBUG("train done\n");
1185
1186                 /* set transcoder timing */
1187                 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1188                 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1189                 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1190
1191                 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1192                 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1193                 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1194
1195                 /* enable PCH transcoder */
1196                 temp = I915_READ(transconf_reg);
1197                 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1198                 I915_READ(transconf_reg);
1199
1200                 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1201                         ;
1202
1203                 /* enable normal */
1204
1205                 temp = I915_READ(fdi_tx_reg);
1206                 temp &= ~FDI_LINK_TRAIN_NONE;
1207                 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1208                                 FDI_TX_ENHANCE_FRAME_ENABLE);
1209                 I915_READ(fdi_tx_reg);
1210
1211                 temp = I915_READ(fdi_rx_reg);
1212                 temp &= ~FDI_LINK_TRAIN_NONE;
1213                 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1214                                 FDI_RX_ENHANCE_FRAME_ENABLE);
1215                 I915_READ(fdi_rx_reg);
1216
1217                 /* wait one idle pattern time */
1218                 udelay(100);
1219
1220                 intel_crtc_load_lut(crtc);
1221
1222         break;
1223         case DRM_MODE_DPMS_OFF:
1224                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1225
1226                 i915_disable_vga(dev);
1227
1228                 /* Disable display plane */
1229                 temp = I915_READ(dspcntr_reg);
1230                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1231                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1232                         /* Flush the plane changes */
1233                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1234                         I915_READ(dspbase_reg);
1235                 }
1236
1237                 /* disable cpu pipe, disable after all planes disabled */
1238                 temp = I915_READ(pipeconf_reg);
1239                 if ((temp & PIPEACONF_ENABLE) != 0) {
1240                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1241                         I915_READ(pipeconf_reg);
1242                         /* wait for cpu pipe off, pipe state */
1243                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
1244                                 ;
1245                 } else
1246                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1247
1248                 /* IGDNG-A : disable cpu panel fitter ? */
1249                 temp = I915_READ(pf_ctl_reg);
1250                 if ((temp & PF_ENABLE) != 0) {
1251                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1252                         I915_READ(pf_ctl_reg);
1253                 }
1254
1255                 /* disable CPU FDI tx and PCH FDI rx */
1256                 temp = I915_READ(fdi_tx_reg);
1257                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1258                 I915_READ(fdi_tx_reg);
1259
1260                 temp = I915_READ(fdi_rx_reg);
1261                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1262                 I915_READ(fdi_rx_reg);
1263
1264                 /* still set train pattern 1 */
1265                 temp = I915_READ(fdi_tx_reg);
1266                 temp &= ~FDI_LINK_TRAIN_NONE;
1267                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1268                 I915_WRITE(fdi_tx_reg, temp);
1269
1270                 temp = I915_READ(fdi_rx_reg);
1271                 temp &= ~FDI_LINK_TRAIN_NONE;
1272                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1273                 I915_WRITE(fdi_rx_reg, temp);
1274
1275                 /* disable PCH transcoder */
1276                 temp = I915_READ(transconf_reg);
1277                 if ((temp & TRANS_ENABLE) != 0) {
1278                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1279                         I915_READ(transconf_reg);
1280                         /* wait for PCH transcoder off, transcoder state */
1281                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
1282                                 ;
1283                 }
1284
1285                 /* disable PCH DPLL */
1286                 temp = I915_READ(pch_dpll_reg);
1287                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1288                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1289                         I915_READ(pch_dpll_reg);
1290                 }
1291
1292                 temp = I915_READ(fdi_rx_reg);
1293                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1294                         temp &= ~FDI_SEL_PCDCLK;
1295                         temp &= ~FDI_RX_PLL_ENABLE;
1296                         I915_WRITE(fdi_rx_reg, temp);
1297                         I915_READ(fdi_rx_reg);
1298                 }
1299
1300                 /* Wait for the clocks to turn off. */
1301                 udelay(150);
1302                 break;
1303         }
1304 }
1305
1306 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1307 {
1308         struct drm_device *dev = crtc->dev;
1309         struct drm_i915_private *dev_priv = dev->dev_private;
1310         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1311         int pipe = intel_crtc->pipe;
1312         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1313         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1314         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1315         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1316         u32 temp;
1317
1318         /* XXX: When our outputs are all unaware of DPMS modes other than off
1319          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1320          */
1321         switch (mode) {
1322         case DRM_MODE_DPMS_ON:
1323         case DRM_MODE_DPMS_STANDBY:
1324         case DRM_MODE_DPMS_SUSPEND:
1325                 /* Enable the DPLL */
1326                 temp = I915_READ(dpll_reg);
1327                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1328                         I915_WRITE(dpll_reg, temp);
1329                         I915_READ(dpll_reg);
1330                         /* Wait for the clocks to stabilize. */
1331                         udelay(150);
1332                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1333                         I915_READ(dpll_reg);
1334                         /* Wait for the clocks to stabilize. */
1335                         udelay(150);
1336                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1337                         I915_READ(dpll_reg);
1338                         /* Wait for the clocks to stabilize. */
1339                         udelay(150);
1340                 }
1341
1342                 /* Enable the pipe */
1343                 temp = I915_READ(pipeconf_reg);
1344                 if ((temp & PIPEACONF_ENABLE) == 0)
1345                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1346
1347                 /* Enable the plane */
1348                 temp = I915_READ(dspcntr_reg);
1349                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1350                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1351                         /* Flush the plane changes */
1352                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1353                 }
1354
1355                 intel_crtc_load_lut(crtc);
1356
1357                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1358                 //intel_crtc_dpms_video(crtc, true); TODO
1359                 intel_update_watermarks(dev);
1360         break;
1361         case DRM_MODE_DPMS_OFF:
1362                 intel_update_watermarks(dev);
1363                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1364                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1365
1366                 /* Disable the VGA plane that we never use */
1367                 i915_disable_vga(dev);
1368
1369                 /* Disable display plane */
1370                 temp = I915_READ(dspcntr_reg);
1371                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1372                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1373                         /* Flush the plane changes */
1374                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1375                         I915_READ(dspbase_reg);
1376                 }
1377
1378                 if (!IS_I9XX(dev)) {
1379                         /* Wait for vblank for the disable to take effect */
1380                         intel_wait_for_vblank(dev);
1381                 }
1382
1383                 /* Next, disable display pipes */
1384                 temp = I915_READ(pipeconf_reg);
1385                 if ((temp & PIPEACONF_ENABLE) != 0) {
1386                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1387                         I915_READ(pipeconf_reg);
1388                 }
1389
1390                 /* Wait for vblank for the disable to take effect. */
1391                 intel_wait_for_vblank(dev);
1392
1393                 temp = I915_READ(dpll_reg);
1394                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1395                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1396                         I915_READ(dpll_reg);
1397                 }
1398
1399                 /* Wait for the clocks to turn off. */
1400                 udelay(150);
1401                 break;
1402         }
1403 }
1404
1405 /**
1406  * Sets the power management mode of the pipe and plane.
1407  *
1408  * This code should probably grow support for turning the cursor off and back
1409  * on appropriately at the same time as we're turning the pipe off/on.
1410  */
1411 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1412 {
1413         struct drm_device *dev = crtc->dev;
1414         struct drm_i915_master_private *master_priv;
1415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1416         int pipe = intel_crtc->pipe;
1417         bool enabled;
1418
1419         if (IS_IGDNG(dev))
1420                 igdng_crtc_dpms(crtc, mode);
1421         else
1422                 i9xx_crtc_dpms(crtc, mode);
1423
1424         if (!dev->primary->master)
1425                 return;
1426
1427         master_priv = dev->primary->master->driver_priv;
1428         if (!master_priv->sarea_priv)
1429                 return;
1430
1431         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1432
1433         switch (pipe) {
1434         case 0:
1435                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1436                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1437                 break;
1438         case 1:
1439                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1440                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1441                 break;
1442         default:
1443                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1444                 break;
1445         }
1446
1447         intel_crtc->dpms_mode = mode;
1448 }
1449
1450 static void intel_crtc_prepare (struct drm_crtc *crtc)
1451 {
1452         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1453         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1454 }
1455
1456 static void intel_crtc_commit (struct drm_crtc *crtc)
1457 {
1458         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1459         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1460 }
1461
1462 void intel_encoder_prepare (struct drm_encoder *encoder)
1463 {
1464         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1465         /* lvds has its own version of prepare see intel_lvds_prepare */
1466         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1467 }
1468
1469 void intel_encoder_commit (struct drm_encoder *encoder)
1470 {
1471         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1472         /* lvds has its own version of commit see intel_lvds_commit */
1473         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1474 }
1475
1476 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1477                                   struct drm_display_mode *mode,
1478                                   struct drm_display_mode *adjusted_mode)
1479 {
1480         struct drm_device *dev = crtc->dev;
1481         if (IS_IGDNG(dev)) {
1482                 /* FDI link clock is fixed at 2.7G */
1483                 if (mode->clock * 3 > 27000 * 4)
1484                         return MODE_CLOCK_HIGH;
1485         }
1486         return true;
1487 }
1488
1489
1490 /** Returns the core display clock speed for i830 - i945 */
1491 static int intel_get_core_clock_speed(struct drm_device *dev)
1492 {
1493
1494         /* Core clock values taken from the published datasheets.
1495          * The 830 may go up to 166 Mhz, which we should check.
1496          */
1497         if (IS_I945G(dev))
1498                 return 400000;
1499         else if (IS_I915G(dev))
1500                 return 333000;
1501         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1502                 return 200000;
1503         else if (IS_I915GM(dev)) {
1504                 u16 gcfgc = 0;
1505
1506                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1507
1508                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1509                         return 133000;
1510                 else {
1511                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1512                         case GC_DISPLAY_CLOCK_333_MHZ:
1513                                 return 333000;
1514                         default:
1515                         case GC_DISPLAY_CLOCK_190_200_MHZ:
1516                                 return 190000;
1517                         }
1518                 }
1519         } else if (IS_I865G(dev))
1520                 return 266000;
1521         else if (IS_I855(dev)) {
1522                 u16 hpllcc = 0;
1523                 /* Assume that the hardware is in the high speed state.  This
1524                  * should be the default.
1525                  */
1526                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1527                 case GC_CLOCK_133_200:
1528                 case GC_CLOCK_100_200:
1529                         return 200000;
1530                 case GC_CLOCK_166_250:
1531                         return 250000;
1532                 case GC_CLOCK_100_133:
1533                         return 133000;
1534                 }
1535         } else /* 852, 830 */
1536                 return 133000;
1537
1538         return 0; /* Silence gcc warning */
1539 }
1540
1541 /**
1542  * Return the pipe currently connected to the panel fitter,
1543  * or -1 if the panel fitter is not present or not in use
1544  */
1545 static int intel_panel_fitter_pipe (struct drm_device *dev)
1546 {
1547         struct drm_i915_private *dev_priv = dev->dev_private;
1548         u32  pfit_control;
1549
1550         /* i830 doesn't have a panel fitter */
1551         if (IS_I830(dev))
1552                 return -1;
1553
1554         pfit_control = I915_READ(PFIT_CONTROL);
1555
1556         /* See if the panel fitter is in use */
1557         if ((pfit_control & PFIT_ENABLE) == 0)
1558                 return -1;
1559
1560         /* 965 can place panel fitter on either pipe */
1561         if (IS_I965G(dev))
1562                 return (pfit_control >> 29) & 0x3;
1563
1564         /* older chips can only use pipe 1 */
1565         return 1;
1566 }
1567
1568 struct fdi_m_n {
1569         u32        tu;
1570         u32        gmch_m;
1571         u32        gmch_n;
1572         u32        link_m;
1573         u32        link_n;
1574 };
1575
1576 static void
1577 fdi_reduce_ratio(u32 *num, u32 *den)
1578 {
1579         while (*num > 0xffffff || *den > 0xffffff) {
1580                 *num >>= 1;
1581                 *den >>= 1;
1582         }
1583 }
1584
1585 #define DATA_N 0x800000
1586 #define LINK_N 0x80000
1587
1588 static void
1589 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1590                 int pixel_clock, int link_clock,
1591                 struct fdi_m_n *m_n)
1592 {
1593         u64 temp;
1594
1595         m_n->tu = 64; /* default size */
1596
1597         temp = (u64) DATA_N * pixel_clock;
1598         temp = div_u64(temp, link_clock);
1599         m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
1600         m_n->gmch_n = DATA_N;
1601         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1602
1603         temp = (u64) LINK_N * pixel_clock;
1604         m_n->link_m = div_u64(temp, link_clock);
1605         m_n->link_n = LINK_N;
1606         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1607 }
1608
1609
1610 struct intel_watermark_params {
1611         unsigned long fifo_size;
1612         unsigned long max_wm;
1613         unsigned long default_wm;
1614         unsigned long guard_size;
1615         unsigned long cacheline_size;
1616 };
1617
1618 /* IGD has different values for various configs */
1619 static struct intel_watermark_params igd_display_wm = {
1620         IGD_DISPLAY_FIFO,
1621         IGD_MAX_WM,
1622         IGD_DFT_WM,
1623         IGD_GUARD_WM,
1624         IGD_FIFO_LINE_SIZE
1625 };
1626 static struct intel_watermark_params igd_display_hplloff_wm = {
1627         IGD_DISPLAY_FIFO,
1628         IGD_MAX_WM,
1629         IGD_DFT_HPLLOFF_WM,
1630         IGD_GUARD_WM,
1631         IGD_FIFO_LINE_SIZE
1632 };
1633 static struct intel_watermark_params igd_cursor_wm = {
1634         IGD_CURSOR_FIFO,
1635         IGD_CURSOR_MAX_WM,
1636         IGD_CURSOR_DFT_WM,
1637         IGD_CURSOR_GUARD_WM,
1638         IGD_FIFO_LINE_SIZE,
1639 };
1640 static struct intel_watermark_params igd_cursor_hplloff_wm = {
1641         IGD_CURSOR_FIFO,
1642         IGD_CURSOR_MAX_WM,
1643         IGD_CURSOR_DFT_WM,
1644         IGD_CURSOR_GUARD_WM,
1645         IGD_FIFO_LINE_SIZE
1646 };
1647 static struct intel_watermark_params i945_wm_info = {
1648         I945_FIFO_SIZE,
1649         I915_MAX_WM,
1650         1,
1651         2,
1652         I915_FIFO_LINE_SIZE
1653 };
1654 static struct intel_watermark_params i915_wm_info = {
1655         I915_FIFO_SIZE,
1656         I915_MAX_WM,
1657         1,
1658         2,
1659         I915_FIFO_LINE_SIZE
1660 };
1661 static struct intel_watermark_params i855_wm_info = {
1662         I855GM_FIFO_SIZE,
1663         I915_MAX_WM,
1664         1,
1665         2,
1666         I830_FIFO_LINE_SIZE
1667 };
1668 static struct intel_watermark_params i830_wm_info = {
1669         I830_FIFO_SIZE,
1670         I915_MAX_WM,
1671         1,
1672         2,
1673         I830_FIFO_LINE_SIZE
1674 };
1675
1676 /**
1677  * intel_calculate_wm - calculate watermark level
1678  * @clock_in_khz: pixel clock
1679  * @wm: chip FIFO params
1680  * @pixel_size: display pixel size
1681  * @latency_ns: memory latency for the platform
1682  *
1683  * Calculate the watermark level (the level at which the display plane will
1684  * start fetching from memory again).  Each chip has a different display
1685  * FIFO size and allocation, so the caller needs to figure that out and pass
1686  * in the correct intel_watermark_params structure.
1687  *
1688  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1689  * on the pixel size.  When it reaches the watermark level, it'll start
1690  * fetching FIFO line sized based chunks from memory until the FIFO fills
1691  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1692  * will occur, and a display engine hang could result.
1693  */
1694 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1695                                         struct intel_watermark_params *wm,
1696                                         int pixel_size,
1697                                         unsigned long latency_ns)
1698 {
1699         long entries_required, wm_size;
1700
1701         entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
1702         entries_required /= wm->cacheline_size;
1703
1704         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
1705
1706         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
1707
1708         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
1709
1710         /* Don't promote wm_size to unsigned... */
1711         if (wm_size > (long)wm->max_wm)
1712                 wm_size = wm->max_wm;
1713         if (wm_size <= 0)
1714                 wm_size = wm->default_wm;
1715         return wm_size;
1716 }
1717
1718 struct cxsr_latency {
1719         int is_desktop;
1720         unsigned long fsb_freq;
1721         unsigned long mem_freq;
1722         unsigned long display_sr;
1723         unsigned long display_hpll_disable;
1724         unsigned long cursor_sr;
1725         unsigned long cursor_hpll_disable;
1726 };
1727
1728 static struct cxsr_latency cxsr_latency_table[] = {
1729         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
1730         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
1731         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
1732
1733         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
1734         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
1735         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
1736
1737         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
1738         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
1739         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
1740
1741         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
1742         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
1743         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
1744
1745         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
1746         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
1747         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
1748
1749         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
1750         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
1751         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
1752 };
1753
1754 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
1755                                                    int mem)
1756 {
1757         int i;
1758         struct cxsr_latency *latency;
1759
1760         if (fsb == 0 || mem == 0)
1761                 return NULL;
1762
1763         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
1764                 latency = &cxsr_latency_table[i];
1765                 if (is_desktop == latency->is_desktop &&
1766                         fsb == latency->fsb_freq && mem == latency->mem_freq)
1767                         break;
1768         }
1769         if (i >= ARRAY_SIZE(cxsr_latency_table)) {
1770                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1771                 return NULL;
1772         }
1773         return latency;
1774 }
1775
1776 static void igd_disable_cxsr(struct drm_device *dev)
1777 {
1778         struct drm_i915_private *dev_priv = dev->dev_private;
1779         u32 reg;
1780
1781         /* deactivate cxsr */
1782         reg = I915_READ(DSPFW3);
1783         reg &= ~(IGD_SELF_REFRESH_EN);
1784         I915_WRITE(DSPFW3, reg);
1785         DRM_INFO("Big FIFO is disabled\n");
1786 }
1787
1788 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
1789                             int pixel_size)
1790 {
1791         struct drm_i915_private *dev_priv = dev->dev_private;
1792         u32 reg;
1793         unsigned long wm;
1794         struct cxsr_latency *latency;
1795
1796         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
1797                 dev_priv->mem_freq);
1798         if (!latency) {
1799                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1800                 igd_disable_cxsr(dev);
1801                 return;
1802         }
1803
1804         /* Display SR */
1805         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
1806                                 latency->display_sr);
1807         reg = I915_READ(DSPFW1);
1808         reg &= 0x7fffff;
1809         reg |= wm << 23;
1810         I915_WRITE(DSPFW1, reg);
1811         DRM_DEBUG("DSPFW1 register is %x\n", reg);
1812
1813         /* cursor SR */
1814         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
1815                                 latency->cursor_sr);
1816         reg = I915_READ(DSPFW3);
1817         reg &= ~(0x3f << 24);
1818         reg |= (wm & 0x3f) << 24;
1819         I915_WRITE(DSPFW3, reg);
1820
1821         /* Display HPLL off SR */
1822         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
1823                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
1824         reg = I915_READ(DSPFW3);
1825         reg &= 0xfffffe00;
1826         reg |= wm & 0x1ff;
1827         I915_WRITE(DSPFW3, reg);
1828
1829         /* cursor HPLL off SR */
1830         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
1831                                 latency->cursor_hpll_disable);
1832         reg = I915_READ(DSPFW3);
1833         reg &= ~(0x3f << 16);
1834         reg |= (wm & 0x3f) << 16;
1835         I915_WRITE(DSPFW3, reg);
1836         DRM_DEBUG("DSPFW3 register is %x\n", reg);
1837
1838         /* activate cxsr */
1839         reg = I915_READ(DSPFW3);
1840         reg |= IGD_SELF_REFRESH_EN;
1841         I915_WRITE(DSPFW3, reg);
1842
1843         DRM_INFO("Big FIFO is enabled\n");
1844
1845         return;
1846 }
1847
1848 const static int latency_ns = 3000; /* default for non-igd platforms */
1849
1850 static int intel_get_fifo_size(struct drm_device *dev, int plane)
1851 {
1852         struct drm_i915_private *dev_priv = dev->dev_private;
1853         uint32_t dsparb = I915_READ(DSPARB);
1854         int size;
1855
1856         if (IS_I9XX(dev)) {
1857                 if (plane == 0)
1858                         size = dsparb & 0x7f;
1859                 else
1860                         size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
1861                                 (dsparb & 0x7f);
1862         } else if (IS_I85X(dev)) {
1863                 if (plane == 0)
1864                         size = dsparb & 0x1ff;
1865                 else
1866                         size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
1867                                 (dsparb & 0x1ff);
1868                 size >>= 1; /* Convert to cachelines */
1869         } else {
1870                 size = dsparb & 0x7f;
1871                 size >>= 1; /* Convert to cachelines */
1872         }
1873
1874         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
1875                   size);
1876
1877         return size;
1878 }
1879
1880 static void i965_update_wm(struct drm_device *dev)
1881 {
1882         struct drm_i915_private *dev_priv = dev->dev_private;
1883
1884         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
1885
1886         /* 965 has limitations... */
1887         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
1888         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1889 }
1890
1891 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
1892                            int planeb_clock, int sr_hdisplay, int pixel_size)
1893 {
1894         struct drm_i915_private *dev_priv = dev->dev_private;
1895         uint32_t fwater_lo;
1896         uint32_t fwater_hi;
1897         int total_size, cacheline_size, cwm, srwm = 1;
1898         int planea_wm, planeb_wm;
1899         struct intel_watermark_params planea_params, planeb_params;
1900         unsigned long line_time_us;
1901         int sr_clock, sr_entries = 0;
1902
1903         /* Create copies of the base settings for each pipe */
1904         if (IS_I965GM(dev) || IS_I945GM(dev))
1905                 planea_params = planeb_params = i945_wm_info;
1906         else if (IS_I9XX(dev))
1907                 planea_params = planeb_params = i915_wm_info;
1908         else
1909                 planea_params = planeb_params = i855_wm_info;
1910
1911         /* Grab a couple of global values before we overwrite them */
1912         total_size = planea_params.fifo_size;
1913         cacheline_size = planea_params.cacheline_size;
1914
1915         /* Update per-plane FIFO sizes */
1916         planea_params.fifo_size = intel_get_fifo_size(dev, 0);
1917         planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
1918
1919         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
1920                                        pixel_size, latency_ns);
1921         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
1922                                        pixel_size, latency_ns);
1923         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1924
1925         /*
1926          * Overlay gets an aggressive default since video jitter is bad.
1927          */
1928         cwm = 2;
1929
1930         /* Calc sr entries for one plane configs */
1931         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
1932                 /* self-refresh has much higher latency */
1933                 const static int sr_latency_ns = 6000;
1934
1935                 sr_clock = planea_clock ? planea_clock : planeb_clock;
1936                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
1937
1938                 /* Use ns/us then divide to preserve precision */
1939                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
1940                               pixel_size * sr_hdisplay) / 1000;
1941                 sr_entries = roundup(sr_entries / cacheline_size, 1);
1942                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
1943                 srwm = total_size - sr_entries;
1944                 if (srwm < 0)
1945                         srwm = 1;
1946                 if (IS_I9XX(dev))
1947                         I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
1948         }
1949
1950         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1951                   planea_wm, planeb_wm, cwm, srwm);
1952
1953         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1954         fwater_hi = (cwm & 0x1f);
1955
1956         /* Set request length to 8 cachelines per fetch */
1957         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1958         fwater_hi = fwater_hi | (1 << 8);
1959
1960         I915_WRITE(FW_BLC, fwater_lo);
1961         I915_WRITE(FW_BLC2, fwater_hi);
1962 }
1963
1964 static void i830_update_wm(struct drm_device *dev, int planea_clock,
1965                            int pixel_size)
1966 {
1967         struct drm_i915_private *dev_priv = dev->dev_private;
1968         uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
1969         int planea_wm;
1970
1971         i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
1972
1973         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
1974                                        pixel_size, latency_ns);
1975         fwater_lo = fwater_lo | planea_wm;
1976
1977         I915_WRITE(FW_BLC, fwater_lo);
1978 }
1979
1980 /**
1981  * intel_update_watermarks - update FIFO watermark values based on current modes
1982  *
1983  * Calculate watermark values for the various WM regs based on current mode
1984  * and plane configuration.
1985  *
1986  * There are several cases to deal with here:
1987  *   - normal (i.e. non-self-refresh)
1988  *   - self-refresh (SR) mode
1989  *   - lines are large relative to FIFO size (buffer can hold up to 2)
1990  *   - lines are small relative to FIFO size (buffer can hold more than 2
1991  *     lines), so need to account for TLB latency
1992  *
1993  *   The normal calculation is:
1994  *     watermark = dotclock * bytes per pixel * latency
1995  *   where latency is platform & configuration dependent (we assume pessimal
1996  *   values here).
1997  *
1998  *   The SR calculation is:
1999  *     watermark = (trunc(latency/line time)+1) * surface width *
2000  *       bytes per pixel
2001  *   where
2002  *     line time = htotal / dotclock
2003  *   and latency is assumed to be high, as above.
2004  *
2005  * The final value programmed to the register should always be rounded up,
2006  * and include an extra 2 entries to account for clock crossings.
2007  *
2008  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2009  * to set the non-SR watermarks to 8.
2010   */
2011 static void intel_update_watermarks(struct drm_device *dev)
2012 {
2013         struct drm_crtc *crtc;
2014         struct intel_crtc *intel_crtc;
2015         int sr_hdisplay = 0;
2016         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2017         int enabled = 0, pixel_size = 0;
2018
2019         if (DSPARB_HWCONTROL(dev))
2020                 return;
2021
2022         /* Get the clock config from both planes */
2023         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2024                 intel_crtc = to_intel_crtc(crtc);
2025                 if (crtc->enabled) {
2026                         enabled++;
2027                         if (intel_crtc->plane == 0) {
2028                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2029                                           intel_crtc->pipe, crtc->mode.clock);
2030                                 planea_clock = crtc->mode.clock;
2031                         } else {
2032                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2033                                           intel_crtc->pipe, crtc->mode.clock);
2034                                 planeb_clock = crtc->mode.clock;
2035                         }
2036                         sr_hdisplay = crtc->mode.hdisplay;
2037                         sr_clock = crtc->mode.clock;
2038                         if (crtc->fb)
2039                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2040                         else
2041                                 pixel_size = 4; /* by default */
2042                 }
2043         }
2044
2045         if (enabled <= 0)
2046                 return;
2047
2048         /* Single plane configs can enable self refresh */
2049         if (enabled == 1 && IS_IGD(dev))
2050                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2051         else if (IS_IGD(dev))
2052                 igd_disable_cxsr(dev);
2053
2054         if (IS_I965G(dev))
2055                 i965_update_wm(dev);
2056         else if (IS_I9XX(dev) || IS_MOBILE(dev))
2057                 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
2058                                pixel_size);
2059         else
2060                 i830_update_wm(dev, planea_clock, pixel_size);
2061 }
2062
2063 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2064                                struct drm_display_mode *mode,
2065                                struct drm_display_mode *adjusted_mode,
2066                                int x, int y,
2067                                struct drm_framebuffer *old_fb)
2068 {
2069         struct drm_device *dev = crtc->dev;
2070         struct drm_i915_private *dev_priv = dev->dev_private;
2071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2072         int pipe = intel_crtc->pipe;
2073         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2074         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2075         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2076         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
2077         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2078         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2079         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2080         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2081         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2082         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2083         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2084         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
2085         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
2086         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2087         int refclk, num_outputs = 0;
2088         intel_clock_t clock;
2089         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
2090         bool ok, is_sdvo = false, is_dvo = false;
2091         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2092         struct drm_mode_config *mode_config = &dev->mode_config;
2093         struct drm_connector *connector;
2094         const intel_limit_t *limit;
2095         int ret;
2096         struct fdi_m_n m_n = {0};
2097         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2098         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2099         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2100         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2101         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2102         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2103         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2104         int lvds_reg = LVDS;
2105         u32 temp;
2106         int sdvo_pixel_multiply;
2107
2108         drm_vblank_pre_modeset(dev, pipe);
2109
2110         list_for_each_entry(connector, &mode_config->connector_list, head) {
2111                 struct intel_output *intel_output = to_intel_output(connector);
2112
2113                 if (!connector->encoder || connector->encoder->crtc != crtc)
2114                         continue;
2115
2116                 switch (intel_output->type) {
2117                 case INTEL_OUTPUT_LVDS:
2118                         is_lvds = true;
2119                         break;
2120                 case INTEL_OUTPUT_SDVO:
2121                 case INTEL_OUTPUT_HDMI:
2122                         is_sdvo = true;
2123                         if (intel_output->needs_tv_clock)
2124                                 is_tv = true;
2125                         break;
2126                 case INTEL_OUTPUT_DVO:
2127                         is_dvo = true;
2128                         break;
2129                 case INTEL_OUTPUT_TVOUT:
2130                         is_tv = true;
2131                         break;
2132                 case INTEL_OUTPUT_ANALOG:
2133                         is_crt = true;
2134                         break;
2135                 case INTEL_OUTPUT_DISPLAYPORT:
2136                         is_dp = true;
2137                         break;
2138                 }
2139
2140                 num_outputs++;
2141         }
2142
2143         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2144                 refclk = dev_priv->lvds_ssc_freq * 1000;
2145                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2146         } else if (IS_I9XX(dev)) {
2147                 refclk = 96000;
2148                 if (IS_IGDNG(dev))
2149                         refclk = 120000; /* 120Mhz refclk */
2150         } else {
2151                 refclk = 48000;
2152         }
2153
2154
2155         /*
2156          * Returns a set of divisors for the desired target clock with the given
2157          * refclk, or FALSE.  The returned values represent the clock equation:
2158          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2159          */
2160         limit = intel_limit(crtc);
2161         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2162         if (!ok) {
2163                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2164                 drm_vblank_post_modeset(dev, pipe);
2165                 return -EINVAL;
2166         }
2167
2168         /* SDVO TV has fixed PLL values depend on its clock range,
2169            this mirrors vbios setting. */
2170         if (is_sdvo && is_tv) {
2171                 if (adjusted_mode->clock >= 100000
2172                                 && adjusted_mode->clock < 140500) {
2173                         clock.p1 = 2;
2174                         clock.p2 = 10;
2175                         clock.n = 3;
2176                         clock.m1 = 16;
2177                         clock.m2 = 8;
2178                 } else if (adjusted_mode->clock >= 140500
2179                                 && adjusted_mode->clock <= 200000) {
2180                         clock.p1 = 1;
2181                         clock.p2 = 10;
2182                         clock.n = 6;
2183                         clock.m1 = 12;
2184                         clock.m2 = 8;
2185                 }
2186         }
2187
2188         /* FDI link */
2189         if (IS_IGDNG(dev))
2190                 igdng_compute_m_n(3, 4, /* lane num 4 */
2191                                 adjusted_mode->clock,
2192                                 270000, /* lane clock */
2193                                 &m_n);
2194
2195         if (IS_IGD(dev))
2196                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2197         else
2198                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2199
2200         if (!IS_IGDNG(dev))
2201                 dpll = DPLL_VGA_MODE_DIS;
2202
2203         if (IS_I9XX(dev)) {
2204                 if (is_lvds)
2205                         dpll |= DPLLB_MODE_LVDS;
2206                 else
2207                         dpll |= DPLLB_MODE_DAC_SERIAL;
2208                 if (is_sdvo) {
2209                         dpll |= DPLL_DVO_HIGH_SPEED;
2210                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2211                         if (IS_I945G(dev) || IS_I945GM(dev))
2212                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2213                         else if (IS_IGDNG(dev))
2214                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2215                 }
2216                 if (is_dp)
2217                         dpll |= DPLL_DVO_HIGH_SPEED;
2218
2219                 /* compute bitmask from p1 value */
2220                 if (IS_IGD(dev))
2221                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2222                 else {
2223                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2224                         /* also FPA1 */
2225                         if (IS_IGDNG(dev))
2226                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2227                 }
2228                 switch (clock.p2) {
2229                 case 5:
2230                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2231                         break;
2232                 case 7:
2233                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2234                         break;
2235                 case 10:
2236                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2237                         break;
2238                 case 14:
2239                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2240                         break;
2241                 }
2242                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2243                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2244         } else {
2245                 if (is_lvds) {
2246                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2247                 } else {
2248                         if (clock.p1 == 2)
2249                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2250                         else
2251                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2252                         if (clock.p2 == 4)
2253                                 dpll |= PLL_P2_DIVIDE_BY_4;
2254                 }
2255         }
2256
2257         if (is_sdvo && is_tv)
2258                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2259         else if (is_tv)
2260                 /* XXX: just matching BIOS for now */
2261                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2262                 dpll |= 3;
2263         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2264                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2265         else
2266                 dpll |= PLL_REF_INPUT_DREFCLK;
2267
2268         /* setup pipeconf */
2269         pipeconf = I915_READ(pipeconf_reg);
2270
2271         /* Set up the display plane register */
2272         dspcntr = DISPPLANE_GAMMA_ENABLE;
2273
2274         /* IGDNG's plane is forced to pipe, bit 24 is to
2275            enable color space conversion */
2276         if (!IS_IGDNG(dev)) {
2277                 if (pipe == 0)
2278                         dspcntr |= DISPPLANE_SEL_PIPE_A;
2279                 else
2280                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2281         }
2282
2283         if (pipe == 0 && !IS_I965G(dev)) {
2284                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2285                  * core speed.
2286                  *
2287                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2288                  * pipe == 0 check?
2289                  */
2290                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2291                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
2292                 else
2293                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2294         }
2295
2296         dspcntr |= DISPLAY_PLANE_ENABLE;
2297         pipeconf |= PIPEACONF_ENABLE;
2298         dpll |= DPLL_VCO_ENABLE;
2299
2300
2301         /* Disable the panel fitter if it was on our pipe */
2302         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2303                 I915_WRITE(PFIT_CONTROL, 0);
2304
2305         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2306         drm_mode_debug_printmodeline(mode);
2307
2308         /* assign to IGDNG registers */
2309         if (IS_IGDNG(dev)) {
2310                 fp_reg = pch_fp_reg;
2311                 dpll_reg = pch_dpll_reg;
2312         }
2313
2314         if (dpll & DPLL_VCO_ENABLE) {
2315                 I915_WRITE(fp_reg, fp);
2316                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2317                 I915_READ(dpll_reg);
2318                 udelay(150);
2319         }
2320
2321         if (IS_IGDNG(dev)) {
2322                 /* enable PCH clock reference source */
2323                 /* XXX need to change the setting for other outputs */
2324                 u32 temp;
2325                 temp = I915_READ(PCH_DREF_CONTROL);
2326                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2327                 temp |= DREF_NONSPREAD_CK505_ENABLE;
2328                 temp &= ~DREF_SSC_SOURCE_MASK;
2329                 temp |= DREF_SSC_SOURCE_ENABLE;
2330                 temp &= ~DREF_SSC1_ENABLE;
2331                 /* if no eDP, disable source output to CPU */
2332                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2333                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2334                 I915_WRITE(PCH_DREF_CONTROL, temp);
2335         }
2336
2337         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2338          * This is an exception to the general rule that mode_set doesn't turn
2339          * things on.
2340          */
2341         if (is_lvds) {
2342                 u32 lvds;
2343
2344                 if (IS_IGDNG(dev))
2345                         lvds_reg = PCH_LVDS;
2346
2347                 lvds = I915_READ(lvds_reg);
2348                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2349                 /* Set the B0-B3 data pairs corresponding to whether we're going to
2350                  * set the DPLLs for dual-channel mode or not.
2351                  */
2352                 if (clock.p2 == 7)
2353                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2354                 else
2355                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2356
2357                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2358                  * appropriately here, but we need to look more thoroughly into how
2359                  * panels behave in the two modes.
2360                  */
2361
2362                 I915_WRITE(lvds_reg, lvds);
2363                 I915_READ(lvds_reg);
2364         }
2365         if (is_dp)
2366                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2367
2368         I915_WRITE(fp_reg, fp);
2369         I915_WRITE(dpll_reg, dpll);
2370         I915_READ(dpll_reg);
2371         /* Wait for the clocks to stabilize. */
2372         udelay(150);
2373
2374         if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2375                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2376                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2377                            ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2378         } else {
2379                 /* write it again -- the BIOS does, after all */
2380                 I915_WRITE(dpll_reg, dpll);
2381         }
2382         I915_READ(dpll_reg);
2383         /* Wait for the clocks to stabilize. */
2384         udelay(150);
2385
2386         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2387                    ((adjusted_mode->crtc_htotal - 1) << 16));
2388         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2389                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
2390         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2391                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
2392         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2393                    ((adjusted_mode->crtc_vtotal - 1) << 16));
2394         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2395                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
2396         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2397                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
2398         /* pipesrc and dspsize control the size that is scaled from, which should
2399          * always be the user's requested size.
2400          */
2401         if (!IS_IGDNG(dev)) {
2402                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2403                                 (mode->hdisplay - 1));
2404                 I915_WRITE(dsppos_reg, 0);
2405         }
2406         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2407
2408         if (IS_IGDNG(dev)) {
2409                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2410                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2411                 I915_WRITE(link_m1_reg, m_n.link_m);
2412                 I915_WRITE(link_n1_reg, m_n.link_n);
2413
2414                  /* enable FDI RX PLL too */
2415                 temp = I915_READ(fdi_rx_reg);
2416                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2417                 udelay(200);
2418         }
2419
2420         I915_WRITE(pipeconf_reg, pipeconf);
2421         I915_READ(pipeconf_reg);
2422
2423         intel_wait_for_vblank(dev);
2424
2425         I915_WRITE(dspcntr_reg, dspcntr);
2426
2427         /* Flush the plane changes */
2428         ret = intel_pipe_set_base(crtc, x, y, old_fb);
2429
2430         intel_update_watermarks(dev);
2431
2432         drm_vblank_post_modeset(dev, pipe);
2433
2434         return ret;
2435 }
2436
2437 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2438 void intel_crtc_load_lut(struct drm_crtc *crtc)
2439 {
2440         struct drm_device *dev = crtc->dev;
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2443         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2444         int i;
2445
2446         /* The clocks have to be on to load the palette. */
2447         if (!crtc->enabled)
2448                 return;
2449
2450         /* use legacy palette for IGDNG */
2451         if (IS_IGDNG(dev))
2452                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2453                                                    LGC_PALETTE_B;
2454
2455         for (i = 0; i < 256; i++) {
2456                 I915_WRITE(palreg + 4 * i,
2457                            (intel_crtc->lut_r[i] << 16) |
2458                            (intel_crtc->lut_g[i] << 8) |
2459                            intel_crtc->lut_b[i]);
2460         }
2461 }
2462
2463 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2464                                  struct drm_file *file_priv,
2465                                  uint32_t handle,
2466                                  uint32_t width, uint32_t height)
2467 {
2468         struct drm_device *dev = crtc->dev;
2469         struct drm_i915_private *dev_priv = dev->dev_private;
2470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2471         struct drm_gem_object *bo;
2472         struct drm_i915_gem_object *obj_priv;
2473         int pipe = intel_crtc->pipe;
2474         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2475         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2476         uint32_t temp = I915_READ(control);
2477         size_t addr;
2478         int ret;
2479
2480         DRM_DEBUG("\n");
2481
2482         /* if we want to turn off the cursor ignore width and height */
2483         if (!handle) {
2484                 DRM_DEBUG("cursor off\n");
2485                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2486                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2487                         temp |= CURSOR_MODE_DISABLE;
2488                 } else {
2489                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2490                 }
2491                 addr = 0;
2492                 bo = NULL;
2493                 mutex_lock(&dev->struct_mutex);
2494                 goto finish;
2495         }
2496
2497         /* Currently we only support 64x64 cursors */
2498         if (width != 64 || height != 64) {
2499                 DRM_ERROR("we currently only support 64x64 cursors\n");
2500                 return -EINVAL;
2501         }
2502
2503         bo = drm_gem_object_lookup(dev, file_priv, handle);
2504         if (!bo)
2505                 return -ENOENT;
2506
2507         obj_priv = bo->driver_private;
2508
2509         if (bo->size < width * height * 4) {
2510                 DRM_ERROR("buffer is to small\n");
2511                 ret = -ENOMEM;
2512                 goto fail;
2513         }
2514
2515         /* we only need to pin inside GTT if cursor is non-phy */
2516         mutex_lock(&dev->struct_mutex);
2517         if (!dev_priv->cursor_needs_physical) {
2518                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
2519                 if (ret) {
2520                         DRM_ERROR("failed to pin cursor bo\n");
2521                         goto fail_locked;
2522                 }
2523                 addr = obj_priv->gtt_offset;
2524         } else {
2525                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
2526                 if (ret) {
2527                         DRM_ERROR("failed to attach phys object\n");
2528                         goto fail_locked;
2529                 }
2530                 addr = obj_priv->phys_obj->handle->busaddr;
2531         }
2532
2533         if (!IS_I9XX(dev))
2534                 I915_WRITE(CURSIZE, (height << 12) | width);
2535
2536         /* Hooray for CUR*CNTR differences */
2537         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2538                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
2539                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
2540                 temp |= (pipe << 28); /* Connect to correct pipe */
2541         } else {
2542                 temp &= ~(CURSOR_FORMAT_MASK);
2543                 temp |= CURSOR_ENABLE;
2544                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
2545         }
2546
2547  finish:
2548         I915_WRITE(control, temp);
2549         I915_WRITE(base, addr);
2550
2551         if (intel_crtc->cursor_bo) {
2552                 if (dev_priv->cursor_needs_physical) {
2553                         if (intel_crtc->cursor_bo != bo)
2554                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
2555                 } else
2556                         i915_gem_object_unpin(intel_crtc->cursor_bo);
2557                 drm_gem_object_unreference(intel_crtc->cursor_bo);
2558         }
2559         mutex_unlock(&dev->struct_mutex);
2560
2561         intel_crtc->cursor_addr = addr;
2562         intel_crtc->cursor_bo = bo;
2563
2564         return 0;
2565 fail:
2566         mutex_lock(&dev->struct_mutex);
2567 fail_locked:
2568         drm_gem_object_unreference(bo);
2569         mutex_unlock(&dev->struct_mutex);
2570         return ret;
2571 }
2572
2573 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2574 {
2575         struct drm_device *dev = crtc->dev;
2576         struct drm_i915_private *dev_priv = dev->dev_private;
2577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2578         int pipe = intel_crtc->pipe;
2579         uint32_t temp = 0;
2580         uint32_t adder;
2581
2582         if (x < 0) {
2583                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
2584                 x = -x;
2585         }
2586         if (y < 0) {
2587                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
2588                 y = -y;
2589         }
2590
2591         temp |= x << CURSOR_X_SHIFT;
2592         temp |= y << CURSOR_Y_SHIFT;
2593
2594         adder = intel_crtc->cursor_addr;
2595         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2596         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2597
2598         return 0;
2599 }
2600
2601 /** Sets the color ramps on behalf of RandR */
2602 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2603                                  u16 blue, int regno)
2604 {
2605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2606
2607         intel_crtc->lut_r[regno] = red >> 8;
2608         intel_crtc->lut_g[regno] = green >> 8;
2609         intel_crtc->lut_b[regno] = blue >> 8;
2610 }
2611
2612 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2613                                  u16 *blue, uint32_t size)
2614 {
2615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2616         int i;
2617
2618         if (size != 256)
2619                 return;
2620
2621         for (i = 0; i < 256; i++) {
2622                 intel_crtc->lut_r[i] = red[i] >> 8;
2623                 intel_crtc->lut_g[i] = green[i] >> 8;
2624                 intel_crtc->lut_b[i] = blue[i] >> 8;
2625         }
2626
2627         intel_crtc_load_lut(crtc);
2628 }
2629
2630 /**
2631  * Get a pipe with a simple mode set on it for doing load-based monitor
2632  * detection.
2633  *
2634  * It will be up to the load-detect code to adjust the pipe as appropriate for
2635  * its requirements.  The pipe will be connected to no other outputs.
2636  *
2637  * Currently this code will only succeed if there is a pipe with no outputs
2638  * configured for it.  In the future, it could choose to temporarily disable
2639  * some outputs to free up a pipe for its use.
2640  *
2641  * \return crtc, or NULL if no pipes are available.
2642  */
2643
2644 /* VESA 640x480x72Hz mode to set on the pipe */
2645 static struct drm_display_mode load_detect_mode = {
2646         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2647                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2648 };
2649
2650 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2651                                             struct drm_display_mode *mode,
2652                                             int *dpms_mode)
2653 {
2654         struct intel_crtc *intel_crtc;
2655         struct drm_crtc *possible_crtc;
2656         struct drm_crtc *supported_crtc =NULL;
2657         struct drm_encoder *encoder = &intel_output->enc;
2658         struct drm_crtc *crtc = NULL;
2659         struct drm_device *dev = encoder->dev;
2660         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2661         struct drm_crtc_helper_funcs *crtc_funcs;
2662         int i = -1;
2663
2664         /*
2665          * Algorithm gets a little messy:
2666          *   - if the connector already has an assigned crtc, use it (but make
2667          *     sure it's on first)
2668          *   - try to find the first unused crtc that can drive this connector,
2669          *     and use that if we find one
2670          *   - if there are no unused crtcs available, try to use the first
2671          *     one we found that supports the connector
2672          */
2673
2674         /* See if we already have a CRTC for this connector */
2675         if (encoder->crtc) {
2676                 crtc = encoder->crtc;
2677                 /* Make sure the crtc and connector are running */
2678                 intel_crtc = to_intel_crtc(crtc);
2679                 *dpms_mode = intel_crtc->dpms_mode;
2680                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2681                         crtc_funcs = crtc->helper_private;
2682                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2683                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2684                 }
2685                 return crtc;
2686         }
2687
2688         /* Find an unused one (if possible) */
2689         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2690                 i++;
2691                 if (!(encoder->possible_crtcs & (1 << i)))
2692                         continue;
2693                 if (!possible_crtc->enabled) {
2694                         crtc = possible_crtc;
2695                         break;
2696                 }
2697                 if (!supported_crtc)
2698                         supported_crtc = possible_crtc;
2699         }
2700
2701         /*
2702          * If we didn't find an unused CRTC, don't use any.
2703          */
2704         if (!crtc) {
2705                 return NULL;
2706         }
2707
2708         encoder->crtc = crtc;
2709         intel_output->base.encoder = encoder;
2710         intel_output->load_detect_temp = true;
2711
2712         intel_crtc = to_intel_crtc(crtc);
2713         *dpms_mode = intel_crtc->dpms_mode;
2714
2715         if (!crtc->enabled) {
2716                 if (!mode)
2717                         mode = &load_detect_mode;
2718                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
2719         } else {
2720                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2721                         crtc_funcs = crtc->helper_private;
2722                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2723                 }
2724
2725                 /* Add this connector to the crtc */
2726                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
2727                 encoder_funcs->commit(encoder);
2728         }
2729         /* let the connector get through one full cycle before testing */
2730         intel_wait_for_vblank(dev);
2731
2732         return crtc;
2733 }
2734
2735 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
2736 {
2737         struct drm_encoder *encoder = &intel_output->enc;
2738         struct drm_device *dev = encoder->dev;
2739         struct drm_crtc *crtc = encoder->crtc;
2740         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2741         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2742
2743         if (intel_output->load_detect_temp) {
2744                 encoder->crtc = NULL;
2745                 intel_output->base.encoder = NULL;
2746                 intel_output->load_detect_temp = false;
2747                 crtc->enabled = drm_helper_crtc_in_use(crtc);
2748                 drm_helper_disable_unused_functions(dev);
2749         }
2750
2751         /* Switch crtc and output back off if necessary */
2752         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
2753                 if (encoder->crtc == crtc)
2754                         encoder_funcs->dpms(encoder, dpms_mode);
2755                 crtc_funcs->dpms(crtc, dpms_mode);
2756         }
2757 }
2758
2759 /* Returns the clock of the currently programmed mode of the given pipe. */
2760 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
2761 {
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2764         int pipe = intel_crtc->pipe;
2765         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
2766         u32 fp;
2767         intel_clock_t clock;
2768
2769         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2770                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
2771         else
2772                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
2773
2774         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
2775         if (IS_IGD(dev)) {
2776                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2777                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2778         } else {
2779                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2780                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2781         }
2782
2783         if (IS_I9XX(dev)) {
2784                 if (IS_IGD(dev))
2785                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2786                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
2787                 else
2788                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2789                                DPLL_FPA01_P1_POST_DIV_SHIFT);
2790
2791                 switch (dpll & DPLL_MODE_MASK) {
2792                 case DPLLB_MODE_DAC_SERIAL:
2793                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
2794                                 5 : 10;
2795                         break;
2796                 case DPLLB_MODE_LVDS:
2797                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
2798                                 7 : 14;
2799                         break;
2800                 default:
2801                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
2802                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
2803                         return 0;
2804                 }
2805
2806                 /* XXX: Handle the 100Mhz refclk */
2807                 intel_clock(dev, 96000, &clock);
2808         } else {
2809                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2810
2811                 if (is_lvds) {
2812                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2813                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
2814                         clock.p2 = 14;
2815
2816                         if ((dpll & PLL_REF_INPUT_MASK) ==
2817                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
2818                                 /* XXX: might not be 66MHz */
2819                                 intel_clock(dev, 66000, &clock);
2820                         } else
2821                                 intel_clock(dev, 48000, &clock);
2822                 } else {
2823                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
2824                                 clock.p1 = 2;
2825                         else {
2826                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2827                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
2828                         }
2829                         if (dpll & PLL_P2_DIVIDE_BY_4)
2830                                 clock.p2 = 4;
2831                         else
2832                                 clock.p2 = 2;
2833
2834                         intel_clock(dev, 48000, &clock);
2835                 }
2836         }
2837
2838         /* XXX: It would be nice to validate the clocks, but we can't reuse
2839          * i830PllIsValid() because it relies on the xf86_config connector
2840          * configuration being accurate, which it isn't necessarily.
2841          */
2842
2843         return clock.dot;
2844 }
2845
2846 /** Returns the currently programmed mode of the given pipe. */
2847 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
2848                                              struct drm_crtc *crtc)
2849 {
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2852         int pipe = intel_crtc->pipe;
2853         struct drm_display_mode *mode;
2854         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
2855         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
2856         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
2857         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
2858
2859         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
2860         if (!mode)
2861                 return NULL;
2862
2863         mode->clock = intel_crtc_clock_get(dev, crtc);
2864         mode->hdisplay = (htot & 0xffff) + 1;
2865         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
2866         mode->hsync_start = (hsync & 0xffff) + 1;
2867         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
2868         mode->vdisplay = (vtot & 0xffff) + 1;
2869         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
2870         mode->vsync_start = (vsync & 0xffff) + 1;
2871         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
2872
2873         drm_mode_set_name(mode);
2874         drm_mode_set_crtcinfo(mode, 0);
2875
2876         return mode;
2877 }
2878
2879 static void intel_crtc_destroy(struct drm_crtc *crtc)
2880 {
2881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2882
2883         if (intel_crtc->mode_set.mode)
2884                 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
2885         drm_crtc_cleanup(crtc);
2886         kfree(intel_crtc);
2887 }
2888
2889 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
2890         .dpms = intel_crtc_dpms,
2891         .mode_fixup = intel_crtc_mode_fixup,
2892         .mode_set = intel_crtc_mode_set,
2893         .mode_set_base = intel_pipe_set_base,
2894         .prepare = intel_crtc_prepare,
2895         .commit = intel_crtc_commit,
2896 };
2897
2898 static const struct drm_crtc_funcs intel_crtc_funcs = {
2899         .cursor_set = intel_crtc_cursor_set,
2900         .cursor_move = intel_crtc_cursor_move,
2901         .gamma_set = intel_crtc_gamma_set,
2902         .set_config = drm_crtc_helper_set_config,
2903         .destroy = intel_crtc_destroy,
2904 };
2905
2906
2907 static void intel_crtc_init(struct drm_device *dev, int pipe)
2908 {
2909         struct intel_crtc *intel_crtc;
2910         int i;
2911
2912         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2913         if (intel_crtc == NULL)
2914                 return;
2915
2916         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2917
2918         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
2919         intel_crtc->pipe = pipe;
2920         intel_crtc->plane = pipe;
2921         for (i = 0; i < 256; i++) {
2922                 intel_crtc->lut_r[i] = i;
2923                 intel_crtc->lut_g[i] = i;
2924                 intel_crtc->lut_b[i] = i;
2925         }
2926
2927         intel_crtc->cursor_addr = 0;
2928         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
2929         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2930
2931         intel_crtc->mode_set.crtc = &intel_crtc->base;
2932         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
2933         intel_crtc->mode_set.num_connectors = 0;
2934
2935         if (i915_fbpercrtc) {
2936
2937
2938
2939         }
2940 }
2941
2942 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
2943                                 struct drm_file *file_priv)
2944 {
2945         drm_i915_private_t *dev_priv = dev->dev_private;
2946         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
2947         struct drm_crtc *crtc = NULL;
2948         int pipe = -1;
2949
2950         if (!dev_priv) {
2951                 DRM_ERROR("called with no initialization\n");
2952                 return -EINVAL;
2953         }
2954
2955         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2956                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2957                 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
2958                         pipe = intel_crtc->pipe;
2959                         break;
2960                 }
2961         }
2962
2963         if (pipe == -1) {
2964                 DRM_ERROR("no such CRTC id\n");
2965                 return -EINVAL;
2966         }
2967
2968         pipe_from_crtc_id->pipe = pipe;
2969
2970        return 0;
2971 }
2972
2973 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
2974 {
2975         struct drm_crtc *crtc = NULL;
2976
2977         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2978                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2979                 if (intel_crtc->pipe == pipe)
2980                         break;
2981         }
2982         return crtc;
2983 }
2984
2985 static int intel_connector_clones(struct drm_device *dev, int type_mask)
2986 {
2987         int index_mask = 0;
2988         struct drm_connector *connector;
2989         int entry = 0;
2990
2991         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2992                 struct intel_output *intel_output = to_intel_output(connector);
2993                 if (type_mask & (1 << intel_output->type))
2994                         index_mask |= (1 << entry);
2995                 entry++;
2996         }
2997         return index_mask;
2998 }
2999
3000
3001 static void intel_setup_outputs(struct drm_device *dev)
3002 {
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         struct drm_connector *connector;
3005
3006         intel_crt_init(dev);
3007
3008         /* Set up integrated LVDS */
3009         if (IS_MOBILE(dev) && !IS_I830(dev))
3010                 intel_lvds_init(dev);
3011
3012         if (IS_IGDNG(dev)) {
3013                 int found;
3014
3015                 if (I915_READ(HDMIB) & PORT_DETECTED) {
3016                         /* check SDVOB */
3017                         /* found = intel_sdvo_init(dev, HDMIB); */
3018                         found = 0;
3019                         if (!found)
3020                                 intel_hdmi_init(dev, HDMIB);
3021                 }
3022
3023                 if (I915_READ(HDMIC) & PORT_DETECTED)
3024                         intel_hdmi_init(dev, HDMIC);
3025
3026                 if (I915_READ(HDMID) & PORT_DETECTED)
3027                         intel_hdmi_init(dev, HDMID);
3028
3029         } else if (IS_I9XX(dev)) {
3030                 int found;
3031                 u32 reg;
3032
3033                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3034                         found = intel_sdvo_init(dev, SDVOB);
3035                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3036                                 intel_hdmi_init(dev, SDVOB);
3037                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
3038                                 intel_dp_init(dev, DP_B);
3039                 }
3040
3041                 /* Before G4X SDVOC doesn't have its own detect register */
3042                 if (IS_G4X(dev))
3043                         reg = SDVOC;
3044                 else
3045                         reg = SDVOB;
3046
3047                 if (I915_READ(reg) & SDVO_DETECTED) {
3048                         found = intel_sdvo_init(dev, SDVOC);
3049                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3050                                 intel_hdmi_init(dev, SDVOC);
3051                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
3052                                 intel_dp_init(dev, DP_C);
3053                 }
3054                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3055                         intel_dp_init(dev, DP_D);
3056         } else
3057                 intel_dvo_init(dev);
3058
3059         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3060                 intel_tv_init(dev);
3061
3062         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3063                 struct intel_output *intel_output = to_intel_output(connector);
3064                 struct drm_encoder *encoder = &intel_output->enc;
3065                 int crtc_mask = 0, clone_mask = 0;
3066
3067                 /* valid crtcs */
3068                 switch(intel_output->type) {
3069                 case INTEL_OUTPUT_HDMI:
3070                         crtc_mask = ((1 << 0)|
3071                                      (1 << 1));
3072                         clone_mask = ((1 << INTEL_OUTPUT_HDMI));
3073                         break;
3074                 case INTEL_OUTPUT_DVO:
3075                 case INTEL_OUTPUT_SDVO:
3076                         crtc_mask = ((1 << 0)|
3077                                      (1 << 1));
3078                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3079                                       (1 << INTEL_OUTPUT_DVO) |
3080                                       (1 << INTEL_OUTPUT_SDVO));
3081                         break;
3082                 case INTEL_OUTPUT_ANALOG:
3083                         crtc_mask = ((1 << 0)|
3084                                      (1 << 1));
3085                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3086                                       (1 << INTEL_OUTPUT_DVO) |
3087                                       (1 << INTEL_OUTPUT_SDVO));
3088                         break;
3089                 case INTEL_OUTPUT_LVDS:
3090                         crtc_mask = (1 << 1);
3091                         clone_mask = (1 << INTEL_OUTPUT_LVDS);
3092                         break;
3093                 case INTEL_OUTPUT_TVOUT:
3094                         crtc_mask = ((1 << 0) |
3095                                      (1 << 1));
3096                         clone_mask = (1 << INTEL_OUTPUT_TVOUT);
3097                         break;
3098                 case INTEL_OUTPUT_DISPLAYPORT:
3099                         crtc_mask = ((1 << 0) |
3100                                      (1 << 1));
3101                         clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
3102                         break;
3103                 }
3104                 encoder->possible_crtcs = crtc_mask;
3105                 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
3106         }
3107 }
3108
3109 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3110 {
3111         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3112         struct drm_device *dev = fb->dev;
3113
3114         if (fb->fbdev)
3115                 intelfb_remove(dev, fb);
3116
3117         drm_framebuffer_cleanup(fb);
3118         mutex_lock(&dev->struct_mutex);
3119         drm_gem_object_unreference(intel_fb->obj);
3120         mutex_unlock(&dev->struct_mutex);
3121
3122         kfree(intel_fb);
3123 }
3124
3125 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3126                                                 struct drm_file *file_priv,
3127                                                 unsigned int *handle)
3128 {
3129         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3130         struct drm_gem_object *object = intel_fb->obj;
3131
3132         return drm_gem_handle_create(file_priv, object, handle);
3133 }
3134
3135 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3136         .destroy = intel_user_framebuffer_destroy,
3137         .create_handle = intel_user_framebuffer_create_handle,
3138 };
3139
3140 int intel_framebuffer_create(struct drm_device *dev,
3141                              struct drm_mode_fb_cmd *mode_cmd,
3142                              struct drm_framebuffer **fb,
3143                              struct drm_gem_object *obj)
3144 {
3145         struct intel_framebuffer *intel_fb;
3146         int ret;
3147
3148         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3149         if (!intel_fb)
3150                 return -ENOMEM;
3151
3152         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3153         if (ret) {
3154                 DRM_ERROR("framebuffer init failed %d\n", ret);
3155                 return ret;
3156         }
3157
3158         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3159
3160         intel_fb->obj = obj;
3161
3162         *fb = &intel_fb->base;
3163
3164         return 0;
3165 }
3166
3167
3168 static struct drm_framebuffer *
3169 intel_user_framebuffer_create(struct drm_device *dev,
3170                               struct drm_file *filp,
3171                               struct drm_mode_fb_cmd *mode_cmd)
3172 {
3173         struct drm_gem_object *obj;
3174         struct drm_framebuffer *fb;
3175         int ret;
3176
3177         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3178         if (!obj)
3179                 return NULL;
3180
3181         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3182         if (ret) {
3183                 mutex_lock(&dev->struct_mutex);
3184                 drm_gem_object_unreference(obj);
3185                 mutex_unlock(&dev->struct_mutex);
3186                 return NULL;
3187         }
3188
3189         return fb;
3190 }
3191
3192 static const struct drm_mode_config_funcs intel_mode_funcs = {
3193         .fb_create = intel_user_framebuffer_create,
3194         .fb_changed = intelfb_probe,
3195 };
3196
3197 void intel_modeset_init(struct drm_device *dev)
3198 {
3199         int num_pipe;
3200         int i;
3201
3202         drm_mode_config_init(dev);
3203
3204         dev->mode_config.min_width = 0;
3205         dev->mode_config.min_height = 0;
3206
3207         dev->mode_config.funcs = (void *)&intel_mode_funcs;
3208
3209         if (IS_I965G(dev)) {
3210                 dev->mode_config.max_width = 8192;
3211                 dev->mode_config.max_height = 8192;
3212         } else if (IS_I9XX(dev)) {
3213                 dev->mode_config.max_width = 4096;
3214                 dev->mode_config.max_height = 4096;
3215         } else {
3216                 dev->mode_config.max_width = 2048;
3217                 dev->mode_config.max_height = 2048;
3218         }
3219
3220         /* set memory base */
3221         if (IS_I9XX(dev))
3222                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
3223         else
3224                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
3225
3226         if (IS_MOBILE(dev) || IS_I9XX(dev))
3227                 num_pipe = 2;
3228         else
3229                 num_pipe = 1;
3230         DRM_DEBUG("%d display pipe%s available.\n",
3231                   num_pipe, num_pipe > 1 ? "s" : "");
3232
3233         for (i = 0; i < num_pipe; i++) {
3234                 intel_crtc_init(dev, i);
3235         }
3236
3237         intel_setup_outputs(dev);
3238 }
3239
3240 void intel_modeset_cleanup(struct drm_device *dev)
3241 {
3242         drm_mode_config_cleanup(dev);
3243 }
3244
3245
3246 /* current intel driver doesn't take advantage of encoders
3247    always give back the encoder for the connector
3248 */
3249 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
3250 {
3251         struct intel_output *intel_output = to_intel_output(connector);
3252
3253         return &intel_output->enc;
3254 }