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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 710                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711                      clock.m1++) {
 712                         for (clock.m2 = limit->m2.min;
 713                              clock.m2 <= limit->m2.max; clock.m2++) {
 714                                 /* m1 is always 0 in IGD */
 715                                 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 716                                         break;
 717                                 for (clock.n = limit->n.min;
 718                                      clock.n <= limit->n.max; clock.n++) {
 719                                         int this_err;
 720
 721                                         intel_clock(dev, refclk, &clock);
 722
 723                                         if (!intel_PLL_is_valid(crtc, &clock))
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739
 740 static bool
 741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                             int target, int refclk, intel_clock_t *best_clock)
 743
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         intel_clock_t clock;
 747         int err = target;
 748         bool found = false;
 749
 750         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 751
 752         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 753                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 754                         /* m1 is always 0 in IGD */
 755                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 756                                 break;
 757                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 758                              clock.n++) {
 759                                 int this_err;
 760
 761                                 intel_clock(dev, refclk, &clock);
 762
 763                                 if (!intel_PLL_is_valid(crtc, &clock))
 764                                         continue;
 765
 766                                 this_err = abs(clock.dot - target);
 767                                 if (this_err < err) {
 768                                         *best_clock = clock;
 769                                         err = this_err;
 770                                         found = true;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return found;
 777 }
 778
 779 static bool
 780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 781                         int target, int refclk, intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found;
 788         /* approximately equals target * 0.00488 */
 789         int err_most = (target >> 8) + (target >> 10);
 790         found = false;
 791
 792         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 793                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 794                     LVDS_CLKB_POWER_UP)
 795                         clock.p2 = limit->p2.p2_fast;
 796                 else
 797                         clock.p2 = limit->p2.p2_slow;
 798         } else {
 799                 if (target < limit->p2.dot_limit)
 800                         clock.p2 = limit->p2.p2_slow;
 801                 else
 802                         clock.p2 = limit->p2.p2_fast;
 803         }
 804
 805         memset(best_clock, 0, sizeof(*best_clock));
 806         max_n = limit->n.max;
 807         /* based on hardware requriment prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirment prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         intel_clock(dev, refclk, &clock);
 819                                         if (!intel_PLL_is_valid(crtc, &clock))
 820                                                 continue;
 821                                         this_err = abs(clock.dot - target) ;
 822                                         if (this_err < err_most) {
 823                                                 *best_clock = clock;
 824                                                 err_most = this_err;
 825                                                 max_n = clock.n;
 826                                                 found = true;
 827                                         }
 828                                 }
 829                         }
 830                 }
 831         }
 832         return found;
 833 }
 834
 835 static bool
 836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *best_clock)
 838 {
 839         struct drm_device *dev = crtc->dev;
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.n = 1;
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.m1 = 12;
 846                 clock.m2 = 9;
 847         } else {
 848                 clock.n = 2;
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.m1 = 14;
 852                 clock.m2 = 8;
 853         }
 854         intel_clock(dev, refclk, &clock);
 855         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 856         return true;
 857 }
 858
 859 static bool
 860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found;
 868         int err_most = 47;
 869         found = false;
 870
 871         /* eDP has only 2 clock choice, no n/m/p setting */
 872         if (HAS_eDP)
 873                 return true;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 876                 return intel_find_pll_igdng_dp(limit, crtc, target,
 877                                                refclk, best_clock);
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 895                 /* based on hardware requriment prefer smaller n to precision */
 896                 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                         /* based on hardware requirment prefere larger m1,m2 */
 898                         for (clock.m1 = limit->m1.max;
 899                              clock.m1 >= limit->m1.min; clock.m1--) {
 900                                 for (clock.m2 = limit->m2.max;
 901                                      clock.m2 >= limit->m2.min; clock.m2--) {
 902                                         int this_err;
 903
 904                                         intel_clock(dev, refclk, &clock);
 905                                         if (!intel_PLL_is_valid(crtc, &clock))
 906                                                 continue;
 907                                         this_err = abs((10000 - (target*10000/clock.dot)));
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                                 /* found on first matching */
 914                                                 goto out;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920 out:
 921         return found;
 922 }
 923
 924 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 925 static bool
 926 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 927                       int target, int refclk, intel_clock_t *best_clock)
 928 {
 929     intel_clock_t clock;
 930     if (target < 200000) {
 931         clock.p1 = 2;
 932         clock.p2 = 10;
 933         clock.n = 2;
 934         clock.m1 = 23;
 935         clock.m2 = 8;
 936     } else {
 937         clock.p1 = 1;
 938         clock.p2 = 10;
 939         clock.n = 1;
 940         clock.m1 = 14;
 941         clock.m2 = 2;
 942     }
 943     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 944     clock.p = (clock.p1 * clock.p2);
 945     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 946     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 947     return true;
 948 }
 949
 950 void
 951 intel_wait_for_vblank(struct drm_device *dev)
 952 {
 953         /* Wait for 20ms, i.e. one cycle at 50hz. */
 954         mdelay(20);
 955 }
 956
 957 /* Parameters have changed, update FBC info */
 958 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 959 {
 960         struct drm_device *dev = crtc->dev;
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         struct drm_framebuffer *fb = crtc->fb;
 963         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 964         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 966         int plane, i;
 967         u32 fbc_ctl, fbc_ctl2;
 968
 969         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 970
 971         if (fb->pitch < dev_priv->cfb_pitch)
 972                 dev_priv->cfb_pitch = fb->pitch;
 973
 974         /* FBC_CTL wants 64B units */
 975         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 976         dev_priv->cfb_fence = obj_priv->fence_reg;
 977         dev_priv->cfb_plane = intel_crtc->plane;
 978         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 979
 980         /* Clear old tags */
 981         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 982                 I915_WRITE(FBC_TAG + (i * 4), 0);
 983
 984         /* Set it up... */
 985         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 986         if (obj_priv->tiling_mode != I915_TILING_NONE)
 987                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 988         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 989         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 990
 991         /* enable it... */
 992         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 993         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 994         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 995         if (obj_priv->tiling_mode != I915_TILING_NONE)
 996                 fbc_ctl |= dev_priv->cfb_fence;
 997         I915_WRITE(FBC_CONTROL, fbc_ctl);
 998
 999         DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1000                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1001 }
1002
1003 void i8xx_disable_fbc(struct drm_device *dev)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         u32 fbc_ctl;
1007
1008         if (!I915_HAS_FBC(dev))
1009                 return;
1010
1011         /* Disable compression */
1012         fbc_ctl = I915_READ(FBC_CONTROL);
1013         fbc_ctl &= ~FBC_CTL_EN;
1014         I915_WRITE(FBC_CONTROL, fbc_ctl);
1015
1016         /* Wait for compressing bit to clear */
1017         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1018                 ; /* nothing */
1019
1020         intel_wait_for_vblank(dev);
1021
1022         DRM_DEBUG("disabled FBC\n");
1023 }
1024
1025 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1026 {
1027         struct drm_device *dev = crtc->dev;
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029
1030         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1031 }
1032
1033 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1034 {
1035         struct drm_device *dev = crtc->dev;
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037         struct drm_framebuffer *fb = crtc->fb;
1038         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1039         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1041         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1042                      DPFC_CTL_PLANEB);
1043         unsigned long stall_watermark = 200;
1044         u32 dpfc_ctl;
1045
1046         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1047         dev_priv->cfb_fence = obj_priv->fence_reg;
1048         dev_priv->cfb_plane = intel_crtc->plane;
1049
1050         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1051         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1052                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1053                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1054         } else {
1055                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1056         }
1057
1058         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1059         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1060                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1061                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1062         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1063
1064         /* enable it... */
1065         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1066
1067         DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
1068 }
1069
1070 void g4x_disable_fbc(struct drm_device *dev)
1071 {
1072         struct drm_i915_private *dev_priv = dev->dev_private;
1073         u32 dpfc_ctl;
1074
1075         /* Disable compression */
1076         dpfc_ctl = I915_READ(DPFC_CONTROL);
1077         dpfc_ctl &= ~DPFC_CTL_EN;
1078         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1079         intel_wait_for_vblank(dev);
1080
1081         DRM_DEBUG("disabled FBC\n");
1082 }
1083
1084 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1085 {
1086         struct drm_device *dev = crtc->dev;
1087         struct drm_i915_private *dev_priv = dev->dev_private;
1088
1089         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1090 }
1091
1092 /**
1093  * intel_update_fbc - enable/disable FBC as needed
1094  * @crtc: CRTC to point the compressor at
1095  * @mode: mode in use
1096  *
1097  * Set up the framebuffer compression hardware at mode set time.  We
1098  * enable it if possible:
1099  *   - plane A only (on pre-965)
1100  *   - no pixel mulitply/line duplication
1101  *   - no alpha buffer discard
1102  *   - no dual wide
1103  *   - framebuffer <= 2048 in width, 1536 in height
1104  *
1105  * We can't assume that any compression will take place (worst case),
1106  * so the compressed buffer has to be the same size as the uncompressed
1107  * one.  It also must reside (along with the line length buffer) in
1108  * stolen memory.
1109  *
1110  * We need to enable/disable FBC on a global basis.
1111  */
1112 static void intel_update_fbc(struct drm_crtc *crtc,
1113                              struct drm_display_mode *mode)
1114 {
1115         struct drm_device *dev = crtc->dev;
1116         struct drm_i915_private *dev_priv = dev->dev_private;
1117         struct drm_framebuffer *fb = crtc->fb;
1118         struct intel_framebuffer *intel_fb;
1119         struct drm_i915_gem_object *obj_priv;
1120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1121         int plane = intel_crtc->plane;
1122
1123         if (!i915_powersave)
1124                 return;
1125
1126         if (!dev_priv->display.fbc_enabled ||
1127             !dev_priv->display.enable_fbc ||
1128             !dev_priv->display.disable_fbc)
1129                 return;
1130
1131         if (!crtc->fb)
1132                 return;
1133
1134         intel_fb = to_intel_framebuffer(fb);
1135         obj_priv = intel_fb->obj->driver_private;
1136
1137         /*
1138          * If FBC is already on, we just have to verify that we can
1139          * keep it that way...
1140          * Need to disable if:
1141          *   - changing FBC params (stride, fence, mode)
1142          *   - new fb is too large to fit in compressed buffer
1143          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1144          */
1145         if (intel_fb->obj->size > dev_priv->cfb_size) {
1146                 DRM_DEBUG("framebuffer too large, disabling compression\n");
1147                 goto out_disable;
1148         }
1149         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151                 DRM_DEBUG("mode incompatible with compression, disabling\n");
1152                 goto out_disable;
1153         }
1154         if ((mode->hdisplay > 2048) ||
1155             (mode->vdisplay > 1536)) {
1156                 DRM_DEBUG("mode too large for compression, disabling\n");
1157                 goto out_disable;
1158         }
1159         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1160                 DRM_DEBUG("plane not 0, disabling compression\n");
1161                 goto out_disable;
1162         }
1163         if (obj_priv->tiling_mode != I915_TILING_X) {
1164                 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1165                 goto out_disable;
1166         }
1167
1168         if (dev_priv->display.fbc_enabled(crtc)) {
1169                 /* We can re-enable it in this case, but need to update pitch */
1170                 if (fb->pitch > dev_priv->cfb_pitch)
1171                         dev_priv->display.disable_fbc(dev);
1172                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1173                         dev_priv->display.disable_fbc(dev);
1174                 if (plane != dev_priv->cfb_plane)
1175                         dev_priv->display.disable_fbc(dev);
1176         }
1177
1178         if (!dev_priv->display.fbc_enabled(crtc)) {
1179                 /* Now try to turn it back on if possible */
1180                 dev_priv->display.enable_fbc(crtc, 500);
1181         }
1182
1183         return;
1184
1185 out_disable:
1186         DRM_DEBUG("unsupported config, disabling FBC\n");
1187         /* Multiple disables should be harmless */
1188         if (dev_priv->display.fbc_enabled(crtc))
1189                 dev_priv->display.disable_fbc(dev);
1190 }
1191
1192 static int
1193 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1194                     struct drm_framebuffer *old_fb)
1195 {
1196         struct drm_device *dev = crtc->dev;
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         struct drm_i915_master_private *master_priv;
1199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1200         struct intel_framebuffer *intel_fb;
1201         struct drm_i915_gem_object *obj_priv;
1202         struct drm_gem_object *obj;
1203         int pipe = intel_crtc->pipe;
1204         int plane = intel_crtc->plane;
1205         unsigned long Start, Offset;
1206         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1207         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1208         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1209         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1210         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1211         u32 dspcntr, alignment;
1212         int ret;
1213
1214         /* no fb bound */
1215         if (!crtc->fb) {
1216                 DRM_DEBUG("No FB bound\n");
1217                 return 0;
1218         }
1219
1220         switch (plane) {
1221         case 0:
1222         case 1:
1223                 break;
1224         default:
1225                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1226                 return -EINVAL;
1227         }
1228
1229         intel_fb = to_intel_framebuffer(crtc->fb);
1230         obj = intel_fb->obj;
1231         obj_priv = obj->driver_private;
1232
1233         switch (obj_priv->tiling_mode) {
1234         case I915_TILING_NONE:
1235                 alignment = 64 * 1024;
1236                 break;
1237         case I915_TILING_X:
1238                 /* pin() will align the object as required by fence */
1239                 alignment = 0;
1240                 break;
1241         case I915_TILING_Y:
1242                 /* FIXME: Is this true? */
1243                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1244                 return -EINVAL;
1245         default:
1246                 BUG();
1247         }
1248
1249         mutex_lock(&dev->struct_mutex);
1250         ret = i915_gem_object_pin(obj, alignment);
1251         if (ret != 0) {
1252                 mutex_unlock(&dev->struct_mutex);
1253                 return ret;
1254         }
1255
1256         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1257         if (ret != 0) {
1258                 i915_gem_object_unpin(obj);
1259                 mutex_unlock(&dev->struct_mutex);
1260                 return ret;
1261         }
1262
1263         /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1264          * whereas 965+ only requires a fence if using framebuffer compression.
1265          * For simplicity, we always install a fence as the cost is not that onerous.
1266          */
1267         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1268             obj_priv->tiling_mode != I915_TILING_NONE) {
1269                 ret = i915_gem_object_get_fence_reg(obj);
1270                 if (ret != 0) {
1271                         i915_gem_object_unpin(obj);
1272                         mutex_unlock(&dev->struct_mutex);
1273                         return ret;
1274                 }
1275         }
1276
1277         dspcntr = I915_READ(dspcntr_reg);
1278         /* Mask out pixel format bits in case we change it */
1279         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1280         switch (crtc->fb->bits_per_pixel) {
1281         case 8:
1282                 dspcntr |= DISPPLANE_8BPP;
1283                 break;
1284         case 16:
1285                 if (crtc->fb->depth == 15)
1286                         dspcntr |= DISPPLANE_15_16BPP;
1287                 else
1288                         dspcntr |= DISPPLANE_16BPP;
1289                 break;
1290         case 24:
1291         case 32:
1292                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1293                 break;
1294         default:
1295                 DRM_ERROR("Unknown color depth\n");
1296                 i915_gem_object_unpin(obj);
1297                 mutex_unlock(&dev->struct_mutex);
1298                 return -EINVAL;
1299         }
1300         if (IS_I965G(dev)) {
1301                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1302                         dspcntr |= DISPPLANE_TILED;
1303                 else
1304                         dspcntr &= ~DISPPLANE_TILED;
1305         }
1306
1307         if (IS_IGDNG(dev))
1308                 /* must disable */
1309                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1310
1311         I915_WRITE(dspcntr_reg, dspcntr);
1312
1313         Start = obj_priv->gtt_offset;
1314         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1315
1316         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1317         I915_WRITE(dspstride, crtc->fb->pitch);
1318         if (IS_I965G(dev)) {
1319                 I915_WRITE(dspbase, Offset);
1320                 I915_READ(dspbase);
1321                 I915_WRITE(dspsurf, Start);
1322                 I915_READ(dspsurf);
1323                 I915_WRITE(dsptileoff, (y << 16) | x);
1324         } else {
1325                 I915_WRITE(dspbase, Start + Offset);
1326                 I915_READ(dspbase);
1327         }
1328
1329         if ((IS_I965G(dev) || plane == 0))
1330                 intel_update_fbc(crtc, &crtc->mode);
1331
1332         intel_wait_for_vblank(dev);
1333
1334         if (old_fb) {
1335                 intel_fb = to_intel_framebuffer(old_fb);
1336                 obj_priv = intel_fb->obj->driver_private;
1337                 i915_gem_object_unpin(intel_fb->obj);
1338         }
1339         intel_increase_pllclock(crtc, true);
1340
1341         mutex_unlock(&dev->struct_mutex);
1342
1343         if (!dev->primary->master)
1344                 return 0;
1345
1346         master_priv = dev->primary->master->driver_priv;
1347         if (!master_priv->sarea_priv)
1348                 return 0;
1349
1350         if (pipe) {
1351                 master_priv->sarea_priv->pipeB_x = x;
1352                 master_priv->sarea_priv->pipeB_y = y;
1353         } else {
1354                 master_priv->sarea_priv->pipeA_x = x;
1355                 master_priv->sarea_priv->pipeA_y = y;
1356         }
1357
1358         return 0;
1359 }
1360
1361 /* Disable the VGA plane that we never use */
1362 static void i915_disable_vga (struct drm_device *dev)
1363 {
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         u8 sr1;
1366         u32 vga_reg;
1367
1368         if (IS_IGDNG(dev))
1369                 vga_reg = CPU_VGACNTRL;
1370         else
1371                 vga_reg = VGACNTRL;
1372
1373         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1374                 return;
1375
1376         I915_WRITE8(VGA_SR_INDEX, 1);
1377         sr1 = I915_READ8(VGA_SR_DATA);
1378         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1379         udelay(100);
1380
1381         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1382 }
1383
1384 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1385 {
1386         struct drm_device *dev = crtc->dev;
1387         struct drm_i915_private *dev_priv = dev->dev_private;
1388         u32 dpa_ctl;
1389
1390         DRM_DEBUG("\n");
1391         dpa_ctl = I915_READ(DP_A);
1392         dpa_ctl &= ~DP_PLL_ENABLE;
1393         I915_WRITE(DP_A, dpa_ctl);
1394 }
1395
1396 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1397 {
1398         struct drm_device *dev = crtc->dev;
1399         struct drm_i915_private *dev_priv = dev->dev_private;
1400         u32 dpa_ctl;
1401
1402         dpa_ctl = I915_READ(DP_A);
1403         dpa_ctl |= DP_PLL_ENABLE;
1404         I915_WRITE(DP_A, dpa_ctl);
1405         udelay(200);
1406 }
1407
1408
1409 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1410 {
1411         struct drm_device *dev = crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         u32 dpa_ctl;
1414
1415         DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1416         dpa_ctl = I915_READ(DP_A);
1417         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1418
1419         if (clock < 200000) {
1420                 u32 temp;
1421                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1422                 /* workaround for 160Mhz:
1423                    1) program 0x4600c bits 15:0 = 0x8124
1424                    2) program 0x46010 bit 0 = 1
1425                    3) program 0x46034 bit 24 = 1
1426                    4) program 0x64000 bit 14 = 1
1427                    */
1428                 temp = I915_READ(0x4600c);
1429                 temp &= 0xffff0000;
1430                 I915_WRITE(0x4600c, temp | 0x8124);
1431
1432                 temp = I915_READ(0x46010);
1433                 I915_WRITE(0x46010, temp | 1);
1434
1435                 temp = I915_READ(0x46034);
1436                 I915_WRITE(0x46034, temp | (1 << 24));
1437         } else {
1438                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1439         }
1440         I915_WRITE(DP_A, dpa_ctl);
1441
1442         udelay(500);
1443 }
1444
1445 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1446 {
1447         struct drm_device *dev = crtc->dev;
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450         int pipe = intel_crtc->pipe;
1451         int plane = intel_crtc->plane;
1452         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1453         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1454         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1455         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1456         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1457         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1458         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1459         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1460         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1461         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1462         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1463         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1464         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1465         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1466         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1467         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1468         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1469         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1470         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1471         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1472         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1473         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1474         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1475         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1476         u32 temp;
1477         int tries = 5, j, n;
1478
1479         /* XXX: When our outputs are all unaware of DPMS modes other than off
1480          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1481          */
1482         switch (mode) {
1483         case DRM_MODE_DPMS_ON:
1484         case DRM_MODE_DPMS_STANDBY:
1485         case DRM_MODE_DPMS_SUSPEND:
1486                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1487                 if (HAS_eDP) {
1488                         /* enable eDP PLL */
1489                         igdng_enable_pll_edp(crtc);
1490                 } else {
1491                         /* enable PCH DPLL */
1492                         temp = I915_READ(pch_dpll_reg);
1493                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1494                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1495                                 I915_READ(pch_dpll_reg);
1496                         }
1497
1498                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1499                         temp = I915_READ(fdi_rx_reg);
1500                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1501                                         FDI_SEL_PCDCLK |
1502                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1503                         I915_READ(fdi_rx_reg);
1504                         udelay(200);
1505
1506                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1507                         temp = I915_READ(fdi_tx_reg);
1508                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1509                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1510                                 I915_READ(fdi_tx_reg);
1511                                 udelay(100);
1512                         }
1513                 }
1514
1515                 /* Enable panel fitting for LVDS */
1516                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1517                         temp = I915_READ(pf_ctl_reg);
1518                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1519
1520                         /* currently full aspect */
1521                         I915_WRITE(pf_win_pos, 0);
1522
1523                         I915_WRITE(pf_win_size,
1524                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1525                                    (dev_priv->panel_fixed_mode->vdisplay));
1526                 }
1527
1528                 /* Enable CPU pipe */
1529                 temp = I915_READ(pipeconf_reg);
1530                 if ((temp & PIPEACONF_ENABLE) == 0) {
1531                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1532                         I915_READ(pipeconf_reg);
1533                         udelay(100);
1534                 }
1535
1536                 /* configure and enable CPU plane */
1537                 temp = I915_READ(dspcntr_reg);
1538                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1539                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1540                         /* Flush the plane changes */
1541                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1542                 }
1543
1544                 if (!HAS_eDP) {
1545                         /* enable CPU FDI TX and PCH FDI RX */
1546                         temp = I915_READ(fdi_tx_reg);
1547                         temp |= FDI_TX_ENABLE;
1548                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1549                         temp &= ~FDI_LINK_TRAIN_NONE;
1550                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1551                         I915_WRITE(fdi_tx_reg, temp);
1552                         I915_READ(fdi_tx_reg);
1553
1554                         temp = I915_READ(fdi_rx_reg);
1555                         temp &= ~FDI_LINK_TRAIN_NONE;
1556                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1557                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1558                         I915_READ(fdi_rx_reg);
1559
1560                         udelay(150);
1561
1562                         /* Train FDI. */
1563                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1564                            for train result */
1565                         temp = I915_READ(fdi_rx_imr_reg);
1566                         temp &= ~FDI_RX_SYMBOL_LOCK;
1567                         temp &= ~FDI_RX_BIT_LOCK;
1568                         I915_WRITE(fdi_rx_imr_reg, temp);
1569                         I915_READ(fdi_rx_imr_reg);
1570                         udelay(150);
1571
1572                         temp = I915_READ(fdi_rx_iir_reg);
1573                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1574
1575                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1576                                 for (j = 0; j < tries; j++) {
1577                                         temp = I915_READ(fdi_rx_iir_reg);
1578                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1579                                         if (temp & FDI_RX_BIT_LOCK)
1580                                                 break;
1581                                         udelay(200);
1582                                 }
1583                                 if (j != tries)
1584                                         I915_WRITE(fdi_rx_iir_reg,
1585                                                         temp | FDI_RX_BIT_LOCK);
1586                                 else
1587                                         DRM_DEBUG("train 1 fail\n");
1588                         } else {
1589                                 I915_WRITE(fdi_rx_iir_reg,
1590                                                 temp | FDI_RX_BIT_LOCK);
1591                                 DRM_DEBUG("train 1 ok 2!\n");
1592                         }
1593                         temp = I915_READ(fdi_tx_reg);
1594                         temp &= ~FDI_LINK_TRAIN_NONE;
1595                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1596                         I915_WRITE(fdi_tx_reg, temp);
1597
1598                         temp = I915_READ(fdi_rx_reg);
1599                         temp &= ~FDI_LINK_TRAIN_NONE;
1600                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1601                         I915_WRITE(fdi_rx_reg, temp);
1602
1603                         udelay(150);
1604
1605                         temp = I915_READ(fdi_rx_iir_reg);
1606                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1607
1608                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1609                                 for (j = 0; j < tries; j++) {
1610                                         temp = I915_READ(fdi_rx_iir_reg);
1611                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1612                                         if (temp & FDI_RX_SYMBOL_LOCK)
1613                                                 break;
1614                                         udelay(200);
1615                                 }
1616                                 if (j != tries) {
1617                                         I915_WRITE(fdi_rx_iir_reg,
1618                                                         temp | FDI_RX_SYMBOL_LOCK);
1619                                         DRM_DEBUG("train 2 ok 1!\n");
1620                                 } else
1621                                         DRM_DEBUG("train 2 fail\n");
1622                         } else {
1623                                 I915_WRITE(fdi_rx_iir_reg,
1624                                                 temp | FDI_RX_SYMBOL_LOCK);
1625                                 DRM_DEBUG("train 2 ok 2!\n");
1626                         }
1627                         DRM_DEBUG("train done\n");
1628
1629                         /* set transcoder timing */
1630                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1631                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1632                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1633
1634                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1635                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1636                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1637
1638                         /* enable PCH transcoder */
1639                         temp = I915_READ(transconf_reg);
1640                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1641                         I915_READ(transconf_reg);
1642
1643                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1644                                 ;
1645
1646                         /* enable normal */
1647
1648                         temp = I915_READ(fdi_tx_reg);
1649                         temp &= ~FDI_LINK_TRAIN_NONE;
1650                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1651                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1652                         I915_READ(fdi_tx_reg);
1653
1654                         temp = I915_READ(fdi_rx_reg);
1655                         temp &= ~FDI_LINK_TRAIN_NONE;
1656                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1657                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1658                         I915_READ(fdi_rx_reg);
1659
1660                         /* wait one idle pattern time */
1661                         udelay(100);
1662
1663                 }
1664
1665                 intel_crtc_load_lut(crtc);
1666
1667         break;
1668         case DRM_MODE_DPMS_OFF:
1669                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1670
1671                 i915_disable_vga(dev);
1672
1673                 /* Disable display plane */
1674                 temp = I915_READ(dspcntr_reg);
1675                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1676                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1677                         /* Flush the plane changes */
1678                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1679                         I915_READ(dspbase_reg);
1680                 }
1681
1682                 /* disable cpu pipe, disable after all planes disabled */
1683                 temp = I915_READ(pipeconf_reg);
1684                 if ((temp & PIPEACONF_ENABLE) != 0) {
1685                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1686                         I915_READ(pipeconf_reg);
1687                         n = 0;
1688                         /* wait for cpu pipe off, pipe state */
1689                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1690                                 n++;
1691                                 if (n < 60) {
1692                                         udelay(500);
1693                                         continue;
1694                                 } else {
1695                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1696                                         break;
1697                                 }
1698                         }
1699                 } else
1700                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1701
1702                 if (HAS_eDP) {
1703                         igdng_disable_pll_edp(crtc);
1704                 }
1705
1706                 /* disable CPU FDI tx and PCH FDI rx */
1707                 temp = I915_READ(fdi_tx_reg);
1708                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1709                 I915_READ(fdi_tx_reg);
1710
1711                 temp = I915_READ(fdi_rx_reg);
1712                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1713                 I915_READ(fdi_rx_reg);
1714
1715                 udelay(100);
1716
1717                 /* still set train pattern 1 */
1718                 temp = I915_READ(fdi_tx_reg);
1719                 temp &= ~FDI_LINK_TRAIN_NONE;
1720                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1721                 I915_WRITE(fdi_tx_reg, temp);
1722
1723                 temp = I915_READ(fdi_rx_reg);
1724                 temp &= ~FDI_LINK_TRAIN_NONE;
1725                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1726                 I915_WRITE(fdi_rx_reg, temp);
1727
1728                 udelay(100);
1729
1730                 /* disable PCH transcoder */
1731                 temp = I915_READ(transconf_reg);
1732                 if ((temp & TRANS_ENABLE) != 0) {
1733                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1734                         I915_READ(transconf_reg);
1735                         n = 0;
1736                         /* wait for PCH transcoder off, transcoder state */
1737                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1738                                 n++;
1739                                 if (n < 60) {
1740                                         udelay(500);
1741                                         continue;
1742                                 } else {
1743                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1744                                         break;
1745                                 }
1746                         }
1747                 }
1748
1749                 /* disable PCH DPLL */
1750                 temp = I915_READ(pch_dpll_reg);
1751                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1752                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1753                         I915_READ(pch_dpll_reg);
1754                 }
1755
1756                 temp = I915_READ(fdi_rx_reg);
1757                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1758                         temp &= ~FDI_SEL_PCDCLK;
1759                         temp &= ~FDI_RX_PLL_ENABLE;
1760                         I915_WRITE(fdi_rx_reg, temp);
1761                         I915_READ(fdi_rx_reg);
1762                 }
1763
1764                 /* Disable CPU FDI TX PLL */
1765                 temp = I915_READ(fdi_tx_reg);
1766                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1767                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1768                         I915_READ(fdi_tx_reg);
1769                         udelay(100);
1770                 }
1771
1772                 /* Disable PF */
1773                 temp = I915_READ(pf_ctl_reg);
1774                 if ((temp & PF_ENABLE) != 0) {
1775                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1776                         I915_READ(pf_ctl_reg);
1777                 }
1778                 I915_WRITE(pf_win_size, 0);
1779
1780                 /* Wait for the clocks to turn off. */
1781                 udelay(150);
1782                 break;
1783         }
1784 }
1785
1786 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1787 {
1788         struct drm_device *dev = crtc->dev;
1789         struct drm_i915_private *dev_priv = dev->dev_private;
1790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1791         int pipe = intel_crtc->pipe;
1792         int plane = intel_crtc->plane;
1793         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1794         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1795         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1796         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1797         u32 temp;
1798
1799         /* XXX: When our outputs are all unaware of DPMS modes other than off
1800          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1801          */
1802         switch (mode) {
1803         case DRM_MODE_DPMS_ON:
1804         case DRM_MODE_DPMS_STANDBY:
1805         case DRM_MODE_DPMS_SUSPEND:
1806                 intel_update_watermarks(dev);
1807
1808                 /* Enable the DPLL */
1809                 temp = I915_READ(dpll_reg);
1810                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1811                         I915_WRITE(dpll_reg, temp);
1812                         I915_READ(dpll_reg);
1813                         /* Wait for the clocks to stabilize. */
1814                         udelay(150);
1815                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1816                         I915_READ(dpll_reg);
1817                         /* Wait for the clocks to stabilize. */
1818                         udelay(150);
1819                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1820                         I915_READ(dpll_reg);
1821                         /* Wait for the clocks to stabilize. */
1822                         udelay(150);
1823                 }
1824
1825                 /* Enable the pipe */
1826                 temp = I915_READ(pipeconf_reg);
1827                 if ((temp & PIPEACONF_ENABLE) == 0)
1828                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1829
1830                 /* Enable the plane */
1831                 temp = I915_READ(dspcntr_reg);
1832                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1833                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1834                         /* Flush the plane changes */
1835                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1836                 }
1837
1838                 intel_crtc_load_lut(crtc);
1839
1840                 if ((IS_I965G(dev) || plane == 0))
1841                         intel_update_fbc(crtc, &crtc->mode);
1842
1843                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1844                 //intel_crtc_dpms_video(crtc, true); TODO
1845         break;
1846         case DRM_MODE_DPMS_OFF:
1847                 intel_update_watermarks(dev);
1848                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1849                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1850
1851                 if (dev_priv->cfb_plane == plane &&
1852                     dev_priv->display.disable_fbc)
1853                         dev_priv->display.disable_fbc(dev);
1854
1855                 /* Disable the VGA plane that we never use */
1856                 i915_disable_vga(dev);
1857
1858                 /* Disable display plane */
1859                 temp = I915_READ(dspcntr_reg);
1860                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1861                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1862                         /* Flush the plane changes */
1863                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1864                         I915_READ(dspbase_reg);
1865                 }
1866
1867                 if (!IS_I9XX(dev)) {
1868                         /* Wait for vblank for the disable to take effect */
1869                         intel_wait_for_vblank(dev);
1870                 }
1871
1872                 /* Next, disable display pipes */
1873                 temp = I915_READ(pipeconf_reg);
1874                 if ((temp & PIPEACONF_ENABLE) != 0) {
1875                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1876                         I915_READ(pipeconf_reg);
1877                 }
1878
1879                 /* Wait for vblank for the disable to take effect. */
1880                 intel_wait_for_vblank(dev);
1881
1882                 temp = I915_READ(dpll_reg);
1883                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1884                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1885                         I915_READ(dpll_reg);
1886                 }
1887
1888                 /* Wait for the clocks to turn off. */
1889                 udelay(150);
1890                 break;
1891         }
1892 }
1893
1894 /**
1895  * Sets the power management mode of the pipe and plane.
1896  *
1897  * This code should probably grow support for turning the cursor off and back
1898  * on appropriately at the same time as we're turning the pipe off/on.
1899  */
1900 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1901 {
1902         struct drm_device *dev = crtc->dev;
1903         struct drm_i915_private *dev_priv = dev->dev_private;
1904         struct drm_i915_master_private *master_priv;
1905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1906         int pipe = intel_crtc->pipe;
1907         bool enabled;
1908
1909         dev_priv->display.dpms(crtc, mode);
1910
1911         intel_crtc->dpms_mode = mode;
1912
1913         if (!dev->primary->master)
1914                 return;
1915
1916         master_priv = dev->primary->master->driver_priv;
1917         if (!master_priv->sarea_priv)
1918                 return;
1919
1920         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1921
1922         switch (pipe) {
1923         case 0:
1924                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1925                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1926                 break;
1927         case 1:
1928                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1929                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1930                 break;
1931         default:
1932                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1933                 break;
1934         }
1935 }
1936
1937 static void intel_crtc_prepare (struct drm_crtc *crtc)
1938 {
1939         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1940         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1941 }
1942
1943 static void intel_crtc_commit (struct drm_crtc *crtc)
1944 {
1945         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1946         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1947 }
1948
1949 void intel_encoder_prepare (struct drm_encoder *encoder)
1950 {
1951         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1952         /* lvds has its own version of prepare see intel_lvds_prepare */
1953         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1954 }
1955
1956 void intel_encoder_commit (struct drm_encoder *encoder)
1957 {
1958         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1959         /* lvds has its own version of commit see intel_lvds_commit */
1960         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1961 }
1962
1963 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1964                                   struct drm_display_mode *mode,
1965                                   struct drm_display_mode *adjusted_mode)
1966 {
1967         struct drm_device *dev = crtc->dev;
1968         if (IS_IGDNG(dev)) {
1969                 /* FDI link clock is fixed at 2.7G */
1970                 if (mode->clock * 3 > 27000 * 4)
1971                         return MODE_CLOCK_HIGH;
1972         }
1973         return true;
1974 }
1975
1976 static int i945_get_display_clock_speed(struct drm_device *dev)
1977 {
1978         return 400000;
1979 }
1980
1981 static int i915_get_display_clock_speed(struct drm_device *dev)
1982 {
1983         return 333000;
1984 }
1985
1986 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
1987 {
1988         return 200000;
1989 }
1990
1991 static int i915gm_get_display_clock_speed(struct drm_device *dev)
1992 {
1993         u16 gcfgc = 0;
1994
1995         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1996
1997         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1998                 return 133000;
1999         else {
2000                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2001                 case GC_DISPLAY_CLOCK_333_MHZ:
2002                         return 333000;
2003                 default:
2004                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2005                         return 190000;
2006                 }
2007         }
2008 }
2009
2010 static int i865_get_display_clock_speed(struct drm_device *dev)
2011 {
2012         return 266000;
2013 }
2014
2015 static int i855_get_display_clock_speed(struct drm_device *dev)
2016 {
2017         u16 hpllcc = 0;
2018         /* Assume that the hardware is in the high speed state.  This
2019          * should be the default.
2020          */
2021         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2022         case GC_CLOCK_133_200:
2023         case GC_CLOCK_100_200:
2024                 return 200000;
2025         case GC_CLOCK_166_250:
2026                 return 250000;
2027         case GC_CLOCK_100_133:
2028                 return 133000;
2029         }
2030
2031         /* Shouldn't happen */
2032         return 0;
2033 }
2034
2035 static int i830_get_display_clock_speed(struct drm_device *dev)
2036 {
2037         return 133000;
2038 }
2039
2040 /**
2041  * Return the pipe currently connected to the panel fitter,
2042  * or -1 if the panel fitter is not present or not in use
2043  */
2044 static int intel_panel_fitter_pipe (struct drm_device *dev)
2045 {
2046         struct drm_i915_private *dev_priv = dev->dev_private;
2047         u32  pfit_control;
2048
2049         /* i830 doesn't have a panel fitter */
2050         if (IS_I830(dev))
2051                 return -1;
2052
2053         pfit_control = I915_READ(PFIT_CONTROL);
2054
2055         /* See if the panel fitter is in use */
2056         if ((pfit_control & PFIT_ENABLE) == 0)
2057                 return -1;
2058
2059         /* 965 can place panel fitter on either pipe */
2060         if (IS_I965G(dev))
2061                 return (pfit_control >> 29) & 0x3;
2062
2063         /* older chips can only use pipe 1 */
2064         return 1;
2065 }
2066
2067 struct fdi_m_n {
2068         u32        tu;
2069         u32        gmch_m;
2070         u32        gmch_n;
2071         u32        link_m;
2072         u32        link_n;
2073 };
2074
2075 static void
2076 fdi_reduce_ratio(u32 *num, u32 *den)
2077 {
2078         while (*num > 0xffffff || *den > 0xffffff) {
2079                 *num >>= 1;
2080                 *den >>= 1;
2081         }
2082 }
2083
2084 #define DATA_N 0x800000
2085 #define LINK_N 0x80000
2086
2087 static void
2088 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2089                 int pixel_clock, int link_clock,
2090                 struct fdi_m_n *m_n)
2091 {
2092         u64 temp;
2093
2094         m_n->tu = 64; /* default size */
2095
2096         temp = (u64) DATA_N * pixel_clock;
2097         temp = div_u64(temp, link_clock);
2098         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2099         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2100         m_n->gmch_n = DATA_N;
2101         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2102
2103         temp = (u64) LINK_N * pixel_clock;
2104         m_n->link_m = div_u64(temp, link_clock);
2105         m_n->link_n = LINK_N;
2106         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2107 }
2108
2109
2110 struct intel_watermark_params {
2111         unsigned long fifo_size;
2112         unsigned long max_wm;
2113         unsigned long default_wm;
2114         unsigned long guard_size;
2115         unsigned long cacheline_size;
2116 };
2117
2118 /* IGD has different values for various configs */
2119 static struct intel_watermark_params igd_display_wm = {
2120         IGD_DISPLAY_FIFO,
2121         IGD_MAX_WM,
2122         IGD_DFT_WM,
2123         IGD_GUARD_WM,
2124         IGD_FIFO_LINE_SIZE
2125 };
2126 static struct intel_watermark_params igd_display_hplloff_wm = {
2127         IGD_DISPLAY_FIFO,
2128         IGD_MAX_WM,
2129         IGD_DFT_HPLLOFF_WM,
2130         IGD_GUARD_WM,
2131         IGD_FIFO_LINE_SIZE
2132 };
2133 static struct intel_watermark_params igd_cursor_wm = {
2134         IGD_CURSOR_FIFO,
2135         IGD_CURSOR_MAX_WM,
2136         IGD_CURSOR_DFT_WM,
2137         IGD_CURSOR_GUARD_WM,
2138         IGD_FIFO_LINE_SIZE,
2139 };
2140 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2141         IGD_CURSOR_FIFO,
2142         IGD_CURSOR_MAX_WM,
2143         IGD_CURSOR_DFT_WM,
2144         IGD_CURSOR_GUARD_WM,
2145         IGD_FIFO_LINE_SIZE
2146 };
2147 static struct intel_watermark_params g4x_wm_info = {
2148         G4X_FIFO_SIZE,
2149         G4X_MAX_WM,
2150         G4X_MAX_WM,
2151         2,
2152         G4X_FIFO_LINE_SIZE,
2153 };
2154 static struct intel_watermark_params i945_wm_info = {
2155         I945_FIFO_SIZE,
2156         I915_MAX_WM,
2157         1,
2158         2,
2159         I915_FIFO_LINE_SIZE
2160 };
2161 static struct intel_watermark_params i915_wm_info = {
2162         I915_FIFO_SIZE,
2163         I915_MAX_WM,
2164         1,
2165         2,
2166         I915_FIFO_LINE_SIZE
2167 };
2168 static struct intel_watermark_params i855_wm_info = {
2169         I855GM_FIFO_SIZE,
2170         I915_MAX_WM,
2171         1,
2172         2,
2173         I830_FIFO_LINE_SIZE
2174 };
2175 static struct intel_watermark_params i830_wm_info = {
2176         I830_FIFO_SIZE,
2177         I915_MAX_WM,
2178         1,
2179         2,
2180         I830_FIFO_LINE_SIZE
2181 };
2182
2183 /**
2184  * intel_calculate_wm - calculate watermark level
2185  * @clock_in_khz: pixel clock
2186  * @wm: chip FIFO params
2187  * @pixel_size: display pixel size
2188  * @latency_ns: memory latency for the platform
2189  *
2190  * Calculate the watermark level (the level at which the display plane will
2191  * start fetching from memory again).  Each chip has a different display
2192  * FIFO size and allocation, so the caller needs to figure that out and pass
2193  * in the correct intel_watermark_params structure.
2194  *
2195  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2196  * on the pixel size.  When it reaches the watermark level, it'll start
2197  * fetching FIFO line sized based chunks from memory until the FIFO fills
2198  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2199  * will occur, and a display engine hang could result.
2200  */
2201 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2202                                         struct intel_watermark_params *wm,
2203                                         int pixel_size,
2204                                         unsigned long latency_ns)
2205 {
2206         long entries_required, wm_size;
2207
2208         /*
2209          * Note: we need to make sure we don't overflow for various clock &
2210          * latency values.
2211          * clocks go from a few thousand to several hundred thousand.
2212          * latency is usually a few thousand
2213          */
2214         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2215                 1000;
2216         entries_required /= wm->cacheline_size;
2217
2218         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2219
2220         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2221
2222         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2223
2224         /* Don't promote wm_size to unsigned... */
2225         if (wm_size > (long)wm->max_wm)
2226                 wm_size = wm->max_wm;
2227         if (wm_size <= 0)
2228                 wm_size = wm->default_wm;
2229         return wm_size;
2230 }
2231
2232 struct cxsr_latency {
2233         int is_desktop;
2234         unsigned long fsb_freq;
2235         unsigned long mem_freq;
2236         unsigned long display_sr;
2237         unsigned long display_hpll_disable;
2238         unsigned long cursor_sr;
2239         unsigned long cursor_hpll_disable;
2240 };
2241
2242 static struct cxsr_latency cxsr_latency_table[] = {
2243         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2244         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2245         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2246
2247         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2248         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2249         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2250
2251         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2252         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2253         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2254
2255         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2256         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2257         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2258
2259         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2260         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2261         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2262
2263         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2264         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2265         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2266 };
2267
2268 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2269                                                    int mem)
2270 {
2271         int i;
2272         struct cxsr_latency *latency;
2273
2274         if (fsb == 0 || mem == 0)
2275                 return NULL;
2276
2277         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2278                 latency = &cxsr_latency_table[i];
2279                 if (is_desktop == latency->is_desktop &&
2280                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2281                         return latency;
2282         }
2283
2284         DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2285
2286         return NULL;
2287 }
2288
2289 static void igd_disable_cxsr(struct drm_device *dev)
2290 {
2291         struct drm_i915_private *dev_priv = dev->dev_private;
2292         u32 reg;
2293
2294         /* deactivate cxsr */
2295         reg = I915_READ(DSPFW3);
2296         reg &= ~(IGD_SELF_REFRESH_EN);
2297         I915_WRITE(DSPFW3, reg);
2298         DRM_INFO("Big FIFO is disabled\n");
2299 }
2300
2301 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2302                             int pixel_size)
2303 {
2304         struct drm_i915_private *dev_priv = dev->dev_private;
2305         u32 reg;
2306         unsigned long wm;
2307         struct cxsr_latency *latency;
2308
2309         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2310                 dev_priv->mem_freq);
2311         if (!latency) {
2312                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2313                 igd_disable_cxsr(dev);
2314                 return;
2315         }
2316
2317         /* Display SR */
2318         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2319                                 latency->display_sr);
2320         reg = I915_READ(DSPFW1);
2321         reg &= 0x7fffff;
2322         reg |= wm << 23;
2323         I915_WRITE(DSPFW1, reg);
2324         DRM_DEBUG("DSPFW1 register is %x\n", reg);
2325
2326         /* cursor SR */
2327         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2328                                 latency->cursor_sr);
2329         reg = I915_READ(DSPFW3);
2330         reg &= ~(0x3f << 24);
2331         reg |= (wm & 0x3f) << 24;
2332         I915_WRITE(DSPFW3, reg);
2333
2334         /* Display HPLL off SR */
2335         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2336                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2337         reg = I915_READ(DSPFW3);
2338         reg &= 0xfffffe00;
2339         reg |= wm & 0x1ff;
2340         I915_WRITE(DSPFW3, reg);
2341
2342         /* cursor HPLL off SR */
2343         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2344                                 latency->cursor_hpll_disable);
2345         reg = I915_READ(DSPFW3);
2346         reg &= ~(0x3f << 16);
2347         reg |= (wm & 0x3f) << 16;
2348         I915_WRITE(DSPFW3, reg);
2349         DRM_DEBUG("DSPFW3 register is %x\n", reg);
2350
2351         /* activate cxsr */
2352         reg = I915_READ(DSPFW3);
2353         reg |= IGD_SELF_REFRESH_EN;
2354         I915_WRITE(DSPFW3, reg);
2355
2356         DRM_INFO("Big FIFO is enabled\n");
2357
2358         return;
2359 }
2360
2361 /*
2362  * Latency for FIFO fetches is dependent on several factors:
2363  *   - memory configuration (speed, channels)
2364  *   - chipset
2365  *   - current MCH state
2366  * It can be fairly high in some situations, so here we assume a fairly
2367  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2368  * set this value too high, the FIFO will fetch frequently to stay full)
2369  * and power consumption (set it too low to save power and we might see
2370  * FIFO underruns and display "flicker").
2371  *
2372  * A value of 5us seems to be a good balance; safe for very low end
2373  * platforms but not overly aggressive on lower latency configs.
2374  */
2375 const static int latency_ns = 5000;
2376
2377 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2378 {
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         uint32_t dsparb = I915_READ(DSPARB);
2381         int size;
2382
2383         if (plane == 0)
2384                 size = dsparb & 0x7f;
2385         else
2386                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2387                         (dsparb & 0x7f);
2388
2389         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2390                   size);
2391
2392         return size;
2393 }
2394
2395 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2396 {
2397         struct drm_i915_private *dev_priv = dev->dev_private;
2398         uint32_t dsparb = I915_READ(DSPARB);
2399         int size;
2400
2401         if (plane == 0)
2402                 size = dsparb & 0x1ff;
2403         else
2404                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2405                         (dsparb & 0x1ff);
2406         size >>= 1; /* Convert to cachelines */
2407
2408         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2409                   size);
2410
2411         return size;
2412 }
2413
2414 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2415 {
2416         struct drm_i915_private *dev_priv = dev->dev_private;
2417         uint32_t dsparb = I915_READ(DSPARB);
2418         int size;
2419
2420         size = dsparb & 0x7f;
2421         size >>= 2; /* Convert to cachelines */
2422
2423         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2424                   size);
2425
2426         return size;
2427 }
2428
2429 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2430 {
2431         struct drm_i915_private *dev_priv = dev->dev_private;
2432         uint32_t dsparb = I915_READ(DSPARB);
2433         int size;
2434
2435         size = dsparb & 0x7f;
2436         size >>= 1; /* Convert to cachelines */
2437
2438         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2439                   size);
2440
2441         return size;
2442 }
2443
2444 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2445                           int planeb_clock, int sr_hdisplay, int pixel_size)
2446 {
2447         struct drm_i915_private *dev_priv = dev->dev_private;
2448         int total_size, cacheline_size;
2449         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2450         struct intel_watermark_params planea_params, planeb_params;
2451         unsigned long line_time_us;
2452         int sr_clock, sr_entries = 0, entries_required;
2453
2454         /* Create copies of the base settings for each pipe */
2455         planea_params = planeb_params = g4x_wm_info;
2456
2457         /* Grab a couple of global values before we overwrite them */
2458         total_size = planea_params.fifo_size;
2459         cacheline_size = planea_params.cacheline_size;
2460
2461         /*
2462          * Note: we need to make sure we don't overflow for various clock &
2463          * latency values.
2464          * clocks go from a few thousand to several hundred thousand.
2465          * latency is usually a few thousand
2466          */
2467         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2468                 1000;
2469         entries_required /= G4X_FIFO_LINE_SIZE;
2470         planea_wm = entries_required + planea_params.guard_size;
2471
2472         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2473                 1000;
2474         entries_required /= G4X_FIFO_LINE_SIZE;
2475         planeb_wm = entries_required + planeb_params.guard_size;
2476
2477         cursora_wm = cursorb_wm = 16;
2478         cursor_sr = 32;
2479
2480         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2481
2482         /* Calc sr entries for one plane configs */
2483         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2484                 /* self-refresh has much higher latency */
2485                 const static int sr_latency_ns = 12000;
2486
2487                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2488                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2489
2490                 /* Use ns/us then divide to preserve precision */
2491                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2492                               pixel_size * sr_hdisplay) / 1000;
2493                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2494                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2495                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2496         }
2497
2498         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2499                   planea_wm, planeb_wm, sr_entries);
2500
2501         planea_wm &= 0x3f;
2502         planeb_wm &= 0x3f;
2503
2504         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2505                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2506                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2507         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2508                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2509         /* HPLL off in SR has some issues on G4x... disable it */
2510         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2511                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2512 }
2513
2514 static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
2515                            int unused3, int unused4)
2516 {
2517         struct drm_i915_private *dev_priv = dev->dev_private;
2518
2519         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2520
2521         /* 965 has limitations... */
2522         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2523         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2524 }
2525
2526 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2527                            int planeb_clock, int sr_hdisplay, int pixel_size)
2528 {
2529         struct drm_i915_private *dev_priv = dev->dev_private;
2530         uint32_t fwater_lo;
2531         uint32_t fwater_hi;
2532         int total_size, cacheline_size, cwm, srwm = 1;
2533         int planea_wm, planeb_wm;
2534         struct intel_watermark_params planea_params, planeb_params;
2535         unsigned long line_time_us;
2536         int sr_clock, sr_entries = 0;
2537
2538         /* Create copies of the base settings for each pipe */
2539         if (IS_I965GM(dev) || IS_I945GM(dev))
2540                 planea_params = planeb_params = i945_wm_info;
2541         else if (IS_I9XX(dev))
2542                 planea_params = planeb_params = i915_wm_info;
2543         else
2544                 planea_params = planeb_params = i855_wm_info;
2545
2546         /* Grab a couple of global values before we overwrite them */
2547         total_size = planea_params.fifo_size;
2548         cacheline_size = planea_params.cacheline_size;
2549
2550         /* Update per-plane FIFO sizes */
2551         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2552         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2553
2554         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2555                                        pixel_size, latency_ns);
2556         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2557                                        pixel_size, latency_ns);
2558         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2559
2560         /*
2561          * Overlay gets an aggressive default since video jitter is bad.
2562          */
2563         cwm = 2;
2564
2565         /* Calc sr entries for one plane configs */
2566         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2567             (!planea_clock || !planeb_clock)) {
2568                 /* self-refresh has much higher latency */
2569                 const static int sr_latency_ns = 6000;
2570
2571                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2572                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2573
2574                 /* Use ns/us then divide to preserve precision */
2575                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2576                               pixel_size * sr_hdisplay) / 1000;
2577                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2578                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2579                 srwm = total_size - sr_entries;
2580                 if (srwm < 0)
2581                         srwm = 1;
2582                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2583         }
2584
2585         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2586                   planea_wm, planeb_wm, cwm, srwm);
2587
2588         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2589         fwater_hi = (cwm & 0x1f);
2590
2591         /* Set request length to 8 cachelines per fetch */
2592         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2593         fwater_hi = fwater_hi | (1 << 8);
2594
2595         I915_WRITE(FW_BLC, fwater_lo);
2596         I915_WRITE(FW_BLC2, fwater_hi);
2597 }
2598
2599 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2600                            int unused2, int pixel_size)
2601 {
2602         struct drm_i915_private *dev_priv = dev->dev_private;
2603         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2604         int planea_wm;
2605
2606         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2607
2608         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2609                                        pixel_size, latency_ns);
2610         fwater_lo |= (3<<8) | planea_wm;
2611
2612         DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2613
2614         I915_WRITE(FW_BLC, fwater_lo);
2615 }
2616
2617 /**
2618  * intel_update_watermarks - update FIFO watermark values based on current modes
2619  *
2620  * Calculate watermark values for the various WM regs based on current mode
2621  * and plane configuration.
2622  *
2623  * There are several cases to deal with here:
2624  *   - normal (i.e. non-self-refresh)
2625  *   - self-refresh (SR) mode
2626  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2627  *   - lines are small relative to FIFO size (buffer can hold more than 2
2628  *     lines), so need to account for TLB latency
2629  *
2630  *   The normal calculation is:
2631  *     watermark = dotclock * bytes per pixel * latency
2632  *   where latency is platform & configuration dependent (we assume pessimal
2633  *   values here).
2634  *
2635  *   The SR calculation is:
2636  *     watermark = (trunc(latency/line time)+1) * surface width *
2637  *       bytes per pixel
2638  *   where
2639  *     line time = htotal / dotclock
2640  *   and latency is assumed to be high, as above.
2641  *
2642  * The final value programmed to the register should always be rounded up,
2643  * and include an extra 2 entries to account for clock crossings.
2644  *
2645  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2646  * to set the non-SR watermarks to 8.
2647   */
2648 static void intel_update_watermarks(struct drm_device *dev)
2649 {
2650         struct drm_i915_private *dev_priv = dev->dev_private;
2651         struct drm_crtc *crtc;
2652         struct intel_crtc *intel_crtc;
2653         int sr_hdisplay = 0;
2654         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2655         int enabled = 0, pixel_size = 0;
2656
2657         if (!dev_priv->display.update_wm)
2658                 return;
2659
2660         /* Get the clock config from both planes */
2661         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2662                 intel_crtc = to_intel_crtc(crtc);
2663                 if (crtc->enabled) {
2664                         enabled++;
2665                         if (intel_crtc->plane == 0) {
2666                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2667                                           intel_crtc->pipe, crtc->mode.clock);
2668                                 planea_clock = crtc->mode.clock;
2669                         } else {
2670                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2671                                           intel_crtc->pipe, crtc->mode.clock);
2672                                 planeb_clock = crtc->mode.clock;
2673                         }
2674                         sr_hdisplay = crtc->mode.hdisplay;
2675                         sr_clock = crtc->mode.clock;
2676                         if (crtc->fb)
2677                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2678                         else
2679                                 pixel_size = 4; /* by default */
2680                 }
2681         }
2682
2683         if (enabled <= 0)
2684                 return;
2685
2686         /* Single plane configs can enable self refresh */
2687         if (enabled == 1 && IS_IGD(dev))
2688                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2689         else if (IS_IGD(dev))
2690                 igd_disable_cxsr(dev);
2691
2692         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2693                                     sr_hdisplay, pixel_size);
2694 }
2695
2696 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2697                                struct drm_display_mode *mode,
2698                                struct drm_display_mode *adjusted_mode,
2699                                int x, int y,
2700                                struct drm_framebuffer *old_fb)
2701 {
2702         struct drm_device *dev = crtc->dev;
2703         struct drm_i915_private *dev_priv = dev->dev_private;
2704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2705         int pipe = intel_crtc->pipe;
2706         int plane = intel_crtc->plane;
2707         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2708         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2709         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2710         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2711         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2712         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2713         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2714         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2715         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2716         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2717         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2718         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2719         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2720         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2721         int refclk, num_outputs = 0;
2722         intel_clock_t clock, reduced_clock;
2723         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2724         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2725         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2726         bool is_edp = false;
2727         struct drm_mode_config *mode_config = &dev->mode_config;
2728         struct drm_connector *connector;
2729         const intel_limit_t *limit;
2730         int ret;
2731         struct fdi_m_n m_n = {0};
2732         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2733         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2734         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2735         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2736         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2737         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2738         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2739         int lvds_reg = LVDS;
2740         u32 temp;
2741         int sdvo_pixel_multiply;
2742         int target_clock;
2743
2744         drm_vblank_pre_modeset(dev, pipe);
2745
2746         list_for_each_entry(connector, &mode_config->connector_list, head) {
2747                 struct intel_output *intel_output = to_intel_output(connector);
2748
2749                 if (!connector->encoder || connector->encoder->crtc != crtc)
2750                         continue;
2751
2752                 switch (intel_output->type) {
2753                 case INTEL_OUTPUT_LVDS:
2754                         is_lvds = true;
2755                         break;
2756                 case INTEL_OUTPUT_SDVO:
2757                 case INTEL_OUTPUT_HDMI:
2758                         is_sdvo = true;
2759                         if (intel_output->needs_tv_clock)
2760                                 is_tv = true;
2761                         break;
2762                 case INTEL_OUTPUT_DVO:
2763                         is_dvo = true;
2764                         break;
2765                 case INTEL_OUTPUT_TVOUT:
2766                         is_tv = true;
2767                         break;
2768                 case INTEL_OUTPUT_ANALOG:
2769                         is_crt = true;
2770                         break;
2771                 case INTEL_OUTPUT_DISPLAYPORT:
2772                         is_dp = true;
2773                         break;
2774                 case INTEL_OUTPUT_EDP:
2775                         is_edp = true;
2776                         break;
2777                 }
2778
2779                 num_outputs++;
2780         }
2781
2782         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2783                 refclk = dev_priv->lvds_ssc_freq * 1000;
2784                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2785         } else if (IS_I9XX(dev)) {
2786                 refclk = 96000;
2787                 if (IS_IGDNG(dev))
2788                         refclk = 120000; /* 120Mhz refclk */
2789         } else {
2790                 refclk = 48000;
2791         }
2792
2793
2794         /*
2795          * Returns a set of divisors for the desired target clock with the given
2796          * refclk, or FALSE.  The returned values represent the clock equation:
2797          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2798          */
2799         limit = intel_limit(crtc);
2800         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2801         if (!ok) {
2802                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2803                 drm_vblank_post_modeset(dev, pipe);
2804                 return -EINVAL;
2805         }
2806
2807         if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2808                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2809                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2810                                                             (adjusted_mode->clock*3/4),
2811                                                             refclk,
2812                                                             &reduced_clock);
2813         }
2814
2815         /* SDVO TV has fixed PLL values depend on its clock range,
2816            this mirrors vbios setting. */
2817         if (is_sdvo && is_tv) {
2818                 if (adjusted_mode->clock >= 100000
2819                                 && adjusted_mode->clock < 140500) {
2820                         clock.p1 = 2;
2821                         clock.p2 = 10;
2822                         clock.n = 3;
2823                         clock.m1 = 16;
2824                         clock.m2 = 8;
2825                 } else if (adjusted_mode->clock >= 140500
2826                                 && adjusted_mode->clock <= 200000) {
2827                         clock.p1 = 1;
2828                         clock.p2 = 10;
2829                         clock.n = 6;
2830                         clock.m1 = 12;
2831                         clock.m2 = 8;
2832                 }
2833         }
2834
2835         /* FDI link */
2836         if (IS_IGDNG(dev)) {
2837                 int lane, link_bw, bpp;
2838                 /* eDP doesn't require FDI link, so just set DP M/N
2839                    according to current link config */
2840                 if (is_edp) {
2841                         struct drm_connector *edp;
2842                         target_clock = mode->clock;
2843                         edp = intel_pipe_get_output(crtc);
2844                         intel_edp_link_config(to_intel_output(edp),
2845                                         &lane, &link_bw);
2846                 } else {
2847                         /* DP over FDI requires target mode clock
2848                            instead of link clock */
2849                         if (is_dp)
2850                                 target_clock = mode->clock;
2851                         else
2852                                 target_clock = adjusted_mode->clock;
2853                         lane = 4;
2854                         link_bw = 270000;
2855                 }
2856
2857                 /* determine panel color depth */
2858                 temp = I915_READ(pipeconf_reg);
2859
2860                 switch (temp & PIPE_BPC_MASK) {
2861                 case PIPE_8BPC:
2862                         bpp = 24;
2863                         break;
2864                 case PIPE_10BPC:
2865                         bpp = 30;
2866                         break;
2867                 case PIPE_6BPC:
2868                         bpp = 18;
2869                         break;
2870                 case PIPE_12BPC:
2871                         bpp = 36;
2872                         break;
2873                 default:
2874                         DRM_ERROR("unknown pipe bpc value\n");
2875                         bpp = 24;
2876                 }
2877
2878                 igdng_compute_m_n(bpp, lane, target_clock,
2879                                   link_bw, &m_n);
2880         }
2881
2882         /* Ironlake: try to setup display ref clock before DPLL
2883          * enabling. This is only under driver's control after
2884          * PCH B stepping, previous chipset stepping should be
2885          * ignoring this setting.
2886          */
2887         if (IS_IGDNG(dev)) {
2888                 temp = I915_READ(PCH_DREF_CONTROL);
2889                 /* Always enable nonspread source */
2890                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2891                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2892                 I915_WRITE(PCH_DREF_CONTROL, temp);
2893                 POSTING_READ(PCH_DREF_CONTROL);
2894
2895                 temp &= ~DREF_SSC_SOURCE_MASK;
2896                 temp |= DREF_SSC_SOURCE_ENABLE;
2897                 I915_WRITE(PCH_DREF_CONTROL, temp);
2898                 POSTING_READ(PCH_DREF_CONTROL);
2899
2900                 udelay(200);
2901
2902                 if (is_edp) {
2903                         if (dev_priv->lvds_use_ssc) {
2904                                 temp |= DREF_SSC1_ENABLE;
2905                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2906                                 POSTING_READ(PCH_DREF_CONTROL);
2907
2908                                 udelay(200);
2909
2910                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2911                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2912                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2913                                 POSTING_READ(PCH_DREF_CONTROL);
2914                         } else {
2915                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2916                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2917                                 POSTING_READ(PCH_DREF_CONTROL);
2918                         }
2919                 }
2920         }
2921
2922         if (IS_IGD(dev)) {
2923                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2924                 if (has_reduced_clock)
2925                         fp2 = (1 << reduced_clock.n) << 16 |
2926                                 reduced_clock.m1 << 8 | reduced_clock.m2;
2927         } else {
2928                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2929                 if (has_reduced_clock)
2930                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2931                                 reduced_clock.m2;
2932         }
2933
2934         if (!IS_IGDNG(dev))
2935                 dpll = DPLL_VGA_MODE_DIS;
2936
2937         if (IS_I9XX(dev)) {
2938                 if (is_lvds)
2939                         dpll |= DPLLB_MODE_LVDS;
2940                 else
2941                         dpll |= DPLLB_MODE_DAC_SERIAL;
2942                 if (is_sdvo) {
2943                         dpll |= DPLL_DVO_HIGH_SPEED;
2944                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2945                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2946                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2947                         else if (IS_IGDNG(dev))
2948                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2949                 }
2950                 if (is_dp)
2951                         dpll |= DPLL_DVO_HIGH_SPEED;
2952
2953                 /* compute bitmask from p1 value */
2954                 if (IS_IGD(dev))
2955                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2956                 else {
2957                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2958                         /* also FPA1 */
2959                         if (IS_IGDNG(dev))
2960                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2961                         if (IS_G4X(dev) && has_reduced_clock)
2962                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2963                 }
2964                 switch (clock.p2) {
2965                 case 5:
2966                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2967                         break;
2968                 case 7:
2969                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2970                         break;
2971                 case 10:
2972                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2973                         break;
2974                 case 14:
2975                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2976                         break;
2977                 }
2978                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2979                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2980         } else {
2981                 if (is_lvds) {
2982                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2983                 } else {
2984                         if (clock.p1 == 2)
2985                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2986                         else
2987                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2988                         if (clock.p2 == 4)
2989                                 dpll |= PLL_P2_DIVIDE_BY_4;
2990                 }
2991         }
2992
2993         if (is_sdvo && is_tv)
2994                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2995         else if (is_tv)
2996                 /* XXX: just matching BIOS for now */
2997                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2998                 dpll |= 3;
2999         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3000                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3001         else
3002                 dpll |= PLL_REF_INPUT_DREFCLK;
3003
3004         /* setup pipeconf */
3005         pipeconf = I915_READ(pipeconf_reg);
3006
3007         /* Set up the display plane register */
3008         dspcntr = DISPPLANE_GAMMA_ENABLE;
3009
3010         /* IGDNG's plane is forced to pipe, bit 24 is to
3011            enable color space conversion */
3012         if (!IS_IGDNG(dev)) {
3013                 if (pipe == 0)
3014                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3015                 else
3016                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3017         }
3018
3019         if (pipe == 0 && !IS_I965G(dev)) {
3020                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3021                  * core speed.
3022                  *
3023                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3024                  * pipe == 0 check?
3025                  */
3026                 if (mode->clock >
3027                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3028                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3029                 else
3030                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3031         }
3032
3033         dspcntr |= DISPLAY_PLANE_ENABLE;
3034         pipeconf |= PIPEACONF_ENABLE;
3035         dpll |= DPLL_VCO_ENABLE;
3036
3037
3038         /* Disable the panel fitter if it was on our pipe */
3039         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3040                 I915_WRITE(PFIT_CONTROL, 0);
3041
3042         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3043         drm_mode_debug_printmodeline(mode);
3044
3045         /* assign to IGDNG registers */
3046         if (IS_IGDNG(dev)) {
3047                 fp_reg = pch_fp_reg;
3048                 dpll_reg = pch_dpll_reg;
3049         }
3050
3051         if (is_edp) {
3052                 igdng_disable_pll_edp(crtc);
3053         } else if ((dpll & DPLL_VCO_ENABLE)) {
3054                 I915_WRITE(fp_reg, fp);
3055                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3056                 I915_READ(dpll_reg);
3057                 udelay(150);
3058         }
3059
3060         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3061          * This is an exception to the general rule that mode_set doesn't turn
3062          * things on.
3063          */
3064         if (is_lvds) {
3065                 u32 lvds;
3066
3067                 if (IS_IGDNG(dev))
3068                         lvds_reg = PCH_LVDS;
3069
3070                 lvds = I915_READ(lvds_reg);
3071                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3072                 /* set the corresponsding LVDS_BORDER bit */
3073                 lvds |= dev_priv->lvds_border_bits;
3074                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3075                  * set the DPLLs for dual-channel mode or not.
3076                  */
3077                 if (clock.p2 == 7)
3078                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3079                 else
3080                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3081
3082                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3083                  * appropriately here, but we need to look more thoroughly into how
3084                  * panels behave in the two modes.
3085                  */
3086
3087                 I915_WRITE(lvds_reg, lvds);
3088                 I915_READ(lvds_reg);
3089         }
3090         if (is_dp)
3091                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3092
3093         if (!is_edp) {
3094                 I915_WRITE(fp_reg, fp);
3095                 I915_WRITE(dpll_reg, dpll);
3096                 I915_READ(dpll_reg);
3097                 /* Wait for the clocks to stabilize. */
3098                 udelay(150);
3099
3100                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3101                         if (is_sdvo) {
3102                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3103                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3104                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3105                         } else
3106                                 I915_WRITE(dpll_md_reg, 0);
3107                 } else {
3108                         /* write it again -- the BIOS does, after all */
3109                         I915_WRITE(dpll_reg, dpll);
3110                 }
3111                 I915_READ(dpll_reg);
3112                 /* Wait for the clocks to stabilize. */
3113                 udelay(150);
3114         }
3115
3116         if (is_lvds && has_reduced_clock && i915_powersave) {
3117                 I915_WRITE(fp_reg + 4, fp2);
3118                 intel_crtc->lowfreq_avail = true;
3119                 if (HAS_PIPE_CXSR(dev)) {
3120                         DRM_DEBUG("enabling CxSR downclocking\n");
3121                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3122                 }
3123         } else {
3124                 I915_WRITE(fp_reg + 4, fp);
3125                 intel_crtc->lowfreq_avail = false;
3126                 if (HAS_PIPE_CXSR(dev)) {
3127                         DRM_DEBUG("disabling CxSR downclocking\n");
3128                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3129                 }
3130         }
3131
3132         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3133                    ((adjusted_mode->crtc_htotal - 1) << 16));
3134         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3135                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3136         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3137                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3138         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3139                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3140         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3141                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3142         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3143                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3144         /* pipesrc and dspsize control the size that is scaled from, which should
3145          * always be the user's requested size.
3146          */
3147         if (!IS_IGDNG(dev)) {
3148                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3149                                 (mode->hdisplay - 1));
3150                 I915_WRITE(dsppos_reg, 0);
3151         }
3152         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3153
3154         if (IS_IGDNG(dev)) {
3155                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3156                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3157                 I915_WRITE(link_m1_reg, m_n.link_m);
3158                 I915_WRITE(link_n1_reg, m_n.link_n);
3159
3160                 if (is_edp) {
3161                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
3162                 } else {
3163                         /* enable FDI RX PLL too */
3164                         temp = I915_READ(fdi_rx_reg);
3165                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3166                         udelay(200);
3167                 }
3168         }
3169
3170         I915_WRITE(pipeconf_reg, pipeconf);
3171         I915_READ(pipeconf_reg);
3172
3173         intel_wait_for_vblank(dev);
3174
3175         if (IS_IGDNG(dev)) {
3176                 /* enable address swizzle for tiling buffer */
3177                 temp = I915_READ(DISP_ARB_CTL);
3178                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3179         }
3180
3181         I915_WRITE(dspcntr_reg, dspcntr);
3182
3183         /* Flush the plane changes */
3184         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3185
3186         if ((IS_I965G(dev) || plane == 0))
3187                 intel_update_fbc(crtc, &crtc->mode);
3188
3189         intel_update_watermarks(dev);
3190
3191         drm_vblank_post_modeset(dev, pipe);
3192
3193         return ret;
3194 }
3195
3196 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3197 void intel_crtc_load_lut(struct drm_crtc *crtc)
3198 {
3199         struct drm_device *dev = crtc->dev;
3200         struct drm_i915_private *dev_priv = dev->dev_private;
3201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3202         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3203         int i;
3204
3205         /* The clocks have to be on to load the palette. */
3206         if (!crtc->enabled)
3207                 return;
3208
3209         /* use legacy palette for IGDNG */
3210         if (IS_IGDNG(dev))
3211                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3212                                                    LGC_PALETTE_B;
3213
3214         for (i = 0; i < 256; i++) {
3215                 I915_WRITE(palreg + 4 * i,
3216                            (intel_crtc->lut_r[i] << 16) |
3217                            (intel_crtc->lut_g[i] << 8) |
3218                            intel_crtc->lut_b[i]);
3219         }
3220 }
3221
3222 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3223                                  struct drm_file *file_priv,
3224                                  uint32_t handle,
3225                                  uint32_t width, uint32_t height)
3226 {
3227         struct drm_device *dev = crtc->dev;
3228         struct drm_i915_private *dev_priv = dev->dev_private;
3229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3230         struct drm_gem_object *bo;
3231         struct drm_i915_gem_object *obj_priv;
3232         int pipe = intel_crtc->pipe;
3233         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3234         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3235         uint32_t temp = I915_READ(control);
3236         size_t addr;
3237         int ret;
3238
3239         DRM_DEBUG("\n");
3240
3241         /* if we want to turn off the cursor ignore width and height */
3242         if (!handle) {
3243                 DRM_DEBUG("cursor off\n");
3244                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3245                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3246                         temp |= CURSOR_MODE_DISABLE;
3247                 } else {
3248                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3249                 }
3250                 addr = 0;
3251                 bo = NULL;
3252                 mutex_lock(&dev->struct_mutex);
3253                 goto finish;
3254         }
3255
3256         /* Currently we only support 64x64 cursors */
3257         if (width != 64 || height != 64) {
3258                 DRM_ERROR("we currently only support 64x64 cursors\n");
3259                 return -EINVAL;
3260         }
3261
3262         bo = drm_gem_object_lookup(dev, file_priv, handle);
3263         if (!bo)
3264                 return -ENOENT;
3265
3266         obj_priv = bo->driver_private;
3267
3268         if (bo->size < width * height * 4) {
3269                 DRM_ERROR("buffer is to small\n");
3270                 ret = -ENOMEM;
3271                 goto fail;
3272         }
3273
3274         /* we only need to pin inside GTT if cursor is non-phy */
3275         mutex_lock(&dev->struct_mutex);
3276         if (!dev_priv->cursor_needs_physical) {
3277                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3278                 if (ret) {
3279                         DRM_ERROR("failed to pin cursor bo\n");
3280                         goto fail_locked;
3281                 }
3282                 addr = obj_priv->gtt_offset;
3283         } else {
3284                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3285                 if (ret) {
3286                         DRM_ERROR("failed to attach phys object\n");
3287                         goto fail_locked;
3288                 }
3289                 addr = obj_priv->phys_obj->handle->busaddr;
3290         }
3291
3292         if (!IS_I9XX(dev))
3293                 I915_WRITE(CURSIZE, (height << 12) | width);
3294
3295         /* Hooray for CUR*CNTR differences */
3296         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3297                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3298                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3299                 temp |= (pipe << 28); /* Connect to correct pipe */
3300         } else {
3301                 temp &= ~(CURSOR_FORMAT_MASK);
3302                 temp |= CURSOR_ENABLE;
3303                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3304         }
3305
3306  finish:
3307         I915_WRITE(control, temp);
3308         I915_WRITE(base, addr);
3309
3310         if (intel_crtc->cursor_bo) {
3311                 if (dev_priv->cursor_needs_physical) {
3312                         if (intel_crtc->cursor_bo != bo)
3313                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3314                 } else
3315                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3316                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3317         }
3318
3319         mutex_unlock(&dev->struct_mutex);
3320
3321         intel_crtc->cursor_addr = addr;
3322         intel_crtc->cursor_bo = bo;
3323
3324         return 0;
3325 fail:
3326         mutex_lock(&dev->struct_mutex);
3327 fail_locked:
3328         drm_gem_object_unreference(bo);
3329         mutex_unlock(&dev->struct_mutex);
3330         return ret;
3331 }
3332
3333 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3334 {
3335         struct drm_device *dev = crtc->dev;
3336         struct drm_i915_private *dev_priv = dev->dev_private;
3337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338         struct intel_framebuffer *intel_fb;
3339         int pipe = intel_crtc->pipe;
3340         uint32_t temp = 0;
3341         uint32_t adder;
3342
3343         if (crtc->fb) {
3344                 intel_fb = to_intel_framebuffer(crtc->fb);
3345                 intel_mark_busy(dev, intel_fb->obj);
3346         }
3347
3348         if (x < 0) {
3349                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3350                 x = -x;
3351         }
3352         if (y < 0) {
3353                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3354                 y = -y;
3355         }
3356
3357         temp |= x << CURSOR_X_SHIFT;
3358         temp |= y << CURSOR_Y_SHIFT;
3359
3360         adder = intel_crtc->cursor_addr;
3361         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3362         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3363
3364         return 0;
3365 }
3366
3367 /** Sets the color ramps on behalf of RandR */
3368 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3369                                  u16 blue, int regno)
3370 {
3371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3372
3373         intel_crtc->lut_r[regno] = red >> 8;
3374         intel_crtc->lut_g[regno] = green >> 8;
3375         intel_crtc->lut_b[regno] = blue >> 8;
3376 }
3377
3378 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3379                              u16 *blue, int regno)
3380 {
3381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382
3383         *red = intel_crtc->lut_r[regno] << 8;
3384         *green = intel_crtc->lut_g[regno] << 8;
3385         *blue = intel_crtc->lut_b[regno] << 8;
3386 }
3387
3388 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3389                                  u16 *blue, uint32_t size)
3390 {
3391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392         int i;
3393
3394         if (size != 256)
3395                 return;
3396
3397         for (i = 0; i < 256; i++) {
3398                 intel_crtc->lut_r[i] = red[i] >> 8;
3399                 intel_crtc->lut_g[i] = green[i] >> 8;
3400                 intel_crtc->lut_b[i] = blue[i] >> 8;
3401         }
3402
3403         intel_crtc_load_lut(crtc);
3404 }
3405
3406 /**
3407  * Get a pipe with a simple mode set on it for doing load-based monitor
3408  * detection.
3409  *
3410  * It will be up to the load-detect code to adjust the pipe as appropriate for
3411  * its requirements.  The pipe will be connected to no other outputs.
3412  *
3413  * Currently this code will only succeed if there is a pipe with no outputs
3414  * configured for it.  In the future, it could choose to temporarily disable
3415  * some outputs to free up a pipe for its use.
3416  *
3417  * \return crtc, or NULL if no pipes are available.
3418  */
3419
3420 /* VESA 640x480x72Hz mode to set on the pipe */
3421 static struct drm_display_mode load_detect_mode = {
3422         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3423                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3424 };
3425
3426 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3427                                             struct drm_display_mode *mode,
3428                                             int *dpms_mode)
3429 {
3430         struct intel_crtc *intel_crtc;
3431         struct drm_crtc *possible_crtc;
3432         struct drm_crtc *supported_crtc =NULL;
3433         struct drm_encoder *encoder = &intel_output->enc;
3434         struct drm_crtc *crtc = NULL;
3435         struct drm_device *dev = encoder->dev;
3436         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3437         struct drm_crtc_helper_funcs *crtc_funcs;
3438         int i = -1;
3439
3440         /*
3441          * Algorithm gets a little messy:
3442          *   - if the connector already has an assigned crtc, use it (but make
3443          *     sure it's on first)
3444          *   - try to find the first unused crtc that can drive this connector,
3445          *     and use that if we find one
3446          *   - if there are no unused crtcs available, try to use the first
3447          *     one we found that supports the connector
3448          */
3449
3450         /* See if we already have a CRTC for this connector */
3451         if (encoder->crtc) {
3452                 crtc = encoder->crtc;
3453                 /* Make sure the crtc and connector are running */
3454                 intel_crtc = to_intel_crtc(crtc);
3455                 *dpms_mode = intel_crtc->dpms_mode;
3456                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3457                         crtc_funcs = crtc->helper_private;
3458                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3459                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3460                 }
3461                 return crtc;
3462         }
3463
3464         /* Find an unused one (if possible) */
3465         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3466                 i++;
3467                 if (!(encoder->possible_crtcs & (1 << i)))
3468                         continue;
3469                 if (!possible_crtc->enabled) {
3470                         crtc = possible_crtc;
3471                         break;
3472                 }
3473                 if (!supported_crtc)
3474                         supported_crtc = possible_crtc;
3475         }
3476
3477         /*
3478          * If we didn't find an unused CRTC, don't use any.
3479          */
3480         if (!crtc) {
3481                 return NULL;
3482         }
3483
3484         encoder->crtc = crtc;
3485         intel_output->base.encoder = encoder;
3486         intel_output->load_detect_temp = true;
3487
3488         intel_crtc = to_intel_crtc(crtc);
3489         *dpms_mode = intel_crtc->dpms_mode;
3490
3491         if (!crtc->enabled) {
3492                 if (!mode)
3493                         mode = &load_detect_mode;
3494                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3495         } else {
3496                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3497                         crtc_funcs = crtc->helper_private;
3498                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3499                 }
3500
3501                 /* Add this connector to the crtc */
3502                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3503                 encoder_funcs->commit(encoder);
3504         }
3505         /* let the connector get through one full cycle before testing */
3506         intel_wait_for_vblank(dev);
3507
3508         return crtc;
3509 }
3510
3511 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3512 {
3513         struct drm_encoder *encoder = &intel_output->enc;
3514         struct drm_device *dev = encoder->dev;
3515         struct drm_crtc *crtc = encoder->crtc;
3516         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3517         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3518
3519         if (intel_output->load_detect_temp) {
3520                 encoder->crtc = NULL;
3521                 intel_output->base.encoder = NULL;
3522                 intel_output->load_detect_temp = false;
3523                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3524                 drm_helper_disable_unused_functions(dev);
3525         }
3526
3527         /* Switch crtc and output back off if necessary */
3528         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3529                 if (encoder->crtc == crtc)
3530                         encoder_funcs->dpms(encoder, dpms_mode);
3531                 crtc_funcs->dpms(crtc, dpms_mode);
3532         }
3533 }
3534
3535 /* Returns the clock of the currently programmed mode of the given pipe. */
3536 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3537 {
3538         struct drm_i915_private *dev_priv = dev->dev_private;
3539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3540         int pipe = intel_crtc->pipe;
3541         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3542         u32 fp;
3543         intel_clock_t clock;
3544
3545         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3546                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3547         else
3548                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3549
3550         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3551         if (IS_IGD(dev)) {
3552                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3553                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3554         } else {
3555                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3556                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3557         }
3558
3559         if (IS_I9XX(dev)) {
3560                 if (IS_IGD(dev))
3561                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3562                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3563                 else
3564                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3565                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3566
3567                 switch (dpll & DPLL_MODE_MASK) {
3568                 case DPLLB_MODE_DAC_SERIAL:
3569                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3570                                 5 : 10;
3571                         break;
3572                 case DPLLB_MODE_LVDS:
3573                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3574                                 7 : 14;
3575                         break;
3576                 default:
3577                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3578                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3579                         return 0;
3580                 }
3581
3582                 /* XXX: Handle the 100Mhz refclk */
3583                 intel_clock(dev, 96000, &clock);
3584         } else {
3585                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3586
3587                 if (is_lvds) {
3588                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3589                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3590                         clock.p2 = 14;
3591
3592                         if ((dpll & PLL_REF_INPUT_MASK) ==
3593                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3594                                 /* XXX: might not be 66MHz */
3595                                 intel_clock(dev, 66000, &clock);
3596                         } else
3597                                 intel_clock(dev, 48000, &clock);
3598                 } else {
3599                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3600                                 clock.p1 = 2;
3601                         else {
3602                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3603                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3604                         }
3605                         if (dpll & PLL_P2_DIVIDE_BY_4)
3606                                 clock.p2 = 4;
3607                         else
3608                                 clock.p2 = 2;
3609
3610                         intel_clock(dev, 48000, &clock);
3611                 }
3612         }
3613
3614         /* XXX: It would be nice to validate the clocks, but we can't reuse
3615          * i830PllIsValid() because it relies on the xf86_config connector
3616          * configuration being accurate, which it isn't necessarily.
3617          */
3618
3619         return clock.dot;
3620 }
3621
3622 /** Returns the currently programmed mode of the given pipe. */
3623 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3624                                              struct drm_crtc *crtc)
3625 {
3626         struct drm_i915_private *dev_priv = dev->dev_private;
3627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628         int pipe = intel_crtc->pipe;
3629         struct drm_display_mode *mode;
3630         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3631         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3632         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3633         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3634
3635         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3636         if (!mode)
3637                 return NULL;
3638
3639         mode->clock = intel_crtc_clock_get(dev, crtc);
3640         mode->hdisplay = (htot & 0xffff) + 1;
3641         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3642         mode->hsync_start = (hsync & 0xffff) + 1;
3643         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3644         mode->vdisplay = (vtot & 0xffff) + 1;
3645         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3646         mode->vsync_start = (vsync & 0xffff) + 1;
3647         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3648
3649         drm_mode_set_name(mode);
3650         drm_mode_set_crtcinfo(mode, 0);
3651
3652         return mode;
3653 }
3654
3655 #define GPU_IDLE_TIMEOUT 500 /* ms */
3656
3657 /* When this timer fires, we've been idle for awhile */
3658 static void intel_gpu_idle_timer(unsigned long arg)
3659 {
3660         struct drm_device *dev = (struct drm_device *)arg;
3661         drm_i915_private_t *dev_priv = dev->dev_private;
3662
3663         DRM_DEBUG("idle timer fired, downclocking\n");
3664
3665         dev_priv->busy = false;
3666
3667         queue_work(dev_priv->wq, &dev_priv->idle_work);
3668 }
3669
3670 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3671 {
3672         drm_i915_private_t *dev_priv = dev->dev_private;
3673
3674         if (IS_IGDNG(dev))
3675                 return;
3676
3677         if (!dev_priv->render_reclock_avail) {
3678                 DRM_DEBUG("not reclocking render clock\n");
3679                 return;
3680         }
3681
3682         /* Restore render clock frequency to original value */
3683         if (IS_G4X(dev) || IS_I9XX(dev))
3684                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3685         else if (IS_I85X(dev))
3686                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3687         DRM_DEBUG("increasing render clock frequency\n");
3688
3689         /* Schedule downclock */
3690         if (schedule)
3691                 mod_timer(&dev_priv->idle_timer, jiffies +
3692                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3693 }
3694
3695 void intel_decrease_renderclock(struct drm_device *dev)
3696 {
3697         drm_i915_private_t *dev_priv = dev->dev_private;
3698
3699         if (IS_IGDNG(dev))
3700                 return;
3701
3702         if (!dev_priv->render_reclock_avail) {
3703                 DRM_DEBUG("not reclocking render clock\n");
3704                 return;
3705         }
3706
3707         if (IS_G4X(dev)) {
3708                 u16 gcfgc;
3709
3710                 /* Adjust render clock... */
3711                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3712
3713                 /* Down to minimum... */
3714                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3715                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3716
3717                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3718         } else if (IS_I965G(dev)) {
3719                 u16 gcfgc;
3720
3721                 /* Adjust render clock... */
3722                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3723
3724                 /* Down to minimum... */
3725                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3726                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3727
3728                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3729         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3730                 u16 gcfgc;
3731
3732                 /* Adjust render clock... */
3733                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3734
3735                 /* Down to minimum... */
3736                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3737                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3738
3739                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3740         } else if (IS_I915G(dev)) {
3741                 u16 gcfgc;
3742
3743                 /* Adjust render clock... */
3744                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3745
3746                 /* Down to minimum... */
3747                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3748                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3749
3750                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3751         } else if (IS_I85X(dev)) {
3752                 u16 hpllcc;
3753
3754                 /* Adjust render clock... */
3755                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3756
3757                 /* Up to maximum... */
3758                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3759                 hpllcc |= GC_CLOCK_133_200;
3760
3761                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3762         }
3763         DRM_DEBUG("decreasing render clock frequency\n");
3764 }
3765
3766 /* Note that no increase function is needed for this - increase_renderclock()
3767  *  will also rewrite these bits
3768  */
3769 void intel_decrease_displayclock(struct drm_device *dev)
3770 {
3771         if (IS_IGDNG(dev))
3772                 return;
3773
3774         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3775             IS_I915GM(dev)) {
3776                 u16 gcfgc;
3777
3778                 /* Adjust render clock... */
3779                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3780
3781                 /* Down to minimum... */
3782                 gcfgc &= ~0xf0;
3783                 gcfgc |= 0x80;
3784
3785                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3786         }
3787 }
3788
3789 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3790
3791 static void intel_crtc_idle_timer(unsigned long arg)
3792 {
3793         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3794         struct drm_crtc *crtc = &intel_crtc->base;
3795         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3796
3797         DRM_DEBUG("idle timer fired, downclocking\n");
3798
3799         intel_crtc->busy = false;
3800
3801         queue_work(dev_priv->wq, &dev_priv->idle_work);
3802 }
3803
3804 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3805 {
3806         struct drm_device *dev = crtc->dev;
3807         drm_i915_private_t *dev_priv = dev->dev_private;
3808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3809         int pipe = intel_crtc->pipe;
3810         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3811         int dpll = I915_READ(dpll_reg);
3812
3813         if (IS_IGDNG(dev))
3814                 return;
3815
3816         if (!dev_priv->lvds_downclock_avail)
3817                 return;
3818
3819         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3820                 DRM_DEBUG("upclocking LVDS\n");
3821
3822                 /* Unlock panel regs */
3823                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3824
3825                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3826                 I915_WRITE(dpll_reg, dpll);
3827                 dpll = I915_READ(dpll_reg);
3828                 intel_wait_for_vblank(dev);
3829                 dpll = I915_READ(dpll_reg);
3830                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3831                         DRM_DEBUG("failed to upclock LVDS!\n");
3832
3833                 /* ...and lock them again */
3834                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3835         }
3836
3837         /* Schedule downclock */
3838         if (schedule)
3839                 mod_timer(&intel_crtc->idle_timer, jiffies +
3840                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3841 }
3842
3843 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3844 {
3845         struct drm_device *dev = crtc->dev;
3846         drm_i915_private_t *dev_priv = dev->dev_private;
3847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3848         int pipe = intel_crtc->pipe;
3849         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3850         int dpll = I915_READ(dpll_reg);
3851
3852         if (IS_IGDNG(dev))
3853                 return;
3854
3855         if (!dev_priv->lvds_downclock_avail)
3856                 return;
3857
3858         /*
3859          * Since this is called by a timer, we should never get here in
3860          * the manual case.
3861          */
3862         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3863                 DRM_DEBUG("downclocking LVDS\n");
3864
3865                 /* Unlock panel regs */
3866                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3867
3868                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3869                 I915_WRITE(dpll_reg, dpll);
3870                 dpll = I915_READ(dpll_reg);
3871                 intel_wait_for_vblank(dev);
3872                 dpll = I915_READ(dpll_reg);
3873                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3874                         DRM_DEBUG("failed to downclock LVDS!\n");
3875
3876                 /* ...and lock them again */
3877                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3878         }
3879
3880 }
3881
3882 /**
3883  * intel_idle_update - adjust clocks for idleness
3884  * @work: work struct
3885  *
3886  * Either the GPU or display (or both) went idle.  Check the busy status
3887  * here and adjust the CRTC and GPU clocks as necessary.
3888  */
3889 static void intel_idle_update(struct work_struct *work)
3890 {
3891         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3892                                                     idle_work);
3893         struct drm_device *dev = dev_priv->dev;
3894         struct drm_crtc *crtc;
3895         struct intel_crtc *intel_crtc;
3896
3897         if (!i915_powersave)
3898                 return;
3899
3900         mutex_lock(&dev->struct_mutex);
3901
3902         /* GPU isn't processing, downclock it. */
3903         if (!dev_priv->busy) {
3904                 intel_decrease_renderclock(dev);
3905                 intel_decrease_displayclock(dev);
3906         }
3907
3908         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3909                 /* Skip inactive CRTCs */
3910                 if (!crtc->fb)
3911                         continue;
3912
3913                 intel_crtc = to_intel_crtc(crtc);
3914                 if (!intel_crtc->busy)
3915                         intel_decrease_pllclock(crtc);
3916         }
3917
3918         mutex_unlock(&dev->struct_mutex);
3919 }
3920
3921 /**
3922  * intel_mark_busy - mark the GPU and possibly the display busy
3923  * @dev: drm device
3924  * @obj: object we're operating on
3925  *
3926  * Callers can use this function to indicate that the GPU is busy processing
3927  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3928  * buffer), we'll also mark the display as busy, so we know to increase its
3929  * clock frequency.
3930  */
3931 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3932 {
3933         drm_i915_private_t *dev_priv = dev->dev_private;
3934         struct drm_crtc *crtc = NULL;
3935         struct intel_framebuffer *intel_fb;
3936         struct intel_crtc *intel_crtc;
3937
3938         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3939                 return;
3940
3941         dev_priv->busy = true;
3942         intel_increase_renderclock(dev, true);
3943
3944         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3945                 if (!crtc->fb)
3946                         continue;
3947
3948                 intel_crtc = to_intel_crtc(crtc);
3949                 intel_fb = to_intel_framebuffer(crtc->fb);
3950                 if (intel_fb->obj == obj) {
3951                         if (!intel_crtc->busy) {
3952                                 /* Non-busy -> busy, upclock */
3953                                 intel_increase_pllclock(crtc, true);
3954                                 intel_crtc->busy = true;
3955                         } else {
3956                                 /* Busy -> busy, put off timer */
3957                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3958                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3959                         }
3960                 }
3961         }
3962 }
3963
3964 static void intel_crtc_destroy(struct drm_crtc *crtc)
3965 {
3966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3967
3968         drm_crtc_cleanup(crtc);
3969         kfree(intel_crtc);
3970 }
3971
3972 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3973         .dpms = intel_crtc_dpms,
3974         .mode_fixup = intel_crtc_mode_fixup,
3975         .mode_set = intel_crtc_mode_set,
3976         .mode_set_base = intel_pipe_set_base,
3977         .prepare = intel_crtc_prepare,
3978         .commit = intel_crtc_commit,
3979         .load_lut = intel_crtc_load_lut,
3980 };
3981
3982 static const struct drm_crtc_funcs intel_crtc_funcs = {
3983         .cursor_set = intel_crtc_cursor_set,
3984         .cursor_move = intel_crtc_cursor_move,
3985         .gamma_set = intel_crtc_gamma_set,
3986         .set_config = drm_crtc_helper_set_config,
3987         .destroy = intel_crtc_destroy,
3988 };
3989
3990
3991 static void intel_crtc_init(struct drm_device *dev, int pipe)
3992 {
3993         struct intel_crtc *intel_crtc;
3994         int i;
3995
3996         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3997         if (intel_crtc == NULL)
3998                 return;
3999
4000         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4001
4002         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4003         intel_crtc->pipe = pipe;
4004         intel_crtc->plane = pipe;
4005         for (i = 0; i < 256; i++) {
4006                 intel_crtc->lut_r[i] = i;
4007                 intel_crtc->lut_g[i] = i;
4008                 intel_crtc->lut_b[i] = i;
4009         }
4010
4011         /* Swap pipes & planes for FBC on pre-965 */
4012         intel_crtc->pipe = pipe;
4013         intel_crtc->plane = pipe;
4014         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4015                 DRM_DEBUG("swapping pipes & planes for FBC\n");
4016                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4017         }
4018
4019         intel_crtc->cursor_addr = 0;
4020         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4021         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4022
4023         intel_crtc->busy = false;
4024
4025         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4026                     (unsigned long)intel_crtc);
4027 }
4028
4029 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4030                                 struct drm_file *file_priv)
4031 {
4032         drm_i915_private_t *dev_priv = dev->dev_private;
4033         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4034         struct drm_mode_object *drmmode_obj;
4035         struct intel_crtc *crtc;
4036
4037         if (!dev_priv) {
4038                 DRM_ERROR("called with no initialization\n");
4039                 return -EINVAL;
4040         }
4041
4042         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4043                         DRM_MODE_OBJECT_CRTC);
4044
4045         if (!drmmode_obj) {
4046                 DRM_ERROR("no such CRTC id\n");
4047                 return -EINVAL;
4048         }
4049
4050         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4051         pipe_from_crtc_id->pipe = crtc->pipe;
4052
4053         return 0;
4054 }
4055
4056 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4057 {
4058         struct drm_crtc *crtc = NULL;
4059
4060         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4061                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4062                 if (intel_crtc->pipe == pipe)
4063                         break;
4064         }
4065         return crtc;
4066 }
4067
4068 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4069 {
4070         int index_mask = 0;
4071         struct drm_connector *connector;
4072         int entry = 0;
4073
4074         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4075                 struct intel_output *intel_output = to_intel_output(connector);
4076                 if (type_mask & intel_output->clone_mask)
4077                         index_mask |= (1 << entry);
4078                 entry++;
4079         }
4080         return index_mask;
4081 }
4082
4083
4084 static void intel_setup_outputs(struct drm_device *dev)
4085 {
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct drm_connector *connector;
4088
4089         intel_crt_init(dev);
4090
4091         /* Set up integrated LVDS */
4092         if (IS_MOBILE(dev) && !IS_I830(dev))
4093                 intel_lvds_init(dev);
4094
4095         if (IS_IGDNG(dev)) {
4096                 int found;
4097
4098                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4099                         intel_dp_init(dev, DP_A);
4100
4101                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4102                         /* check SDVOB */
4103                         /* found = intel_sdvo_init(dev, HDMIB); */
4104                         found = 0;
4105                         if (!found)
4106                                 intel_hdmi_init(dev, HDMIB);
4107                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4108                                 intel_dp_init(dev, PCH_DP_B);
4109                 }
4110
4111                 if (I915_READ(HDMIC) & PORT_DETECTED)
4112                         intel_hdmi_init(dev, HDMIC);
4113
4114                 if (I915_READ(HDMID) & PORT_DETECTED)
4115                         intel_hdmi_init(dev, HDMID);
4116
4117                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4118                         intel_dp_init(dev, PCH_DP_C);
4119
4120                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4121                         intel_dp_init(dev, PCH_DP_D);
4122
4123         } else if (IS_I9XX(dev)) {
4124                 bool found = false;
4125
4126                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4127                         found = intel_sdvo_init(dev, SDVOB);
4128                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4129                                 intel_hdmi_init(dev, SDVOB);
4130
4131                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
4132                                 intel_dp_init(dev, DP_B);
4133                 }
4134
4135                 /* Before G4X SDVOC doesn't have its own detect register */
4136
4137                 if (I915_READ(SDVOB) & SDVO_DETECTED)
4138                         found = intel_sdvo_init(dev, SDVOC);
4139
4140                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4141
4142                         if (SUPPORTS_INTEGRATED_HDMI(dev))
4143                                 intel_hdmi_init(dev, SDVOC);
4144                         if (SUPPORTS_INTEGRATED_DP(dev))
4145                                 intel_dp_init(dev, DP_C);
4146                 }
4147
4148                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4149                         intel_dp_init(dev, DP_D);
4150         } else
4151                 intel_dvo_init(dev);
4152
4153         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
4154                 intel_tv_init(dev);
4155
4156         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4157                 struct intel_output *intel_output = to_intel_output(connector);
4158                 struct drm_encoder *encoder = &intel_output->enc;
4159
4160                 encoder->possible_crtcs = intel_output->crtc_mask;
4161                 encoder->possible_clones = intel_connector_clones(dev,
4162                                                 intel_output->clone_mask);
4163         }
4164 }
4165
4166 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4167 {
4168         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4169         struct drm_device *dev = fb->dev;
4170
4171         if (fb->fbdev)
4172                 intelfb_remove(dev, fb);
4173
4174         drm_framebuffer_cleanup(fb);
4175         mutex_lock(&dev->struct_mutex);
4176         drm_gem_object_unreference(intel_fb->obj);
4177         mutex_unlock(&dev->struct_mutex);
4178
4179         kfree(intel_fb);
4180 }
4181
4182 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4183                                                 struct drm_file *file_priv,
4184                                                 unsigned int *handle)
4185 {
4186         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4187         struct drm_gem_object *object = intel_fb->obj;
4188
4189         return drm_gem_handle_create(file_priv, object, handle);
4190 }
4191
4192 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4193         .destroy = intel_user_framebuffer_destroy,
4194         .create_handle = intel_user_framebuffer_create_handle,
4195 };
4196
4197 int intel_framebuffer_create(struct drm_device *dev,
4198                              struct drm_mode_fb_cmd *mode_cmd,
4199                              struct drm_framebuffer **fb,
4200                              struct drm_gem_object *obj)
4201 {
4202         struct intel_framebuffer *intel_fb;
4203         int ret;
4204
4205         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4206         if (!intel_fb)
4207                 return -ENOMEM;
4208
4209         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4210         if (ret) {
4211                 DRM_ERROR("framebuffer init failed %d\n", ret);
4212                 return ret;
4213         }
4214
4215         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4216
4217         intel_fb->obj = obj;
4218
4219         *fb = &intel_fb->base;
4220
4221         return 0;
4222 }
4223
4224
4225 static struct drm_framebuffer *
4226 intel_user_framebuffer_create(struct drm_device *dev,
4227                               struct drm_file *filp,
4228                               struct drm_mode_fb_cmd *mode_cmd)
4229 {
4230         struct drm_gem_object *obj;
4231         struct drm_framebuffer *fb;
4232         int ret;
4233
4234         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4235         if (!obj)
4236                 return NULL;
4237
4238         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4239         if (ret) {
4240                 mutex_lock(&dev->struct_mutex);
4241                 drm_gem_object_unreference(obj);
4242                 mutex_unlock(&dev->struct_mutex);
4243                 return NULL;
4244         }
4245
4246         return fb;
4247 }
4248
4249 static const struct drm_mode_config_funcs intel_mode_funcs = {
4250         .fb_create = intel_user_framebuffer_create,
4251         .fb_changed = intelfb_probe,
4252 };
4253
4254 void intel_init_clock_gating(struct drm_device *dev)
4255 {
4256         struct drm_i915_private *dev_priv = dev->dev_private;
4257
4258         /*
4259          * Disable clock gating reported to work incorrectly according to the
4260          * specs, but enable as much else as we can.
4261          */
4262         if (IS_IGDNG(dev)) {
4263                 return;
4264         } else if (IS_G4X(dev)) {
4265                 uint32_t dspclk_gate;
4266                 I915_WRITE(RENCLK_GATE_D1, 0);
4267                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4268                        GS_UNIT_CLOCK_GATE_DISABLE |
4269                        CL_UNIT_CLOCK_GATE_DISABLE);
4270                 I915_WRITE(RAMCLK_GATE_D, 0);
4271                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4272                         OVRUNIT_CLOCK_GATE_DISABLE |
4273                         OVCUNIT_CLOCK_GATE_DISABLE;
4274                 if (IS_GM45(dev))
4275                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4276                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4277         } else if (IS_I965GM(dev)) {
4278                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4279                 I915_WRITE(RENCLK_GATE_D2, 0);
4280                 I915_WRITE(DSPCLK_GATE_D, 0);
4281                 I915_WRITE(RAMCLK_GATE_D, 0);
4282                 I915_WRITE16(DEUC, 0);
4283         } else if (IS_I965G(dev)) {
4284                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4285                        I965_RCC_CLOCK_GATE_DISABLE |
4286                        I965_RCPB_CLOCK_GATE_DISABLE |
4287                        I965_ISC_CLOCK_GATE_DISABLE |
4288                        I965_FBC_CLOCK_GATE_DISABLE);
4289                 I915_WRITE(RENCLK_GATE_D2, 0);
4290         } else if (IS_I9XX(dev)) {
4291                 u32 dstate = I915_READ(D_STATE);
4292
4293                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4294                         DSTATE_DOT_CLOCK_GATING;
4295                 I915_WRITE(D_STATE, dstate);
4296         } else if (IS_I855(dev) || IS_I865G(dev)) {
4297                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4298         } else if (IS_I830(dev)) {
4299                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4300         }
4301 }
4302
4303 /* Set up chip specific display functions */
4304 static void intel_init_display(struct drm_device *dev)
4305 {
4306         struct drm_i915_private *dev_priv = dev->dev_private;
4307
4308         /* We always want a DPMS function */
4309         if (IS_IGDNG(dev))
4310                 dev_priv->display.dpms = igdng_crtc_dpms;
4311         else
4312                 dev_priv->display.dpms = i9xx_crtc_dpms;
4313
4314         /* Only mobile has FBC, leave pointers NULL for other chips */
4315         if (IS_MOBILE(dev)) {
4316                 if (IS_GM45(dev)) {
4317                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4318                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4319                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4320                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4321                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4322                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4323                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4324                 }
4325                 /* 855GM needs testing */
4326         }
4327
4328         /* Returns the core display clock speed */
4329         if (IS_I945G(dev))
4330                 dev_priv->display.get_display_clock_speed =
4331                         i945_get_display_clock_speed;
4332         else if (IS_I915G(dev))
4333                 dev_priv->display.get_display_clock_speed =
4334                         i915_get_display_clock_speed;
4335         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4336                 dev_priv->display.get_display_clock_speed =
4337                         i9xx_misc_get_display_clock_speed;
4338         else if (IS_I915GM(dev))
4339                 dev_priv->display.get_display_clock_speed =
4340                         i915gm_get_display_clock_speed;
4341         else if (IS_I865G(dev))
4342                 dev_priv->display.get_display_clock_speed =
4343                         i865_get_display_clock_speed;
4344         else if (IS_I855(dev))
4345                 dev_priv->display.get_display_clock_speed =
4346                         i855_get_display_clock_speed;
4347         else /* 852, 830 */
4348                 dev_priv->display.get_display_clock_speed =
4349                         i830_get_display_clock_speed;
4350
4351         /* For FIFO watermark updates */
4352         if (IS_IGDNG(dev))
4353                 dev_priv->display.update_wm = NULL;
4354         else if (IS_G4X(dev))
4355                 dev_priv->display.update_wm = g4x_update_wm;
4356         else if (IS_I965G(dev))
4357                 dev_priv->display.update_wm = i965_update_wm;
4358         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4359                 dev_priv->display.update_wm = i9xx_update_wm;
4360                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4361         } else {
4362                 if (IS_I85X(dev))
4363                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4364                 else if (IS_845G(dev))
4365                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4366                 else
4367                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4368                 dev_priv->display.update_wm = i830_update_wm;
4369         }
4370 }
4371
4372 void intel_modeset_init(struct drm_device *dev)
4373 {
4374         struct drm_i915_private *dev_priv = dev->dev_private;
4375         int num_pipe;
4376         int i;
4377
4378         drm_mode_config_init(dev);
4379
4380         dev->mode_config.min_width = 0;
4381         dev->mode_config.min_height = 0;
4382
4383         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4384
4385         intel_init_display(dev);
4386
4387         if (IS_I965G(dev)) {
4388                 dev->mode_config.max_width = 8192;
4389                 dev->mode_config.max_height = 8192;
4390         } else if (IS_I9XX(dev)) {
4391                 dev->mode_config.max_width = 4096;
4392                 dev->mode_config.max_height = 4096;
4393         } else {
4394                 dev->mode_config.max_width = 2048;
4395                 dev->mode_config.max_height = 2048;
4396         }
4397
4398         /* set memory base */
4399         if (IS_I9XX(dev))
4400                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4401         else
4402                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4403
4404         if (IS_MOBILE(dev) || IS_I9XX(dev))
4405                 num_pipe = 2;
4406         else
4407                 num_pipe = 1;
4408         DRM_DEBUG("%d display pipe%s available.\n",
4409                   num_pipe, num_pipe > 1 ? "s" : "");
4410
4411         if (IS_I85X(dev))
4412                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4413         else if (IS_I9XX(dev) || IS_G4X(dev))
4414                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4415
4416         for (i = 0; i < num_pipe; i++) {
4417                 intel_crtc_init(dev, i);
4418         }
4419
4420         intel_setup_outputs(dev);
4421
4422         intel_init_clock_gating(dev);
4423
4424         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4425         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4426                     (unsigned long)dev);
4427 }
4428
4429 void intel_modeset_cleanup(struct drm_device *dev)
4430 {
4431         struct drm_i915_private *dev_priv = dev->dev_private;
4432         struct drm_crtc *crtc;
4433         struct intel_crtc *intel_crtc;
4434
4435         mutex_lock(&dev->struct_mutex);
4436
4437         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4438                 /* Skip inactive CRTCs */
4439                 if (!crtc->fb)
4440                         continue;
4441
4442                 intel_crtc = to_intel_crtc(crtc);
4443                 intel_increase_pllclock(crtc, false);
4444                 del_timer_sync(&intel_crtc->idle_timer);
4445         }
4446
4447         intel_increase_renderclock(dev, false);
4448         del_timer_sync(&dev_priv->idle_timer);
4449
4450         mutex_unlock(&dev->struct_mutex);
4451
4452         if (dev_priv->display.disable_fbc)
4453                 dev_priv->display.disable_fbc(dev);
4454
4455         drm_mode_config_cleanup(dev);
4456 }
4457
4458
4459 /* current intel driver doesn't take advantage of encoders
4460    always give back the encoder for the connector
4461 */
4462 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4463 {
4464         struct intel_output *intel_output = to_intel_output(connector);
4465
4466         return &intel_output->enc;
4467 }
4468
4469 /*
4470  * set vga decode state - true == enable VGA decode
4471  */
4472 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4473 {
4474         struct drm_i915_private *dev_priv = dev->dev_private;
4475         u16 gmch_ctrl;
4476
4477         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4478         if (state)
4479                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4480         else
4481                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4482         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4483         return 0;
4484 }