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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include "drmP.h"
  29 #include "intel_drv.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "intel_dp.h"
  33
  34 #include "drm_crtc_helper.h"
  35
  36 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  37
  38 typedef struct {
  39     /* given values */
  40     int n;
  41     int m1, m2;
  42     int p1, p2;
  43     /* derived values */
  44     int dot;
  45     int vco;
  46     int m;
  47     int p;
  48 } intel_clock_t;
  49
  50 typedef struct {
  51     int min, max;
  52 } intel_range_t;
  53
  54 typedef struct {
  55     int dot_limit;
  56     int p2_slow, p2_fast;
  57 } intel_p2_t;
  58
  59 #define INTEL_P2_NUM                  2
  60 typedef struct intel_limit intel_limit_t;
  61 struct intel_limit {
  62     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  63     intel_p2_t      p2;
  64     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  65                       int, int, intel_clock_t *);
  66 };
  67
  68 #define I8XX_DOT_MIN              25000
  69 #define I8XX_DOT_MAX             350000
  70 #define I8XX_VCO_MIN             930000
  71 #define I8XX_VCO_MAX            1400000
  72 #define I8XX_N_MIN                    3
  73 #define I8XX_N_MAX                   16
  74 #define I8XX_M_MIN                   96
  75 #define I8XX_M_MAX                  140
  76 #define I8XX_M1_MIN                  18
  77 #define I8XX_M1_MAX                  26
  78 #define I8XX_M2_MIN                   6
  79 #define I8XX_M2_MAX                  16
  80 #define I8XX_P_MIN                    4
  81 #define I8XX_P_MAX                  128
  82 #define I8XX_P1_MIN                   2
  83 #define I8XX_P1_MAX                  33
  84 #define I8XX_P1_LVDS_MIN              1
  85 #define I8XX_P1_LVDS_MAX              6
  86 #define I8XX_P2_SLOW                  4
  87 #define I8XX_P2_FAST                  2
  88 #define I8XX_P2_LVDS_SLOW             14
  89 #define I8XX_P2_LVDS_FAST             14 /* No fast option */
  90 #define I8XX_P2_SLOW_LIMIT       165000
  91
  92 #define I9XX_DOT_MIN              20000
  93 #define I9XX_DOT_MAX             400000
  94 #define I9XX_VCO_MIN            1400000
  95 #define I9XX_VCO_MAX            2800000
  96 #define IGD_VCO_MIN             1700000
  97 #define IGD_VCO_MAX             3500000
  98 #define I9XX_N_MIN                    1
  99 #define I9XX_N_MAX                    6
 100 /* IGD's Ncounter is a ring counter */
 101 #define IGD_N_MIN                     3
 102 #define IGD_N_MAX                     6
 103 #define I9XX_M_MIN                   70
 104 #define I9XX_M_MAX                  120
 105 #define IGD_M_MIN                     2
 106 #define IGD_M_MAX                   256
 107 #define I9XX_M1_MIN                  10
 108 #define I9XX_M1_MAX                  22
 109 #define I9XX_M2_MIN                   5
 110 #define I9XX_M2_MAX                   9
 111 /* IGD M1 is reserved, and must be 0 */
 112 #define IGD_M1_MIN                    0
 113 #define IGD_M1_MAX                    0
 114 #define IGD_M2_MIN                    0
 115 #define IGD_M2_MAX                    254
 116 #define I9XX_P_SDVO_DAC_MIN           5
 117 #define I9XX_P_SDVO_DAC_MAX          80
 118 #define I9XX_P_LVDS_MIN               7
 119 #define I9XX_P_LVDS_MAX              98
 120 #define IGD_P_LVDS_MIN                7
 121 #define IGD_P_LVDS_MAX               112
 122 #define I9XX_P1_MIN                   1
 123 #define I9XX_P1_MAX                   8
 124 #define I9XX_P2_SDVO_DAC_SLOW                10
 125 #define I9XX_P2_SDVO_DAC_FAST                 5
 126 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 127 #define I9XX_P2_LVDS_SLOW                    14
 128 #define I9XX_P2_LVDS_FAST                     7
 129 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 130
 131 #define INTEL_LIMIT_I8XX_DVO_DAC    0
 132 #define INTEL_LIMIT_I8XX_LVDS       1
 133 #define INTEL_LIMIT_I9XX_SDVO_DAC   2
 134 #define INTEL_LIMIT_I9XX_LVDS       3
 135 #define INTEL_LIMIT_G4X_SDVO        4
 136 #define INTEL_LIMIT_G4X_HDMI_DAC   5
 137 #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS   6
 138 #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS   7
 139 #define INTEL_LIMIT_G4X_DISPLAY_PORT    8
 140 #define INTEL_LIMIT_IGD_SDVO_DAC    9
 141 #define INTEL_LIMIT_IGD_LVDS        10
 142 #define INTEL_LIMIT_IGDNG_SDVO_DAC  11
 143 #define INTEL_LIMIT_IGDNG_LVDS      12
 144
 145 /*The parameter is for SDVO on G4x platform*/
 146 #define G4X_DOT_SDVO_MIN           25000
 147 #define G4X_DOT_SDVO_MAX           270000
 148 #define G4X_VCO_MIN                1750000
 149 #define G4X_VCO_MAX                3500000
 150 #define G4X_N_SDVO_MIN             1
 151 #define G4X_N_SDVO_MAX             4
 152 #define G4X_M_SDVO_MIN             104
 153 #define G4X_M_SDVO_MAX             138
 154 #define G4X_M1_SDVO_MIN            17
 155 #define G4X_M1_SDVO_MAX            23
 156 #define G4X_M2_SDVO_MIN            5
 157 #define G4X_M2_SDVO_MAX            11
 158 #define G4X_P_SDVO_MIN             10
 159 #define G4X_P_SDVO_MAX             30
 160 #define G4X_P1_SDVO_MIN            1
 161 #define G4X_P1_SDVO_MAX            3
 162 #define G4X_P2_SDVO_SLOW           10
 163 #define G4X_P2_SDVO_FAST           10
 164 #define G4X_P2_SDVO_LIMIT          270000
 165
 166 /*The parameter is for HDMI_DAC on G4x platform*/
 167 #define G4X_DOT_HDMI_DAC_MIN           22000
 168 #define G4X_DOT_HDMI_DAC_MAX           400000
 169 #define G4X_N_HDMI_DAC_MIN             1
 170 #define G4X_N_HDMI_DAC_MAX             4
 171 #define G4X_M_HDMI_DAC_MIN             104
 172 #define G4X_M_HDMI_DAC_MAX             138
 173 #define G4X_M1_HDMI_DAC_MIN            16
 174 #define G4X_M1_HDMI_DAC_MAX            23
 175 #define G4X_M2_HDMI_DAC_MIN            5
 176 #define G4X_M2_HDMI_DAC_MAX            11
 177 #define G4X_P_HDMI_DAC_MIN             5
 178 #define G4X_P_HDMI_DAC_MAX             80
 179 #define G4X_P1_HDMI_DAC_MIN            1
 180 #define G4X_P1_HDMI_DAC_MAX            8
 181 #define G4X_P2_HDMI_DAC_SLOW           10
 182 #define G4X_P2_HDMI_DAC_FAST           5
 183 #define G4X_P2_HDMI_DAC_LIMIT          165000
 184
 185 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 186 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 187 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 188 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 189 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 190 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 191 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 192 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 193 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 194 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 195 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 196 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 197 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 198 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 199 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 200 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 201 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 202 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 203
 204 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 205 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 206 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 207 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 208 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 209 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 210 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 211 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 212 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 213 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 214 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 215 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 216 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 217 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 218 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 219 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 220 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 221 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 222
 223 /*The parameter is for DISPLAY PORT on G4x platform*/
 224 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 225 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 226 #define G4X_N_DISPLAY_PORT_MIN             1
 227 #define G4X_N_DISPLAY_PORT_MAX             2
 228 #define G4X_M_DISPLAY_PORT_MIN             97
 229 #define G4X_M_DISPLAY_PORT_MAX             108
 230 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 231 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 232 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 233 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 234 #define G4X_P_DISPLAY_PORT_MIN             10
 235 #define G4X_P_DISPLAY_PORT_MAX             20
 236 #define G4X_P1_DISPLAY_PORT_MIN            1
 237 #define G4X_P1_DISPLAY_PORT_MAX            2
 238 #define G4X_P2_DISPLAY_PORT_SLOW           10
 239 #define G4X_P2_DISPLAY_PORT_FAST           10
 240 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 241
 242 /* IGDNG */
 243 /* as we calculate clock using (register_value + 2) for
 244    N/M1/M2, so here the range value for them is (actual_value-2).
 245  */
 246 #define IGDNG_DOT_MIN         25000
 247 #define IGDNG_DOT_MAX         350000
 248 #define IGDNG_VCO_MIN         1760000
 249 #define IGDNG_VCO_MAX         3510000
 250 #define IGDNG_N_MIN           1
 251 #define IGDNG_N_MAX           5
 252 #define IGDNG_M_MIN           79
 253 #define IGDNG_M_MAX           118
 254 #define IGDNG_M1_MIN          12
 255 #define IGDNG_M1_MAX          23
 256 #define IGDNG_M2_MIN          5
 257 #define IGDNG_M2_MAX          9
 258 #define IGDNG_P_SDVO_DAC_MIN  5
 259 #define IGDNG_P_SDVO_DAC_MAX  80
 260 #define IGDNG_P_LVDS_MIN      28
 261 #define IGDNG_P_LVDS_MAX      112
 262 #define IGDNG_P1_MIN          1
 263 #define IGDNG_P1_MAX          8
 264 #define IGDNG_P2_SDVO_DAC_SLOW 10
 265 #define IGDNG_P2_SDVO_DAC_FAST 5
 266 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 267 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 268 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 269
 270 static bool
 271 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 272                     int target, int refclk, intel_clock_t *best_clock);
 273 static bool
 274 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 275                         int target, int refclk, intel_clock_t *best_clock);
 276 static bool
 277 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 278                         int target, int refclk, intel_clock_t *best_clock);
 279
 280 static bool
 281 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 282                       int target, int refclk, intel_clock_t *best_clock);
 283
 284 static const intel_limit_t intel_limits[] = {
 285     { /* INTEL_LIMIT_I8XX_DVO_DAC */
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297     },
 298     { /* INTEL_LIMIT_I8XX_LVDS */
 299         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 300         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 301         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 302         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 303         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 304         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 305         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 306         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 307         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 308                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 309         .find_pll = intel_find_best_PLL,
 310     },
 311     { /* INTEL_LIMIT_I9XX_SDVO_DAC */
 312         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 313         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 314         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 315         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 316         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 317         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 318         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 319         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 320         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 321                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 322         .find_pll = intel_find_best_PLL,
 323     },
 324     { /* INTEL_LIMIT_I9XX_LVDS */
 325         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 326         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 327         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 328         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 329         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 330         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 331         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 332         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 333         /* The single-channel range is 25-112Mhz, and dual-channel
 334          * is 80-224Mhz.  Prefer single channel as much as possible.
 335          */
 336         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 337                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 338         .find_pll = intel_find_best_PLL,
 339     },
 340     /* below parameter and function is for G4X Chipset Family*/
 341     { /* INTEL_LIMIT_G4X_SDVO */
 342         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 343         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 344         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 345         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 346         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 347         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 348         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 349         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 350         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 351                  .p2_slow = G4X_P2_SDVO_SLOW,
 352                  .p2_fast = G4X_P2_SDVO_FAST
 353         },
 354         .find_pll = intel_g4x_find_best_PLL,
 355     },
 356     { /* INTEL_LIMIT_G4X_HDMI_DAC */
 357         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 358         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 359         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 360         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 361         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 362         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 363         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 364         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 365         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 366                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 367                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 368         },
 369         .find_pll = intel_g4x_find_best_PLL,
 370     },
 371     { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
 372         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 373                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 374         .vco = { .min = G4X_VCO_MIN,
 375                  .max = G4X_VCO_MAX },
 376         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 377                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 378         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 379                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 380         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 381                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 382         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 383                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 384         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 386         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 387                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 388         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 389                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 390                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 391         },
 392         .find_pll = intel_g4x_find_best_PLL,
 393     },
 394     { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
 395         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 396                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 397         .vco = { .min = G4X_VCO_MIN,
 398                  .max = G4X_VCO_MAX },
 399         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 400                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 401         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 402                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 403         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 404                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 405         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 406                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 407         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 408                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 409         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 411         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 412                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 413                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 414         },
 415         .find_pll = intel_g4x_find_best_PLL,
 416     },
 417     {   /* INTEL_LIMIT_G4X_DISPLAY_PORT */
 418         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 419                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 420         .vco = { .min = G4X_VCO_MIN,
 421                  .max = G4X_VCO_MAX},
 422         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 423                  .max = G4X_N_DISPLAY_PORT_MAX },
 424         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 425                  .max = G4X_M_DISPLAY_PORT_MAX },
 426         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 427                  .max = G4X_M1_DISPLAY_PORT_MAX },
 428         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 429                  .max = G4X_M2_DISPLAY_PORT_MAX },
 430         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 431                  .max = G4X_P_DISPLAY_PORT_MAX },
 432         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 433                  .max = G4X_P1_DISPLAY_PORT_MAX},
 434         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 435                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 436                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 437         .find_pll = intel_find_pll_g4x_dp,
 438     },
 439     { /* INTEL_LIMIT_IGD_SDVO */
 440         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 441         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 442         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 443         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 444         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 445         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 446         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 447         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 448         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 449                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 450         .find_pll = intel_find_best_PLL,
 451     },
 452     { /* INTEL_LIMIT_IGD_LVDS */
 453         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 454         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 455         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 456         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 457         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 458         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 459         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 460         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 461         /* IGD only supports single-channel mode. */
 462         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 463                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 464         .find_pll = intel_find_best_PLL,
 465     },
 466     { /* INTEL_LIMIT_IGDNG_SDVO_DAC */
 467         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 468         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 469         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 470         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 471         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 472         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 473         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 474         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 475         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 476                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 477                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 478         .find_pll = intel_igdng_find_best_PLL,
 479     },
 480     { /* INTEL_LIMIT_IGDNG_LVDS */
 481         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 482         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 483         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 484         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 485         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 486         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 487         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 488         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 489         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 490                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 491                  .p2_fast = IGDNG_P2_LVDS_FAST },
 492         .find_pll = intel_igdng_find_best_PLL,
 493     },
 494 };
 495
 496 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 497 {
 498         const intel_limit_t *limit;
 499         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 500                 limit = &intel_limits[INTEL_LIMIT_IGDNG_LVDS];
 501         else
 502                 limit = &intel_limits[INTEL_LIMIT_IGDNG_SDVO_DAC];
 503
 504         return limit;
 505 }
 506
 507 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 508 {
 509         struct drm_device *dev = crtc->dev;
 510         struct drm_i915_private *dev_priv = dev->dev_private;
 511         const intel_limit_t *limit;
 512
 513         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 514                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 515                     LVDS_CLKB_POWER_UP)
 516                         /* LVDS with dual channel */
 517                         limit = &intel_limits
 518                                         [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS];
 519                 else
 520                         /* LVDS with dual channel */
 521                         limit = &intel_limits
 522                                         [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS];
 523         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 524                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 525                 limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
 526         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 527                 limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
 528         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 529                 limit = &intel_limits[INTEL_LIMIT_G4X_DISPLAY_PORT];
 530         } else /* The option is for other outputs */
 531                 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 532
 533         return limit;
 534 }
 535
 536 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 537 {
 538         struct drm_device *dev = crtc->dev;
 539         const intel_limit_t *limit;
 540
 541         if (IS_IGDNG(dev))
 542                 limit = intel_igdng_limit(crtc);
 543         else if (IS_G4X(dev)) {
 544                 limit = intel_g4x_limit(crtc);
 545         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 546                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 547                         limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
 548                 else
 549                         limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 550         } else if (IS_IGD(dev)) {
 551                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 552                         limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
 553                 else
 554                         limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
 555         } else {
 556                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 557                         limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
 558                 else
 559                         limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
 560         }
 561         return limit;
 562 }
 563
 564 /* m1 is reserved as 0 in IGD, n is a ring counter */
 565 static void igd_clock(int refclk, intel_clock_t *clock)
 566 {
 567         clock->m = clock->m2 + 2;
 568         clock->p = clock->p1 * clock->p2;
 569         clock->vco = refclk * clock->m / clock->n;
 570         clock->dot = clock->vco / clock->p;
 571 }
 572
 573 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 574 {
 575         if (IS_IGD(dev)) {
 576                 igd_clock(refclk, clock);
 577                 return;
 578         }
 579         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 580         clock->p = clock->p1 * clock->p2;
 581         clock->vco = refclk * clock->m / (clock->n + 2);
 582         clock->dot = clock->vco / clock->p;
 583 }
 584
 585 /**
 586  * Returns whether any output on the specified pipe is of the specified type
 587  */
 588 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 589 {
 590     struct drm_device *dev = crtc->dev;
 591     struct drm_mode_config *mode_config = &dev->mode_config;
 592     struct drm_connector *l_entry;
 593
 594     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 595             if (l_entry->encoder &&
 596                 l_entry->encoder->crtc == crtc) {
 597                     struct intel_output *intel_output = to_intel_output(l_entry);
 598                     if (intel_output->type == type)
 599                             return true;
 600             }
 601     }
 602     return false;
 603 }
 604
 605 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 606 /**
 607  * Returns whether the given set of divisors are valid for a given refclk with
 608  * the given connectors.
 609  */
 610
 611 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 612 {
 613         const intel_limit_t *limit = intel_limit (crtc);
 614         struct drm_device *dev = crtc->dev;
 615
 616         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 617                 INTELPllInvalid ("p1 out of range\n");
 618         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 619                 INTELPllInvalid ("p out of range\n");
 620         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 621                 INTELPllInvalid ("m2 out of range\n");
 622         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 623                 INTELPllInvalid ("m1 out of range\n");
 624         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 625                 INTELPllInvalid ("m1 <= m2\n");
 626         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 627                 INTELPllInvalid ("m out of range\n");
 628         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 629                 INTELPllInvalid ("n out of range\n");
 630         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 631                 INTELPllInvalid ("vco out of range\n");
 632         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 633          * connector, etc., rather than just a single range.
 634          */
 635         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 636                 INTELPllInvalid ("dot out of range\n");
 637
 638         return true;
 639 }
 640
 641 static bool
 642 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 643                     int target, int refclk, intel_clock_t *best_clock)
 644
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         struct drm_i915_private *dev_priv = dev->dev_private;
 648         intel_clock_t clock;
 649         int err = target;
 650
 651         if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 652             (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
 653                 /*
 654                  * For LVDS, if the panel is on, just rely on its current
 655                  * settings for dual-channel.  We haven't figured out how to
 656                  * reliably set up different single/dual channel state, if we
 657                  * even can.
 658                  */
 659                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 660                     LVDS_CLKB_POWER_UP)
 661                         clock.p2 = limit->p2.p2_fast;
 662                 else
 663                         clock.p2 = limit->p2.p2_slow;
 664         } else {
 665                 if (target < limit->p2.dot_limit)
 666                         clock.p2 = limit->p2.p2_slow;
 667                 else
 668                         clock.p2 = limit->p2.p2_fast;
 669         }
 670
 671         memset (best_clock, 0, sizeof (*best_clock));
 672
 673         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 674                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 675                         /* m1 is always 0 in IGD */
 676                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 677                                 break;
 678                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 679                              clock.n++) {
 680                                 for (clock.p1 = limit->p1.min;
 681                                      clock.p1 <= limit->p1.max; clock.p1++) {
 682                                         int this_err;
 683
 684                                         intel_clock(dev, refclk, &clock);
 685
 686                                         if (!intel_PLL_is_valid(crtc, &clock))
 687                                                 continue;
 688
 689                                         this_err = abs(clock.dot - target);
 690                                         if (this_err < err) {
 691                                                 *best_clock = clock;
 692                                                 err = this_err;
 693                                         }
 694                                 }
 695                         }
 696                 }
 697         }
 698
 699         return (err != target);
 700 }
 701
 702 static bool
 703 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 704                         int target, int refclk, intel_clock_t *best_clock)
 705 {
 706         struct drm_device *dev = crtc->dev;
 707         struct drm_i915_private *dev_priv = dev->dev_private;
 708         intel_clock_t clock;
 709         int max_n;
 710         bool found;
 711         /* approximately equals target * 0.00488 */
 712         int err_most = (target >> 8) + (target >> 10);
 713         found = false;
 714
 715         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 716                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 717                     LVDS_CLKB_POWER_UP)
 718                         clock.p2 = limit->p2.p2_fast;
 719                 else
 720                         clock.p2 = limit->p2.p2_slow;
 721         } else {
 722                 if (target < limit->p2.dot_limit)
 723                         clock.p2 = limit->p2.p2_slow;
 724                 else
 725                         clock.p2 = limit->p2.p2_fast;
 726         }
 727
 728         memset(best_clock, 0, sizeof(*best_clock));
 729         max_n = limit->n.max;
 730         /* based on hardware requriment prefer smaller n to precision */
 731         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 732                 /* based on hardware requirment prefere larger m1,m2, p1 */
 733                 for (clock.m1 = limit->m1.max;
 734                      clock.m1 >= limit->m1.min; clock.m1--) {
 735                         for (clock.m2 = limit->m2.max;
 736                              clock.m2 >= limit->m2.min; clock.m2--) {
 737                                 for (clock.p1 = limit->p1.max;
 738                                      clock.p1 >= limit->p1.min; clock.p1--) {
 739                                         int this_err;
 740
 741                                         intel_clock(dev, refclk, &clock);
 742                                         if (!intel_PLL_is_valid(crtc, &clock))
 743                                                 continue;
 744                                         this_err = abs(clock.dot - target) ;
 745                                         if (this_err < err_most) {
 746                                                 *best_clock = clock;
 747                                                 err_most = this_err;
 748                                                 max_n = clock.n;
 749                                                 found = true;
 750                                         }
 751                                 }
 752                         }
 753                 }
 754         }
 755         return found;
 756 }
 757
 758 static bool
 759 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 760                         int target, int refclk, intel_clock_t *best_clock)
 761 {
 762         struct drm_device *dev = crtc->dev;
 763         struct drm_i915_private *dev_priv = dev->dev_private;
 764         intel_clock_t clock;
 765         int max_n;
 766         bool found;
 767         int err_most = 47;
 768         found = false;
 769
 770         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 771                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requriment prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirment prefere larger m1,m2, p1 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(crtc, &clock))
 798                                                 continue;
 799                                         this_err = abs((10000 - (target*10000/clock.dot)));
 800                                         if (this_err < err_most) {
 801                                                 *best_clock = clock;
 802                                                 err_most = this_err;
 803                                                 max_n = clock.n;
 804                                                 found = true;
 805                                                 /* found on first matching */
 806                                                 goto out;
 807                                         }
 808                                 }
 809                         }
 810                 }
 811         }
 812 out:
 813         return found;
 814 }
 815
 816 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 817 static bool
 818 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 819                       int target, int refclk, intel_clock_t *best_clock)
 820 {
 821     intel_clock_t clock;
 822     if (target < 200000) {
 823         clock.dot = 161670;
 824         clock.p = 20;
 825         clock.p1 = 2;
 826         clock.p2 = 10;
 827         clock.n = 0x01;
 828         clock.m = 97;
 829         clock.m1 = 0x10;
 830         clock.m2 = 0x05;
 831     } else {
 832         clock.dot = 270000;
 833         clock.p = 10;
 834         clock.p1 = 1;
 835         clock.p2 = 10;
 836         clock.n = 0x02;
 837         clock.m = 108;
 838         clock.m1 = 0x12;
 839         clock.m2 = 0x06;
 840     }
 841     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 842     return true;
 843 }
 844
 845 void
 846 intel_wait_for_vblank(struct drm_device *dev)
 847 {
 848         /* Wait for 20ms, i.e. one cycle at 50hz. */
 849         mdelay(20);
 850 }
 851
 852 static int
 853 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 854                     struct drm_framebuffer *old_fb)
 855 {
 856         struct drm_device *dev = crtc->dev;
 857         struct drm_i915_private *dev_priv = dev->dev_private;
 858         struct drm_i915_master_private *master_priv;
 859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 860         struct intel_framebuffer *intel_fb;
 861         struct drm_i915_gem_object *obj_priv;
 862         struct drm_gem_object *obj;
 863         int pipe = intel_crtc->pipe;
 864         unsigned long Start, Offset;
 865         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 866         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 867         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 868         int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
 869         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 870         u32 dspcntr, alignment;
 871         int ret;
 872
 873         /* no fb bound */
 874         if (!crtc->fb) {
 875                 DRM_DEBUG("No FB bound\n");
 876                 return 0;
 877         }
 878
 879         switch (pipe) {
 880         case 0:
 881         case 1:
 882                 break;
 883         default:
 884                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 885                 return -EINVAL;
 886         }
 887
 888         intel_fb = to_intel_framebuffer(crtc->fb);
 889         obj = intel_fb->obj;
 890         obj_priv = obj->driver_private;
 891
 892         switch (obj_priv->tiling_mode) {
 893         case I915_TILING_NONE:
 894                 alignment = 64 * 1024;
 895                 break;
 896         case I915_TILING_X:
 897                 /* pin() will align the object as required by fence */
 898                 alignment = 0;
 899                 break;
 900         case I915_TILING_Y:
 901                 /* FIXME: Is this true? */
 902                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 903                 return -EINVAL;
 904         default:
 905                 BUG();
 906         }
 907
 908         mutex_lock(&dev->struct_mutex);
 909         ret = i915_gem_object_pin(obj, alignment);
 910         if (ret != 0) {
 911                 mutex_unlock(&dev->struct_mutex);
 912                 return ret;
 913         }
 914
 915         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 916         if (ret != 0) {
 917                 i915_gem_object_unpin(obj);
 918                 mutex_unlock(&dev->struct_mutex);
 919                 return ret;
 920         }
 921
 922         /* Pre-i965 needs to install a fence for tiled scan-out */
 923         if (!IS_I965G(dev) &&
 924             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
 925             obj_priv->tiling_mode != I915_TILING_NONE) {
 926                 ret = i915_gem_object_get_fence_reg(obj);
 927                 if (ret != 0) {
 928                         i915_gem_object_unpin(obj);
 929                         mutex_unlock(&dev->struct_mutex);
 930                         return ret;
 931                 }
 932         }
 933
 934         dspcntr = I915_READ(dspcntr_reg);
 935         /* Mask out pixel format bits in case we change it */
 936         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 937         switch (crtc->fb->bits_per_pixel) {
 938         case 8:
 939                 dspcntr |= DISPPLANE_8BPP;
 940                 break;
 941         case 16:
 942                 if (crtc->fb->depth == 15)
 943                         dspcntr |= DISPPLANE_15_16BPP;
 944                 else
 945                         dspcntr |= DISPPLANE_16BPP;
 946                 break;
 947         case 24:
 948         case 32:
 949                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 950                 break;
 951         default:
 952                 DRM_ERROR("Unknown color depth\n");
 953                 i915_gem_object_unpin(obj);
 954                 mutex_unlock(&dev->struct_mutex);
 955                 return -EINVAL;
 956         }
 957         if (IS_I965G(dev)) {
 958                 if (obj_priv->tiling_mode != I915_TILING_NONE)
 959                         dspcntr |= DISPPLANE_TILED;
 960                 else
 961                         dspcntr &= ~DISPPLANE_TILED;
 962         }
 963
 964         I915_WRITE(dspcntr_reg, dspcntr);
 965
 966         Start = obj_priv->gtt_offset;
 967         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 968
 969         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 970         I915_WRITE(dspstride, crtc->fb->pitch);
 971         if (IS_I965G(dev)) {
 972                 I915_WRITE(dspbase, Offset);
 973                 I915_READ(dspbase);
 974                 I915_WRITE(dspsurf, Start);
 975                 I915_READ(dspsurf);
 976                 I915_WRITE(dsptileoff, (y << 16) | x);
 977         } else {
 978                 I915_WRITE(dspbase, Start + Offset);
 979                 I915_READ(dspbase);
 980         }
 981
 982         intel_wait_for_vblank(dev);
 983
 984         if (old_fb) {
 985                 intel_fb = to_intel_framebuffer(old_fb);
 986                 i915_gem_object_unpin(intel_fb->obj);
 987         }
 988         mutex_unlock(&dev->struct_mutex);
 989
 990         if (!dev->primary->master)
 991                 return 0;
 992
 993         master_priv = dev->primary->master->driver_priv;
 994         if (!master_priv->sarea_priv)
 995                 return 0;
 996
 997         if (pipe) {
 998                 master_priv->sarea_priv->pipeB_x = x;
 999                 master_priv->sarea_priv->pipeB_y = y;
1000         } else {
1001                 master_priv->sarea_priv->pipeA_x = x;
1002                 master_priv->sarea_priv->pipeA_y = y;
1003         }
1004
1005         return 0;
1006 }
1007
1008 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1009 {
1010         struct drm_device *dev = crtc->dev;
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1013         int pipe = intel_crtc->pipe;
1014         int plane = intel_crtc->pipe;
1015         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1016         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1017         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1018         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1019         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1020         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1021         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1022         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1023         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1024         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1025         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1026         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1027         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1028         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1029         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1030         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1031         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1032         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1033         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1034         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1035         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1036         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1037         u32 temp;
1038         int tries = 5, j;
1039
1040         /* XXX: When our outputs are all unaware of DPMS modes other than off
1041          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1042          */
1043         switch (mode) {
1044         case DRM_MODE_DPMS_ON:
1045         case DRM_MODE_DPMS_STANDBY:
1046         case DRM_MODE_DPMS_SUSPEND:
1047                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1048                 /* enable PCH DPLL */
1049                 temp = I915_READ(pch_dpll_reg);
1050                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1051                         I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1052                         I915_READ(pch_dpll_reg);
1053                 }
1054
1055                 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1056                 temp = I915_READ(fdi_rx_reg);
1057                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1058                                 FDI_SEL_PCDCLK |
1059                                 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1060                 I915_READ(fdi_rx_reg);
1061                 udelay(200);
1062
1063                 /* Enable CPU FDI TX PLL, always on for IGDNG */
1064                 temp = I915_READ(fdi_tx_reg);
1065                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1066                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1067                         I915_READ(fdi_tx_reg);
1068                         udelay(100);
1069                 }
1070
1071                 /* Enable CPU pipe */
1072                 temp = I915_READ(pipeconf_reg);
1073                 if ((temp & PIPEACONF_ENABLE) == 0) {
1074                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1075                         I915_READ(pipeconf_reg);
1076                         udelay(100);
1077                 }
1078
1079                 /* configure and enable CPU plane */
1080                 temp = I915_READ(dspcntr_reg);
1081                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1082                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1083                         /* Flush the plane changes */
1084                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1085                 }
1086
1087                 /* enable CPU FDI TX and PCH FDI RX */
1088                 temp = I915_READ(fdi_tx_reg);
1089                 temp |= FDI_TX_ENABLE;
1090                 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1091                 temp &= ~FDI_LINK_TRAIN_NONE;
1092                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1093                 I915_WRITE(fdi_tx_reg, temp);
1094                 I915_READ(fdi_tx_reg);
1095
1096                 temp = I915_READ(fdi_rx_reg);
1097                 temp &= ~FDI_LINK_TRAIN_NONE;
1098                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1099                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1100                 I915_READ(fdi_rx_reg);
1101
1102                 udelay(150);
1103
1104                 /* Train FDI. */
1105                 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1106                    for train result */
1107                 temp = I915_READ(fdi_rx_imr_reg);
1108                 temp &= ~FDI_RX_SYMBOL_LOCK;
1109                 temp &= ~FDI_RX_BIT_LOCK;
1110                 I915_WRITE(fdi_rx_imr_reg, temp);
1111                 I915_READ(fdi_rx_imr_reg);
1112                 udelay(150);
1113
1114                 temp = I915_READ(fdi_rx_iir_reg);
1115                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1116
1117                 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1118                         for (j = 0; j < tries; j++) {
1119                                 temp = I915_READ(fdi_rx_iir_reg);
1120                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1121                                 if (temp & FDI_RX_BIT_LOCK)
1122                                         break;
1123                                 udelay(200);
1124                         }
1125                         if (j != tries)
1126                                 I915_WRITE(fdi_rx_iir_reg,
1127                                                 temp | FDI_RX_BIT_LOCK);
1128                         else
1129                                 DRM_DEBUG("train 1 fail\n");
1130                 } else {
1131                         I915_WRITE(fdi_rx_iir_reg,
1132                                         temp | FDI_RX_BIT_LOCK);
1133                         DRM_DEBUG("train 1 ok 2!\n");
1134                 }
1135                 temp = I915_READ(fdi_tx_reg);
1136                 temp &= ~FDI_LINK_TRAIN_NONE;
1137                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1138                 I915_WRITE(fdi_tx_reg, temp);
1139
1140                 temp = I915_READ(fdi_rx_reg);
1141                 temp &= ~FDI_LINK_TRAIN_NONE;
1142                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1143                 I915_WRITE(fdi_rx_reg, temp);
1144
1145                 udelay(150);
1146
1147                 temp = I915_READ(fdi_rx_iir_reg);
1148                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1149
1150                 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1151                         for (j = 0; j < tries; j++) {
1152                                 temp = I915_READ(fdi_rx_iir_reg);
1153                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1154                                 if (temp & FDI_RX_SYMBOL_LOCK)
1155                                         break;
1156                                 udelay(200);
1157                         }
1158                         if (j != tries) {
1159                                 I915_WRITE(fdi_rx_iir_reg,
1160                                                 temp | FDI_RX_SYMBOL_LOCK);
1161                                 DRM_DEBUG("train 2 ok 1!\n");
1162                         } else
1163                                 DRM_DEBUG("train 2 fail\n");
1164                 } else {
1165                         I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1166                         DRM_DEBUG("train 2 ok 2!\n");
1167                 }
1168                 DRM_DEBUG("train done\n");
1169
1170                 /* set transcoder timing */
1171                 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1172                 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1173                 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1174
1175                 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1176                 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1177                 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1178
1179                 /* enable PCH transcoder */
1180                 temp = I915_READ(transconf_reg);
1181                 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1182                 I915_READ(transconf_reg);
1183
1184                 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1185                         ;
1186
1187                 /* enable normal */
1188
1189                 temp = I915_READ(fdi_tx_reg);
1190                 temp &= ~FDI_LINK_TRAIN_NONE;
1191                 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1192                                 FDI_TX_ENHANCE_FRAME_ENABLE);
1193                 I915_READ(fdi_tx_reg);
1194
1195                 temp = I915_READ(fdi_rx_reg);
1196                 temp &= ~FDI_LINK_TRAIN_NONE;
1197                 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1198                                 FDI_RX_ENHANCE_FRAME_ENABLE);
1199                 I915_READ(fdi_rx_reg);
1200
1201                 /* wait one idle pattern time */
1202                 udelay(100);
1203
1204                 intel_crtc_load_lut(crtc);
1205
1206         break;
1207         case DRM_MODE_DPMS_OFF:
1208                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1209
1210                 /* Disable the VGA plane that we never use */
1211                 I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
1212
1213                 /* Disable display plane */
1214                 temp = I915_READ(dspcntr_reg);
1215                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1216                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1217                         /* Flush the plane changes */
1218                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1219                         I915_READ(dspbase_reg);
1220                 }
1221
1222                 /* disable cpu pipe, disable after all planes disabled */
1223                 temp = I915_READ(pipeconf_reg);
1224                 if ((temp & PIPEACONF_ENABLE) != 0) {
1225                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1226                         I915_READ(pipeconf_reg);
1227                         /* wait for cpu pipe off, pipe state */
1228                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
1229                                 ;
1230                 } else
1231                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1232
1233                 /* IGDNG-A : disable cpu panel fitter ? */
1234                 temp = I915_READ(pf_ctl_reg);
1235                 if ((temp & PF_ENABLE) != 0) {
1236                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1237                         I915_READ(pf_ctl_reg);
1238                 }
1239
1240                 /* disable CPU FDI tx and PCH FDI rx */
1241                 temp = I915_READ(fdi_tx_reg);
1242                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1243                 I915_READ(fdi_tx_reg);
1244
1245                 temp = I915_READ(fdi_rx_reg);
1246                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1247                 I915_READ(fdi_rx_reg);
1248
1249                 /* still set train pattern 1 */
1250                 temp = I915_READ(fdi_tx_reg);
1251                 temp &= ~FDI_LINK_TRAIN_NONE;
1252                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1253                 I915_WRITE(fdi_tx_reg, temp);
1254
1255                 temp = I915_READ(fdi_rx_reg);
1256                 temp &= ~FDI_LINK_TRAIN_NONE;
1257                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1258                 I915_WRITE(fdi_rx_reg, temp);
1259
1260                 /* disable PCH transcoder */
1261                 temp = I915_READ(transconf_reg);
1262                 if ((temp & TRANS_ENABLE) != 0) {
1263                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1264                         I915_READ(transconf_reg);
1265                         /* wait for PCH transcoder off, transcoder state */
1266                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
1267                                 ;
1268                 }
1269
1270                 /* disable PCH DPLL */
1271                 temp = I915_READ(pch_dpll_reg);
1272                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1273                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1274                         I915_READ(pch_dpll_reg);
1275                 }
1276
1277                 temp = I915_READ(fdi_rx_reg);
1278                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1279                         temp &= ~FDI_SEL_PCDCLK;
1280                         temp &= ~FDI_RX_PLL_ENABLE;
1281                         I915_WRITE(fdi_rx_reg, temp);
1282                         I915_READ(fdi_rx_reg);
1283                 }
1284
1285                 /* Wait for the clocks to turn off. */
1286                 udelay(150);
1287                 break;
1288         }
1289 }
1290
1291 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1292 {
1293         struct drm_device *dev = crtc->dev;
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1296         int pipe = intel_crtc->pipe;
1297         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1298         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1299         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1300         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1301         u32 temp;
1302
1303         /* XXX: When our outputs are all unaware of DPMS modes other than off
1304          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1305          */
1306         switch (mode) {
1307         case DRM_MODE_DPMS_ON:
1308         case DRM_MODE_DPMS_STANDBY:
1309         case DRM_MODE_DPMS_SUSPEND:
1310                 /* Enable the DPLL */
1311                 temp = I915_READ(dpll_reg);
1312                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1313                         I915_WRITE(dpll_reg, temp);
1314                         I915_READ(dpll_reg);
1315                         /* Wait for the clocks to stabilize. */
1316                         udelay(150);
1317                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1318                         I915_READ(dpll_reg);
1319                         /* Wait for the clocks to stabilize. */
1320                         udelay(150);
1321                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1322                         I915_READ(dpll_reg);
1323                         /* Wait for the clocks to stabilize. */
1324                         udelay(150);
1325                 }
1326
1327                 /* Enable the pipe */
1328                 temp = I915_READ(pipeconf_reg);
1329                 if ((temp & PIPEACONF_ENABLE) == 0)
1330                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1331
1332                 /* Enable the plane */
1333                 temp = I915_READ(dspcntr_reg);
1334                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1335                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1336                         /* Flush the plane changes */
1337                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1338                 }
1339
1340                 intel_crtc_load_lut(crtc);
1341
1342                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1343                 //intel_crtc_dpms_video(crtc, true); TODO
1344         break;
1345         case DRM_MODE_DPMS_OFF:
1346                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1347                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1348
1349                 /* Disable the VGA plane that we never use */
1350                 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
1351
1352                 /* Disable display plane */
1353                 temp = I915_READ(dspcntr_reg);
1354                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1355                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1356                         /* Flush the plane changes */
1357                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1358                         I915_READ(dspbase_reg);
1359                 }
1360
1361                 if (!IS_I9XX(dev)) {
1362                         /* Wait for vblank for the disable to take effect */
1363                         intel_wait_for_vblank(dev);
1364                 }
1365
1366                 /* Next, disable display pipes */
1367                 temp = I915_READ(pipeconf_reg);
1368                 if ((temp & PIPEACONF_ENABLE) != 0) {
1369                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1370                         I915_READ(pipeconf_reg);
1371                 }
1372
1373                 /* Wait for vblank for the disable to take effect. */
1374                 intel_wait_for_vblank(dev);
1375
1376                 temp = I915_READ(dpll_reg);
1377                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1378                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1379                         I915_READ(dpll_reg);
1380                 }
1381
1382                 /* Wait for the clocks to turn off. */
1383                 udelay(150);
1384                 break;
1385         }
1386 }
1387
1388 /**
1389  * Sets the power management mode of the pipe and plane.
1390  *
1391  * This code should probably grow support for turning the cursor off and back
1392  * on appropriately at the same time as we're turning the pipe off/on.
1393  */
1394 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1395 {
1396         struct drm_device *dev = crtc->dev;
1397         struct drm_i915_master_private *master_priv;
1398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1399         int pipe = intel_crtc->pipe;
1400         bool enabled;
1401
1402         if (IS_IGDNG(dev))
1403                 igdng_crtc_dpms(crtc, mode);
1404         else
1405                 i9xx_crtc_dpms(crtc, mode);
1406
1407         if (!dev->primary->master)
1408                 return;
1409
1410         master_priv = dev->primary->master->driver_priv;
1411         if (!master_priv->sarea_priv)
1412                 return;
1413
1414         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1415
1416         switch (pipe) {
1417         case 0:
1418                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1419                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1420                 break;
1421         case 1:
1422                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1423                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1424                 break;
1425         default:
1426                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1427                 break;
1428         }
1429
1430         intel_crtc->dpms_mode = mode;
1431 }
1432
1433 static void intel_crtc_prepare (struct drm_crtc *crtc)
1434 {
1435         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1436         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1437 }
1438
1439 static void intel_crtc_commit (struct drm_crtc *crtc)
1440 {
1441         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1442         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1443 }
1444
1445 void intel_encoder_prepare (struct drm_encoder *encoder)
1446 {
1447         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1448         /* lvds has its own version of prepare see intel_lvds_prepare */
1449         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1450 }
1451
1452 void intel_encoder_commit (struct drm_encoder *encoder)
1453 {
1454         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1455         /* lvds has its own version of commit see intel_lvds_commit */
1456         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1457 }
1458
1459 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1460                                   struct drm_display_mode *mode,
1461                                   struct drm_display_mode *adjusted_mode)
1462 {
1463         struct drm_device *dev = crtc->dev;
1464         if (IS_IGDNG(dev)) {
1465                 /* FDI link clock is fixed at 2.7G */
1466                 if (mode->clock * 3 > 27000 * 4)
1467                         return MODE_CLOCK_HIGH;
1468         }
1469         return true;
1470 }
1471
1472
1473 /** Returns the core display clock speed for i830 - i945 */
1474 static int intel_get_core_clock_speed(struct drm_device *dev)
1475 {
1476
1477         /* Core clock values taken from the published datasheets.
1478          * The 830 may go up to 166 Mhz, which we should check.
1479          */
1480         if (IS_I945G(dev))
1481                 return 400000;
1482         else if (IS_I915G(dev))
1483                 return 333000;
1484         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1485                 return 200000;
1486         else if (IS_I915GM(dev)) {
1487                 u16 gcfgc = 0;
1488
1489                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1490
1491                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1492                         return 133000;
1493                 else {
1494                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1495                         case GC_DISPLAY_CLOCK_333_MHZ:
1496                                 return 333000;
1497                         default:
1498                         case GC_DISPLAY_CLOCK_190_200_MHZ:
1499                                 return 190000;
1500                         }
1501                 }
1502         } else if (IS_I865G(dev))
1503                 return 266000;
1504         else if (IS_I855(dev)) {
1505                 u16 hpllcc = 0;
1506                 /* Assume that the hardware is in the high speed state.  This
1507                  * should be the default.
1508                  */
1509                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1510                 case GC_CLOCK_133_200:
1511                 case GC_CLOCK_100_200:
1512                         return 200000;
1513                 case GC_CLOCK_166_250:
1514                         return 250000;
1515                 case GC_CLOCK_100_133:
1516                         return 133000;
1517                 }
1518         } else /* 852, 830 */
1519                 return 133000;
1520
1521         return 0; /* Silence gcc warning */
1522 }
1523
1524
1525 /**
1526  * Return the pipe currently connected to the panel fitter,
1527  * or -1 if the panel fitter is not present or not in use
1528  */
1529 static int intel_panel_fitter_pipe (struct drm_device *dev)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         u32  pfit_control;
1533
1534         /* i830 doesn't have a panel fitter */
1535         if (IS_I830(dev))
1536                 return -1;
1537
1538         pfit_control = I915_READ(PFIT_CONTROL);
1539
1540         /* See if the panel fitter is in use */
1541         if ((pfit_control & PFIT_ENABLE) == 0)
1542                 return -1;
1543
1544         /* 965 can place panel fitter on either pipe */
1545         if (IS_I965G(dev))
1546                 return (pfit_control >> 29) & 0x3;
1547
1548         /* older chips can only use pipe 1 */
1549         return 1;
1550 }
1551
1552 struct fdi_m_n {
1553         u32        tu;
1554         u32        gmch_m;
1555         u32        gmch_n;
1556         u32        link_m;
1557         u32        link_n;
1558 };
1559
1560 static void
1561 fdi_reduce_ratio(u32 *num, u32 *den)
1562 {
1563         while (*num > 0xffffff || *den > 0xffffff) {
1564                 *num >>= 1;
1565                 *den >>= 1;
1566         }
1567 }
1568
1569 #define DATA_N 0x800000
1570 #define LINK_N 0x80000
1571
1572 static void
1573 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1574                 int pixel_clock, int link_clock,
1575                 struct fdi_m_n *m_n)
1576 {
1577         u64 temp;
1578
1579         m_n->tu = 64; /* default size */
1580
1581         temp = (u64) DATA_N * pixel_clock;
1582         temp = div_u64(temp, link_clock);
1583         m_n->gmch_m = (temp * bytes_per_pixel) / nlanes;
1584         m_n->gmch_n = DATA_N;
1585         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1586
1587         temp = (u64) LINK_N * pixel_clock;
1588         m_n->link_m = div_u64(temp, link_clock);
1589         m_n->link_n = LINK_N;
1590         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1591 }
1592
1593
1594 static int intel_crtc_mode_set(struct drm_crtc *crtc,
1595                                struct drm_display_mode *mode,
1596                                struct drm_display_mode *adjusted_mode,
1597                                int x, int y,
1598                                struct drm_framebuffer *old_fb)
1599 {
1600         struct drm_device *dev = crtc->dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1603         int pipe = intel_crtc->pipe;
1604         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
1605         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1606         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
1607         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1608         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1609         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1610         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1611         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1612         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1613         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1614         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1615         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
1616         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
1617         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
1618         int refclk, num_outputs = 0;
1619         intel_clock_t clock;
1620         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
1621         bool ok, is_sdvo = false, is_dvo = false;
1622         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
1623         struct drm_mode_config *mode_config = &dev->mode_config;
1624         struct drm_connector *connector;
1625         const intel_limit_t *limit;
1626         int ret;
1627         struct fdi_m_n m_n = {0};
1628         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
1629         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
1630         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
1631         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
1632         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
1633         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1634         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1635         int lvds_reg = LVDS;
1636         u32 temp;
1637         int sdvo_pixel_multiply;
1638
1639         drm_vblank_pre_modeset(dev, pipe);
1640
1641         list_for_each_entry(connector, &mode_config->connector_list, head) {
1642                 struct intel_output *intel_output = to_intel_output(connector);
1643
1644                 if (!connector->encoder || connector->encoder->crtc != crtc)
1645                         continue;
1646
1647                 switch (intel_output->type) {
1648                 case INTEL_OUTPUT_LVDS:
1649                         is_lvds = true;
1650                         break;
1651                 case INTEL_OUTPUT_SDVO:
1652                 case INTEL_OUTPUT_HDMI:
1653                         is_sdvo = true;
1654                         if (intel_output->needs_tv_clock)
1655                                 is_tv = true;
1656                         break;
1657                 case INTEL_OUTPUT_DVO:
1658                         is_dvo = true;
1659                         break;
1660                 case INTEL_OUTPUT_TVOUT:
1661                         is_tv = true;
1662                         break;
1663                 case INTEL_OUTPUT_ANALOG:
1664                         is_crt = true;
1665                         break;
1666                 case INTEL_OUTPUT_DISPLAYPORT:
1667                         is_dp = true;
1668                         break;
1669                 }
1670
1671                 num_outputs++;
1672         }
1673
1674         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
1675                 refclk = dev_priv->lvds_ssc_freq * 1000;
1676                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
1677         } else if (IS_I9XX(dev)) {
1678                 refclk = 96000;
1679                 if (IS_IGDNG(dev))
1680                         refclk = 120000; /* 120Mhz refclk */
1681         } else {
1682                 refclk = 48000;
1683         }
1684
1685
1686         /*
1687          * Returns a set of divisors for the desired target clock with the given
1688          * refclk, or FALSE.  The returned values represent the clock equation:
1689          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
1690          */
1691         limit = intel_limit(crtc);
1692         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
1693         if (!ok) {
1694                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
1695                 drm_vblank_post_modeset(dev, pipe);
1696                 return -EINVAL;
1697         }
1698
1699         /* SDVO TV has fixed PLL values depend on its clock range,
1700            this mirrors vbios setting. */
1701         if (is_sdvo && is_tv) {
1702                 if (adjusted_mode->clock >= 100000
1703                                 && adjusted_mode->clock < 140500) {
1704                         clock.p1 = 2;
1705                         clock.p2 = 10;
1706                         clock.n = 3;
1707                         clock.m1 = 16;
1708                         clock.m2 = 8;
1709                 } else if (adjusted_mode->clock >= 140500
1710                                 && adjusted_mode->clock <= 200000) {
1711                         clock.p1 = 1;
1712                         clock.p2 = 10;
1713                         clock.n = 6;
1714                         clock.m1 = 12;
1715                         clock.m2 = 8;
1716                 }
1717         }
1718
1719         /* FDI link */
1720         if (IS_IGDNG(dev))
1721                 igdng_compute_m_n(3, 4, /* lane num 4 */
1722                                 adjusted_mode->clock,
1723                                 270000, /* lane clock */
1724                                 &m_n);
1725
1726         if (IS_IGD(dev))
1727                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1728         else
1729                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
1730
1731         if (!IS_IGDNG(dev))
1732                 dpll = DPLL_VGA_MODE_DIS;
1733
1734         if (IS_I9XX(dev)) {
1735                 if (is_lvds)
1736                         dpll |= DPLLB_MODE_LVDS;
1737                 else
1738                         dpll |= DPLLB_MODE_DAC_SERIAL;
1739                 if (is_sdvo) {
1740                         dpll |= DPLL_DVO_HIGH_SPEED;
1741                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1742                         if (IS_I945G(dev) || IS_I945GM(dev))
1743                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1744                         else if (IS_IGDNG(dev))
1745                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
1746                 }
1747                 if (is_dp)
1748                         dpll |= DPLL_DVO_HIGH_SPEED;
1749
1750                 /* compute bitmask from p1 value */
1751                 if (IS_IGD(dev))
1752                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1753                 else {
1754                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1755                         /* also FPA1 */
1756                         if (IS_IGDNG(dev))
1757                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1758                 }
1759                 switch (clock.p2) {
1760                 case 5:
1761                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1762                         break;
1763                 case 7:
1764                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1765                         break;
1766                 case 10:
1767                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1768                         break;
1769                 case 14:
1770                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1771                         break;
1772                 }
1773                 if (IS_I965G(dev) && !IS_IGDNG(dev))
1774                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1775         } else {
1776                 if (is_lvds) {
1777                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1778                 } else {
1779                         if (clock.p1 == 2)
1780                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
1781                         else
1782                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1783                         if (clock.p2 == 4)
1784                                 dpll |= PLL_P2_DIVIDE_BY_4;
1785                 }
1786         }
1787
1788         if (is_sdvo && is_tv)
1789                 dpll |= PLL_REF_INPUT_TVCLKINBC;
1790         else if (is_tv)
1791                 /* XXX: just matching BIOS for now */
1792                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
1793                 dpll |= 3;
1794         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
1795                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1796         else
1797                 dpll |= PLL_REF_INPUT_DREFCLK;
1798
1799         /* setup pipeconf */
1800         pipeconf = I915_READ(pipeconf_reg);
1801
1802         /* Set up the display plane register */
1803         dspcntr = DISPPLANE_GAMMA_ENABLE;
1804
1805         /* IGDNG's plane is forced to pipe, bit 24 is to
1806            enable color space conversion */
1807         if (!IS_IGDNG(dev)) {
1808                 if (pipe == 0)
1809                         dspcntr |= DISPPLANE_SEL_PIPE_A;
1810                 else
1811                         dspcntr |= DISPPLANE_SEL_PIPE_B;
1812         }
1813
1814         if (pipe == 0 && !IS_I965G(dev)) {
1815                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
1816                  * core speed.
1817                  *
1818                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
1819                  * pipe == 0 check?
1820                  */
1821                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
1822                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
1823                 else
1824                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
1825         }
1826
1827         dspcntr |= DISPLAY_PLANE_ENABLE;
1828         pipeconf |= PIPEACONF_ENABLE;
1829         dpll |= DPLL_VCO_ENABLE;
1830
1831
1832         /* Disable the panel fitter if it was on our pipe */
1833         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
1834                 I915_WRITE(PFIT_CONTROL, 0);
1835
1836         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1837         drm_mode_debug_printmodeline(mode);
1838
1839         /* assign to IGDNG registers */
1840         if (IS_IGDNG(dev)) {
1841                 fp_reg = pch_fp_reg;
1842                 dpll_reg = pch_dpll_reg;
1843         }
1844
1845         if (dpll & DPLL_VCO_ENABLE) {
1846                 I915_WRITE(fp_reg, fp);
1847                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
1848                 I915_READ(dpll_reg);
1849                 udelay(150);
1850         }
1851
1852         if (IS_IGDNG(dev)) {
1853                 /* enable PCH clock reference source */
1854                 /* XXX need to change the setting for other outputs */
1855                 u32 temp;
1856                 temp = I915_READ(PCH_DREF_CONTROL);
1857                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
1858                 temp |= DREF_NONSPREAD_CK505_ENABLE;
1859                 temp &= ~DREF_SSC_SOURCE_MASK;
1860                 temp |= DREF_SSC_SOURCE_ENABLE;
1861                 temp &= ~DREF_SSC1_ENABLE;
1862                 /* if no eDP, disable source output to CPU */
1863                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
1864                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
1865                 I915_WRITE(PCH_DREF_CONTROL, temp);
1866         }
1867
1868         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1869          * This is an exception to the general rule that mode_set doesn't turn
1870          * things on.
1871          */
1872         if (is_lvds) {
1873                 u32 lvds;
1874
1875                 if (IS_IGDNG(dev))
1876                         lvds_reg = PCH_LVDS;
1877
1878                 lvds = I915_READ(lvds_reg);
1879                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
1880                 /* Set the B0-B3 data pairs corresponding to whether we're going to
1881                  * set the DPLLs for dual-channel mode or not.
1882                  */
1883                 if (clock.p2 == 7)
1884                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1885                 else
1886                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1887
1888                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1889                  * appropriately here, but we need to look more thoroughly into how
1890                  * panels behave in the two modes.
1891                  */
1892
1893                 I915_WRITE(lvds_reg, lvds);
1894                 I915_READ(lvds_reg);
1895         }
1896         if (is_dp)
1897                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
1898
1899         I915_WRITE(fp_reg, fp);
1900         I915_WRITE(dpll_reg, dpll);
1901         I915_READ(dpll_reg);
1902         /* Wait for the clocks to stabilize. */
1903         udelay(150);
1904
1905         if (IS_I965G(dev) && !IS_IGDNG(dev)) {
1906                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1907                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
1908                            ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1909         } else {
1910                 /* write it again -- the BIOS does, after all */
1911                 I915_WRITE(dpll_reg, dpll);
1912         }
1913         I915_READ(dpll_reg);
1914         /* Wait for the clocks to stabilize. */
1915         udelay(150);
1916
1917         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
1918                    ((adjusted_mode->crtc_htotal - 1) << 16));
1919         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
1920                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
1921         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
1922                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
1923         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
1924                    ((adjusted_mode->crtc_vtotal - 1) << 16));
1925         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
1926                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
1927         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
1928                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
1929         /* pipesrc and dspsize control the size that is scaled from, which should
1930          * always be the user's requested size.
1931          */
1932         if (!IS_IGDNG(dev)) {
1933                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
1934                                 (mode->hdisplay - 1));
1935                 I915_WRITE(dsppos_reg, 0);
1936         }
1937         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1938
1939         if (IS_IGDNG(dev)) {
1940                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
1941                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
1942                 I915_WRITE(link_m1_reg, m_n.link_m);
1943                 I915_WRITE(link_n1_reg, m_n.link_n);
1944
1945                  /* enable FDI RX PLL too */
1946                 temp = I915_READ(fdi_rx_reg);
1947                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1948                 udelay(200);
1949         }
1950
1951         I915_WRITE(pipeconf_reg, pipeconf);
1952         I915_READ(pipeconf_reg);
1953
1954         intel_wait_for_vblank(dev);
1955
1956         I915_WRITE(dspcntr_reg, dspcntr);
1957
1958         /* Flush the plane changes */
1959         ret = intel_pipe_set_base(crtc, x, y, old_fb);
1960         drm_vblank_post_modeset(dev, pipe);
1961
1962         return ret;
1963 }
1964
1965 /** Loads the palette/gamma unit for the CRTC with the prepared values */
1966 void intel_crtc_load_lut(struct drm_crtc *crtc)
1967 {
1968         struct drm_device *dev = crtc->dev;
1969         struct drm_i915_private *dev_priv = dev->dev_private;
1970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1971         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
1972         int i;
1973
1974         /* The clocks have to be on to load the palette. */
1975         if (!crtc->enabled)
1976                 return;
1977
1978         /* use legacy palette for IGDNG */
1979         if (IS_IGDNG(dev))
1980                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
1981                                                    LGC_PALETTE_B;
1982
1983         for (i = 0; i < 256; i++) {
1984                 I915_WRITE(palreg + 4 * i,
1985                            (intel_crtc->lut_r[i] << 16) |
1986                            (intel_crtc->lut_g[i] << 8) |
1987                            intel_crtc->lut_b[i]);
1988         }
1989 }
1990
1991 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
1992                                  struct drm_file *file_priv,
1993                                  uint32_t handle,
1994                                  uint32_t width, uint32_t height)
1995 {
1996         struct drm_device *dev = crtc->dev;
1997         struct drm_i915_private *dev_priv = dev->dev_private;
1998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1999         struct drm_gem_object *bo;
2000         struct drm_i915_gem_object *obj_priv;
2001         int pipe = intel_crtc->pipe;
2002         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2003         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2004         uint32_t temp = I915_READ(control);
2005         size_t addr;
2006         int ret;
2007
2008         DRM_DEBUG("\n");
2009
2010         /* if we want to turn off the cursor ignore width and height */
2011         if (!handle) {
2012                 DRM_DEBUG("cursor off\n");
2013                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2014                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2015                         temp |= CURSOR_MODE_DISABLE;
2016                 } else {
2017                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2018                 }
2019                 addr = 0;
2020                 bo = NULL;
2021                 mutex_lock(&dev->struct_mutex);
2022                 goto finish;
2023         }
2024
2025         /* Currently we only support 64x64 cursors */
2026         if (width != 64 || height != 64) {
2027                 DRM_ERROR("we currently only support 64x64 cursors\n");
2028                 return -EINVAL;
2029         }
2030
2031         bo = drm_gem_object_lookup(dev, file_priv, handle);
2032         if (!bo)
2033                 return -ENOENT;
2034
2035         obj_priv = bo->driver_private;
2036
2037         if (bo->size < width * height * 4) {
2038                 DRM_ERROR("buffer is to small\n");
2039                 ret = -ENOMEM;
2040                 goto fail;
2041         }
2042
2043         /* we only need to pin inside GTT if cursor is non-phy */
2044         mutex_lock(&dev->struct_mutex);
2045         if (!dev_priv->cursor_needs_physical) {
2046                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
2047                 if (ret) {
2048                         DRM_ERROR("failed to pin cursor bo\n");
2049                         goto fail_locked;
2050                 }
2051                 addr = obj_priv->gtt_offset;
2052         } else {
2053                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
2054                 if (ret) {
2055                         DRM_ERROR("failed to attach phys object\n");
2056                         goto fail_locked;
2057                 }
2058                 addr = obj_priv->phys_obj->handle->busaddr;
2059         }
2060
2061         if (!IS_I9XX(dev))
2062                 I915_WRITE(CURSIZE, (height << 12) | width);
2063
2064         /* Hooray for CUR*CNTR differences */
2065         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2066                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
2067                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
2068                 temp |= (pipe << 28); /* Connect to correct pipe */
2069         } else {
2070                 temp &= ~(CURSOR_FORMAT_MASK);
2071                 temp |= CURSOR_ENABLE;
2072                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
2073         }
2074
2075  finish:
2076         I915_WRITE(control, temp);
2077         I915_WRITE(base, addr);
2078
2079         if (intel_crtc->cursor_bo) {
2080                 if (dev_priv->cursor_needs_physical) {
2081                         if (intel_crtc->cursor_bo != bo)
2082                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
2083                 } else
2084                         i915_gem_object_unpin(intel_crtc->cursor_bo);
2085                 drm_gem_object_unreference(intel_crtc->cursor_bo);
2086         }
2087         mutex_unlock(&dev->struct_mutex);
2088
2089         intel_crtc->cursor_addr = addr;
2090         intel_crtc->cursor_bo = bo;
2091
2092         return 0;
2093 fail:
2094         mutex_lock(&dev->struct_mutex);
2095 fail_locked:
2096         drm_gem_object_unreference(bo);
2097         mutex_unlock(&dev->struct_mutex);
2098         return ret;
2099 }
2100
2101 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2102 {
2103         struct drm_device *dev = crtc->dev;
2104         struct drm_i915_private *dev_priv = dev->dev_private;
2105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2106         int pipe = intel_crtc->pipe;
2107         uint32_t temp = 0;
2108         uint32_t adder;
2109
2110         if (x < 0) {
2111                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
2112                 x = -x;
2113         }
2114         if (y < 0) {
2115                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
2116                 y = -y;
2117         }
2118
2119         temp |= x << CURSOR_X_SHIFT;
2120         temp |= y << CURSOR_Y_SHIFT;
2121
2122         adder = intel_crtc->cursor_addr;
2123         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2124         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2125
2126         return 0;
2127 }
2128
2129 /** Sets the color ramps on behalf of RandR */
2130 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2131                                  u16 blue, int regno)
2132 {
2133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134
2135         intel_crtc->lut_r[regno] = red >> 8;
2136         intel_crtc->lut_g[regno] = green >> 8;
2137         intel_crtc->lut_b[regno] = blue >> 8;
2138 }
2139
2140 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2141                                  u16 *blue, uint32_t size)
2142 {
2143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2144         int i;
2145
2146         if (size != 256)
2147                 return;
2148
2149         for (i = 0; i < 256; i++) {
2150                 intel_crtc->lut_r[i] = red[i] >> 8;
2151                 intel_crtc->lut_g[i] = green[i] >> 8;
2152                 intel_crtc->lut_b[i] = blue[i] >> 8;
2153         }
2154
2155         intel_crtc_load_lut(crtc);
2156 }
2157
2158 /**
2159  * Get a pipe with a simple mode set on it for doing load-based monitor
2160  * detection.
2161  *
2162  * It will be up to the load-detect code to adjust the pipe as appropriate for
2163  * its requirements.  The pipe will be connected to no other outputs.
2164  *
2165  * Currently this code will only succeed if there is a pipe with no outputs
2166  * configured for it.  In the future, it could choose to temporarily disable
2167  * some outputs to free up a pipe for its use.
2168  *
2169  * \return crtc, or NULL if no pipes are available.
2170  */
2171
2172 /* VESA 640x480x72Hz mode to set on the pipe */
2173 static struct drm_display_mode load_detect_mode = {
2174         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2175                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2176 };
2177
2178 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2179                                             struct drm_display_mode *mode,
2180                                             int *dpms_mode)
2181 {
2182         struct intel_crtc *intel_crtc;
2183         struct drm_crtc *possible_crtc;
2184         struct drm_crtc *supported_crtc =NULL;
2185         struct drm_encoder *encoder = &intel_output->enc;
2186         struct drm_crtc *crtc = NULL;
2187         struct drm_device *dev = encoder->dev;
2188         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2189         struct drm_crtc_helper_funcs *crtc_funcs;
2190         int i = -1;
2191
2192         /*
2193          * Algorithm gets a little messy:
2194          *   - if the connector already has an assigned crtc, use it (but make
2195          *     sure it's on first)
2196          *   - try to find the first unused crtc that can drive this connector,
2197          *     and use that if we find one
2198          *   - if there are no unused crtcs available, try to use the first
2199          *     one we found that supports the connector
2200          */
2201
2202         /* See if we already have a CRTC for this connector */
2203         if (encoder->crtc) {
2204                 crtc = encoder->crtc;
2205                 /* Make sure the crtc and connector are running */
2206                 intel_crtc = to_intel_crtc(crtc);
2207                 *dpms_mode = intel_crtc->dpms_mode;
2208                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2209                         crtc_funcs = crtc->helper_private;
2210                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2211                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2212                 }
2213                 return crtc;
2214         }
2215
2216         /* Find an unused one (if possible) */
2217         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2218                 i++;
2219                 if (!(encoder->possible_crtcs & (1 << i)))
2220                         continue;
2221                 if (!possible_crtc->enabled) {
2222                         crtc = possible_crtc;
2223                         break;
2224                 }
2225                 if (!supported_crtc)
2226                         supported_crtc = possible_crtc;
2227         }
2228
2229         /*
2230          * If we didn't find an unused CRTC, don't use any.
2231          */
2232         if (!crtc) {
2233                 return NULL;
2234         }
2235
2236         encoder->crtc = crtc;
2237         intel_output->base.encoder = encoder;
2238         intel_output->load_detect_temp = true;
2239
2240         intel_crtc = to_intel_crtc(crtc);
2241         *dpms_mode = intel_crtc->dpms_mode;
2242
2243         if (!crtc->enabled) {
2244                 if (!mode)
2245                         mode = &load_detect_mode;
2246                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
2247         } else {
2248                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2249                         crtc_funcs = crtc->helper_private;
2250                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2251                 }
2252
2253                 /* Add this connector to the crtc */
2254                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
2255                 encoder_funcs->commit(encoder);
2256         }
2257         /* let the connector get through one full cycle before testing */
2258         intel_wait_for_vblank(dev);
2259
2260         return crtc;
2261 }
2262
2263 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
2264 {
2265         struct drm_encoder *encoder = &intel_output->enc;
2266         struct drm_device *dev = encoder->dev;
2267         struct drm_crtc *crtc = encoder->crtc;
2268         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2269         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2270
2271         if (intel_output->load_detect_temp) {
2272                 encoder->crtc = NULL;
2273                 intel_output->base.encoder = NULL;
2274                 intel_output->load_detect_temp = false;
2275                 crtc->enabled = drm_helper_crtc_in_use(crtc);
2276                 drm_helper_disable_unused_functions(dev);
2277         }
2278
2279         /* Switch crtc and output back off if necessary */
2280         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
2281                 if (encoder->crtc == crtc)
2282                         encoder_funcs->dpms(encoder, dpms_mode);
2283                 crtc_funcs->dpms(crtc, dpms_mode);
2284         }
2285 }
2286
2287 /* Returns the clock of the currently programmed mode of the given pipe. */
2288 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
2289 {
2290         struct drm_i915_private *dev_priv = dev->dev_private;
2291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2292         int pipe = intel_crtc->pipe;
2293         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
2294         u32 fp;
2295         intel_clock_t clock;
2296
2297         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2298                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
2299         else
2300                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
2301
2302         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
2303         if (IS_IGD(dev)) {
2304                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2305                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2306         } else {
2307                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2308                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2309         }
2310
2311         if (IS_I9XX(dev)) {
2312                 if (IS_IGD(dev))
2313                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2314                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
2315                 else
2316                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2317                                DPLL_FPA01_P1_POST_DIV_SHIFT);
2318
2319                 switch (dpll & DPLL_MODE_MASK) {
2320                 case DPLLB_MODE_DAC_SERIAL:
2321                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
2322                                 5 : 10;
2323                         break;
2324                 case DPLLB_MODE_LVDS:
2325                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
2326                                 7 : 14;
2327                         break;
2328                 default:
2329                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
2330                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
2331                         return 0;
2332                 }
2333
2334                 /* XXX: Handle the 100Mhz refclk */
2335                 intel_clock(dev, 96000, &clock);
2336         } else {
2337                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2338
2339                 if (is_lvds) {
2340                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2341                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
2342                         clock.p2 = 14;
2343
2344                         if ((dpll & PLL_REF_INPUT_MASK) ==
2345                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
2346                                 /* XXX: might not be 66MHz */
2347                                 intel_clock(dev, 66000, &clock);
2348                         } else
2349                                 intel_clock(dev, 48000, &clock);
2350                 } else {
2351                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
2352                                 clock.p1 = 2;
2353                         else {
2354                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2355                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
2356                         }
2357                         if (dpll & PLL_P2_DIVIDE_BY_4)
2358                                 clock.p2 = 4;
2359                         else
2360                                 clock.p2 = 2;
2361
2362                         intel_clock(dev, 48000, &clock);
2363                 }
2364         }
2365
2366         /* XXX: It would be nice to validate the clocks, but we can't reuse
2367          * i830PllIsValid() because it relies on the xf86_config connector
2368          * configuration being accurate, which it isn't necessarily.
2369          */
2370
2371         return clock.dot;
2372 }
2373
2374 /** Returns the currently programmed mode of the given pipe. */
2375 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
2376                                              struct drm_crtc *crtc)
2377 {
2378         struct drm_i915_private *dev_priv = dev->dev_private;
2379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2380         int pipe = intel_crtc->pipe;
2381         struct drm_display_mode *mode;
2382         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
2383         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
2384         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
2385         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
2386
2387         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
2388         if (!mode)
2389                 return NULL;
2390
2391         mode->clock = intel_crtc_clock_get(dev, crtc);
2392         mode->hdisplay = (htot & 0xffff) + 1;
2393         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
2394         mode->hsync_start = (hsync & 0xffff) + 1;
2395         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
2396         mode->vdisplay = (vtot & 0xffff) + 1;
2397         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
2398         mode->vsync_start = (vsync & 0xffff) + 1;
2399         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
2400
2401         drm_mode_set_name(mode);
2402         drm_mode_set_crtcinfo(mode, 0);
2403
2404         return mode;
2405 }
2406
2407 static void intel_crtc_destroy(struct drm_crtc *crtc)
2408 {
2409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410
2411         if (intel_crtc->mode_set.mode)
2412                 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
2413         drm_crtc_cleanup(crtc);
2414         kfree(intel_crtc);
2415 }
2416
2417 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
2418         .dpms = intel_crtc_dpms,
2419         .mode_fixup = intel_crtc_mode_fixup,
2420         .mode_set = intel_crtc_mode_set,
2421         .mode_set_base = intel_pipe_set_base,
2422         .prepare = intel_crtc_prepare,
2423         .commit = intel_crtc_commit,
2424 };
2425
2426 static const struct drm_crtc_funcs intel_crtc_funcs = {
2427         .cursor_set = intel_crtc_cursor_set,
2428         .cursor_move = intel_crtc_cursor_move,
2429         .gamma_set = intel_crtc_gamma_set,
2430         .set_config = drm_crtc_helper_set_config,
2431         .destroy = intel_crtc_destroy,
2432 };
2433
2434
2435 static void intel_crtc_init(struct drm_device *dev, int pipe)
2436 {
2437         struct intel_crtc *intel_crtc;
2438         int i;
2439
2440         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2441         if (intel_crtc == NULL)
2442                 return;
2443
2444         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2445
2446         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
2447         intel_crtc->pipe = pipe;
2448         for (i = 0; i < 256; i++) {
2449                 intel_crtc->lut_r[i] = i;
2450                 intel_crtc->lut_g[i] = i;
2451                 intel_crtc->lut_b[i] = i;
2452         }
2453
2454         intel_crtc->cursor_addr = 0;
2455         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
2456         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2457
2458         intel_crtc->mode_set.crtc = &intel_crtc->base;
2459         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
2460         intel_crtc->mode_set.num_connectors = 0;
2461
2462         if (i915_fbpercrtc) {
2463
2464
2465
2466         }
2467 }
2468
2469 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
2470                                 struct drm_file *file_priv)
2471 {
2472         drm_i915_private_t *dev_priv = dev->dev_private;
2473         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
2474         struct drm_crtc *crtc = NULL;
2475         int pipe = -1;
2476
2477         if (!dev_priv) {
2478                 DRM_ERROR("called with no initialization\n");
2479                 return -EINVAL;
2480         }
2481
2482         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2483                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2484                 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
2485                         pipe = intel_crtc->pipe;
2486                         break;
2487                 }
2488         }
2489
2490         if (pipe == -1) {
2491                 DRM_ERROR("no such CRTC id\n");
2492                 return -EINVAL;
2493         }
2494
2495         pipe_from_crtc_id->pipe = pipe;
2496
2497        return 0;
2498 }
2499
2500 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
2501 {
2502         struct drm_crtc *crtc = NULL;
2503
2504         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2505                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2506                 if (intel_crtc->pipe == pipe)
2507                         break;
2508         }
2509         return crtc;
2510 }
2511
2512 static int intel_connector_clones(struct drm_device *dev, int type_mask)
2513 {
2514         int index_mask = 0;
2515         struct drm_connector *connector;
2516         int entry = 0;
2517
2518         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2519                 struct intel_output *intel_output = to_intel_output(connector);
2520                 if (type_mask & (1 << intel_output->type))
2521                         index_mask |= (1 << entry);
2522                 entry++;
2523         }
2524         return index_mask;
2525 }
2526
2527
2528 static void intel_setup_outputs(struct drm_device *dev)
2529 {
2530         struct drm_i915_private *dev_priv = dev->dev_private;
2531         struct drm_connector *connector;
2532
2533         intel_crt_init(dev);
2534
2535         /* Set up integrated LVDS */
2536         if (IS_MOBILE(dev) && !IS_I830(dev))
2537                 intel_lvds_init(dev);
2538
2539         if (IS_IGDNG(dev)) {
2540                 int found;
2541
2542                 if (I915_READ(HDMIB) & PORT_DETECTED) {
2543                         /* check SDVOB */
2544                         /* found = intel_sdvo_init(dev, HDMIB); */
2545                         found = 0;
2546                         if (!found)
2547                                 intel_hdmi_init(dev, HDMIB);
2548                 }
2549
2550                 if (I915_READ(HDMIC) & PORT_DETECTED)
2551                         intel_hdmi_init(dev, HDMIC);
2552
2553                 if (I915_READ(HDMID) & PORT_DETECTED)
2554                         intel_hdmi_init(dev, HDMID);
2555
2556         } else if (IS_I9XX(dev)) {
2557                 int found;
2558                 u32 reg;
2559
2560                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
2561                         found = intel_sdvo_init(dev, SDVOB);
2562                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2563                                 intel_hdmi_init(dev, SDVOB);
2564                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
2565                                 intel_dp_init(dev, DP_B);
2566                 }
2567
2568                 /* Before G4X SDVOC doesn't have its own detect register */
2569                 if (IS_G4X(dev))
2570                         reg = SDVOC;
2571                 else
2572                         reg = SDVOB;
2573
2574                 if (I915_READ(reg) & SDVO_DETECTED) {
2575                         found = intel_sdvo_init(dev, SDVOC);
2576                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2577                                 intel_hdmi_init(dev, SDVOC);
2578                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
2579                                 intel_dp_init(dev, DP_C);
2580                 }
2581                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
2582                         intel_dp_init(dev, DP_D);
2583         } else
2584                 intel_dvo_init(dev);
2585
2586         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
2587                 intel_tv_init(dev);
2588
2589         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2590                 struct intel_output *intel_output = to_intel_output(connector);
2591                 struct drm_encoder *encoder = &intel_output->enc;
2592                 int crtc_mask = 0, clone_mask = 0;
2593
2594                 /* valid crtcs */
2595                 switch(intel_output->type) {
2596                 case INTEL_OUTPUT_HDMI:
2597                         crtc_mask = ((1 << 0)|
2598                                      (1 << 1));
2599                         clone_mask = ((1 << INTEL_OUTPUT_HDMI));
2600                         break;
2601                 case INTEL_OUTPUT_DVO:
2602                 case INTEL_OUTPUT_SDVO:
2603                         crtc_mask = ((1 << 0)|
2604                                      (1 << 1));
2605                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
2606                                       (1 << INTEL_OUTPUT_DVO) |
2607                                       (1 << INTEL_OUTPUT_SDVO));
2608                         break;
2609                 case INTEL_OUTPUT_ANALOG:
2610                         crtc_mask = ((1 << 0)|
2611                                      (1 << 1));
2612                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
2613                                       (1 << INTEL_OUTPUT_DVO) |
2614                                       (1 << INTEL_OUTPUT_SDVO));
2615                         break;
2616                 case INTEL_OUTPUT_LVDS:
2617                         crtc_mask = (1 << 1);
2618                         clone_mask = (1 << INTEL_OUTPUT_LVDS);
2619                         break;
2620                 case INTEL_OUTPUT_TVOUT:
2621                         crtc_mask = ((1 << 0) |
2622                                      (1 << 1));
2623                         clone_mask = (1 << INTEL_OUTPUT_TVOUT);
2624                         break;
2625                 case INTEL_OUTPUT_DISPLAYPORT:
2626                         crtc_mask = ((1 << 0) |
2627                                      (1 << 1));
2628                         clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
2629                         break;
2630                 }
2631                 encoder->possible_crtcs = crtc_mask;
2632                 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
2633         }
2634 }
2635
2636 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
2637 {
2638         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2639         struct drm_device *dev = fb->dev;
2640
2641         if (fb->fbdev)
2642                 intelfb_remove(dev, fb);
2643
2644         drm_framebuffer_cleanup(fb);
2645         mutex_lock(&dev->struct_mutex);
2646         drm_gem_object_unreference(intel_fb->obj);
2647         mutex_unlock(&dev->struct_mutex);
2648
2649         kfree(intel_fb);
2650 }
2651
2652 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
2653                                                 struct drm_file *file_priv,
2654                                                 unsigned int *handle)
2655 {
2656         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2657         struct drm_gem_object *object = intel_fb->obj;
2658
2659         return drm_gem_handle_create(file_priv, object, handle);
2660 }
2661
2662 static const struct drm_framebuffer_funcs intel_fb_funcs = {
2663         .destroy = intel_user_framebuffer_destroy,
2664         .create_handle = intel_user_framebuffer_create_handle,
2665 };
2666
2667 int intel_framebuffer_create(struct drm_device *dev,
2668                              struct drm_mode_fb_cmd *mode_cmd,
2669                              struct drm_framebuffer **fb,
2670                              struct drm_gem_object *obj)
2671 {
2672         struct intel_framebuffer *intel_fb;
2673         int ret;
2674
2675         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2676         if (!intel_fb)
2677                 return -ENOMEM;
2678
2679         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
2680         if (ret) {
2681                 DRM_ERROR("framebuffer init failed %d\n", ret);
2682                 return ret;
2683         }
2684
2685         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
2686
2687         intel_fb->obj = obj;
2688
2689         *fb = &intel_fb->base;
2690
2691         return 0;
2692 }
2693
2694
2695 static struct drm_framebuffer *
2696 intel_user_framebuffer_create(struct drm_device *dev,
2697                               struct drm_file *filp,
2698                               struct drm_mode_fb_cmd *mode_cmd)
2699 {
2700         struct drm_gem_object *obj;
2701         struct drm_framebuffer *fb;
2702         int ret;
2703
2704         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
2705         if (!obj)
2706                 return NULL;
2707
2708         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
2709         if (ret) {
2710                 mutex_lock(&dev->struct_mutex);
2711                 drm_gem_object_unreference(obj);
2712                 mutex_unlock(&dev->struct_mutex);
2713                 return NULL;
2714         }
2715
2716         return fb;
2717 }
2718
2719 static const struct drm_mode_config_funcs intel_mode_funcs = {
2720         .fb_create = intel_user_framebuffer_create,
2721         .fb_changed = intelfb_probe,
2722 };
2723
2724 void intel_modeset_init(struct drm_device *dev)
2725 {
2726         int num_pipe;
2727         int i;
2728
2729         drm_mode_config_init(dev);
2730
2731         dev->mode_config.min_width = 0;
2732         dev->mode_config.min_height = 0;
2733
2734         dev->mode_config.funcs = (void *)&intel_mode_funcs;
2735
2736         if (IS_I965G(dev)) {
2737                 dev->mode_config.max_width = 8192;
2738                 dev->mode_config.max_height = 8192;
2739         } else {
2740                 dev->mode_config.max_width = 2048;
2741                 dev->mode_config.max_height = 2048;
2742         }
2743
2744         /* set memory base */
2745         if (IS_I9XX(dev))
2746                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
2747         else
2748                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
2749
2750         if (IS_MOBILE(dev) || IS_I9XX(dev))
2751                 num_pipe = 2;
2752         else
2753                 num_pipe = 1;
2754         DRM_DEBUG("%d display pipe%s available.\n",
2755                   num_pipe, num_pipe > 1 ? "s" : "");
2756
2757         for (i = 0; i < num_pipe; i++) {
2758                 intel_crtc_init(dev, i);
2759         }
2760
2761         intel_setup_outputs(dev);
2762 }
2763
2764 void intel_modeset_cleanup(struct drm_device *dev)
2765 {
2766         drm_mode_config_cleanup(dev);
2767 }
2768
2769
2770 /* current intel driver doesn't take advantage of encoders
2771    always give back the encoder for the connector
2772 */
2773 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
2774 {
2775         struct intel_output *intel_output = to_intel_output(connector);
2776
2777         return &intel_output->enc;
2778 }