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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 710                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711                      clock.m1++) {
 712                         for (clock.m2 = limit->m2.min;
 713                              clock.m2 <= limit->m2.max; clock.m2++) {
 714                                 /* m1 is always 0 in IGD */
 715                                 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 716                                         break;
 717                                 for (clock.n = limit->n.min;
 718                                      clock.n <= limit->n.max; clock.n++) {
 719                                         int this_err;
 720
 721                                         intel_clock(dev, refclk, &clock);
 722
 723                                         if (!intel_PLL_is_valid(crtc, &clock))
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739
 740 static bool
 741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                             int target, int refclk, intel_clock_t *best_clock)
 743
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         intel_clock_t clock;
 747         int err = target;
 748         bool found = false;
 749
 750         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 751
 752         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 753                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 754                         /* m1 is always 0 in IGD */
 755                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 756                                 break;
 757                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 758                              clock.n++) {
 759                                 int this_err;
 760
 761                                 intel_clock(dev, refclk, &clock);
 762
 763                                 if (!intel_PLL_is_valid(crtc, &clock))
 764                                         continue;
 765
 766                                 this_err = abs(clock.dot - target);
 767                                 if (this_err < err) {
 768                                         *best_clock = clock;
 769                                         err = this_err;
 770                                         found = true;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return found;
 777 }
 778
 779 static bool
 780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 781                         int target, int refclk, intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found;
 788         /* approximately equals target * 0.00488 */
 789         int err_most = (target >> 8) + (target >> 10);
 790         found = false;
 791
 792         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 793                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 794                     LVDS_CLKB_POWER_UP)
 795                         clock.p2 = limit->p2.p2_fast;
 796                 else
 797                         clock.p2 = limit->p2.p2_slow;
 798         } else {
 799                 if (target < limit->p2.dot_limit)
 800                         clock.p2 = limit->p2.p2_slow;
 801                 else
 802                         clock.p2 = limit->p2.p2_fast;
 803         }
 804
 805         memset(best_clock, 0, sizeof(*best_clock));
 806         max_n = limit->n.max;
 807         /* based on hardware requriment prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirment prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         intel_clock(dev, refclk, &clock);
 819                                         if (!intel_PLL_is_valid(crtc, &clock))
 820                                                 continue;
 821                                         this_err = abs(clock.dot - target) ;
 822                                         if (this_err < err_most) {
 823                                                 *best_clock = clock;
 824                                                 err_most = this_err;
 825                                                 max_n = clock.n;
 826                                                 found = true;
 827                                         }
 828                                 }
 829                         }
 830                 }
 831         }
 832         return found;
 833 }
 834
 835 static bool
 836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *best_clock)
 838 {
 839         struct drm_device *dev = crtc->dev;
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.n = 1;
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.m1 = 12;
 846                 clock.m2 = 9;
 847         } else {
 848                 clock.n = 2;
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.m1 = 14;
 852                 clock.m2 = 8;
 853         }
 854         intel_clock(dev, refclk, &clock);
 855         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 856         return true;
 857 }
 858
 859 static bool
 860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found;
 868         int err_most = 47;
 869         found = false;
 870
 871         /* eDP has only 2 clock choice, no n/m/p setting */
 872         if (HAS_eDP)
 873                 return true;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 876                 return intel_find_pll_igdng_dp(limit, crtc, target,
 877                                                refclk, best_clock);
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 881                     LVDS_CLKB_POWER_UP)
 882                         clock.p2 = limit->p2.p2_fast;
 883                 else
 884                         clock.p2 = limit->p2.p2_slow;
 885         } else {
 886                 if (target < limit->p2.dot_limit)
 887                         clock.p2 = limit->p2.p2_slow;
 888                 else
 889                         clock.p2 = limit->p2.p2_fast;
 890         }
 891
 892         memset(best_clock, 0, sizeof(*best_clock));
 893         max_n = limit->n.max;
 894         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 895                 /* based on hardware requriment prefer smaller n to precision */
 896                 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                         /* based on hardware requirment prefere larger m1,m2 */
 898                         for (clock.m1 = limit->m1.max;
 899                              clock.m1 >= limit->m1.min; clock.m1--) {
 900                                 for (clock.m2 = limit->m2.max;
 901                                      clock.m2 >= limit->m2.min; clock.m2--) {
 902                                         int this_err;
 903
 904                                         intel_clock(dev, refclk, &clock);
 905                                         if (!intel_PLL_is_valid(crtc, &clock))
 906                                                 continue;
 907                                         this_err = abs((10000 - (target*10000/clock.dot)));
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                                 /* found on first matching */
 914                                                 goto out;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920 out:
 921         return found;
 922 }
 923
 924 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 925 static bool
 926 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 927                       int target, int refclk, intel_clock_t *best_clock)
 928 {
 929     intel_clock_t clock;
 930     if (target < 200000) {
 931         clock.p1 = 2;
 932         clock.p2 = 10;
 933         clock.n = 2;
 934         clock.m1 = 23;
 935         clock.m2 = 8;
 936     } else {
 937         clock.p1 = 1;
 938         clock.p2 = 10;
 939         clock.n = 1;
 940         clock.m1 = 14;
 941         clock.m2 = 2;
 942     }
 943     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 944     clock.p = (clock.p1 * clock.p2);
 945     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 946     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 947     return true;
 948 }
 949
 950 void
 951 intel_wait_for_vblank(struct drm_device *dev)
 952 {
 953         /* Wait for 20ms, i.e. one cycle at 50hz. */
 954         mdelay(20);
 955 }
 956
 957 /* Parameters have changed, update FBC info */
 958 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 959 {
 960         struct drm_device *dev = crtc->dev;
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         struct drm_framebuffer *fb = crtc->fb;
 963         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 964         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 966         int plane, i;
 967         u32 fbc_ctl, fbc_ctl2;
 968
 969         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 970
 971         if (fb->pitch < dev_priv->cfb_pitch)
 972                 dev_priv->cfb_pitch = fb->pitch;
 973
 974         /* FBC_CTL wants 64B units */
 975         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 976         dev_priv->cfb_fence = obj_priv->fence_reg;
 977         dev_priv->cfb_plane = intel_crtc->plane;
 978         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 979
 980         /* Clear old tags */
 981         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 982                 I915_WRITE(FBC_TAG + (i * 4), 0);
 983
 984         /* Set it up... */
 985         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 986         if (obj_priv->tiling_mode != I915_TILING_NONE)
 987                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 988         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 989         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 990
 991         /* enable it... */
 992         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 993         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 994         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 995         if (obj_priv->tiling_mode != I915_TILING_NONE)
 996                 fbc_ctl |= dev_priv->cfb_fence;
 997         I915_WRITE(FBC_CONTROL, fbc_ctl);
 998
 999         DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1000                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1001 }
1002
1003 void i8xx_disable_fbc(struct drm_device *dev)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         u32 fbc_ctl;
1007
1008         if (!I915_HAS_FBC(dev))
1009                 return;
1010
1011         /* Disable compression */
1012         fbc_ctl = I915_READ(FBC_CONTROL);
1013         fbc_ctl &= ~FBC_CTL_EN;
1014         I915_WRITE(FBC_CONTROL, fbc_ctl);
1015
1016         /* Wait for compressing bit to clear */
1017         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1018                 ; /* nothing */
1019
1020         intel_wait_for_vblank(dev);
1021
1022         DRM_DEBUG("disabled FBC\n");
1023 }
1024
1025 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1026 {
1027         struct drm_device *dev = crtc->dev;
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029
1030         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1031 }
1032
1033 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1034 {
1035         struct drm_device *dev = crtc->dev;
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037         struct drm_framebuffer *fb = crtc->fb;
1038         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1039         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1041         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1042                      DPFC_CTL_PLANEB);
1043         unsigned long stall_watermark = 200;
1044         u32 dpfc_ctl;
1045
1046         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1047         dev_priv->cfb_fence = obj_priv->fence_reg;
1048         dev_priv->cfb_plane = intel_crtc->plane;
1049
1050         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1051         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1052                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1053                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1054         } else {
1055                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1056         }
1057
1058         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1059         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1060                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1061                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1062         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1063
1064         /* enable it... */
1065         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1066
1067         DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
1068 }
1069
1070 void g4x_disable_fbc(struct drm_device *dev)
1071 {
1072         struct drm_i915_private *dev_priv = dev->dev_private;
1073         u32 dpfc_ctl;
1074
1075         /* Disable compression */
1076         dpfc_ctl = I915_READ(DPFC_CONTROL);
1077         dpfc_ctl &= ~DPFC_CTL_EN;
1078         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1079         intel_wait_for_vblank(dev);
1080
1081         DRM_DEBUG("disabled FBC\n");
1082 }
1083
1084 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1085 {
1086         struct drm_device *dev = crtc->dev;
1087         struct drm_i915_private *dev_priv = dev->dev_private;
1088
1089         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1090 }
1091
1092 /**
1093  * intel_update_fbc - enable/disable FBC as needed
1094  * @crtc: CRTC to point the compressor at
1095  * @mode: mode in use
1096  *
1097  * Set up the framebuffer compression hardware at mode set time.  We
1098  * enable it if possible:
1099  *   - plane A only (on pre-965)
1100  *   - no pixel mulitply/line duplication
1101  *   - no alpha buffer discard
1102  *   - no dual wide
1103  *   - framebuffer <= 2048 in width, 1536 in height
1104  *
1105  * We can't assume that any compression will take place (worst case),
1106  * so the compressed buffer has to be the same size as the uncompressed
1107  * one.  It also must reside (along with the line length buffer) in
1108  * stolen memory.
1109  *
1110  * We need to enable/disable FBC on a global basis.
1111  */
1112 static void intel_update_fbc(struct drm_crtc *crtc,
1113                              struct drm_display_mode *mode)
1114 {
1115         struct drm_device *dev = crtc->dev;
1116         struct drm_i915_private *dev_priv = dev->dev_private;
1117         struct drm_framebuffer *fb = crtc->fb;
1118         struct intel_framebuffer *intel_fb;
1119         struct drm_i915_gem_object *obj_priv;
1120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1121         int plane = intel_crtc->plane;
1122
1123         if (!i915_powersave)
1124                 return;
1125
1126         if (!dev_priv->display.fbc_enabled ||
1127             !dev_priv->display.enable_fbc ||
1128             !dev_priv->display.disable_fbc)
1129                 return;
1130
1131         if (!crtc->fb)
1132                 return;
1133
1134         intel_fb = to_intel_framebuffer(fb);
1135         obj_priv = intel_fb->obj->driver_private;
1136
1137         /*
1138          * If FBC is already on, we just have to verify that we can
1139          * keep it that way...
1140          * Need to disable if:
1141          *   - changing FBC params (stride, fence, mode)
1142          *   - new fb is too large to fit in compressed buffer
1143          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1144          */
1145         if (intel_fb->obj->size > dev_priv->cfb_size) {
1146                 DRM_DEBUG("framebuffer too large, disabling compression\n");
1147                 goto out_disable;
1148         }
1149         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151                 DRM_DEBUG("mode incompatible with compression, disabling\n");
1152                 goto out_disable;
1153         }
1154         if ((mode->hdisplay > 2048) ||
1155             (mode->vdisplay > 1536)) {
1156                 DRM_DEBUG("mode too large for compression, disabling\n");
1157                 goto out_disable;
1158         }
1159         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1160                 DRM_DEBUG("plane not 0, disabling compression\n");
1161                 goto out_disable;
1162         }
1163         if (obj_priv->tiling_mode != I915_TILING_X) {
1164                 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1165                 goto out_disable;
1166         }
1167
1168         if (dev_priv->display.fbc_enabled(crtc)) {
1169                 /* We can re-enable it in this case, but need to update pitch */
1170                 if (fb->pitch > dev_priv->cfb_pitch)
1171                         dev_priv->display.disable_fbc(dev);
1172                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1173                         dev_priv->display.disable_fbc(dev);
1174                 if (plane != dev_priv->cfb_plane)
1175                         dev_priv->display.disable_fbc(dev);
1176         }
1177
1178         if (!dev_priv->display.fbc_enabled(crtc)) {
1179                 /* Now try to turn it back on if possible */
1180                 dev_priv->display.enable_fbc(crtc, 500);
1181         }
1182
1183         return;
1184
1185 out_disable:
1186         DRM_DEBUG("unsupported config, disabling FBC\n");
1187         /* Multiple disables should be harmless */
1188         if (dev_priv->display.fbc_enabled(crtc))
1189                 dev_priv->display.disable_fbc(dev);
1190 }
1191
1192 static int
1193 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1194                     struct drm_framebuffer *old_fb)
1195 {
1196         struct drm_device *dev = crtc->dev;
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         struct drm_i915_master_private *master_priv;
1199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1200         struct intel_framebuffer *intel_fb;
1201         struct drm_i915_gem_object *obj_priv;
1202         struct drm_gem_object *obj;
1203         int pipe = intel_crtc->pipe;
1204         int plane = intel_crtc->plane;
1205         unsigned long Start, Offset;
1206         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1207         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1208         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1209         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1210         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1211         u32 dspcntr, alignment;
1212         int ret;
1213
1214         /* no fb bound */
1215         if (!crtc->fb) {
1216                 DRM_DEBUG("No FB bound\n");
1217                 return 0;
1218         }
1219
1220         switch (plane) {
1221         case 0:
1222         case 1:
1223                 break;
1224         default:
1225                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1226                 return -EINVAL;
1227         }
1228
1229         intel_fb = to_intel_framebuffer(crtc->fb);
1230         obj = intel_fb->obj;
1231         obj_priv = obj->driver_private;
1232
1233         switch (obj_priv->tiling_mode) {
1234         case I915_TILING_NONE:
1235                 alignment = 64 * 1024;
1236                 break;
1237         case I915_TILING_X:
1238                 /* pin() will align the object as required by fence */
1239                 alignment = 0;
1240                 break;
1241         case I915_TILING_Y:
1242                 /* FIXME: Is this true? */
1243                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1244                 return -EINVAL;
1245         default:
1246                 BUG();
1247         }
1248
1249         mutex_lock(&dev->struct_mutex);
1250         ret = i915_gem_object_pin(obj, alignment);
1251         if (ret != 0) {
1252                 mutex_unlock(&dev->struct_mutex);
1253                 return ret;
1254         }
1255
1256         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1257         if (ret != 0) {
1258                 i915_gem_object_unpin(obj);
1259                 mutex_unlock(&dev->struct_mutex);
1260                 return ret;
1261         }
1262
1263         /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1264          * whereas 965+ only requires a fence if using framebuffer compression.
1265          * For simplicity, we always install a fence as the cost is not that onerous.
1266          */
1267         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1268             obj_priv->tiling_mode != I915_TILING_NONE) {
1269                 ret = i915_gem_object_get_fence_reg(obj);
1270                 if (ret != 0) {
1271                         i915_gem_object_unpin(obj);
1272                         mutex_unlock(&dev->struct_mutex);
1273                         return ret;
1274                 }
1275         }
1276
1277         dspcntr = I915_READ(dspcntr_reg);
1278         /* Mask out pixel format bits in case we change it */
1279         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1280         switch (crtc->fb->bits_per_pixel) {
1281         case 8:
1282                 dspcntr |= DISPPLANE_8BPP;
1283                 break;
1284         case 16:
1285                 if (crtc->fb->depth == 15)
1286                         dspcntr |= DISPPLANE_15_16BPP;
1287                 else
1288                         dspcntr |= DISPPLANE_16BPP;
1289                 break;
1290         case 24:
1291         case 32:
1292                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1293                 break;
1294         default:
1295                 DRM_ERROR("Unknown color depth\n");
1296                 i915_gem_object_unpin(obj);
1297                 mutex_unlock(&dev->struct_mutex);
1298                 return -EINVAL;
1299         }
1300         if (IS_I965G(dev)) {
1301                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1302                         dspcntr |= DISPPLANE_TILED;
1303                 else
1304                         dspcntr &= ~DISPPLANE_TILED;
1305         }
1306
1307         if (IS_IGDNG(dev))
1308                 /* must disable */
1309                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1310
1311         I915_WRITE(dspcntr_reg, dspcntr);
1312
1313         Start = obj_priv->gtt_offset;
1314         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1315
1316         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1317         I915_WRITE(dspstride, crtc->fb->pitch);
1318         if (IS_I965G(dev)) {
1319                 I915_WRITE(dspbase, Offset);
1320                 I915_READ(dspbase);
1321                 I915_WRITE(dspsurf, Start);
1322                 I915_READ(dspsurf);
1323                 I915_WRITE(dsptileoff, (y << 16) | x);
1324         } else {
1325                 I915_WRITE(dspbase, Start + Offset);
1326                 I915_READ(dspbase);
1327         }
1328
1329         if ((IS_I965G(dev) || plane == 0))
1330                 intel_update_fbc(crtc, &crtc->mode);
1331
1332         intel_wait_for_vblank(dev);
1333
1334         if (old_fb) {
1335                 intel_fb = to_intel_framebuffer(old_fb);
1336                 obj_priv = intel_fb->obj->driver_private;
1337                 i915_gem_object_unpin(intel_fb->obj);
1338         }
1339         intel_increase_pllclock(crtc, true);
1340
1341         mutex_unlock(&dev->struct_mutex);
1342
1343         if (!dev->primary->master)
1344                 return 0;
1345
1346         master_priv = dev->primary->master->driver_priv;
1347         if (!master_priv->sarea_priv)
1348                 return 0;
1349
1350         if (pipe) {
1351                 master_priv->sarea_priv->pipeB_x = x;
1352                 master_priv->sarea_priv->pipeB_y = y;
1353         } else {
1354                 master_priv->sarea_priv->pipeA_x = x;
1355                 master_priv->sarea_priv->pipeA_y = y;
1356         }
1357
1358         return 0;
1359 }
1360
1361 /* Disable the VGA plane that we never use */
1362 static void i915_disable_vga (struct drm_device *dev)
1363 {
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         u8 sr1;
1366         u32 vga_reg;
1367
1368         if (IS_IGDNG(dev))
1369                 vga_reg = CPU_VGACNTRL;
1370         else
1371                 vga_reg = VGACNTRL;
1372
1373         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1374                 return;
1375
1376         I915_WRITE8(VGA_SR_INDEX, 1);
1377         sr1 = I915_READ8(VGA_SR_DATA);
1378         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1379         udelay(100);
1380
1381         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1382 }
1383
1384 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1385 {
1386         struct drm_device *dev = crtc->dev;
1387         struct drm_i915_private *dev_priv = dev->dev_private;
1388         u32 dpa_ctl;
1389
1390         DRM_DEBUG("\n");
1391         dpa_ctl = I915_READ(DP_A);
1392         dpa_ctl &= ~DP_PLL_ENABLE;
1393         I915_WRITE(DP_A, dpa_ctl);
1394 }
1395
1396 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1397 {
1398         struct drm_device *dev = crtc->dev;
1399         struct drm_i915_private *dev_priv = dev->dev_private;
1400         u32 dpa_ctl;
1401
1402         dpa_ctl = I915_READ(DP_A);
1403         dpa_ctl |= DP_PLL_ENABLE;
1404         I915_WRITE(DP_A, dpa_ctl);
1405         udelay(200);
1406 }
1407
1408
1409 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1410 {
1411         struct drm_device *dev = crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         u32 dpa_ctl;
1414
1415         DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1416         dpa_ctl = I915_READ(DP_A);
1417         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1418
1419         if (clock < 200000) {
1420                 u32 temp;
1421                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1422                 /* workaround for 160Mhz:
1423                    1) program 0x4600c bits 15:0 = 0x8124
1424                    2) program 0x46010 bit 0 = 1
1425                    3) program 0x46034 bit 24 = 1
1426                    4) program 0x64000 bit 14 = 1
1427                    */
1428                 temp = I915_READ(0x4600c);
1429                 temp &= 0xffff0000;
1430                 I915_WRITE(0x4600c, temp | 0x8124);
1431
1432                 temp = I915_READ(0x46010);
1433                 I915_WRITE(0x46010, temp | 1);
1434
1435                 temp = I915_READ(0x46034);
1436                 I915_WRITE(0x46034, temp | (1 << 24));
1437         } else {
1438                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1439         }
1440         I915_WRITE(DP_A, dpa_ctl);
1441
1442         udelay(500);
1443 }
1444
1445 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1446 {
1447         struct drm_device *dev = crtc->dev;
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450         int pipe = intel_crtc->pipe;
1451         int plane = intel_crtc->plane;
1452         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1453         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1454         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1455         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1456         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1457         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1458         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1459         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1460         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1461         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1462         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1463         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1464         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1465         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1466         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1467         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1468         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1469         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1470         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1471         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1472         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1473         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1474         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1475         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1476         u32 temp;
1477         int tries = 5, j, n;
1478
1479         /* XXX: When our outputs are all unaware of DPMS modes other than off
1480          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1481          */
1482         switch (mode) {
1483         case DRM_MODE_DPMS_ON:
1484         case DRM_MODE_DPMS_STANDBY:
1485         case DRM_MODE_DPMS_SUSPEND:
1486                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1487                 if (HAS_eDP) {
1488                         /* enable eDP PLL */
1489                         igdng_enable_pll_edp(crtc);
1490                 } else {
1491                         /* enable PCH DPLL */
1492                         temp = I915_READ(pch_dpll_reg);
1493                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1494                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1495                                 I915_READ(pch_dpll_reg);
1496                         }
1497
1498                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1499                         temp = I915_READ(fdi_rx_reg);
1500                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1501                                         FDI_SEL_PCDCLK |
1502                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1503                         I915_READ(fdi_rx_reg);
1504                         udelay(200);
1505
1506                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1507                         temp = I915_READ(fdi_tx_reg);
1508                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1509                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1510                                 I915_READ(fdi_tx_reg);
1511                                 udelay(100);
1512                         }
1513                 }
1514
1515                 /* Enable panel fitting for LVDS */
1516                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1517                         temp = I915_READ(pf_ctl_reg);
1518                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1519
1520                         /* currently full aspect */
1521                         I915_WRITE(pf_win_pos, 0);
1522
1523                         I915_WRITE(pf_win_size,
1524                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1525                                    (dev_priv->panel_fixed_mode->vdisplay));
1526                 }
1527
1528                 /* Enable CPU pipe */
1529                 temp = I915_READ(pipeconf_reg);
1530                 if ((temp & PIPEACONF_ENABLE) == 0) {
1531                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1532                         I915_READ(pipeconf_reg);
1533                         udelay(100);
1534                 }
1535
1536                 /* configure and enable CPU plane */
1537                 temp = I915_READ(dspcntr_reg);
1538                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1539                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1540                         /* Flush the plane changes */
1541                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1542                 }
1543
1544                 if (!HAS_eDP) {
1545                         /* enable CPU FDI TX and PCH FDI RX */
1546                         temp = I915_READ(fdi_tx_reg);
1547                         temp |= FDI_TX_ENABLE;
1548                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1549                         temp &= ~FDI_LINK_TRAIN_NONE;
1550                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1551                         I915_WRITE(fdi_tx_reg, temp);
1552                         I915_READ(fdi_tx_reg);
1553
1554                         temp = I915_READ(fdi_rx_reg);
1555                         temp &= ~FDI_LINK_TRAIN_NONE;
1556                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1557                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1558                         I915_READ(fdi_rx_reg);
1559
1560                         udelay(150);
1561
1562                         /* Train FDI. */
1563                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1564                            for train result */
1565                         temp = I915_READ(fdi_rx_imr_reg);
1566                         temp &= ~FDI_RX_SYMBOL_LOCK;
1567                         temp &= ~FDI_RX_BIT_LOCK;
1568                         I915_WRITE(fdi_rx_imr_reg, temp);
1569                         I915_READ(fdi_rx_imr_reg);
1570                         udelay(150);
1571
1572                         temp = I915_READ(fdi_rx_iir_reg);
1573                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1574
1575                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1576                                 for (j = 0; j < tries; j++) {
1577                                         temp = I915_READ(fdi_rx_iir_reg);
1578                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1579                                         if (temp & FDI_RX_BIT_LOCK)
1580                                                 break;
1581                                         udelay(200);
1582                                 }
1583                                 if (j != tries)
1584                                         I915_WRITE(fdi_rx_iir_reg,
1585                                                         temp | FDI_RX_BIT_LOCK);
1586                                 else
1587                                         DRM_DEBUG("train 1 fail\n");
1588                         } else {
1589                                 I915_WRITE(fdi_rx_iir_reg,
1590                                                 temp | FDI_RX_BIT_LOCK);
1591                                 DRM_DEBUG("train 1 ok 2!\n");
1592                         }
1593                         temp = I915_READ(fdi_tx_reg);
1594                         temp &= ~FDI_LINK_TRAIN_NONE;
1595                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1596                         I915_WRITE(fdi_tx_reg, temp);
1597
1598                         temp = I915_READ(fdi_rx_reg);
1599                         temp &= ~FDI_LINK_TRAIN_NONE;
1600                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1601                         I915_WRITE(fdi_rx_reg, temp);
1602
1603                         udelay(150);
1604
1605                         temp = I915_READ(fdi_rx_iir_reg);
1606                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1607
1608                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1609                                 for (j = 0; j < tries; j++) {
1610                                         temp = I915_READ(fdi_rx_iir_reg);
1611                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1612                                         if (temp & FDI_RX_SYMBOL_LOCK)
1613                                                 break;
1614                                         udelay(200);
1615                                 }
1616                                 if (j != tries) {
1617                                         I915_WRITE(fdi_rx_iir_reg,
1618                                                         temp | FDI_RX_SYMBOL_LOCK);
1619                                         DRM_DEBUG("train 2 ok 1!\n");
1620                                 } else
1621                                         DRM_DEBUG("train 2 fail\n");
1622                         } else {
1623                                 I915_WRITE(fdi_rx_iir_reg,
1624                                                 temp | FDI_RX_SYMBOL_LOCK);
1625                                 DRM_DEBUG("train 2 ok 2!\n");
1626                         }
1627                         DRM_DEBUG("train done\n");
1628
1629                         /* set transcoder timing */
1630                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1631                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1632                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1633
1634                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1635                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1636                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1637
1638                         /* enable PCH transcoder */
1639                         temp = I915_READ(transconf_reg);
1640                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1641                         I915_READ(transconf_reg);
1642
1643                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1644                                 ;
1645
1646                         /* enable normal */
1647
1648                         temp = I915_READ(fdi_tx_reg);
1649                         temp &= ~FDI_LINK_TRAIN_NONE;
1650                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1651                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1652                         I915_READ(fdi_tx_reg);
1653
1654                         temp = I915_READ(fdi_rx_reg);
1655                         temp &= ~FDI_LINK_TRAIN_NONE;
1656                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1657                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1658                         I915_READ(fdi_rx_reg);
1659
1660                         /* wait one idle pattern time */
1661                         udelay(100);
1662
1663                 }
1664
1665                 intel_crtc_load_lut(crtc);
1666
1667         break;
1668         case DRM_MODE_DPMS_OFF:
1669                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1670
1671                 i915_disable_vga(dev);
1672
1673                 /* Disable display plane */
1674                 temp = I915_READ(dspcntr_reg);
1675                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1676                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1677                         /* Flush the plane changes */
1678                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1679                         I915_READ(dspbase_reg);
1680                 }
1681
1682                 /* disable cpu pipe, disable after all planes disabled */
1683                 temp = I915_READ(pipeconf_reg);
1684                 if ((temp & PIPEACONF_ENABLE) != 0) {
1685                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1686                         I915_READ(pipeconf_reg);
1687                         n = 0;
1688                         /* wait for cpu pipe off, pipe state */
1689                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1690                                 n++;
1691                                 if (n < 60) {
1692                                         udelay(500);
1693                                         continue;
1694                                 } else {
1695                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1696                                         break;
1697                                 }
1698                         }
1699                 } else
1700                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1701
1702                 if (HAS_eDP) {
1703                         igdng_disable_pll_edp(crtc);
1704                 }
1705
1706                 /* disable CPU FDI tx and PCH FDI rx */
1707                 temp = I915_READ(fdi_tx_reg);
1708                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1709                 I915_READ(fdi_tx_reg);
1710
1711                 temp = I915_READ(fdi_rx_reg);
1712                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1713                 I915_READ(fdi_rx_reg);
1714
1715                 udelay(100);
1716
1717                 /* still set train pattern 1 */
1718                 temp = I915_READ(fdi_tx_reg);
1719                 temp &= ~FDI_LINK_TRAIN_NONE;
1720                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1721                 I915_WRITE(fdi_tx_reg, temp);
1722
1723                 temp = I915_READ(fdi_rx_reg);
1724                 temp &= ~FDI_LINK_TRAIN_NONE;
1725                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1726                 I915_WRITE(fdi_rx_reg, temp);
1727
1728                 udelay(100);
1729
1730                 /* disable PCH transcoder */
1731                 temp = I915_READ(transconf_reg);
1732                 if ((temp & TRANS_ENABLE) != 0) {
1733                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1734                         I915_READ(transconf_reg);
1735                         n = 0;
1736                         /* wait for PCH transcoder off, transcoder state */
1737                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1738                                 n++;
1739                                 if (n < 60) {
1740                                         udelay(500);
1741                                         continue;
1742                                 } else {
1743                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1744                                         break;
1745                                 }
1746                         }
1747                 }
1748
1749                 /* disable PCH DPLL */
1750                 temp = I915_READ(pch_dpll_reg);
1751                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1752                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1753                         I915_READ(pch_dpll_reg);
1754                 }
1755
1756                 temp = I915_READ(fdi_rx_reg);
1757                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1758                         temp &= ~FDI_SEL_PCDCLK;
1759                         temp &= ~FDI_RX_PLL_ENABLE;
1760                         I915_WRITE(fdi_rx_reg, temp);
1761                         I915_READ(fdi_rx_reg);
1762                 }
1763
1764                 /* Disable CPU FDI TX PLL */
1765                 temp = I915_READ(fdi_tx_reg);
1766                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1767                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1768                         I915_READ(fdi_tx_reg);
1769                         udelay(100);
1770                 }
1771
1772                 /* Disable PF */
1773                 temp = I915_READ(pf_ctl_reg);
1774                 if ((temp & PF_ENABLE) != 0) {
1775                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1776                         I915_READ(pf_ctl_reg);
1777                 }
1778                 I915_WRITE(pf_win_size, 0);
1779
1780                 /* Wait for the clocks to turn off. */
1781                 udelay(150);
1782                 break;
1783         }
1784 }
1785
1786 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1787 {
1788         struct drm_device *dev = crtc->dev;
1789         struct drm_i915_private *dev_priv = dev->dev_private;
1790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1791         int pipe = intel_crtc->pipe;
1792         int plane = intel_crtc->plane;
1793         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1794         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1795         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1796         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1797         u32 temp;
1798
1799         /* XXX: When our outputs are all unaware of DPMS modes other than off
1800          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1801          */
1802         switch (mode) {
1803         case DRM_MODE_DPMS_ON:
1804         case DRM_MODE_DPMS_STANDBY:
1805         case DRM_MODE_DPMS_SUSPEND:
1806                 /* Enable the DPLL */
1807                 temp = I915_READ(dpll_reg);
1808                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1809                         I915_WRITE(dpll_reg, temp);
1810                         I915_READ(dpll_reg);
1811                         /* Wait for the clocks to stabilize. */
1812                         udelay(150);
1813                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1814                         I915_READ(dpll_reg);
1815                         /* Wait for the clocks to stabilize. */
1816                         udelay(150);
1817                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1818                         I915_READ(dpll_reg);
1819                         /* Wait for the clocks to stabilize. */
1820                         udelay(150);
1821                 }
1822
1823                 /* Enable the pipe */
1824                 temp = I915_READ(pipeconf_reg);
1825                 if ((temp & PIPEACONF_ENABLE) == 0)
1826                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1827
1828                 /* Enable the plane */
1829                 temp = I915_READ(dspcntr_reg);
1830                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1831                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1832                         /* Flush the plane changes */
1833                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1834                 }
1835
1836                 intel_crtc_load_lut(crtc);
1837
1838                 if ((IS_I965G(dev) || plane == 0))
1839                         intel_update_fbc(crtc, &crtc->mode);
1840
1841                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1842                 //intel_crtc_dpms_video(crtc, true); TODO
1843                 intel_update_watermarks(dev);
1844         break;
1845         case DRM_MODE_DPMS_OFF:
1846                 intel_update_watermarks(dev);
1847                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1848                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1849
1850                 if (dev_priv->cfb_plane == plane &&
1851                     dev_priv->display.disable_fbc)
1852                         dev_priv->display.disable_fbc(dev);
1853
1854                 /* Disable the VGA plane that we never use */
1855                 i915_disable_vga(dev);
1856
1857                 /* Disable display plane */
1858                 temp = I915_READ(dspcntr_reg);
1859                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1860                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1861                         /* Flush the plane changes */
1862                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1863                         I915_READ(dspbase_reg);
1864                 }
1865
1866                 if (!IS_I9XX(dev)) {
1867                         /* Wait for vblank for the disable to take effect */
1868                         intel_wait_for_vblank(dev);
1869                 }
1870
1871                 /* Next, disable display pipes */
1872                 temp = I915_READ(pipeconf_reg);
1873                 if ((temp & PIPEACONF_ENABLE) != 0) {
1874                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1875                         I915_READ(pipeconf_reg);
1876                 }
1877
1878                 /* Wait for vblank for the disable to take effect. */
1879                 intel_wait_for_vblank(dev);
1880
1881                 temp = I915_READ(dpll_reg);
1882                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1883                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1884                         I915_READ(dpll_reg);
1885                 }
1886
1887                 /* Wait for the clocks to turn off. */
1888                 udelay(150);
1889                 break;
1890         }
1891 }
1892
1893 /**
1894  * Sets the power management mode of the pipe and plane.
1895  *
1896  * This code should probably grow support for turning the cursor off and back
1897  * on appropriately at the same time as we're turning the pipe off/on.
1898  */
1899 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1900 {
1901         struct drm_device *dev = crtc->dev;
1902         struct drm_i915_private *dev_priv = dev->dev_private;
1903         struct drm_i915_master_private *master_priv;
1904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905         int pipe = intel_crtc->pipe;
1906         bool enabled;
1907
1908         dev_priv->display.dpms(crtc, mode);
1909
1910         intel_crtc->dpms_mode = mode;
1911
1912         if (!dev->primary->master)
1913                 return;
1914
1915         master_priv = dev->primary->master->driver_priv;
1916         if (!master_priv->sarea_priv)
1917                 return;
1918
1919         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1920
1921         switch (pipe) {
1922         case 0:
1923                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1924                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1925                 break;
1926         case 1:
1927                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1928                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1929                 break;
1930         default:
1931                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1932                 break;
1933         }
1934 }
1935
1936 static void intel_crtc_prepare (struct drm_crtc *crtc)
1937 {
1938         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1939         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1940 }
1941
1942 static void intel_crtc_commit (struct drm_crtc *crtc)
1943 {
1944         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1945         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1946 }
1947
1948 void intel_encoder_prepare (struct drm_encoder *encoder)
1949 {
1950         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1951         /* lvds has its own version of prepare see intel_lvds_prepare */
1952         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1953 }
1954
1955 void intel_encoder_commit (struct drm_encoder *encoder)
1956 {
1957         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1958         /* lvds has its own version of commit see intel_lvds_commit */
1959         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1960 }
1961
1962 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1963                                   struct drm_display_mode *mode,
1964                                   struct drm_display_mode *adjusted_mode)
1965 {
1966         struct drm_device *dev = crtc->dev;
1967         if (IS_IGDNG(dev)) {
1968                 /* FDI link clock is fixed at 2.7G */
1969                 if (mode->clock * 3 > 27000 * 4)
1970                         return MODE_CLOCK_HIGH;
1971         }
1972         return true;
1973 }
1974
1975 static int i945_get_display_clock_speed(struct drm_device *dev)
1976 {
1977         return 400000;
1978 }
1979
1980 static int i915_get_display_clock_speed(struct drm_device *dev)
1981 {
1982         return 333000;
1983 }
1984
1985 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
1986 {
1987         return 200000;
1988 }
1989
1990 static int i915gm_get_display_clock_speed(struct drm_device *dev)
1991 {
1992         u16 gcfgc = 0;
1993
1994         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1995
1996         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1997                 return 133000;
1998         else {
1999                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2000                 case GC_DISPLAY_CLOCK_333_MHZ:
2001                         return 333000;
2002                 default:
2003                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2004                         return 190000;
2005                 }
2006         }
2007 }
2008
2009 static int i865_get_display_clock_speed(struct drm_device *dev)
2010 {
2011         return 266000;
2012 }
2013
2014 static int i855_get_display_clock_speed(struct drm_device *dev)
2015 {
2016         u16 hpllcc = 0;
2017         /* Assume that the hardware is in the high speed state.  This
2018          * should be the default.
2019          */
2020         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2021         case GC_CLOCK_133_200:
2022         case GC_CLOCK_100_200:
2023                 return 200000;
2024         case GC_CLOCK_166_250:
2025                 return 250000;
2026         case GC_CLOCK_100_133:
2027                 return 133000;
2028         }
2029
2030         /* Shouldn't happen */
2031         return 0;
2032 }
2033
2034 static int i830_get_display_clock_speed(struct drm_device *dev)
2035 {
2036         return 133000;
2037 }
2038
2039 /**
2040  * Return the pipe currently connected to the panel fitter,
2041  * or -1 if the panel fitter is not present or not in use
2042  */
2043 static int intel_panel_fitter_pipe (struct drm_device *dev)
2044 {
2045         struct drm_i915_private *dev_priv = dev->dev_private;
2046         u32  pfit_control;
2047
2048         /* i830 doesn't have a panel fitter */
2049         if (IS_I830(dev))
2050                 return -1;
2051
2052         pfit_control = I915_READ(PFIT_CONTROL);
2053
2054         /* See if the panel fitter is in use */
2055         if ((pfit_control & PFIT_ENABLE) == 0)
2056                 return -1;
2057
2058         /* 965 can place panel fitter on either pipe */
2059         if (IS_I965G(dev))
2060                 return (pfit_control >> 29) & 0x3;
2061
2062         /* older chips can only use pipe 1 */
2063         return 1;
2064 }
2065
2066 struct fdi_m_n {
2067         u32        tu;
2068         u32        gmch_m;
2069         u32        gmch_n;
2070         u32        link_m;
2071         u32        link_n;
2072 };
2073
2074 static void
2075 fdi_reduce_ratio(u32 *num, u32 *den)
2076 {
2077         while (*num > 0xffffff || *den > 0xffffff) {
2078                 *num >>= 1;
2079                 *den >>= 1;
2080         }
2081 }
2082
2083 #define DATA_N 0x800000
2084 #define LINK_N 0x80000
2085
2086 static void
2087 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2088                 int pixel_clock, int link_clock,
2089                 struct fdi_m_n *m_n)
2090 {
2091         u64 temp;
2092
2093         m_n->tu = 64; /* default size */
2094
2095         temp = (u64) DATA_N * pixel_clock;
2096         temp = div_u64(temp, link_clock);
2097         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2098         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2099         m_n->gmch_n = DATA_N;
2100         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2101
2102         temp = (u64) LINK_N * pixel_clock;
2103         m_n->link_m = div_u64(temp, link_clock);
2104         m_n->link_n = LINK_N;
2105         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2106 }
2107
2108
2109 struct intel_watermark_params {
2110         unsigned long fifo_size;
2111         unsigned long max_wm;
2112         unsigned long default_wm;
2113         unsigned long guard_size;
2114         unsigned long cacheline_size;
2115 };
2116
2117 /* IGD has different values for various configs */
2118 static struct intel_watermark_params igd_display_wm = {
2119         IGD_DISPLAY_FIFO,
2120         IGD_MAX_WM,
2121         IGD_DFT_WM,
2122         IGD_GUARD_WM,
2123         IGD_FIFO_LINE_SIZE
2124 };
2125 static struct intel_watermark_params igd_display_hplloff_wm = {
2126         IGD_DISPLAY_FIFO,
2127         IGD_MAX_WM,
2128         IGD_DFT_HPLLOFF_WM,
2129         IGD_GUARD_WM,
2130         IGD_FIFO_LINE_SIZE
2131 };
2132 static struct intel_watermark_params igd_cursor_wm = {
2133         IGD_CURSOR_FIFO,
2134         IGD_CURSOR_MAX_WM,
2135         IGD_CURSOR_DFT_WM,
2136         IGD_CURSOR_GUARD_WM,
2137         IGD_FIFO_LINE_SIZE,
2138 };
2139 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2140         IGD_CURSOR_FIFO,
2141         IGD_CURSOR_MAX_WM,
2142         IGD_CURSOR_DFT_WM,
2143         IGD_CURSOR_GUARD_WM,
2144         IGD_FIFO_LINE_SIZE
2145 };
2146 static struct intel_watermark_params g4x_wm_info = {
2147         G4X_FIFO_SIZE,
2148         G4X_MAX_WM,
2149         G4X_MAX_WM,
2150         2,
2151         G4X_FIFO_LINE_SIZE,
2152 };
2153 static struct intel_watermark_params i945_wm_info = {
2154         I945_FIFO_SIZE,
2155         I915_MAX_WM,
2156         1,
2157         2,
2158         I915_FIFO_LINE_SIZE
2159 };
2160 static struct intel_watermark_params i915_wm_info = {
2161         I915_FIFO_SIZE,
2162         I915_MAX_WM,
2163         1,
2164         2,
2165         I915_FIFO_LINE_SIZE
2166 };
2167 static struct intel_watermark_params i855_wm_info = {
2168         I855GM_FIFO_SIZE,
2169         I915_MAX_WM,
2170         1,
2171         2,
2172         I830_FIFO_LINE_SIZE
2173 };
2174 static struct intel_watermark_params i830_wm_info = {
2175         I830_FIFO_SIZE,
2176         I915_MAX_WM,
2177         1,
2178         2,
2179         I830_FIFO_LINE_SIZE
2180 };
2181
2182 /**
2183  * intel_calculate_wm - calculate watermark level
2184  * @clock_in_khz: pixel clock
2185  * @wm: chip FIFO params
2186  * @pixel_size: display pixel size
2187  * @latency_ns: memory latency for the platform
2188  *
2189  * Calculate the watermark level (the level at which the display plane will
2190  * start fetching from memory again).  Each chip has a different display
2191  * FIFO size and allocation, so the caller needs to figure that out and pass
2192  * in the correct intel_watermark_params structure.
2193  *
2194  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2195  * on the pixel size.  When it reaches the watermark level, it'll start
2196  * fetching FIFO line sized based chunks from memory until the FIFO fills
2197  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2198  * will occur, and a display engine hang could result.
2199  */
2200 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2201                                         struct intel_watermark_params *wm,
2202                                         int pixel_size,
2203                                         unsigned long latency_ns)
2204 {
2205         long entries_required, wm_size;
2206
2207         /*
2208          * Note: we need to make sure we don't overflow for various clock &
2209          * latency values.
2210          * clocks go from a few thousand to several hundred thousand.
2211          * latency is usually a few thousand
2212          */
2213         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2214                 1000;
2215         entries_required /= wm->cacheline_size;
2216
2217         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2218
2219         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2220
2221         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2222
2223         /* Don't promote wm_size to unsigned... */
2224         if (wm_size > (long)wm->max_wm)
2225                 wm_size = wm->max_wm;
2226         if (wm_size <= 0)
2227                 wm_size = wm->default_wm;
2228         return wm_size;
2229 }
2230
2231 struct cxsr_latency {
2232         int is_desktop;
2233         unsigned long fsb_freq;
2234         unsigned long mem_freq;
2235         unsigned long display_sr;
2236         unsigned long display_hpll_disable;
2237         unsigned long cursor_sr;
2238         unsigned long cursor_hpll_disable;
2239 };
2240
2241 static struct cxsr_latency cxsr_latency_table[] = {
2242         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2243         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2244         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2245
2246         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2247         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2248         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2249
2250         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2251         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2252         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2253
2254         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2255         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2256         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2257
2258         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2259         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2260         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2261
2262         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2263         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2264         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2265 };
2266
2267 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2268                                                    int mem)
2269 {
2270         int i;
2271         struct cxsr_latency *latency;
2272
2273         if (fsb == 0 || mem == 0)
2274                 return NULL;
2275
2276         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2277                 latency = &cxsr_latency_table[i];
2278                 if (is_desktop == latency->is_desktop &&
2279                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2280                         return latency;
2281         }
2282
2283         DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2284
2285         return NULL;
2286 }
2287
2288 static void igd_disable_cxsr(struct drm_device *dev)
2289 {
2290         struct drm_i915_private *dev_priv = dev->dev_private;
2291         u32 reg;
2292
2293         /* deactivate cxsr */
2294         reg = I915_READ(DSPFW3);
2295         reg &= ~(IGD_SELF_REFRESH_EN);
2296         I915_WRITE(DSPFW3, reg);
2297         DRM_INFO("Big FIFO is disabled\n");
2298 }
2299
2300 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2301                             int pixel_size)
2302 {
2303         struct drm_i915_private *dev_priv = dev->dev_private;
2304         u32 reg;
2305         unsigned long wm;
2306         struct cxsr_latency *latency;
2307
2308         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2309                 dev_priv->mem_freq);
2310         if (!latency) {
2311                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2312                 igd_disable_cxsr(dev);
2313                 return;
2314         }
2315
2316         /* Display SR */
2317         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2318                                 latency->display_sr);
2319         reg = I915_READ(DSPFW1);
2320         reg &= 0x7fffff;
2321         reg |= wm << 23;
2322         I915_WRITE(DSPFW1, reg);
2323         DRM_DEBUG("DSPFW1 register is %x\n", reg);
2324
2325         /* cursor SR */
2326         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2327                                 latency->cursor_sr);
2328         reg = I915_READ(DSPFW3);
2329         reg &= ~(0x3f << 24);
2330         reg |= (wm & 0x3f) << 24;
2331         I915_WRITE(DSPFW3, reg);
2332
2333         /* Display HPLL off SR */
2334         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2335                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2336         reg = I915_READ(DSPFW3);
2337         reg &= 0xfffffe00;
2338         reg |= wm & 0x1ff;
2339         I915_WRITE(DSPFW3, reg);
2340
2341         /* cursor HPLL off SR */
2342         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2343                                 latency->cursor_hpll_disable);
2344         reg = I915_READ(DSPFW3);
2345         reg &= ~(0x3f << 16);
2346         reg |= (wm & 0x3f) << 16;
2347         I915_WRITE(DSPFW3, reg);
2348         DRM_DEBUG("DSPFW3 register is %x\n", reg);
2349
2350         /* activate cxsr */
2351         reg = I915_READ(DSPFW3);
2352         reg |= IGD_SELF_REFRESH_EN;
2353         I915_WRITE(DSPFW3, reg);
2354
2355         DRM_INFO("Big FIFO is enabled\n");
2356
2357         return;
2358 }
2359
2360 /*
2361  * Latency for FIFO fetches is dependent on several factors:
2362  *   - memory configuration (speed, channels)
2363  *   - chipset
2364  *   - current MCH state
2365  * It can be fairly high in some situations, so here we assume a fairly
2366  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2367  * set this value too high, the FIFO will fetch frequently to stay full)
2368  * and power consumption (set it too low to save power and we might see
2369  * FIFO underruns and display "flicker").
2370  *
2371  * A value of 5us seems to be a good balance; safe for very low end
2372  * platforms but not overly aggressive on lower latency configs.
2373  */
2374 const static int latency_ns = 5000;
2375
2376 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2377 {
2378         struct drm_i915_private *dev_priv = dev->dev_private;
2379         uint32_t dsparb = I915_READ(DSPARB);
2380         int size;
2381
2382         if (plane == 0)
2383                 size = dsparb & 0x7f;
2384         else
2385                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2386                         (dsparb & 0x7f);
2387
2388         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2389                   size);
2390
2391         return size;
2392 }
2393
2394 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2395 {
2396         struct drm_i915_private *dev_priv = dev->dev_private;
2397         uint32_t dsparb = I915_READ(DSPARB);
2398         int size;
2399
2400         if (plane == 0)
2401                 size = dsparb & 0x1ff;
2402         else
2403                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2404                         (dsparb & 0x1ff);
2405         size >>= 1; /* Convert to cachelines */
2406
2407         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2408                   size);
2409
2410         return size;
2411 }
2412
2413 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2414 {
2415         struct drm_i915_private *dev_priv = dev->dev_private;
2416         uint32_t dsparb = I915_READ(DSPARB);
2417         int size;
2418
2419         size = dsparb & 0x7f;
2420         size >>= 2; /* Convert to cachelines */
2421
2422         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2423                   size);
2424
2425         return size;
2426 }
2427
2428 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2429 {
2430         struct drm_i915_private *dev_priv = dev->dev_private;
2431         uint32_t dsparb = I915_READ(DSPARB);
2432         int size;
2433
2434         size = dsparb & 0x7f;
2435         size >>= 1; /* Convert to cachelines */
2436
2437         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2438                   size);
2439
2440         return size;
2441 }
2442
2443 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2444                           int planeb_clock, int sr_hdisplay, int pixel_size)
2445 {
2446         struct drm_i915_private *dev_priv = dev->dev_private;
2447         int total_size, cacheline_size;
2448         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2449         struct intel_watermark_params planea_params, planeb_params;
2450         unsigned long line_time_us;
2451         int sr_clock, sr_entries = 0, entries_required;
2452
2453         /* Create copies of the base settings for each pipe */
2454         planea_params = planeb_params = g4x_wm_info;
2455
2456         /* Grab a couple of global values before we overwrite them */
2457         total_size = planea_params.fifo_size;
2458         cacheline_size = planea_params.cacheline_size;
2459
2460         /*
2461          * Note: we need to make sure we don't overflow for various clock &
2462          * latency values.
2463          * clocks go from a few thousand to several hundred thousand.
2464          * latency is usually a few thousand
2465          */
2466         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2467                 1000;
2468         entries_required /= G4X_FIFO_LINE_SIZE;
2469         planea_wm = entries_required + planea_params.guard_size;
2470
2471         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2472                 1000;
2473         entries_required /= G4X_FIFO_LINE_SIZE;
2474         planeb_wm = entries_required + planeb_params.guard_size;
2475
2476         cursora_wm = cursorb_wm = 16;
2477         cursor_sr = 32;
2478
2479         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2480
2481         /* Calc sr entries for one plane configs */
2482         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2483                 /* self-refresh has much higher latency */
2484                 const static int sr_latency_ns = 12000;
2485
2486                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2487                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2488
2489                 /* Use ns/us then divide to preserve precision */
2490                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2491                               pixel_size * sr_hdisplay) / 1000;
2492                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2493                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2494                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2495         }
2496
2497         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2498                   planea_wm, planeb_wm, sr_entries);
2499
2500         planea_wm &= 0x3f;
2501         planeb_wm &= 0x3f;
2502
2503         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2504                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2505                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2506         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2507                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2508         /* HPLL off in SR has some issues on G4x... disable it */
2509         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2510                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2511 }
2512
2513 static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
2514                            int unused3, int unused4)
2515 {
2516         struct drm_i915_private *dev_priv = dev->dev_private;
2517
2518         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2519
2520         /* 965 has limitations... */
2521         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2522         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2523 }
2524
2525 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2526                            int planeb_clock, int sr_hdisplay, int pixel_size)
2527 {
2528         struct drm_i915_private *dev_priv = dev->dev_private;
2529         uint32_t fwater_lo;
2530         uint32_t fwater_hi;
2531         int total_size, cacheline_size, cwm, srwm = 1;
2532         int planea_wm, planeb_wm;
2533         struct intel_watermark_params planea_params, planeb_params;
2534         unsigned long line_time_us;
2535         int sr_clock, sr_entries = 0;
2536
2537         /* Create copies of the base settings for each pipe */
2538         if (IS_I965GM(dev) || IS_I945GM(dev))
2539                 planea_params = planeb_params = i945_wm_info;
2540         else if (IS_I9XX(dev))
2541                 planea_params = planeb_params = i915_wm_info;
2542         else
2543                 planea_params = planeb_params = i855_wm_info;
2544
2545         /* Grab a couple of global values before we overwrite them */
2546         total_size = planea_params.fifo_size;
2547         cacheline_size = planea_params.cacheline_size;
2548
2549         /* Update per-plane FIFO sizes */
2550         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2551         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2552
2553         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2554                                        pixel_size, latency_ns);
2555         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2556                                        pixel_size, latency_ns);
2557         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2558
2559         /*
2560          * Overlay gets an aggressive default since video jitter is bad.
2561          */
2562         cwm = 2;
2563
2564         /* Calc sr entries for one plane configs */
2565         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2566             (!planea_clock || !planeb_clock)) {
2567                 /* self-refresh has much higher latency */
2568                 const static int sr_latency_ns = 6000;
2569
2570                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2571                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2572
2573                 /* Use ns/us then divide to preserve precision */
2574                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2575                               pixel_size * sr_hdisplay) / 1000;
2576                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2577                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2578                 srwm = total_size - sr_entries;
2579                 if (srwm < 0)
2580                         srwm = 1;
2581                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2582         }
2583
2584         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2585                   planea_wm, planeb_wm, cwm, srwm);
2586
2587         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2588         fwater_hi = (cwm & 0x1f);
2589
2590         /* Set request length to 8 cachelines per fetch */
2591         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2592         fwater_hi = fwater_hi | (1 << 8);
2593
2594         I915_WRITE(FW_BLC, fwater_lo);
2595         I915_WRITE(FW_BLC2, fwater_hi);
2596 }
2597
2598 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2599                            int unused2, int pixel_size)
2600 {
2601         struct drm_i915_private *dev_priv = dev->dev_private;
2602         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2603         int planea_wm;
2604
2605         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2606
2607         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2608                                        pixel_size, latency_ns);
2609         fwater_lo |= (3<<8) | planea_wm;
2610
2611         DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2612
2613         I915_WRITE(FW_BLC, fwater_lo);
2614 }
2615
2616 /**
2617  * intel_update_watermarks - update FIFO watermark values based on current modes
2618  *
2619  * Calculate watermark values for the various WM regs based on current mode
2620  * and plane configuration.
2621  *
2622  * There are several cases to deal with here:
2623  *   - normal (i.e. non-self-refresh)
2624  *   - self-refresh (SR) mode
2625  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2626  *   - lines are small relative to FIFO size (buffer can hold more than 2
2627  *     lines), so need to account for TLB latency
2628  *
2629  *   The normal calculation is:
2630  *     watermark = dotclock * bytes per pixel * latency
2631  *   where latency is platform & configuration dependent (we assume pessimal
2632  *   values here).
2633  *
2634  *   The SR calculation is:
2635  *     watermark = (trunc(latency/line time)+1) * surface width *
2636  *       bytes per pixel
2637  *   where
2638  *     line time = htotal / dotclock
2639  *   and latency is assumed to be high, as above.
2640  *
2641  * The final value programmed to the register should always be rounded up,
2642  * and include an extra 2 entries to account for clock crossings.
2643  *
2644  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2645  * to set the non-SR watermarks to 8.
2646   */
2647 static void intel_update_watermarks(struct drm_device *dev)
2648 {
2649         struct drm_i915_private *dev_priv = dev->dev_private;
2650         struct drm_crtc *crtc;
2651         struct intel_crtc *intel_crtc;
2652         int sr_hdisplay = 0;
2653         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2654         int enabled = 0, pixel_size = 0;
2655
2656         if (!dev_priv->display.update_wm)
2657                 return;
2658
2659         /* Get the clock config from both planes */
2660         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2661                 intel_crtc = to_intel_crtc(crtc);
2662                 if (crtc->enabled) {
2663                         enabled++;
2664                         if (intel_crtc->plane == 0) {
2665                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2666                                           intel_crtc->pipe, crtc->mode.clock);
2667                                 planea_clock = crtc->mode.clock;
2668                         } else {
2669                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2670                                           intel_crtc->pipe, crtc->mode.clock);
2671                                 planeb_clock = crtc->mode.clock;
2672                         }
2673                         sr_hdisplay = crtc->mode.hdisplay;
2674                         sr_clock = crtc->mode.clock;
2675                         if (crtc->fb)
2676                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2677                         else
2678                                 pixel_size = 4; /* by default */
2679                 }
2680         }
2681
2682         if (enabled <= 0)
2683                 return;
2684
2685         /* Single plane configs can enable self refresh */
2686         if (enabled == 1 && IS_IGD(dev))
2687                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2688         else if (IS_IGD(dev))
2689                 igd_disable_cxsr(dev);
2690
2691         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2692                                     sr_hdisplay, pixel_size);
2693 }
2694
2695 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2696                                struct drm_display_mode *mode,
2697                                struct drm_display_mode *adjusted_mode,
2698                                int x, int y,
2699                                struct drm_framebuffer *old_fb)
2700 {
2701         struct drm_device *dev = crtc->dev;
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704         int pipe = intel_crtc->pipe;
2705         int plane = intel_crtc->plane;
2706         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2707         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2708         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2709         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2710         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2711         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2712         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2713         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2714         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2715         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2716         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2717         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2718         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2719         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2720         int refclk, num_outputs = 0;
2721         intel_clock_t clock, reduced_clock;
2722         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2723         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2724         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2725         bool is_edp = false;
2726         struct drm_mode_config *mode_config = &dev->mode_config;
2727         struct drm_connector *connector;
2728         const intel_limit_t *limit;
2729         int ret;
2730         struct fdi_m_n m_n = {0};
2731         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2732         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2733         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2734         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2735         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2736         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2737         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2738         int lvds_reg = LVDS;
2739         u32 temp;
2740         int sdvo_pixel_multiply;
2741         int target_clock;
2742
2743         drm_vblank_pre_modeset(dev, pipe);
2744
2745         list_for_each_entry(connector, &mode_config->connector_list, head) {
2746                 struct intel_output *intel_output = to_intel_output(connector);
2747
2748                 if (!connector->encoder || connector->encoder->crtc != crtc)
2749                         continue;
2750
2751                 switch (intel_output->type) {
2752                 case INTEL_OUTPUT_LVDS:
2753                         is_lvds = true;
2754                         break;
2755                 case INTEL_OUTPUT_SDVO:
2756                 case INTEL_OUTPUT_HDMI:
2757                         is_sdvo = true;
2758                         if (intel_output->needs_tv_clock)
2759                                 is_tv = true;
2760                         break;
2761                 case INTEL_OUTPUT_DVO:
2762                         is_dvo = true;
2763                         break;
2764                 case INTEL_OUTPUT_TVOUT:
2765                         is_tv = true;
2766                         break;
2767                 case INTEL_OUTPUT_ANALOG:
2768                         is_crt = true;
2769                         break;
2770                 case INTEL_OUTPUT_DISPLAYPORT:
2771                         is_dp = true;
2772                         break;
2773                 case INTEL_OUTPUT_EDP:
2774                         is_edp = true;
2775                         break;
2776                 }
2777
2778                 num_outputs++;
2779         }
2780
2781         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2782                 refclk = dev_priv->lvds_ssc_freq * 1000;
2783                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2784         } else if (IS_I9XX(dev)) {
2785                 refclk = 96000;
2786                 if (IS_IGDNG(dev))
2787                         refclk = 120000; /* 120Mhz refclk */
2788         } else {
2789                 refclk = 48000;
2790         }
2791
2792
2793         /*
2794          * Returns a set of divisors for the desired target clock with the given
2795          * refclk, or FALSE.  The returned values represent the clock equation:
2796          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2797          */
2798         limit = intel_limit(crtc);
2799         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2800         if (!ok) {
2801                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2802                 drm_vblank_post_modeset(dev, pipe);
2803                 return -EINVAL;
2804         }
2805
2806         if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2807                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2808                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2809                                                             (adjusted_mode->clock*3/4),
2810                                                             refclk,
2811                                                             &reduced_clock);
2812         }
2813
2814         /* SDVO TV has fixed PLL values depend on its clock range,
2815            this mirrors vbios setting. */
2816         if (is_sdvo && is_tv) {
2817                 if (adjusted_mode->clock >= 100000
2818                                 && adjusted_mode->clock < 140500) {
2819                         clock.p1 = 2;
2820                         clock.p2 = 10;
2821                         clock.n = 3;
2822                         clock.m1 = 16;
2823                         clock.m2 = 8;
2824                 } else if (adjusted_mode->clock >= 140500
2825                                 && adjusted_mode->clock <= 200000) {
2826                         clock.p1 = 1;
2827                         clock.p2 = 10;
2828                         clock.n = 6;
2829                         clock.m1 = 12;
2830                         clock.m2 = 8;
2831                 }
2832         }
2833
2834         /* FDI link */
2835         if (IS_IGDNG(dev)) {
2836                 int lane, link_bw, bpp;
2837                 /* eDP doesn't require FDI link, so just set DP M/N
2838                    according to current link config */
2839                 if (is_edp) {
2840                         struct drm_connector *edp;
2841                         target_clock = mode->clock;
2842                         edp = intel_pipe_get_output(crtc);
2843                         intel_edp_link_config(to_intel_output(edp),
2844                                         &lane, &link_bw);
2845                 } else {
2846                         /* DP over FDI requires target mode clock
2847                            instead of link clock */
2848                         if (is_dp)
2849                                 target_clock = mode->clock;
2850                         else
2851                                 target_clock = adjusted_mode->clock;
2852                         lane = 4;
2853                         link_bw = 270000;
2854                 }
2855
2856                 /* determine panel color depth */
2857                 temp = I915_READ(pipeconf_reg);
2858
2859                 switch (temp & PIPE_BPC_MASK) {
2860                 case PIPE_8BPC:
2861                         bpp = 24;
2862                         break;
2863                 case PIPE_10BPC:
2864                         bpp = 30;
2865                         break;
2866                 case PIPE_6BPC:
2867                         bpp = 18;
2868                         break;
2869                 case PIPE_12BPC:
2870                         bpp = 36;
2871                         break;
2872                 default:
2873                         DRM_ERROR("unknown pipe bpc value\n");
2874                         bpp = 24;
2875                 }
2876
2877                 igdng_compute_m_n(bpp, lane, target_clock,
2878                                   link_bw, &m_n);
2879         }
2880
2881         /* Ironlake: try to setup display ref clock before DPLL
2882          * enabling. This is only under driver's control after
2883          * PCH B stepping, previous chipset stepping should be
2884          * ignoring this setting.
2885          */
2886         if (IS_IGDNG(dev)) {
2887                 temp = I915_READ(PCH_DREF_CONTROL);
2888                 /* Always enable nonspread source */
2889                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2890                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2891                 I915_WRITE(PCH_DREF_CONTROL, temp);
2892                 POSTING_READ(PCH_DREF_CONTROL);
2893
2894                 temp &= ~DREF_SSC_SOURCE_MASK;
2895                 temp |= DREF_SSC_SOURCE_ENABLE;
2896                 I915_WRITE(PCH_DREF_CONTROL, temp);
2897                 POSTING_READ(PCH_DREF_CONTROL);
2898
2899                 udelay(200);
2900
2901                 if (is_edp) {
2902                         if (dev_priv->lvds_use_ssc) {
2903                                 temp |= DREF_SSC1_ENABLE;
2904                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2905                                 POSTING_READ(PCH_DREF_CONTROL);
2906
2907                                 udelay(200);
2908
2909                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2910                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2911                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2912                                 POSTING_READ(PCH_DREF_CONTROL);
2913                         } else {
2914                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2915                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2916                                 POSTING_READ(PCH_DREF_CONTROL);
2917                         }
2918                 }
2919         }
2920
2921         if (IS_IGD(dev)) {
2922                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2923                 if (has_reduced_clock)
2924                         fp2 = (1 << reduced_clock.n) << 16 |
2925                                 reduced_clock.m1 << 8 | reduced_clock.m2;
2926         } else {
2927                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2928                 if (has_reduced_clock)
2929                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2930                                 reduced_clock.m2;
2931         }
2932
2933         if (!IS_IGDNG(dev))
2934                 dpll = DPLL_VGA_MODE_DIS;
2935
2936         if (IS_I9XX(dev)) {
2937                 if (is_lvds)
2938                         dpll |= DPLLB_MODE_LVDS;
2939                 else
2940                         dpll |= DPLLB_MODE_DAC_SERIAL;
2941                 if (is_sdvo) {
2942                         dpll |= DPLL_DVO_HIGH_SPEED;
2943                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2944                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2945                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2946                         else if (IS_IGDNG(dev))
2947                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2948                 }
2949                 if (is_dp)
2950                         dpll |= DPLL_DVO_HIGH_SPEED;
2951
2952                 /* compute bitmask from p1 value */
2953                 if (IS_IGD(dev))
2954                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2955                 else {
2956                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2957                         /* also FPA1 */
2958                         if (IS_IGDNG(dev))
2959                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2960                         if (IS_G4X(dev) && has_reduced_clock)
2961                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2962                 }
2963                 switch (clock.p2) {
2964                 case 5:
2965                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2966                         break;
2967                 case 7:
2968                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2969                         break;
2970                 case 10:
2971                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2972                         break;
2973                 case 14:
2974                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2975                         break;
2976                 }
2977                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2978                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2979         } else {
2980                 if (is_lvds) {
2981                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2982                 } else {
2983                         if (clock.p1 == 2)
2984                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2985                         else
2986                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2987                         if (clock.p2 == 4)
2988                                 dpll |= PLL_P2_DIVIDE_BY_4;
2989                 }
2990         }
2991
2992         if (is_sdvo && is_tv)
2993                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2994         else if (is_tv)
2995                 /* XXX: just matching BIOS for now */
2996                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2997                 dpll |= 3;
2998         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2999                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3000         else
3001                 dpll |= PLL_REF_INPUT_DREFCLK;
3002
3003         /* setup pipeconf */
3004         pipeconf = I915_READ(pipeconf_reg);
3005
3006         /* Set up the display plane register */
3007         dspcntr = DISPPLANE_GAMMA_ENABLE;
3008
3009         /* IGDNG's plane is forced to pipe, bit 24 is to
3010            enable color space conversion */
3011         if (!IS_IGDNG(dev)) {
3012                 if (pipe == 0)
3013                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3014                 else
3015                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3016         }
3017
3018         if (pipe == 0 && !IS_I965G(dev)) {
3019                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3020                  * core speed.
3021                  *
3022                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3023                  * pipe == 0 check?
3024                  */
3025                 if (mode->clock >
3026                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3027                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3028                 else
3029                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3030         }
3031
3032         dspcntr |= DISPLAY_PLANE_ENABLE;
3033         pipeconf |= PIPEACONF_ENABLE;
3034         dpll |= DPLL_VCO_ENABLE;
3035
3036
3037         /* Disable the panel fitter if it was on our pipe */
3038         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3039                 I915_WRITE(PFIT_CONTROL, 0);
3040
3041         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3042         drm_mode_debug_printmodeline(mode);
3043
3044         /* assign to IGDNG registers */
3045         if (IS_IGDNG(dev)) {
3046                 fp_reg = pch_fp_reg;
3047                 dpll_reg = pch_dpll_reg;
3048         }
3049
3050         if (is_edp) {
3051                 igdng_disable_pll_edp(crtc);
3052         } else if ((dpll & DPLL_VCO_ENABLE)) {
3053                 I915_WRITE(fp_reg, fp);
3054                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3055                 I915_READ(dpll_reg);
3056                 udelay(150);
3057         }
3058
3059         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3060          * This is an exception to the general rule that mode_set doesn't turn
3061          * things on.
3062          */
3063         if (is_lvds) {
3064                 u32 lvds;
3065
3066                 if (IS_IGDNG(dev))
3067                         lvds_reg = PCH_LVDS;
3068
3069                 lvds = I915_READ(lvds_reg);
3070                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3071                 /* set the corresponsding LVDS_BORDER bit */
3072                 lvds |= dev_priv->lvds_border_bits;
3073                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3074                  * set the DPLLs for dual-channel mode or not.
3075                  */
3076                 if (clock.p2 == 7)
3077                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3078                 else
3079                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3080
3081                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3082                  * appropriately here, but we need to look more thoroughly into how
3083                  * panels behave in the two modes.
3084                  */
3085
3086                 I915_WRITE(lvds_reg, lvds);
3087                 I915_READ(lvds_reg);
3088         }
3089         if (is_dp)
3090                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3091
3092         if (!is_edp) {
3093                 I915_WRITE(fp_reg, fp);
3094                 I915_WRITE(dpll_reg, dpll);
3095                 I915_READ(dpll_reg);
3096                 /* Wait for the clocks to stabilize. */
3097                 udelay(150);
3098
3099                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3100                         if (is_sdvo) {
3101                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3102                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3103                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3104                         } else
3105                                 I915_WRITE(dpll_md_reg, 0);
3106                 } else {
3107                         /* write it again -- the BIOS does, after all */
3108                         I915_WRITE(dpll_reg, dpll);
3109                 }
3110                 I915_READ(dpll_reg);
3111                 /* Wait for the clocks to stabilize. */
3112                 udelay(150);
3113         }
3114
3115         if (is_lvds && has_reduced_clock && i915_powersave) {
3116                 I915_WRITE(fp_reg + 4, fp2);
3117                 intel_crtc->lowfreq_avail = true;
3118                 if (HAS_PIPE_CXSR(dev)) {
3119                         DRM_DEBUG("enabling CxSR downclocking\n");
3120                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3121                 }
3122         } else {
3123                 I915_WRITE(fp_reg + 4, fp);
3124                 intel_crtc->lowfreq_avail = false;
3125                 if (HAS_PIPE_CXSR(dev)) {
3126                         DRM_DEBUG("disabling CxSR downclocking\n");
3127                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3128                 }
3129         }
3130
3131         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3132                    ((adjusted_mode->crtc_htotal - 1) << 16));
3133         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3134                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3135         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3136                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3137         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3138                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3139         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3140                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3141         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3142                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3143         /* pipesrc and dspsize control the size that is scaled from, which should
3144          * always be the user's requested size.
3145          */
3146         if (!IS_IGDNG(dev)) {
3147                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3148                                 (mode->hdisplay - 1));
3149                 I915_WRITE(dsppos_reg, 0);
3150         }
3151         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3152
3153         if (IS_IGDNG(dev)) {
3154                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3155                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3156                 I915_WRITE(link_m1_reg, m_n.link_m);
3157                 I915_WRITE(link_n1_reg, m_n.link_n);
3158
3159                 if (is_edp) {
3160                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
3161                 } else {
3162                         /* enable FDI RX PLL too */
3163                         temp = I915_READ(fdi_rx_reg);
3164                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3165                         udelay(200);
3166                 }
3167         }
3168
3169         I915_WRITE(pipeconf_reg, pipeconf);
3170         I915_READ(pipeconf_reg);
3171
3172         intel_wait_for_vblank(dev);
3173
3174         if (IS_IGDNG(dev)) {
3175                 /* enable address swizzle for tiling buffer */
3176                 temp = I915_READ(DISP_ARB_CTL);
3177                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3178         }
3179
3180         I915_WRITE(dspcntr_reg, dspcntr);
3181
3182         /* Flush the plane changes */
3183         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3184
3185         if ((IS_I965G(dev) || plane == 0))
3186                 intel_update_fbc(crtc, &crtc->mode);
3187
3188         intel_update_watermarks(dev);
3189
3190         drm_vblank_post_modeset(dev, pipe);
3191
3192         return ret;
3193 }
3194
3195 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3196 void intel_crtc_load_lut(struct drm_crtc *crtc)
3197 {
3198         struct drm_device *dev = crtc->dev;
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3202         int i;
3203
3204         /* The clocks have to be on to load the palette. */
3205         if (!crtc->enabled)
3206                 return;
3207
3208         /* use legacy palette for IGDNG */
3209         if (IS_IGDNG(dev))
3210                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3211                                                    LGC_PALETTE_B;
3212
3213         for (i = 0; i < 256; i++) {
3214                 I915_WRITE(palreg + 4 * i,
3215                            (intel_crtc->lut_r[i] << 16) |
3216                            (intel_crtc->lut_g[i] << 8) |
3217                            intel_crtc->lut_b[i]);
3218         }
3219 }
3220
3221 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3222                                  struct drm_file *file_priv,
3223                                  uint32_t handle,
3224                                  uint32_t width, uint32_t height)
3225 {
3226         struct drm_device *dev = crtc->dev;
3227         struct drm_i915_private *dev_priv = dev->dev_private;
3228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3229         struct drm_gem_object *bo;
3230         struct drm_i915_gem_object *obj_priv;
3231         int pipe = intel_crtc->pipe;
3232         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3233         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3234         uint32_t temp = I915_READ(control);
3235         size_t addr;
3236         int ret;
3237
3238         DRM_DEBUG("\n");
3239
3240         /* if we want to turn off the cursor ignore width and height */
3241         if (!handle) {
3242                 DRM_DEBUG("cursor off\n");
3243                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3244                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3245                         temp |= CURSOR_MODE_DISABLE;
3246                 } else {
3247                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3248                 }
3249                 addr = 0;
3250                 bo = NULL;
3251                 mutex_lock(&dev->struct_mutex);
3252                 goto finish;
3253         }
3254
3255         /* Currently we only support 64x64 cursors */
3256         if (width != 64 || height != 64) {
3257                 DRM_ERROR("we currently only support 64x64 cursors\n");
3258                 return -EINVAL;
3259         }
3260
3261         bo = drm_gem_object_lookup(dev, file_priv, handle);
3262         if (!bo)
3263                 return -ENOENT;
3264
3265         obj_priv = bo->driver_private;
3266
3267         if (bo->size < width * height * 4) {
3268                 DRM_ERROR("buffer is to small\n");
3269                 ret = -ENOMEM;
3270                 goto fail;
3271         }
3272
3273         /* we only need to pin inside GTT if cursor is non-phy */
3274         mutex_lock(&dev->struct_mutex);
3275         if (!dev_priv->cursor_needs_physical) {
3276                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3277                 if (ret) {
3278                         DRM_ERROR("failed to pin cursor bo\n");
3279                         goto fail_locked;
3280                 }
3281                 addr = obj_priv->gtt_offset;
3282         } else {
3283                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3284                 if (ret) {
3285                         DRM_ERROR("failed to attach phys object\n");
3286                         goto fail_locked;
3287                 }
3288                 addr = obj_priv->phys_obj->handle->busaddr;
3289         }
3290
3291         if (!IS_I9XX(dev))
3292                 I915_WRITE(CURSIZE, (height << 12) | width);
3293
3294         /* Hooray for CUR*CNTR differences */
3295         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3296                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3297                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3298                 temp |= (pipe << 28); /* Connect to correct pipe */
3299         } else {
3300                 temp &= ~(CURSOR_FORMAT_MASK);
3301                 temp |= CURSOR_ENABLE;
3302                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3303         }
3304
3305  finish:
3306         I915_WRITE(control, temp);
3307         I915_WRITE(base, addr);
3308
3309         if (intel_crtc->cursor_bo) {
3310                 if (dev_priv->cursor_needs_physical) {
3311                         if (intel_crtc->cursor_bo != bo)
3312                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3313                 } else
3314                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3315                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3316         }
3317
3318         mutex_unlock(&dev->struct_mutex);
3319
3320         intel_crtc->cursor_addr = addr;
3321         intel_crtc->cursor_bo = bo;
3322
3323         return 0;
3324 fail:
3325         mutex_lock(&dev->struct_mutex);
3326 fail_locked:
3327         drm_gem_object_unreference(bo);
3328         mutex_unlock(&dev->struct_mutex);
3329         return ret;
3330 }
3331
3332 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3333 {
3334         struct drm_device *dev = crtc->dev;
3335         struct drm_i915_private *dev_priv = dev->dev_private;
3336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337         struct intel_framebuffer *intel_fb;
3338         int pipe = intel_crtc->pipe;
3339         uint32_t temp = 0;
3340         uint32_t adder;
3341
3342         if (crtc->fb) {
3343                 intel_fb = to_intel_framebuffer(crtc->fb);
3344                 intel_mark_busy(dev, intel_fb->obj);
3345         }
3346
3347         if (x < 0) {
3348                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3349                 x = -x;
3350         }
3351         if (y < 0) {
3352                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3353                 y = -y;
3354         }
3355
3356         temp |= x << CURSOR_X_SHIFT;
3357         temp |= y << CURSOR_Y_SHIFT;
3358
3359         adder = intel_crtc->cursor_addr;
3360         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3361         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3362
3363         return 0;
3364 }
3365
3366 /** Sets the color ramps on behalf of RandR */
3367 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3368                                  u16 blue, int regno)
3369 {
3370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3371
3372         intel_crtc->lut_r[regno] = red >> 8;
3373         intel_crtc->lut_g[regno] = green >> 8;
3374         intel_crtc->lut_b[regno] = blue >> 8;
3375 }
3376
3377 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3378                              u16 *blue, int regno)
3379 {
3380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3381
3382         *red = intel_crtc->lut_r[regno] << 8;
3383         *green = intel_crtc->lut_g[regno] << 8;
3384         *blue = intel_crtc->lut_b[regno] << 8;
3385 }
3386
3387 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3388                                  u16 *blue, uint32_t size)
3389 {
3390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3391         int i;
3392
3393         if (size != 256)
3394                 return;
3395
3396         for (i = 0; i < 256; i++) {
3397                 intel_crtc->lut_r[i] = red[i] >> 8;
3398                 intel_crtc->lut_g[i] = green[i] >> 8;
3399                 intel_crtc->lut_b[i] = blue[i] >> 8;
3400         }
3401
3402         intel_crtc_load_lut(crtc);
3403 }
3404
3405 /**
3406  * Get a pipe with a simple mode set on it for doing load-based monitor
3407  * detection.
3408  *
3409  * It will be up to the load-detect code to adjust the pipe as appropriate for
3410  * its requirements.  The pipe will be connected to no other outputs.
3411  *
3412  * Currently this code will only succeed if there is a pipe with no outputs
3413  * configured for it.  In the future, it could choose to temporarily disable
3414  * some outputs to free up a pipe for its use.
3415  *
3416  * \return crtc, or NULL if no pipes are available.
3417  */
3418
3419 /* VESA 640x480x72Hz mode to set on the pipe */
3420 static struct drm_display_mode load_detect_mode = {
3421         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3422                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3423 };
3424
3425 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3426                                             struct drm_display_mode *mode,
3427                                             int *dpms_mode)
3428 {
3429         struct intel_crtc *intel_crtc;
3430         struct drm_crtc *possible_crtc;
3431         struct drm_crtc *supported_crtc =NULL;
3432         struct drm_encoder *encoder = &intel_output->enc;
3433         struct drm_crtc *crtc = NULL;
3434         struct drm_device *dev = encoder->dev;
3435         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3436         struct drm_crtc_helper_funcs *crtc_funcs;
3437         int i = -1;
3438
3439         /*
3440          * Algorithm gets a little messy:
3441          *   - if the connector already has an assigned crtc, use it (but make
3442          *     sure it's on first)
3443          *   - try to find the first unused crtc that can drive this connector,
3444          *     and use that if we find one
3445          *   - if there are no unused crtcs available, try to use the first
3446          *     one we found that supports the connector
3447          */
3448
3449         /* See if we already have a CRTC for this connector */
3450         if (encoder->crtc) {
3451                 crtc = encoder->crtc;
3452                 /* Make sure the crtc and connector are running */
3453                 intel_crtc = to_intel_crtc(crtc);
3454                 *dpms_mode = intel_crtc->dpms_mode;
3455                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3456                         crtc_funcs = crtc->helper_private;
3457                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3458                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3459                 }
3460                 return crtc;
3461         }
3462
3463         /* Find an unused one (if possible) */
3464         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3465                 i++;
3466                 if (!(encoder->possible_crtcs & (1 << i)))
3467                         continue;
3468                 if (!possible_crtc->enabled) {
3469                         crtc = possible_crtc;
3470                         break;
3471                 }
3472                 if (!supported_crtc)
3473                         supported_crtc = possible_crtc;
3474         }
3475
3476         /*
3477          * If we didn't find an unused CRTC, don't use any.
3478          */
3479         if (!crtc) {
3480                 return NULL;
3481         }
3482
3483         encoder->crtc = crtc;
3484         intel_output->base.encoder = encoder;
3485         intel_output->load_detect_temp = true;
3486
3487         intel_crtc = to_intel_crtc(crtc);
3488         *dpms_mode = intel_crtc->dpms_mode;
3489
3490         if (!crtc->enabled) {
3491                 if (!mode)
3492                         mode = &load_detect_mode;
3493                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3494         } else {
3495                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3496                         crtc_funcs = crtc->helper_private;
3497                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3498                 }
3499
3500                 /* Add this connector to the crtc */
3501                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3502                 encoder_funcs->commit(encoder);
3503         }
3504         /* let the connector get through one full cycle before testing */
3505         intel_wait_for_vblank(dev);
3506
3507         return crtc;
3508 }
3509
3510 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3511 {
3512         struct drm_encoder *encoder = &intel_output->enc;
3513         struct drm_device *dev = encoder->dev;
3514         struct drm_crtc *crtc = encoder->crtc;
3515         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3516         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3517
3518         if (intel_output->load_detect_temp) {
3519                 encoder->crtc = NULL;
3520                 intel_output->base.encoder = NULL;
3521                 intel_output->load_detect_temp = false;
3522                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3523                 drm_helper_disable_unused_functions(dev);
3524         }
3525
3526         /* Switch crtc and output back off if necessary */
3527         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3528                 if (encoder->crtc == crtc)
3529                         encoder_funcs->dpms(encoder, dpms_mode);
3530                 crtc_funcs->dpms(crtc, dpms_mode);
3531         }
3532 }
3533
3534 /* Returns the clock of the currently programmed mode of the given pipe. */
3535 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3536 {
3537         struct drm_i915_private *dev_priv = dev->dev_private;
3538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3539         int pipe = intel_crtc->pipe;
3540         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3541         u32 fp;
3542         intel_clock_t clock;
3543
3544         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3545                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3546         else
3547                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3548
3549         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3550         if (IS_IGD(dev)) {
3551                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3552                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3553         } else {
3554                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3555                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3556         }
3557
3558         if (IS_I9XX(dev)) {
3559                 if (IS_IGD(dev))
3560                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3561                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3562                 else
3563                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3564                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3565
3566                 switch (dpll & DPLL_MODE_MASK) {
3567                 case DPLLB_MODE_DAC_SERIAL:
3568                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3569                                 5 : 10;
3570                         break;
3571                 case DPLLB_MODE_LVDS:
3572                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3573                                 7 : 14;
3574                         break;
3575                 default:
3576                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3577                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3578                         return 0;
3579                 }
3580
3581                 /* XXX: Handle the 100Mhz refclk */
3582                 intel_clock(dev, 96000, &clock);
3583         } else {
3584                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3585
3586                 if (is_lvds) {
3587                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3588                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3589                         clock.p2 = 14;
3590
3591                         if ((dpll & PLL_REF_INPUT_MASK) ==
3592                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3593                                 /* XXX: might not be 66MHz */
3594                                 intel_clock(dev, 66000, &clock);
3595                         } else
3596                                 intel_clock(dev, 48000, &clock);
3597                 } else {
3598                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3599                                 clock.p1 = 2;
3600                         else {
3601                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3602                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3603                         }
3604                         if (dpll & PLL_P2_DIVIDE_BY_4)
3605                                 clock.p2 = 4;
3606                         else
3607                                 clock.p2 = 2;
3608
3609                         intel_clock(dev, 48000, &clock);
3610                 }
3611         }
3612
3613         /* XXX: It would be nice to validate the clocks, but we can't reuse
3614          * i830PllIsValid() because it relies on the xf86_config connector
3615          * configuration being accurate, which it isn't necessarily.
3616          */
3617
3618         return clock.dot;
3619 }
3620
3621 /** Returns the currently programmed mode of the given pipe. */
3622 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3623                                              struct drm_crtc *crtc)
3624 {
3625         struct drm_i915_private *dev_priv = dev->dev_private;
3626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3627         int pipe = intel_crtc->pipe;
3628         struct drm_display_mode *mode;
3629         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3630         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3631         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3632         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3633
3634         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3635         if (!mode)
3636                 return NULL;
3637
3638         mode->clock = intel_crtc_clock_get(dev, crtc);
3639         mode->hdisplay = (htot & 0xffff) + 1;
3640         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3641         mode->hsync_start = (hsync & 0xffff) + 1;
3642         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3643         mode->vdisplay = (vtot & 0xffff) + 1;
3644         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3645         mode->vsync_start = (vsync & 0xffff) + 1;
3646         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3647
3648         drm_mode_set_name(mode);
3649         drm_mode_set_crtcinfo(mode, 0);
3650
3651         return mode;
3652 }
3653
3654 #define GPU_IDLE_TIMEOUT 500 /* ms */
3655
3656 /* When this timer fires, we've been idle for awhile */
3657 static void intel_gpu_idle_timer(unsigned long arg)
3658 {
3659         struct drm_device *dev = (struct drm_device *)arg;
3660         drm_i915_private_t *dev_priv = dev->dev_private;
3661
3662         DRM_DEBUG("idle timer fired, downclocking\n");
3663
3664         dev_priv->busy = false;
3665
3666         queue_work(dev_priv->wq, &dev_priv->idle_work);
3667 }
3668
3669 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3670 {
3671         drm_i915_private_t *dev_priv = dev->dev_private;
3672
3673         if (IS_IGDNG(dev))
3674                 return;
3675
3676         if (!dev_priv->render_reclock_avail) {
3677                 DRM_DEBUG("not reclocking render clock\n");
3678                 return;
3679         }
3680
3681         /* Restore render clock frequency to original value */
3682         if (IS_G4X(dev) || IS_I9XX(dev))
3683                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3684         else if (IS_I85X(dev))
3685                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3686         DRM_DEBUG("increasing render clock frequency\n");
3687
3688         /* Schedule downclock */
3689         if (schedule)
3690                 mod_timer(&dev_priv->idle_timer, jiffies +
3691                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3692 }
3693
3694 void intel_decrease_renderclock(struct drm_device *dev)
3695 {
3696         drm_i915_private_t *dev_priv = dev->dev_private;
3697
3698         if (IS_IGDNG(dev))
3699                 return;
3700
3701         if (!dev_priv->render_reclock_avail) {
3702                 DRM_DEBUG("not reclocking render clock\n");
3703                 return;
3704         }
3705
3706         if (IS_G4X(dev)) {
3707                 u16 gcfgc;
3708
3709                 /* Adjust render clock... */
3710                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3711
3712                 /* Down to minimum... */
3713                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3714                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3715
3716                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3717         } else if (IS_I965G(dev)) {
3718                 u16 gcfgc;
3719
3720                 /* Adjust render clock... */
3721                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3722
3723                 /* Down to minimum... */
3724                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3725                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3726
3727                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3728         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3729                 u16 gcfgc;
3730
3731                 /* Adjust render clock... */
3732                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3733
3734                 /* Down to minimum... */
3735                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3736                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3737
3738                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3739         } else if (IS_I915G(dev)) {
3740                 u16 gcfgc;
3741
3742                 /* Adjust render clock... */
3743                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3744
3745                 /* Down to minimum... */
3746                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3747                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3748
3749                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3750         } else if (IS_I85X(dev)) {
3751                 u16 hpllcc;
3752
3753                 /* Adjust render clock... */
3754                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3755
3756                 /* Up to maximum... */
3757                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3758                 hpllcc |= GC_CLOCK_133_200;
3759
3760                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3761         }
3762         DRM_DEBUG("decreasing render clock frequency\n");
3763 }
3764
3765 /* Note that no increase function is needed for this - increase_renderclock()
3766  *  will also rewrite these bits
3767  */
3768 void intel_decrease_displayclock(struct drm_device *dev)
3769 {
3770         if (IS_IGDNG(dev))
3771                 return;
3772
3773         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3774             IS_I915GM(dev)) {
3775                 u16 gcfgc;
3776
3777                 /* Adjust render clock... */
3778                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3779
3780                 /* Down to minimum... */
3781                 gcfgc &= ~0xf0;
3782                 gcfgc |= 0x80;
3783
3784                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3785         }
3786 }
3787
3788 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3789
3790 static void intel_crtc_idle_timer(unsigned long arg)
3791 {
3792         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3793         struct drm_crtc *crtc = &intel_crtc->base;
3794         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3795
3796         DRM_DEBUG("idle timer fired, downclocking\n");
3797
3798         intel_crtc->busy = false;
3799
3800         queue_work(dev_priv->wq, &dev_priv->idle_work);
3801 }
3802
3803 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3804 {
3805         struct drm_device *dev = crtc->dev;
3806         drm_i915_private_t *dev_priv = dev->dev_private;
3807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3808         int pipe = intel_crtc->pipe;
3809         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3810         int dpll = I915_READ(dpll_reg);
3811
3812         if (IS_IGDNG(dev))
3813                 return;
3814
3815         if (!dev_priv->lvds_downclock_avail)
3816                 return;
3817
3818         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3819                 DRM_DEBUG("upclocking LVDS\n");
3820
3821                 /* Unlock panel regs */
3822                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3823
3824                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3825                 I915_WRITE(dpll_reg, dpll);
3826                 dpll = I915_READ(dpll_reg);
3827                 intel_wait_for_vblank(dev);
3828                 dpll = I915_READ(dpll_reg);
3829                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3830                         DRM_DEBUG("failed to upclock LVDS!\n");
3831
3832                 /* ...and lock them again */
3833                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3834         }
3835
3836         /* Schedule downclock */
3837         if (schedule)
3838                 mod_timer(&intel_crtc->idle_timer, jiffies +
3839                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3840 }
3841
3842 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3843 {
3844         struct drm_device *dev = crtc->dev;
3845         drm_i915_private_t *dev_priv = dev->dev_private;
3846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3847         int pipe = intel_crtc->pipe;
3848         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3849         int dpll = I915_READ(dpll_reg);
3850
3851         if (IS_IGDNG(dev))
3852                 return;
3853
3854         if (!dev_priv->lvds_downclock_avail)
3855                 return;
3856
3857         /*
3858          * Since this is called by a timer, we should never get here in
3859          * the manual case.
3860          */
3861         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3862                 DRM_DEBUG("downclocking LVDS\n");
3863
3864                 /* Unlock panel regs */
3865                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3866
3867                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3868                 I915_WRITE(dpll_reg, dpll);
3869                 dpll = I915_READ(dpll_reg);
3870                 intel_wait_for_vblank(dev);
3871                 dpll = I915_READ(dpll_reg);
3872                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3873                         DRM_DEBUG("failed to downclock LVDS!\n");
3874
3875                 /* ...and lock them again */
3876                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3877         }
3878
3879 }
3880
3881 /**
3882  * intel_idle_update - adjust clocks for idleness
3883  * @work: work struct
3884  *
3885  * Either the GPU or display (or both) went idle.  Check the busy status
3886  * here and adjust the CRTC and GPU clocks as necessary.
3887  */
3888 static void intel_idle_update(struct work_struct *work)
3889 {
3890         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3891                                                     idle_work);
3892         struct drm_device *dev = dev_priv->dev;
3893         struct drm_crtc *crtc;
3894         struct intel_crtc *intel_crtc;
3895
3896         if (!i915_powersave)
3897                 return;
3898
3899         mutex_lock(&dev->struct_mutex);
3900
3901         /* GPU isn't processing, downclock it. */
3902         if (!dev_priv->busy) {
3903                 intel_decrease_renderclock(dev);
3904                 intel_decrease_displayclock(dev);
3905         }
3906
3907         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3908                 /* Skip inactive CRTCs */
3909                 if (!crtc->fb)
3910                         continue;
3911
3912                 intel_crtc = to_intel_crtc(crtc);
3913                 if (!intel_crtc->busy)
3914                         intel_decrease_pllclock(crtc);
3915         }
3916
3917         mutex_unlock(&dev->struct_mutex);
3918 }
3919
3920 /**
3921  * intel_mark_busy - mark the GPU and possibly the display busy
3922  * @dev: drm device
3923  * @obj: object we're operating on
3924  *
3925  * Callers can use this function to indicate that the GPU is busy processing
3926  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3927  * buffer), we'll also mark the display as busy, so we know to increase its
3928  * clock frequency.
3929  */
3930 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3931 {
3932         drm_i915_private_t *dev_priv = dev->dev_private;
3933         struct drm_crtc *crtc = NULL;
3934         struct intel_framebuffer *intel_fb;
3935         struct intel_crtc *intel_crtc;
3936
3937         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3938                 return;
3939
3940         dev_priv->busy = true;
3941         intel_increase_renderclock(dev, true);
3942
3943         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3944                 if (!crtc->fb)
3945                         continue;
3946
3947                 intel_crtc = to_intel_crtc(crtc);
3948                 intel_fb = to_intel_framebuffer(crtc->fb);
3949                 if (intel_fb->obj == obj) {
3950                         if (!intel_crtc->busy) {
3951                                 /* Non-busy -> busy, upclock */
3952                                 intel_increase_pllclock(crtc, true);
3953                                 intel_crtc->busy = true;
3954                         } else {
3955                                 /* Busy -> busy, put off timer */
3956                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3957                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3958                         }
3959                 }
3960         }
3961 }
3962
3963 static void intel_crtc_destroy(struct drm_crtc *crtc)
3964 {
3965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3966
3967         drm_crtc_cleanup(crtc);
3968         kfree(intel_crtc);
3969 }
3970
3971 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3972         .dpms = intel_crtc_dpms,
3973         .mode_fixup = intel_crtc_mode_fixup,
3974         .mode_set = intel_crtc_mode_set,
3975         .mode_set_base = intel_pipe_set_base,
3976         .prepare = intel_crtc_prepare,
3977         .commit = intel_crtc_commit,
3978         .load_lut = intel_crtc_load_lut,
3979 };
3980
3981 static const struct drm_crtc_funcs intel_crtc_funcs = {
3982         .cursor_set = intel_crtc_cursor_set,
3983         .cursor_move = intel_crtc_cursor_move,
3984         .gamma_set = intel_crtc_gamma_set,
3985         .set_config = drm_crtc_helper_set_config,
3986         .destroy = intel_crtc_destroy,
3987 };
3988
3989
3990 static void intel_crtc_init(struct drm_device *dev, int pipe)
3991 {
3992         struct intel_crtc *intel_crtc;
3993         int i;
3994
3995         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3996         if (intel_crtc == NULL)
3997                 return;
3998
3999         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4000
4001         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4002         intel_crtc->pipe = pipe;
4003         intel_crtc->plane = pipe;
4004         for (i = 0; i < 256; i++) {
4005                 intel_crtc->lut_r[i] = i;
4006                 intel_crtc->lut_g[i] = i;
4007                 intel_crtc->lut_b[i] = i;
4008         }
4009
4010         /* Swap pipes & planes for FBC on pre-965 */
4011         intel_crtc->pipe = pipe;
4012         intel_crtc->plane = pipe;
4013         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4014                 DRM_DEBUG("swapping pipes & planes for FBC\n");
4015                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4016         }
4017
4018         intel_crtc->cursor_addr = 0;
4019         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4020         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4021
4022         intel_crtc->busy = false;
4023
4024         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4025                     (unsigned long)intel_crtc);
4026 }
4027
4028 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4029                                 struct drm_file *file_priv)
4030 {
4031         drm_i915_private_t *dev_priv = dev->dev_private;
4032         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4033         struct drm_mode_object *drmmode_obj;
4034         struct intel_crtc *crtc;
4035
4036         if (!dev_priv) {
4037                 DRM_ERROR("called with no initialization\n");
4038                 return -EINVAL;
4039         }
4040
4041         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4042                         DRM_MODE_OBJECT_CRTC);
4043
4044         if (!drmmode_obj) {
4045                 DRM_ERROR("no such CRTC id\n");
4046                 return -EINVAL;
4047         }
4048
4049         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4050         pipe_from_crtc_id->pipe = crtc->pipe;
4051
4052         return 0;
4053 }
4054
4055 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4056 {
4057         struct drm_crtc *crtc = NULL;
4058
4059         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4060                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4061                 if (intel_crtc->pipe == pipe)
4062                         break;
4063         }
4064         return crtc;
4065 }
4066
4067 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4068 {
4069         int index_mask = 0;
4070         struct drm_connector *connector;
4071         int entry = 0;
4072
4073         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4074                 struct intel_output *intel_output = to_intel_output(connector);
4075                 if (type_mask & intel_output->clone_mask)
4076                         index_mask |= (1 << entry);
4077                 entry++;
4078         }
4079         return index_mask;
4080 }
4081
4082
4083 static void intel_setup_outputs(struct drm_device *dev)
4084 {
4085         struct drm_i915_private *dev_priv = dev->dev_private;
4086         struct drm_connector *connector;
4087
4088         intel_crt_init(dev);
4089
4090         /* Set up integrated LVDS */
4091         if (IS_MOBILE(dev) && !IS_I830(dev))
4092                 intel_lvds_init(dev);
4093
4094         if (IS_IGDNG(dev)) {
4095                 int found;
4096
4097                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4098                         intel_dp_init(dev, DP_A);
4099
4100                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4101                         /* check SDVOB */
4102                         /* found = intel_sdvo_init(dev, HDMIB); */
4103                         found = 0;
4104                         if (!found)
4105                                 intel_hdmi_init(dev, HDMIB);
4106                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4107                                 intel_dp_init(dev, PCH_DP_B);
4108                 }
4109
4110                 if (I915_READ(HDMIC) & PORT_DETECTED)
4111                         intel_hdmi_init(dev, HDMIC);
4112
4113                 if (I915_READ(HDMID) & PORT_DETECTED)
4114                         intel_hdmi_init(dev, HDMID);
4115
4116                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4117                         intel_dp_init(dev, PCH_DP_C);
4118
4119                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4120                         intel_dp_init(dev, PCH_DP_D);
4121
4122         } else if (IS_I9XX(dev)) {
4123                 bool found = false;
4124
4125                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4126                         found = intel_sdvo_init(dev, SDVOB);
4127                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4128                                 intel_hdmi_init(dev, SDVOB);
4129
4130                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
4131                                 intel_dp_init(dev, DP_B);
4132                 }
4133
4134                 /* Before G4X SDVOC doesn't have its own detect register */
4135
4136                 if (I915_READ(SDVOB) & SDVO_DETECTED)
4137                         found = intel_sdvo_init(dev, SDVOC);
4138
4139                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4140
4141                         if (SUPPORTS_INTEGRATED_HDMI(dev))
4142                                 intel_hdmi_init(dev, SDVOC);
4143                         if (SUPPORTS_INTEGRATED_DP(dev))
4144                                 intel_dp_init(dev, DP_C);
4145                 }
4146
4147                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4148                         intel_dp_init(dev, DP_D);
4149         } else
4150                 intel_dvo_init(dev);
4151
4152         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
4153                 intel_tv_init(dev);
4154
4155         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4156                 struct intel_output *intel_output = to_intel_output(connector);
4157                 struct drm_encoder *encoder = &intel_output->enc;
4158
4159                 encoder->possible_crtcs = intel_output->crtc_mask;
4160                 encoder->possible_clones = intel_connector_clones(dev,
4161                                                 intel_output->clone_mask);
4162         }
4163 }
4164
4165 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4166 {
4167         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4168         struct drm_device *dev = fb->dev;
4169
4170         if (fb->fbdev)
4171                 intelfb_remove(dev, fb);
4172
4173         drm_framebuffer_cleanup(fb);
4174         mutex_lock(&dev->struct_mutex);
4175         drm_gem_object_unreference(intel_fb->obj);
4176         mutex_unlock(&dev->struct_mutex);
4177
4178         kfree(intel_fb);
4179 }
4180
4181 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4182                                                 struct drm_file *file_priv,
4183                                                 unsigned int *handle)
4184 {
4185         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4186         struct drm_gem_object *object = intel_fb->obj;
4187
4188         return drm_gem_handle_create(file_priv, object, handle);
4189 }
4190
4191 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4192         .destroy = intel_user_framebuffer_destroy,
4193         .create_handle = intel_user_framebuffer_create_handle,
4194 };
4195
4196 int intel_framebuffer_create(struct drm_device *dev,
4197                              struct drm_mode_fb_cmd *mode_cmd,
4198                              struct drm_framebuffer **fb,
4199                              struct drm_gem_object *obj)
4200 {
4201         struct intel_framebuffer *intel_fb;
4202         int ret;
4203
4204         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4205         if (!intel_fb)
4206                 return -ENOMEM;
4207
4208         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4209         if (ret) {
4210                 DRM_ERROR("framebuffer init failed %d\n", ret);
4211                 return ret;
4212         }
4213
4214         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4215
4216         intel_fb->obj = obj;
4217
4218         *fb = &intel_fb->base;
4219
4220         return 0;
4221 }
4222
4223
4224 static struct drm_framebuffer *
4225 intel_user_framebuffer_create(struct drm_device *dev,
4226                               struct drm_file *filp,
4227                               struct drm_mode_fb_cmd *mode_cmd)
4228 {
4229         struct drm_gem_object *obj;
4230         struct drm_framebuffer *fb;
4231         int ret;
4232
4233         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4234         if (!obj)
4235                 return NULL;
4236
4237         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4238         if (ret) {
4239                 mutex_lock(&dev->struct_mutex);
4240                 drm_gem_object_unreference(obj);
4241                 mutex_unlock(&dev->struct_mutex);
4242                 return NULL;
4243         }
4244
4245         return fb;
4246 }
4247
4248 static const struct drm_mode_config_funcs intel_mode_funcs = {
4249         .fb_create = intel_user_framebuffer_create,
4250         .fb_changed = intelfb_probe,
4251 };
4252
4253 void intel_init_clock_gating(struct drm_device *dev)
4254 {
4255         struct drm_i915_private *dev_priv = dev->dev_private;
4256
4257         /*
4258          * Disable clock gating reported to work incorrectly according to the
4259          * specs, but enable as much else as we can.
4260          */
4261         if (IS_IGDNG(dev)) {
4262                 return;
4263         } else if (IS_G4X(dev)) {
4264                 uint32_t dspclk_gate;
4265                 I915_WRITE(RENCLK_GATE_D1, 0);
4266                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4267                        GS_UNIT_CLOCK_GATE_DISABLE |
4268                        CL_UNIT_CLOCK_GATE_DISABLE);
4269                 I915_WRITE(RAMCLK_GATE_D, 0);
4270                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4271                         OVRUNIT_CLOCK_GATE_DISABLE |
4272                         OVCUNIT_CLOCK_GATE_DISABLE;
4273                 if (IS_GM45(dev))
4274                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4275                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4276         } else if (IS_I965GM(dev)) {
4277                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4278                 I915_WRITE(RENCLK_GATE_D2, 0);
4279                 I915_WRITE(DSPCLK_GATE_D, 0);
4280                 I915_WRITE(RAMCLK_GATE_D, 0);
4281                 I915_WRITE16(DEUC, 0);
4282         } else if (IS_I965G(dev)) {
4283                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4284                        I965_RCC_CLOCK_GATE_DISABLE |
4285                        I965_RCPB_CLOCK_GATE_DISABLE |
4286                        I965_ISC_CLOCK_GATE_DISABLE |
4287                        I965_FBC_CLOCK_GATE_DISABLE);
4288                 I915_WRITE(RENCLK_GATE_D2, 0);
4289         } else if (IS_I9XX(dev)) {
4290                 u32 dstate = I915_READ(D_STATE);
4291
4292                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4293                         DSTATE_DOT_CLOCK_GATING;
4294                 I915_WRITE(D_STATE, dstate);
4295         } else if (IS_I855(dev) || IS_I865G(dev)) {
4296                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4297         } else if (IS_I830(dev)) {
4298                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4299         }
4300 }
4301
4302 /* Set up chip specific display functions */
4303 static void intel_init_display(struct drm_device *dev)
4304 {
4305         struct drm_i915_private *dev_priv = dev->dev_private;
4306
4307         /* We always want a DPMS function */
4308         if (IS_IGDNG(dev))
4309                 dev_priv->display.dpms = igdng_crtc_dpms;
4310         else
4311                 dev_priv->display.dpms = i9xx_crtc_dpms;
4312
4313         /* Only mobile has FBC, leave pointers NULL for other chips */
4314         if (IS_MOBILE(dev)) {
4315                 if (IS_GM45(dev)) {
4316                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4317                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4318                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4319                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4320                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4321                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4322                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4323                 }
4324                 /* 855GM needs testing */
4325         }
4326
4327         /* Returns the core display clock speed */
4328         if (IS_I945G(dev))
4329                 dev_priv->display.get_display_clock_speed =
4330                         i945_get_display_clock_speed;
4331         else if (IS_I915G(dev))
4332                 dev_priv->display.get_display_clock_speed =
4333                         i915_get_display_clock_speed;
4334         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4335                 dev_priv->display.get_display_clock_speed =
4336                         i9xx_misc_get_display_clock_speed;
4337         else if (IS_I915GM(dev))
4338                 dev_priv->display.get_display_clock_speed =
4339                         i915gm_get_display_clock_speed;
4340         else if (IS_I865G(dev))
4341                 dev_priv->display.get_display_clock_speed =
4342                         i865_get_display_clock_speed;
4343         else if (IS_I855(dev))
4344                 dev_priv->display.get_display_clock_speed =
4345                         i855_get_display_clock_speed;
4346         else /* 852, 830 */
4347                 dev_priv->display.get_display_clock_speed =
4348                         i830_get_display_clock_speed;
4349
4350         /* For FIFO watermark updates */
4351         if (IS_IGDNG(dev))
4352                 dev_priv->display.update_wm = NULL;
4353         else if (IS_G4X(dev))
4354                 dev_priv->display.update_wm = g4x_update_wm;
4355         else if (IS_I965G(dev))
4356                 dev_priv->display.update_wm = i965_update_wm;
4357         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4358                 dev_priv->display.update_wm = i9xx_update_wm;
4359                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4360         } else {
4361                 if (IS_I85X(dev))
4362                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4363                 else if (IS_845G(dev))
4364                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4365                 else
4366                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4367                 dev_priv->display.update_wm = i830_update_wm;
4368         }
4369 }
4370
4371 void intel_modeset_init(struct drm_device *dev)
4372 {
4373         struct drm_i915_private *dev_priv = dev->dev_private;
4374         int num_pipe;
4375         int i;
4376
4377         drm_mode_config_init(dev);
4378
4379         dev->mode_config.min_width = 0;
4380         dev->mode_config.min_height = 0;
4381
4382         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4383
4384         intel_init_display(dev);
4385
4386         if (IS_I965G(dev)) {
4387                 dev->mode_config.max_width = 8192;
4388                 dev->mode_config.max_height = 8192;
4389         } else if (IS_I9XX(dev)) {
4390                 dev->mode_config.max_width = 4096;
4391                 dev->mode_config.max_height = 4096;
4392         } else {
4393                 dev->mode_config.max_width = 2048;
4394                 dev->mode_config.max_height = 2048;
4395         }
4396
4397         /* set memory base */
4398         if (IS_I9XX(dev))
4399                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4400         else
4401                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4402
4403         if (IS_MOBILE(dev) || IS_I9XX(dev))
4404                 num_pipe = 2;
4405         else
4406                 num_pipe = 1;
4407         DRM_DEBUG("%d display pipe%s available.\n",
4408                   num_pipe, num_pipe > 1 ? "s" : "");
4409
4410         if (IS_I85X(dev))
4411                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4412         else if (IS_I9XX(dev) || IS_G4X(dev))
4413                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4414
4415         for (i = 0; i < num_pipe; i++) {
4416                 intel_crtc_init(dev, i);
4417         }
4418
4419         intel_setup_outputs(dev);
4420
4421         intel_init_clock_gating(dev);
4422
4423         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4424         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4425                     (unsigned long)dev);
4426 }
4427
4428 void intel_modeset_cleanup(struct drm_device *dev)
4429 {
4430         struct drm_i915_private *dev_priv = dev->dev_private;
4431         struct drm_crtc *crtc;
4432         struct intel_crtc *intel_crtc;
4433
4434         mutex_lock(&dev->struct_mutex);
4435
4436         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4437                 /* Skip inactive CRTCs */
4438                 if (!crtc->fb)
4439                         continue;
4440
4441                 intel_crtc = to_intel_crtc(crtc);
4442                 intel_increase_pllclock(crtc, false);
4443                 del_timer_sync(&intel_crtc->idle_timer);
4444         }
4445
4446         intel_increase_renderclock(dev, false);
4447         del_timer_sync(&dev_priv->idle_timer);
4448
4449         mutex_unlock(&dev->struct_mutex);
4450
4451         if (dev_priv->display.disable_fbc)
4452                 dev_priv->display.disable_fbc(dev);
4453
4454         drm_mode_config_cleanup(dev);
4455 }
4456
4457
4458 /* current intel driver doesn't take advantage of encoders
4459    always give back the encoder for the connector
4460 */
4461 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4462 {
4463         struct intel_output *intel_output = to_intel_output(connector);
4464
4465         return &intel_output->enc;
4466 }
4467
4468 /*
4469  * set vga decode state - true == enable VGA decode
4470  */
4471 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4472 {
4473         struct drm_i915_private *dev_priv = dev->dev_private;
4474         u16 gmch_ctrl;
4475
4476         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4477         if (state)
4478                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4479         else
4480                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4481         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4482         return 0;
4483 }