1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
32 #define INTEL_GMCH_CTRL 0x52
33 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
34 #define INTEL_GMCH_ENABLED 0x4
35 #define INTEL_GMCH_MEM_MASK 0x1
36 #define INTEL_GMCH_MEM_64M 0x1
37 #define INTEL_GMCH_MEM_128M 0
39 #define INTEL_GMCH_GMS_MASK (0xf << 4)
40 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
41 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
42 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
45 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
47 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
48 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
49 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
50 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
51 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
52 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
53 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
54 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
56 /* PCI config space */
58 #define HPLLCC 0xc0 /* 855 only */
59 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
60 #define GC_CLOCK_133_200 (0 << 0)
61 #define GC_CLOCK_100_200 (1 << 0)
62 #define GC_CLOCK_100_133 (2 << 0)
63 #define GC_CLOCK_166_250 (3 << 0)
65 #define GCFGC 0xf0 /* 915+ only */
66 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
67 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
68 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
69 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
70 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
71 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
72 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
73 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
74 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
75 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
76 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
77 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
78 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
79 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
80 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
81 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
82 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
83 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
84 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
85 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
86 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
87 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
88 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
91 #define GDRST_FULL (0<<2)
92 #define GDRST_RENDER (1<<2)
93 #define GDRST_MEDIA (3<<2)
97 #define VGA_ST01_MDA 0x3ba
98 #define VGA_ST01_CGA 0x3da
100 #define VGA_MSR_WRITE 0x3c2
101 #define VGA_MSR_READ 0x3cc
102 #define VGA_MSR_MEM_EN (1<<1)
103 #define VGA_MSR_CGA_MODE (1<<0)
105 #define VGA_SR_INDEX 0x3c4
106 #define VGA_SR_DATA 0x3c5
108 #define VGA_AR_INDEX 0x3c0
109 #define VGA_AR_VID_EN (1<<5)
110 #define VGA_AR_DATA_WRITE 0x3c0
111 #define VGA_AR_DATA_READ 0x3c1
113 #define VGA_GR_INDEX 0x3ce
114 #define VGA_GR_DATA 0x3cf
116 #define VGA_GR_MEM_READ_MODE_SHIFT 3
117 #define VGA_GR_MEM_READ_MODE_PLANE 1
119 #define VGA_GR_MEM_MODE_MASK 0xc
120 #define VGA_GR_MEM_MODE_SHIFT 2
121 #define VGA_GR_MEM_A0000_AFFFF 0
122 #define VGA_GR_MEM_A0000_BFFFF 1
123 #define VGA_GR_MEM_B0000_B7FFF 2
124 #define VGA_GR_MEM_B0000_BFFFF 3
126 #define VGA_DACMASK 0x3c6
127 #define VGA_DACRX 0x3c7
128 #define VGA_DACWX 0x3c8
129 #define VGA_DACDATA 0x3c9
131 #define VGA_CR_INDEX_MDA 0x3b4
132 #define VGA_CR_DATA_MDA 0x3b5
133 #define VGA_CR_INDEX_CGA 0x3d4
134 #define VGA_CR_DATA_CGA 0x3d5
137 * Memory interface instructions used by the kernel
139 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
141 #define MI_NOOP MI_INSTR(0, 0)
142 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
143 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
144 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
145 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
146 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
147 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
148 #define MI_FLUSH MI_INSTR(0x04, 0)
149 #define MI_READ_FLUSH (1 << 0)
150 #define MI_EXE_FLUSH (1 << 1)
151 #define MI_NO_WRITE_FLUSH (1 << 2)
152 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
153 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
154 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
155 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
156 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
157 #define MI_OVERLAY_CONTINUE (0x0<<21)
158 #define MI_OVERLAY_ON (0x1<<21)
159 #define MI_OVERLAY_OFF (0x2<<21)
160 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
161 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
162 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
163 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
164 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
165 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
166 #define MI_STORE_DWORD_INDEX_SHIFT 2
167 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
168 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
169 #define MI_BATCH_NON_SECURE (1)
170 #define MI_BATCH_NON_SECURE_I965 (1<<8)
171 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
174 * 3D instructions used by the kernel
176 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
178 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
179 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
180 #define SC_UPDATE_SCISSOR (0x1<<1)
181 #define SC_ENABLE_MASK (0x1<<0)
182 #define SC_ENABLE (0x1<<0)
183 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
184 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
185 #define SCI_YMIN_MASK (0xffff<<16)
186 #define SCI_XMIN_MASK (0xffff<<0)
187 #define SCI_YMAX_MASK (0xffff<<16)
188 #define SCI_XMAX_MASK (0xffff<<0)
189 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
190 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
191 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
192 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
193 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
194 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
195 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
196 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
197 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
198 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
199 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
200 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
201 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
202 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
203 #define BLT_DEPTH_8 (0<<24)
204 #define BLT_DEPTH_16_565 (1<<24)
205 #define BLT_DEPTH_16_1555 (2<<24)
206 #define BLT_DEPTH_32 (3<<24)
207 #define BLT_ROP_GXCOPY (0xcc<<16)
208 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
209 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
210 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
211 #define ASYNC_FLIP (1<<22)
212 #define DISPLAY_PLANE_A (0<<20)
213 #define DISPLAY_PLANE_B (1<<20)
218 #define FENCE_REG_830_0 0x2000
219 #define FENCE_REG_945_8 0x3000
220 #define I830_FENCE_START_MASK 0x07f80000
221 #define I830_FENCE_TILING_Y_SHIFT 12
222 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
223 #define I830_FENCE_PITCH_SHIFT 4
224 #define I830_FENCE_REG_VALID (1<<0)
225 #define I915_FENCE_MAX_PITCH_VAL 0x10
226 #define I830_FENCE_MAX_PITCH_VAL 6
227 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
229 #define I915_FENCE_START_MASK 0x0ff00000
230 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
232 #define FENCE_REG_965_0 0x03000
233 #define I965_FENCE_PITCH_SHIFT 2
234 #define I965_FENCE_TILING_Y_SHIFT 1
235 #define I965_FENCE_REG_VALID (1<<0)
236 #define I965_FENCE_MAX_PITCH_VAL 0x0400
239 * Instruction and interrupt control regs
241 #define PGTBL_ER 0x02024
242 #define PRB0_TAIL 0x02030
243 #define PRB0_HEAD 0x02034
244 #define PRB0_START 0x02038
245 #define PRB0_CTL 0x0203c
246 #define TAIL_ADDR 0x001FFFF8
247 #define HEAD_WRAP_COUNT 0xFFE00000
248 #define HEAD_WRAP_ONE 0x00200000
249 #define HEAD_ADDR 0x001FFFFC
250 #define RING_NR_PAGES 0x001FF000
251 #define RING_REPORT_MASK 0x00000006
252 #define RING_REPORT_64K 0x00000002
253 #define RING_REPORT_128K 0x00000004
254 #define RING_NO_REPORT 0x00000000
255 #define RING_VALID_MASK 0x00000001
256 #define RING_VALID 0x00000001
257 #define RING_INVALID 0x00000000
258 #define PRB1_TAIL 0x02040 /* 915+ only */
259 #define PRB1_HEAD 0x02044 /* 915+ only */
260 #define PRB1_START 0x02048 /* 915+ only */
261 #define PRB1_CTL 0x0204c /* 915+ only */
262 #define IPEIR_I965 0x02064
263 #define IPEHR_I965 0x02068
264 #define INSTDONE_I965 0x0206c
265 #define INSTPS 0x02070 /* 965+ only */
266 #define INSTDONE1 0x0207c /* 965+ only */
267 #define ACTHD_I965 0x02074
268 #define HWS_PGA 0x02080
269 #define HWS_ADDRESS_MASK 0xfffff000
270 #define HWS_START_ADDRESS_SHIFT 4
271 #define PWRCTXA 0x2088 /* 965GM+ only */
272 #define PWRCTX_EN (1<<0)
273 #define IPEIR 0x02088
274 #define IPEHR 0x0208c
275 #define INSTDONE 0x02090
276 #define NOPID 0x02094
277 #define HWSTAM 0x02098
278 #define SCPD0 0x0209c /* 915+ only */
283 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
284 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
285 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
286 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
287 #define I915_HWB_OOM_INTERRUPT (1<<13)
288 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
289 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
290 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
291 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
292 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
293 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
294 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
295 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
296 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
297 #define I915_DEBUG_INTERRUPT (1<<2)
298 #define I915_USER_INTERRUPT (1<<1)
299 #define I915_ASLE_INTERRUPT (1<<0)
303 #define GM45_ERROR_PAGE_TABLE (1<<5)
304 #define GM45_ERROR_MEM_PRIV (1<<4)
305 #define I915_ERROR_PAGE_TABLE (1<<4)
306 #define GM45_ERROR_CP_PRIV (1<<3)
307 #define I915_ERROR_MEMORY_REFRESH (1<<1)
308 #define I915_ERROR_INSTRUCTION (1<<0)
309 #define INSTPM 0x020c0
310 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
311 #define ACTHD 0x020c8
312 #define FW_BLC 0x020d8
313 #define FW_BLC2 0x020dc
314 #define FW_BLC_SELF 0x020e0 /* 915+ only */
315 #define FW_BLC_SELF_EN_MASK (1<<31)
316 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
317 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
318 #define MM_BURST_LENGTH 0x00700000
319 #define MM_FIFO_WATERMARK 0x0001F000
320 #define LM_BURST_LENGTH 0x00000700
321 #define LM_FIFO_WATERMARK 0x0000001F
322 #define MI_ARB_STATE 0x020e4 /* 915+ only */
323 #define CACHE_MODE_0 0x02120 /* 915+ only */
324 #define CM0_MASK_SHIFT 16
325 #define CM0_IZ_OPT_DISABLE (1<<6)
326 #define CM0_ZR_OPT_DISABLE (1<<5)
327 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
328 #define CM0_COLOR_EVICT_DISABLE (1<<3)
329 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
330 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
331 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
335 * Framebuffer compression (915+ only)
338 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
339 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
340 #define FBC_CONTROL 0x03208
341 #define FBC_CTL_EN (1<<31)
342 #define FBC_CTL_PERIODIC (1<<30)
343 #define FBC_CTL_INTERVAL_SHIFT (16)
344 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
345 #define FBC_C3_IDLE (1<<13)
346 #define FBC_CTL_STRIDE_SHIFT (5)
347 #define FBC_CTL_FENCENO (1<<0)
348 #define FBC_COMMAND 0x0320c
349 #define FBC_CMD_COMPRESS (1<<0)
350 #define FBC_STATUS 0x03210
351 #define FBC_STAT_COMPRESSING (1<<31)
352 #define FBC_STAT_COMPRESSED (1<<30)
353 #define FBC_STAT_MODIFIED (1<<29)
354 #define FBC_STAT_CURRENT_LINE (1<<0)
355 #define FBC_CONTROL2 0x03214
356 #define FBC_CTL_FENCE_DBL (0<<4)
357 #define FBC_CTL_IDLE_IMM (0<<2)
358 #define FBC_CTL_IDLE_FULL (1<<2)
359 #define FBC_CTL_IDLE_LINE (2<<2)
360 #define FBC_CTL_IDLE_DEBUG (3<<2)
361 #define FBC_CTL_CPU_FENCE (1<<1)
362 #define FBC_CTL_PLANEA (0<<0)
363 #define FBC_CTL_PLANEB (1<<0)
364 #define FBC_FENCE_OFF 0x0321b
365 #define FBC_TAG 0x03300
367 #define FBC_LL_SIZE (1536)
369 /* Framebuffer compression for GM45+ */
370 #define DPFC_CB_BASE 0x3200
371 #define DPFC_CONTROL 0x3208
372 #define DPFC_CTL_EN (1<<31)
373 #define DPFC_CTL_PLANEA (0<<30)
374 #define DPFC_CTL_PLANEB (1<<30)
375 #define DPFC_CTL_FENCE_EN (1<<29)
376 #define DPFC_SR_EN (1<<10)
377 #define DPFC_CTL_LIMIT_1X (0<<6)
378 #define DPFC_CTL_LIMIT_2X (1<<6)
379 #define DPFC_CTL_LIMIT_4X (2<<6)
380 #define DPFC_RECOMP_CTL 0x320c
381 #define DPFC_RECOMP_STALL_EN (1<<27)
382 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
383 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
384 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
385 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
386 #define DPFC_STATUS 0x3210
387 #define DPFC_INVAL_SEG_SHIFT (16)
388 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
389 #define DPFC_COMP_SEG_SHIFT (0)
390 #define DPFC_COMP_SEG_MASK (0x000003ff)
391 #define DPFC_STATUS2 0x3214
392 #define DPFC_FENCE_YOFF 0x3218
393 #define DPFC_CHICKEN 0x3224
394 #define DPFC_HT_MODIFY (1<<31)
407 # define GPIO_CLOCK_DIR_MASK (1 << 0)
408 # define GPIO_CLOCK_DIR_IN (0 << 1)
409 # define GPIO_CLOCK_DIR_OUT (1 << 1)
410 # define GPIO_CLOCK_VAL_MASK (1 << 2)
411 # define GPIO_CLOCK_VAL_OUT (1 << 3)
412 # define GPIO_CLOCK_VAL_IN (1 << 4)
413 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
414 # define GPIO_DATA_DIR_MASK (1 << 8)
415 # define GPIO_DATA_DIR_IN (0 << 9)
416 # define GPIO_DATA_DIR_OUT (1 << 9)
417 # define GPIO_DATA_VAL_MASK (1 << 10)
418 # define GPIO_DATA_VAL_OUT (1 << 11)
419 # define GPIO_DATA_VAL_IN (1 << 12)
420 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
422 #define GMBUS0 0x5100
423 #define GMBUS1 0x5104
424 #define GMBUS2 0x5108
425 #define GMBUS3 0x510c
426 #define GMBUS4 0x5110
427 #define GMBUS5 0x5120
430 * Clock control & power management
435 #define VGA_PD 0x6010
436 #define VGA0_PD_P2_DIV_4 (1 << 7)
437 #define VGA0_PD_P1_DIV_2 (1 << 5)
438 #define VGA0_PD_P1_SHIFT 0
439 #define VGA0_PD_P1_MASK (0x1f << 0)
440 #define VGA1_PD_P2_DIV_4 (1 << 15)
441 #define VGA1_PD_P1_DIV_2 (1 << 13)
442 #define VGA1_PD_P1_SHIFT 8
443 #define VGA1_PD_P1_MASK (0x1f << 8)
444 #define DPLL_A 0x06014
445 #define DPLL_B 0x06018
446 #define DPLL_VCO_ENABLE (1 << 31)
447 #define DPLL_DVO_HIGH_SPEED (1 << 30)
448 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
449 #define DPLL_VGA_MODE_DIS (1 << 28)
450 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
451 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
452 #define DPLL_MODE_MASK (3 << 26)
453 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
454 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
455 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
456 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
457 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
458 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
459 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
461 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
462 #define I915_CRC_ERROR_ENABLE (1UL<<29)
463 #define I915_CRC_DONE_ENABLE (1UL<<28)
464 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
465 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
466 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
467 #define I915_DPST_EVENT_ENABLE (1UL<<23)
468 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
469 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
470 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
471 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
472 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
473 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
474 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
475 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
476 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
477 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
478 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
479 #define I915_DPST_EVENT_STATUS (1UL<<7)
480 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
481 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
482 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
483 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
484 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
485 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
487 #define SRX_INDEX 0x3c4
488 #define SRX_DATA 0x3c5
490 #define SR01_SCREEN_OFF (1<<5)
493 #define PPCR_ON (1<<0)
496 #define DVOB_ON (1<<31)
498 #define DVOC_ON (1<<31)
500 #define LVDS_ON (1<<31)
503 #define ADPA_DPMS_MASK (~(3<<10))
504 #define ADPA_DPMS_ON (0<<10)
505 #define ADPA_DPMS_SUSPEND (1<<10)
506 #define ADPA_DPMS_STANDBY (2<<10)
507 #define ADPA_DPMS_OFF (3<<10)
509 #define RING_TAIL 0x00
510 #define TAIL_ADDR 0x001FFFF8
511 #define RING_HEAD 0x04
512 #define HEAD_WRAP_COUNT 0xFFE00000
513 #define HEAD_WRAP_ONE 0x00200000
514 #define HEAD_ADDR 0x001FFFFC
515 #define RING_START 0x08
516 #define START_ADDR 0xFFFFF000
517 #define RING_LEN 0x0C
518 #define RING_NR_PAGES 0x001FF000
519 #define RING_REPORT_MASK 0x00000006
520 #define RING_REPORT_64K 0x00000002
521 #define RING_REPORT_128K 0x00000004
522 #define RING_NO_REPORT 0x00000000
523 #define RING_VALID_MASK 0x00000001
524 #define RING_VALID 0x00000001
525 #define RING_INVALID 0x00000000
527 /* Scratch pad debug 0 reg:
529 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
531 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
532 * this field (only one bit may be set).
534 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
535 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
536 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
537 /* i830, required in DVO non-gang */
538 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
539 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
540 #define PLL_REF_INPUT_DREFCLK (0 << 13)
541 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
542 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
543 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
544 #define PLL_REF_INPUT_MASK (3 << 13)
545 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
547 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
548 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
549 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
550 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
551 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
554 * Parallel to Serial Load Pulse phase selection.
555 * Selects the phase for the 10X DPLL clock for the PCIe
556 * digital display port. The range is 4 to 13; 10 or more
557 * is just a flip delay. The default is 6
559 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
560 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
562 * SDVO multiplier for 945G/GM. Not used on 965.
564 #define SDVO_MULTIPLIER_MASK 0x000000ff
565 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
566 #define SDVO_MULTIPLIER_SHIFT_VGA 0
567 #define DPLL_A_MD 0x0601c /* 965+ only */
569 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
571 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
573 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
574 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
575 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
576 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
577 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
579 * SDVO/UDI pixel multiplier.
581 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
582 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
583 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
584 * dummy bytes in the datastream at an increased clock rate, with both sides of
585 * the link knowing how many bytes are fill.
587 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
588 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
589 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
590 * through an SDVO command.
592 * This register field has values of multiplication factor minus 1, with
593 * a maximum multiplier of 5 for SDVO.
595 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
596 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
598 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
599 * This best be set to the default value (3) or the CRT won't work. No,
600 * I don't entirely understand what this does...
602 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
603 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
604 #define DPLL_B_MD 0x06020 /* 965+ only */
609 #define FP_N_DIV_MASK 0x003f0000
610 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
611 #define FP_N_DIV_SHIFT 16
612 #define FP_M1_DIV_MASK 0x00003f00
613 #define FP_M1_DIV_SHIFT 8
614 #define FP_M2_DIV_MASK 0x0000003f
615 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
616 #define FP_M2_DIV_SHIFT 0
617 #define DPLL_TEST 0x606c
618 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
619 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
620 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
621 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
622 #define DPLLB_TEST_N_BYPASS (1 << 19)
623 #define DPLLB_TEST_M_BYPASS (1 << 18)
624 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
625 #define DPLLA_TEST_N_BYPASS (1 << 3)
626 #define DPLLA_TEST_M_BYPASS (1 << 2)
627 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
628 #define D_STATE 0x6104
629 #define DSTATE_PLL_D3_OFF (1<<3)
630 #define DSTATE_GFX_CLOCK_GATING (1<<1)
631 #define DSTATE_DOT_CLOCK_GATING (1<<0)
632 #define DSPCLK_GATE_D 0x6200
633 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
634 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
635 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
636 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
637 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
638 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
639 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
640 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
641 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
642 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
643 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
644 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
645 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
646 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
647 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
648 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
649 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
650 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
651 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
652 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
653 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
654 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
655 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
656 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
657 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
658 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
659 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
660 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
662 * This bit must be set on the 830 to prevent hangs when turning off the
665 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
666 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
667 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
668 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
669 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
671 #define RENCLK_GATE_D1 0x6204
672 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
673 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
674 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
675 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
676 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
677 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
678 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
679 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
680 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
681 /** This bit must be unset on 855,865 */
682 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
683 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
684 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
685 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
686 /** This bit must be set on 855,865. */
687 # define SV_CLOCK_GATE_DISABLE (1 << 0)
688 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
689 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
690 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
691 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
692 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
693 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
694 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
695 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
696 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
697 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
698 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
699 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
700 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
701 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
702 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
703 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
704 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
706 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
707 /** This bit must always be set on 965G/965GM */
708 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
709 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
710 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
711 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
712 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
713 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
714 /** This bit must always be set on 965G */
715 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
716 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
717 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
718 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
719 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
720 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
721 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
722 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
723 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
724 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
725 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
726 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
727 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
728 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
729 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
730 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
731 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
732 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
733 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
735 #define RENCLK_GATE_D2 0x6208
736 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
737 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
738 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
739 #define RAMCLK_GATE_D 0x6210 /* CRL only */
740 #define DEUC 0x6214 /* CRL only */
746 #define PALETTE_A 0x0a000
747 #define PALETTE_B 0x0a800
754 * This mirrors the MCHBAR MMIO space whose location is determined by
755 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
756 * every way. It is not accessible from the CP register read instructions.
759 #define MCHBAR_MIRROR_BASE 0x10000
761 /** 915-945 and GM965 MCH register controlling DRAM channel access */
763 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
764 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
765 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
766 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
767 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
768 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
770 /** 965 MCH register controlling DRAM channel configuration */
771 #define C0DRB3 0x10206
772 #define C1DRB3 0x10606
774 /* Clocking configuration register */
775 #define CLKCFG 0x10c00
776 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
777 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
778 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
779 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
780 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
781 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
782 /* Note, below two are guess */
783 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
784 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
785 #define CLKCFG_FSB_MASK (7 << 0)
786 #define CLKCFG_MEM_533 (1 << 4)
787 #define CLKCFG_MEM_667 (2 << 4)
788 #define CLKCFG_MEM_800 (3 << 4)
789 #define CLKCFG_MEM_MASK (7 << 4)
791 #define CRSTANDVID 0x11100
792 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
793 #define PXVFREQ_PX_MASK 0x7f000000
794 #define PXVFREQ_PX_SHIFT 24
795 #define VIDFREQ_BASE 0x11110
796 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
797 #define VIDFREQ2 0x11114
798 #define VIDFREQ3 0x11118
799 #define VIDFREQ4 0x1111c
800 #define VIDFREQ_P0_MASK 0x1f000000
801 #define VIDFREQ_P0_SHIFT 24
802 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
803 #define VIDFREQ_P0_CSCLK_SHIFT 20
804 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
805 #define VIDFREQ_P0_CRCLK_SHIFT 16
806 #define VIDFREQ_P1_MASK 0x00001f00
807 #define VIDFREQ_P1_SHIFT 8
808 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
809 #define VIDFREQ_P1_CSCLK_SHIFT 4
810 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
811 #define INTTOEXT_BASE_ILK 0x11300
812 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
813 #define INTTOEXT_MAP3_SHIFT 24
814 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
815 #define INTTOEXT_MAP2_SHIFT 16
816 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
817 #define INTTOEXT_MAP1_SHIFT 8
818 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
819 #define INTTOEXT_MAP0_SHIFT 0
820 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
821 #define MEMSWCTL 0x11170 /* Ironlake only */
822 #define MEMCTL_CMD_MASK 0xe000
823 #define MEMCTL_CMD_SHIFT 13
824 #define MEMCTL_CMD_RCLK_OFF 0
825 #define MEMCTL_CMD_RCLK_ON 1
826 #define MEMCTL_CMD_CHFREQ 2
827 #define MEMCTL_CMD_CHVID 3
828 #define MEMCTL_CMD_VMMOFF 4
829 #define MEMCTL_CMD_VMMON 5
830 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
831 when command complete */
832 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
833 #define MEMCTL_FREQ_SHIFT 8
834 #define MEMCTL_SFCAVM (1<<7)
835 #define MEMCTL_TGT_VID_MASK 0x007f
836 #define MEMIHYST 0x1117c
837 #define MEMINTREN 0x11180 /* 16 bits */
838 #define MEMINT_RSEXIT_EN (1<<8)
839 #define MEMINT_CX_SUPR_EN (1<<7)
840 #define MEMINT_CONT_BUSY_EN (1<<6)
841 #define MEMINT_AVG_BUSY_EN (1<<5)
842 #define MEMINT_EVAL_CHG_EN (1<<4)
843 #define MEMINT_MON_IDLE_EN (1<<3)
844 #define MEMINT_UP_EVAL_EN (1<<2)
845 #define MEMINT_DOWN_EVAL_EN (1<<1)
846 #define MEMINT_SW_CMD_EN (1<<0)
847 #define MEMINTRSTR 0x11182 /* 16 bits */
848 #define MEM_RSEXIT_MASK 0xc000
849 #define MEM_RSEXIT_SHIFT 14
850 #define MEM_CONT_BUSY_MASK 0x3000
851 #define MEM_CONT_BUSY_SHIFT 12
852 #define MEM_AVG_BUSY_MASK 0x0c00
853 #define MEM_AVG_BUSY_SHIFT 10
854 #define MEM_EVAL_CHG_MASK 0x0300
855 #define MEM_EVAL_BUSY_SHIFT 8
856 #define MEM_MON_IDLE_MASK 0x00c0
857 #define MEM_MON_IDLE_SHIFT 6
858 #define MEM_UP_EVAL_MASK 0x0030
859 #define MEM_UP_EVAL_SHIFT 4
860 #define MEM_DOWN_EVAL_MASK 0x000c
861 #define MEM_DOWN_EVAL_SHIFT 2
862 #define MEM_SW_CMD_MASK 0x0003
863 #define MEM_INT_STEER_GFX 0
864 #define MEM_INT_STEER_CMR 1
865 #define MEM_INT_STEER_SMI 2
866 #define MEM_INT_STEER_SCI 3
867 #define MEMINTRSTS 0x11184
868 #define MEMINT_RSEXIT (1<<7)
869 #define MEMINT_CONT_BUSY (1<<6)
870 #define MEMINT_AVG_BUSY (1<<5)
871 #define MEMINT_EVAL_CHG (1<<4)
872 #define MEMINT_MON_IDLE (1<<3)
873 #define MEMINT_UP_EVAL (1<<2)
874 #define MEMINT_DOWN_EVAL (1<<1)
875 #define MEMINT_SW_CMD (1<<0)
876 #define MEMMODECTL 0x11190
877 #define MEMMODE_BOOST_EN (1<<31)
878 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
879 #define MEMMODE_BOOST_FREQ_SHIFT 24
880 #define MEMMODE_IDLE_MODE_MASK 0x00030000
881 #define MEMMODE_IDLE_MODE_SHIFT 16
882 #define MEMMODE_IDLE_MODE_EVAL 0
883 #define MEMMODE_IDLE_MODE_CONT 1
884 #define MEMMODE_HWIDLE_EN (1<<15)
885 #define MEMMODE_SWMODE_EN (1<<14)
886 #define MEMMODE_RCLK_GATE (1<<13)
887 #define MEMMODE_HW_UPDATE (1<<12)
888 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
889 #define MEMMODE_FSTART_SHIFT 8
890 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
891 #define MEMMODE_FMAX_SHIFT 4
892 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
893 #define RCBMAXAVG 0x1119c
894 #define MEMSWCTL2 0x1119e /* Cantiga only */
895 #define SWMEMCMD_RENDER_OFF (0 << 13)
896 #define SWMEMCMD_RENDER_ON (1 << 13)
897 #define SWMEMCMD_SWFREQ (2 << 13)
898 #define SWMEMCMD_TARVID (3 << 13)
899 #define SWMEMCMD_VRM_OFF (4 << 13)
900 #define SWMEMCMD_VRM_ON (5 << 13)
901 #define CMDSTS (1<<12)
902 #define SFCAVM (1<<11)
903 #define SWFREQ_MASK 0x0380 /* P0-7 */
904 #define SWFREQ_SHIFT 7
905 #define TARVID_MASK 0x001f
906 #define MEMSTAT_CTG 0x111a0
907 #define RCBMINAVG 0x111a0
908 #define RCUPEI 0x111b0
909 #define RCDNEI 0x111b4
910 #define RSTDBYCTL 0x111b8
911 #define RCX_SW_EXIT (1<<23)
912 #define RSX_STATUS_MASK 0x00700000
913 #define VIDCTL 0x111c0
914 #define VIDSTS 0x111c8
915 #define VIDSTART 0x111cc /* 8 bits */
916 #define MEMSTAT_ILK 0x111f8
917 #define MEMSTAT_VID_MASK 0x7f00
918 #define MEMSTAT_VID_SHIFT 8
919 #define MEMSTAT_PSTATE_MASK 0x00f8
920 #define MEMSTAT_PSTATE_SHIFT 3
921 #define MEMSTAT_MON_ACTV (1<<2)
922 #define MEMSTAT_SRC_CTL_MASK 0x0003
923 #define MEMSTAT_SRC_CTL_CORE 0
924 #define MEMSTAT_SRC_CTL_TRB 1
925 #define MEMSTAT_SRC_CTL_THM 2
926 #define MEMSTAT_SRC_CTL_STDBY 3
927 #define RCPREVBSYTUPAVG 0x113b8
928 #define RCPREVBSYTDNAVG 0x113bc
929 #define PEG_BAND_GAP_DATA 0x14d68
935 #define OVADD 0x30000
936 #define DOVSTA 0x30008
937 #define OC_BUF (0x3<<20)
938 #define OGAMC5 0x30010
939 #define OGAMC4 0x30014
940 #define OGAMC3 0x30018
941 #define OGAMC2 0x3001c
942 #define OGAMC1 0x30020
943 #define OGAMC0 0x30024
946 * Display engine regs
949 /* Pipe A timing regs */
950 #define HTOTAL_A 0x60000
951 #define HBLANK_A 0x60004
952 #define HSYNC_A 0x60008
953 #define VTOTAL_A 0x6000c
954 #define VBLANK_A 0x60010
955 #define VSYNC_A 0x60014
956 #define PIPEASRC 0x6001c
957 #define BCLRPAT_A 0x60020
959 /* Pipe B timing regs */
960 #define HTOTAL_B 0x61000
961 #define HBLANK_B 0x61004
962 #define HSYNC_B 0x61008
963 #define VTOTAL_B 0x6100c
964 #define VBLANK_B 0x61010
965 #define VSYNC_B 0x61014
966 #define PIPEBSRC 0x6101c
967 #define BCLRPAT_B 0x61020
969 /* VGA port control */
971 #define ADPA_DAC_ENABLE (1<<31)
972 #define ADPA_DAC_DISABLE 0
973 #define ADPA_PIPE_SELECT_MASK (1<<30)
974 #define ADPA_PIPE_A_SELECT 0
975 #define ADPA_PIPE_B_SELECT (1<<30)
976 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
977 #define ADPA_SETS_HVPOLARITY 0
978 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
979 #define ADPA_VSYNC_CNTL_ENABLE 0
980 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
981 #define ADPA_HSYNC_CNTL_ENABLE 0
982 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
983 #define ADPA_VSYNC_ACTIVE_LOW 0
984 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
985 #define ADPA_HSYNC_ACTIVE_LOW 0
986 #define ADPA_DPMS_MASK (~(3<<10))
987 #define ADPA_DPMS_ON (0<<10)
988 #define ADPA_DPMS_SUSPEND (1<<10)
989 #define ADPA_DPMS_STANDBY (2<<10)
990 #define ADPA_DPMS_OFF (3<<10)
992 /* Hotplug control (945+ only) */
993 #define PORT_HOTPLUG_EN 0x61110
994 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
995 #define DPB_HOTPLUG_INT_EN (1 << 29)
996 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
997 #define DPC_HOTPLUG_INT_EN (1 << 28)
998 #define HDMID_HOTPLUG_INT_EN (1 << 27)
999 #define DPD_HOTPLUG_INT_EN (1 << 27)
1000 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1001 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1002 #define TV_HOTPLUG_INT_EN (1 << 18)
1003 #define CRT_HOTPLUG_INT_EN (1 << 9)
1004 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1005 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1006 /* must use period 64 on GM45 according to docs */
1007 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1008 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1009 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1010 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1011 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1012 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1013 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1014 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1015 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1016 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1017 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1018 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1019 #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
1020 #define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f
1022 #define PORT_HOTPLUG_STAT 0x61114
1023 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1024 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
1025 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1026 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
1027 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1028 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
1029 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1030 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1031 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1032 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1033 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1034 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1035 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1036 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1038 /* SDVO port control */
1039 #define SDVOB 0x61140
1040 #define SDVOC 0x61160
1041 #define SDVO_ENABLE (1 << 31)
1042 #define SDVO_PIPE_B_SELECT (1 << 30)
1043 #define SDVO_STALL_SELECT (1 << 29)
1044 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1046 * 915G/GM SDVO pixel multiplier.
1048 * Programmed value is multiplier - 1, up to 5x.
1050 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1052 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1053 #define SDVO_PORT_MULTIPLY_SHIFT 23
1054 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1055 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1056 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1057 #define SDVOC_GANG_MODE (1 << 16)
1058 #define SDVO_ENCODING_SDVO (0x0 << 10)
1059 #define SDVO_ENCODING_HDMI (0x2 << 10)
1060 /** Requird for HDMI operation */
1061 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1062 #define SDVO_BORDER_ENABLE (1 << 7)
1063 #define SDVO_AUDIO_ENABLE (1 << 6)
1064 /** New with 965, default is to be set */
1065 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1066 /** New with 965, default is to be set */
1067 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1068 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1069 #define SDVO_DETECTED (1 << 2)
1070 /* Bits to be preserved when writing */
1071 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1072 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1074 /* DVO port control */
1075 #define DVOA 0x61120
1076 #define DVOB 0x61140
1077 #define DVOC 0x61160
1078 #define DVO_ENABLE (1 << 31)
1079 #define DVO_PIPE_B_SELECT (1 << 30)
1080 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1081 #define DVO_PIPE_STALL (1 << 28)
1082 #define DVO_PIPE_STALL_TV (2 << 28)
1083 #define DVO_PIPE_STALL_MASK (3 << 28)
1084 #define DVO_USE_VGA_SYNC (1 << 15)
1085 #define DVO_DATA_ORDER_I740 (0 << 14)
1086 #define DVO_DATA_ORDER_FP (1 << 14)
1087 #define DVO_VSYNC_DISABLE (1 << 11)
1088 #define DVO_HSYNC_DISABLE (1 << 10)
1089 #define DVO_VSYNC_TRISTATE (1 << 9)
1090 #define DVO_HSYNC_TRISTATE (1 << 8)
1091 #define DVO_BORDER_ENABLE (1 << 7)
1092 #define DVO_DATA_ORDER_GBRG (1 << 6)
1093 #define DVO_DATA_ORDER_RGGB (0 << 6)
1094 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1095 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1096 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1097 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1098 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1099 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1100 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1101 #define DVO_PRESERVE_MASK (0x7<<24)
1102 #define DVOA_SRCDIM 0x61124
1103 #define DVOB_SRCDIM 0x61144
1104 #define DVOC_SRCDIM 0x61164
1105 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1106 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1108 /* LVDS port control */
1109 #define LVDS 0x61180
1111 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1112 * the DPLL semantics change when the LVDS is assigned to that pipe.
1114 #define LVDS_PORT_EN (1 << 31)
1115 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1116 #define LVDS_PIPEB_SELECT (1 << 30)
1117 /* LVDS dithering flag on 965/g4x platform */
1118 #define LVDS_ENABLE_DITHER (1 << 25)
1119 /* Enable border for unscaled (or aspect-scaled) display */
1120 #define LVDS_BORDER_ENABLE (1 << 15)
1122 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1125 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1126 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1127 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1129 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1130 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1133 #define LVDS_A3_POWER_MASK (3 << 6)
1134 #define LVDS_A3_POWER_DOWN (0 << 6)
1135 #define LVDS_A3_POWER_UP (3 << 6)
1137 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1140 #define LVDS_CLKB_POWER_MASK (3 << 4)
1141 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1142 #define LVDS_CLKB_POWER_UP (3 << 4)
1144 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1145 * setting for whether we are in dual-channel mode. The B3 pair will
1146 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1148 #define LVDS_B0B3_POWER_MASK (3 << 2)
1149 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1150 #define LVDS_B0B3_POWER_UP (3 << 2)
1152 /* Panel power sequencing */
1153 #define PP_STATUS 0x61200
1154 #define PP_ON (1 << 31)
1156 * Indicates that all dependencies of the panel are on:
1160 * - LVDS/DVOB/DVOC on
1162 #define PP_READY (1 << 30)
1163 #define PP_SEQUENCE_NONE (0 << 28)
1164 #define PP_SEQUENCE_ON (1 << 28)
1165 #define PP_SEQUENCE_OFF (2 << 28)
1166 #define PP_SEQUENCE_MASK 0x30000000
1167 #define PP_CONTROL 0x61204
1168 #define POWER_TARGET_ON (1 << 0)
1169 #define PP_ON_DELAYS 0x61208
1170 #define PP_OFF_DELAYS 0x6120c
1171 #define PP_DIVISOR 0x61210
1174 #define PFIT_CONTROL 0x61230
1175 #define PFIT_ENABLE (1 << 31)
1176 #define PFIT_PIPE_MASK (3 << 29)
1177 #define PFIT_PIPE_SHIFT 29
1178 #define VERT_INTERP_DISABLE (0 << 10)
1179 #define VERT_INTERP_BILINEAR (1 << 10)
1180 #define VERT_INTERP_MASK (3 << 10)
1181 #define VERT_AUTO_SCALE (1 << 9)
1182 #define HORIZ_INTERP_DISABLE (0 << 6)
1183 #define HORIZ_INTERP_BILINEAR (1 << 6)
1184 #define HORIZ_INTERP_MASK (3 << 6)
1185 #define HORIZ_AUTO_SCALE (1 << 5)
1186 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1187 #define PFIT_FILTER_FUZZY (0 << 24)
1188 #define PFIT_SCALING_AUTO (0 << 26)
1189 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1190 #define PFIT_SCALING_PILLAR (2 << 26)
1191 #define PFIT_SCALING_LETTER (3 << 26)
1192 #define PFIT_PGM_RATIOS 0x61234
1193 #define PFIT_VERT_SCALE_MASK 0xfff00000
1194 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1196 #define PFIT_VERT_SCALE_SHIFT 20
1197 #define PFIT_VERT_SCALE_MASK 0xfff00000
1198 #define PFIT_HORIZ_SCALE_SHIFT 4
1199 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1201 #define PFIT_VERT_SCALE_SHIFT_965 16
1202 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1203 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1204 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1206 #define PFIT_AUTO_RATIOS 0x61238
1208 /* Backlight control */
1209 #define BLC_PWM_CTL 0x61254
1210 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1211 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1212 #define BLM_COMBINATION_MODE (1 << 30)
1214 * This is the most significant 15 bits of the number of backlight cycles in a
1215 * complete cycle of the modulated backlight control.
1217 * The actual value is this field multiplied by two.
1219 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1220 #define BLM_LEGACY_MODE (1 << 16)
1222 * This is the number of cycles out of the backlight modulation cycle for which
1223 * the backlight is on.
1225 * This field must be no greater than the number of cycles in the complete
1226 * backlight modulation cycle.
1228 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1229 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1231 #define BLC_HIST_CTL 0x61260
1233 /* TV port control */
1234 #define TV_CTL 0x68000
1235 /** Enables the TV encoder */
1236 # define TV_ENC_ENABLE (1 << 31)
1237 /** Sources the TV encoder input from pipe B instead of A. */
1238 # define TV_ENC_PIPEB_SELECT (1 << 30)
1239 /** Outputs composite video (DAC A only) */
1240 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1241 /** Outputs SVideo video (DAC B/C) */
1242 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1243 /** Outputs Component video (DAC A/B/C) */
1244 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1245 /** Outputs Composite and SVideo (DAC A/B/C) */
1246 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1247 # define TV_TRILEVEL_SYNC (1 << 21)
1248 /** Enables slow sync generation (945GM only) */
1249 # define TV_SLOW_SYNC (1 << 20)
1250 /** Selects 4x oversampling for 480i and 576p */
1251 # define TV_OVERSAMPLE_4X (0 << 18)
1252 /** Selects 2x oversampling for 720p and 1080i */
1253 # define TV_OVERSAMPLE_2X (1 << 18)
1254 /** Selects no oversampling for 1080p */
1255 # define TV_OVERSAMPLE_NONE (2 << 18)
1256 /** Selects 8x oversampling */
1257 # define TV_OVERSAMPLE_8X (3 << 18)
1258 /** Selects progressive mode rather than interlaced */
1259 # define TV_PROGRESSIVE (1 << 17)
1260 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1261 # define TV_PAL_BURST (1 << 16)
1262 /** Field for setting delay of Y compared to C */
1263 # define TV_YC_SKEW_MASK (7 << 12)
1264 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1265 # define TV_ENC_SDP_FIX (1 << 11)
1267 * Enables a fix for the 915GM only.
1269 * Not sure what it does.
1271 # define TV_ENC_C0_FIX (1 << 10)
1272 /** Bits that must be preserved by software */
1273 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1274 # define TV_FUSE_STATE_MASK (3 << 4)
1275 /** Read-only state that reports all features enabled */
1276 # define TV_FUSE_STATE_ENABLED (0 << 4)
1277 /** Read-only state that reports that Macrovision is disabled in hardware*/
1278 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1279 /** Read-only state that reports that TV-out is disabled in hardware. */
1280 # define TV_FUSE_STATE_DISABLED (2 << 4)
1281 /** Normal operation */
1282 # define TV_TEST_MODE_NORMAL (0 << 0)
1283 /** Encoder test pattern 1 - combo pattern */
1284 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1285 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1286 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1287 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1288 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1289 /** Encoder test pattern 4 - random noise */
1290 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1291 /** Encoder test pattern 5 - linear color ramps */
1292 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1294 * This test mode forces the DACs to 50% of full output.
1296 * This is used for load detection in combination with TVDAC_SENSE_MASK
1298 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1299 # define TV_TEST_MODE_MASK (7 << 0)
1301 #define TV_DAC 0x68004
1303 * Reports that DAC state change logic has reported change (RO).
1305 * This gets cleared when TV_DAC_STATE_EN is cleared
1307 # define TVDAC_STATE_CHG (1 << 31)
1308 # define TVDAC_SENSE_MASK (7 << 28)
1309 /** Reports that DAC A voltage is above the detect threshold */
1310 # define TVDAC_A_SENSE (1 << 30)
1311 /** Reports that DAC B voltage is above the detect threshold */
1312 # define TVDAC_B_SENSE (1 << 29)
1313 /** Reports that DAC C voltage is above the detect threshold */
1314 # define TVDAC_C_SENSE (1 << 28)
1316 * Enables DAC state detection logic, for load-based TV detection.
1318 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1319 * to off, for load detection to work.
1321 # define TVDAC_STATE_CHG_EN (1 << 27)
1322 /** Sets the DAC A sense value to high */
1323 # define TVDAC_A_SENSE_CTL (1 << 26)
1324 /** Sets the DAC B sense value to high */
1325 # define TVDAC_B_SENSE_CTL (1 << 25)
1326 /** Sets the DAC C sense value to high */
1327 # define TVDAC_C_SENSE_CTL (1 << 24)
1328 /** Overrides the ENC_ENABLE and DAC voltage levels */
1329 # define DAC_CTL_OVERRIDE (1 << 7)
1330 /** Sets the slew rate. Must be preserved in software */
1331 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1332 # define DAC_A_1_3_V (0 << 4)
1333 # define DAC_A_1_1_V (1 << 4)
1334 # define DAC_A_0_7_V (2 << 4)
1335 # define DAC_A_MASK (3 << 4)
1336 # define DAC_B_1_3_V (0 << 2)
1337 # define DAC_B_1_1_V (1 << 2)
1338 # define DAC_B_0_7_V (2 << 2)
1339 # define DAC_B_MASK (3 << 2)
1340 # define DAC_C_1_3_V (0 << 0)
1341 # define DAC_C_1_1_V (1 << 0)
1342 # define DAC_C_0_7_V (2 << 0)
1343 # define DAC_C_MASK (3 << 0)
1346 * CSC coefficients are stored in a floating point format with 9 bits of
1347 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1348 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1349 * -1 (0x3) being the only legal negative value.
1351 #define TV_CSC_Y 0x68010
1352 # define TV_RY_MASK 0x07ff0000
1353 # define TV_RY_SHIFT 16
1354 # define TV_GY_MASK 0x00000fff
1355 # define TV_GY_SHIFT 0
1357 #define TV_CSC_Y2 0x68014
1358 # define TV_BY_MASK 0x07ff0000
1359 # define TV_BY_SHIFT 16
1361 * Y attenuation for component video.
1363 * Stored in 1.9 fixed point.
1365 # define TV_AY_MASK 0x000003ff
1366 # define TV_AY_SHIFT 0
1368 #define TV_CSC_U 0x68018
1369 # define TV_RU_MASK 0x07ff0000
1370 # define TV_RU_SHIFT 16
1371 # define TV_GU_MASK 0x000007ff
1372 # define TV_GU_SHIFT 0
1374 #define TV_CSC_U2 0x6801c
1375 # define TV_BU_MASK 0x07ff0000
1376 # define TV_BU_SHIFT 16
1378 * U attenuation for component video.
1380 * Stored in 1.9 fixed point.
1382 # define TV_AU_MASK 0x000003ff
1383 # define TV_AU_SHIFT 0
1385 #define TV_CSC_V 0x68020
1386 # define TV_RV_MASK 0x0fff0000
1387 # define TV_RV_SHIFT 16
1388 # define TV_GV_MASK 0x000007ff
1389 # define TV_GV_SHIFT 0
1391 #define TV_CSC_V2 0x68024
1392 # define TV_BV_MASK 0x07ff0000
1393 # define TV_BV_SHIFT 16
1395 * V attenuation for component video.
1397 * Stored in 1.9 fixed point.
1399 # define TV_AV_MASK 0x000007ff
1400 # define TV_AV_SHIFT 0
1402 #define TV_CLR_KNOBS 0x68028
1403 /** 2s-complement brightness adjustment */
1404 # define TV_BRIGHTNESS_MASK 0xff000000
1405 # define TV_BRIGHTNESS_SHIFT 24
1406 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1407 # define TV_CONTRAST_MASK 0x00ff0000
1408 # define TV_CONTRAST_SHIFT 16
1409 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1410 # define TV_SATURATION_MASK 0x0000ff00
1411 # define TV_SATURATION_SHIFT 8
1412 /** Hue adjustment, as an integer phase angle in degrees */
1413 # define TV_HUE_MASK 0x000000ff
1414 # define TV_HUE_SHIFT 0
1416 #define TV_CLR_LEVEL 0x6802c
1417 /** Controls the DAC level for black */
1418 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1419 # define TV_BLACK_LEVEL_SHIFT 16
1420 /** Controls the DAC level for blanking */
1421 # define TV_BLANK_LEVEL_MASK 0x000001ff
1422 # define TV_BLANK_LEVEL_SHIFT 0
1424 #define TV_H_CTL_1 0x68030
1425 /** Number of pixels in the hsync. */
1426 # define TV_HSYNC_END_MASK 0x1fff0000
1427 # define TV_HSYNC_END_SHIFT 16
1428 /** Total number of pixels minus one in the line (display and blanking). */
1429 # define TV_HTOTAL_MASK 0x00001fff
1430 # define TV_HTOTAL_SHIFT 0
1432 #define TV_H_CTL_2 0x68034
1433 /** Enables the colorburst (needed for non-component color) */
1434 # define TV_BURST_ENA (1 << 31)
1435 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1436 # define TV_HBURST_START_SHIFT 16
1437 # define TV_HBURST_START_MASK 0x1fff0000
1438 /** Length of the colorburst */
1439 # define TV_HBURST_LEN_SHIFT 0
1440 # define TV_HBURST_LEN_MASK 0x0001fff
1442 #define TV_H_CTL_3 0x68038
1443 /** End of hblank, measured in pixels minus one from start of hsync */
1444 # define TV_HBLANK_END_SHIFT 16
1445 # define TV_HBLANK_END_MASK 0x1fff0000
1446 /** Start of hblank, measured in pixels minus one from start of hsync */
1447 # define TV_HBLANK_START_SHIFT 0
1448 # define TV_HBLANK_START_MASK 0x0001fff
1450 #define TV_V_CTL_1 0x6803c
1452 # define TV_NBR_END_SHIFT 16
1453 # define TV_NBR_END_MASK 0x07ff0000
1455 # define TV_VI_END_F1_SHIFT 8
1456 # define TV_VI_END_F1_MASK 0x00003f00
1458 # define TV_VI_END_F2_SHIFT 0
1459 # define TV_VI_END_F2_MASK 0x0000003f
1461 #define TV_V_CTL_2 0x68040
1462 /** Length of vsync, in half lines */
1463 # define TV_VSYNC_LEN_MASK 0x07ff0000
1464 # define TV_VSYNC_LEN_SHIFT 16
1465 /** Offset of the start of vsync in field 1, measured in one less than the
1466 * number of half lines.
1468 # define TV_VSYNC_START_F1_MASK 0x00007f00
1469 # define TV_VSYNC_START_F1_SHIFT 8
1471 * Offset of the start of vsync in field 2, measured in one less than the
1472 * number of half lines.
1474 # define TV_VSYNC_START_F2_MASK 0x0000007f
1475 # define TV_VSYNC_START_F2_SHIFT 0
1477 #define TV_V_CTL_3 0x68044
1478 /** Enables generation of the equalization signal */
1479 # define TV_EQUAL_ENA (1 << 31)
1480 /** Length of vsync, in half lines */
1481 # define TV_VEQ_LEN_MASK 0x007f0000
1482 # define TV_VEQ_LEN_SHIFT 16
1483 /** Offset of the start of equalization in field 1, measured in one less than
1484 * the number of half lines.
1486 # define TV_VEQ_START_F1_MASK 0x0007f00
1487 # define TV_VEQ_START_F1_SHIFT 8
1489 * Offset of the start of equalization in field 2, measured in one less than
1490 * the number of half lines.
1492 # define TV_VEQ_START_F2_MASK 0x000007f
1493 # define TV_VEQ_START_F2_SHIFT 0
1495 #define TV_V_CTL_4 0x68048
1497 * Offset to start of vertical colorburst, measured in one less than the
1498 * number of lines from vertical start.
1500 # define TV_VBURST_START_F1_MASK 0x003f0000
1501 # define TV_VBURST_START_F1_SHIFT 16
1503 * Offset to the end of vertical colorburst, measured in one less than the
1504 * number of lines from the start of NBR.
1506 # define TV_VBURST_END_F1_MASK 0x000000ff
1507 # define TV_VBURST_END_F1_SHIFT 0
1509 #define TV_V_CTL_5 0x6804c
1511 * Offset to start of vertical colorburst, measured in one less than the
1512 * number of lines from vertical start.
1514 # define TV_VBURST_START_F2_MASK 0x003f0000
1515 # define TV_VBURST_START_F2_SHIFT 16
1517 * Offset to the end of vertical colorburst, measured in one less than the
1518 * number of lines from the start of NBR.
1520 # define TV_VBURST_END_F2_MASK 0x000000ff
1521 # define TV_VBURST_END_F2_SHIFT 0
1523 #define TV_V_CTL_6 0x68050
1525 * Offset to start of vertical colorburst, measured in one less than the
1526 * number of lines from vertical start.
1528 # define TV_VBURST_START_F3_MASK 0x003f0000
1529 # define TV_VBURST_START_F3_SHIFT 16
1531 * Offset to the end of vertical colorburst, measured in one less than the
1532 * number of lines from the start of NBR.
1534 # define TV_VBURST_END_F3_MASK 0x000000ff
1535 # define TV_VBURST_END_F3_SHIFT 0
1537 #define TV_V_CTL_7 0x68054
1539 * Offset to start of vertical colorburst, measured in one less than the
1540 * number of lines from vertical start.
1542 # define TV_VBURST_START_F4_MASK 0x003f0000
1543 # define TV_VBURST_START_F4_SHIFT 16
1545 * Offset to the end of vertical colorburst, measured in one less than the
1546 * number of lines from the start of NBR.
1548 # define TV_VBURST_END_F4_MASK 0x000000ff
1549 # define TV_VBURST_END_F4_SHIFT 0
1551 #define TV_SC_CTL_1 0x68060
1552 /** Turns on the first subcarrier phase generation DDA */
1553 # define TV_SC_DDA1_EN (1 << 31)
1554 /** Turns on the first subcarrier phase generation DDA */
1555 # define TV_SC_DDA2_EN (1 << 30)
1556 /** Turns on the first subcarrier phase generation DDA */
1557 # define TV_SC_DDA3_EN (1 << 29)
1558 /** Sets the subcarrier DDA to reset frequency every other field */
1559 # define TV_SC_RESET_EVERY_2 (0 << 24)
1560 /** Sets the subcarrier DDA to reset frequency every fourth field */
1561 # define TV_SC_RESET_EVERY_4 (1 << 24)
1562 /** Sets the subcarrier DDA to reset frequency every eighth field */
1563 # define TV_SC_RESET_EVERY_8 (2 << 24)
1564 /** Sets the subcarrier DDA to never reset the frequency */
1565 # define TV_SC_RESET_NEVER (3 << 24)
1566 /** Sets the peak amplitude of the colorburst.*/
1567 # define TV_BURST_LEVEL_MASK 0x00ff0000
1568 # define TV_BURST_LEVEL_SHIFT 16
1569 /** Sets the increment of the first subcarrier phase generation DDA */
1570 # define TV_SCDDA1_INC_MASK 0x00000fff
1571 # define TV_SCDDA1_INC_SHIFT 0
1573 #define TV_SC_CTL_2 0x68064
1574 /** Sets the rollover for the second subcarrier phase generation DDA */
1575 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1576 # define TV_SCDDA2_SIZE_SHIFT 16
1577 /** Sets the increent of the second subcarrier phase generation DDA */
1578 # define TV_SCDDA2_INC_MASK 0x00007fff
1579 # define TV_SCDDA2_INC_SHIFT 0
1581 #define TV_SC_CTL_3 0x68068
1582 /** Sets the rollover for the third subcarrier phase generation DDA */
1583 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1584 # define TV_SCDDA3_SIZE_SHIFT 16
1585 /** Sets the increent of the third subcarrier phase generation DDA */
1586 # define TV_SCDDA3_INC_MASK 0x00007fff
1587 # define TV_SCDDA3_INC_SHIFT 0
1589 #define TV_WIN_POS 0x68070
1590 /** X coordinate of the display from the start of horizontal active */
1591 # define TV_XPOS_MASK 0x1fff0000
1592 # define TV_XPOS_SHIFT 16
1593 /** Y coordinate of the display from the start of vertical active (NBR) */
1594 # define TV_YPOS_MASK 0x00000fff
1595 # define TV_YPOS_SHIFT 0
1597 #define TV_WIN_SIZE 0x68074
1598 /** Horizontal size of the display window, measured in pixels*/
1599 # define TV_XSIZE_MASK 0x1fff0000
1600 # define TV_XSIZE_SHIFT 16
1602 * Vertical size of the display window, measured in pixels.
1604 * Must be even for interlaced modes.
1606 # define TV_YSIZE_MASK 0x00000fff
1607 # define TV_YSIZE_SHIFT 0
1609 #define TV_FILTER_CTL_1 0x68080
1611 * Enables automatic scaling calculation.
1613 * If set, the rest of the registers are ignored, and the calculated values can
1614 * be read back from the register.
1616 # define TV_AUTO_SCALE (1 << 31)
1618 * Disables the vertical filter.
1620 * This is required on modes more than 1024 pixels wide */
1621 # define TV_V_FILTER_BYPASS (1 << 29)
1622 /** Enables adaptive vertical filtering */
1623 # define TV_VADAPT (1 << 28)
1624 # define TV_VADAPT_MODE_MASK (3 << 26)
1625 /** Selects the least adaptive vertical filtering mode */
1626 # define TV_VADAPT_MODE_LEAST (0 << 26)
1627 /** Selects the moderately adaptive vertical filtering mode */
1628 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1629 /** Selects the most adaptive vertical filtering mode */
1630 # define TV_VADAPT_MODE_MOST (3 << 26)
1632 * Sets the horizontal scaling factor.
1634 * This should be the fractional part of the horizontal scaling factor divided
1635 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1637 * (src width - 1) / ((oversample * dest width) - 1)
1639 # define TV_HSCALE_FRAC_MASK 0x00003fff
1640 # define TV_HSCALE_FRAC_SHIFT 0
1642 #define TV_FILTER_CTL_2 0x68084
1644 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1646 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1648 # define TV_VSCALE_INT_MASK 0x00038000
1649 # define TV_VSCALE_INT_SHIFT 15
1651 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1653 * \sa TV_VSCALE_INT_MASK
1655 # define TV_VSCALE_FRAC_MASK 0x00007fff
1656 # define TV_VSCALE_FRAC_SHIFT 0
1658 #define TV_FILTER_CTL_3 0x68088
1660 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1662 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1664 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1666 # define TV_VSCALE_IP_INT_MASK 0x00038000
1667 # define TV_VSCALE_IP_INT_SHIFT 15
1669 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1671 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1673 * \sa TV_VSCALE_IP_INT_MASK
1675 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1676 # define TV_VSCALE_IP_FRAC_SHIFT 0
1678 #define TV_CC_CONTROL 0x68090
1679 # define TV_CC_ENABLE (1 << 31)
1681 * Specifies which field to send the CC data in.
1683 * CC data is usually sent in field 0.
1685 # define TV_CC_FID_MASK (1 << 27)
1686 # define TV_CC_FID_SHIFT 27
1687 /** Sets the horizontal position of the CC data. Usually 135. */
1688 # define TV_CC_HOFF_MASK 0x03ff0000
1689 # define TV_CC_HOFF_SHIFT 16
1690 /** Sets the vertical position of the CC data. Usually 21 */
1691 # define TV_CC_LINE_MASK 0x0000003f
1692 # define TV_CC_LINE_SHIFT 0
1694 #define TV_CC_DATA 0x68094
1695 # define TV_CC_RDY (1 << 31)
1696 /** Second word of CC data to be transmitted. */
1697 # define TV_CC_DATA_2_MASK 0x007f0000
1698 # define TV_CC_DATA_2_SHIFT 16
1699 /** First word of CC data to be transmitted. */
1700 # define TV_CC_DATA_1_MASK 0x0000007f
1701 # define TV_CC_DATA_1_SHIFT 0
1703 #define TV_H_LUMA_0 0x68100
1704 #define TV_H_LUMA_59 0x681ec
1705 #define TV_H_CHROMA_0 0x68200
1706 #define TV_H_CHROMA_59 0x682ec
1707 #define TV_V_LUMA_0 0x68300
1708 #define TV_V_LUMA_42 0x683a8
1709 #define TV_V_CHROMA_0 0x68400
1710 #define TV_V_CHROMA_42 0x684a8
1713 #define DP_A 0x64000 /* eDP */
1714 #define DP_B 0x64100
1715 #define DP_C 0x64200
1716 #define DP_D 0x64300
1718 #define DP_PORT_EN (1 << 31)
1719 #define DP_PIPEB_SELECT (1 << 30)
1721 /* Link training mode - select a suitable mode for each stage */
1722 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1723 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
1724 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1725 #define DP_LINK_TRAIN_OFF (3 << 28)
1726 #define DP_LINK_TRAIN_MASK (3 << 28)
1727 #define DP_LINK_TRAIN_SHIFT 28
1729 /* Signal voltages. These are mostly controlled by the other end */
1730 #define DP_VOLTAGE_0_4 (0 << 25)
1731 #define DP_VOLTAGE_0_6 (1 << 25)
1732 #define DP_VOLTAGE_0_8 (2 << 25)
1733 #define DP_VOLTAGE_1_2 (3 << 25)
1734 #define DP_VOLTAGE_MASK (7 << 25)
1735 #define DP_VOLTAGE_SHIFT 25
1737 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1740 #define DP_PRE_EMPHASIS_0 (0 << 22)
1741 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
1742 #define DP_PRE_EMPHASIS_6 (2 << 22)
1743 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
1744 #define DP_PRE_EMPHASIS_MASK (7 << 22)
1745 #define DP_PRE_EMPHASIS_SHIFT 22
1747 /* How many wires to use. I guess 3 was too hard */
1748 #define DP_PORT_WIDTH_1 (0 << 19)
1749 #define DP_PORT_WIDTH_2 (1 << 19)
1750 #define DP_PORT_WIDTH_4 (3 << 19)
1751 #define DP_PORT_WIDTH_MASK (7 << 19)
1753 /* Mystic DPCD version 1.1 special mode */
1754 #define DP_ENHANCED_FRAMING (1 << 18)
1757 #define DP_PLL_FREQ_270MHZ (0 << 16)
1758 #define DP_PLL_FREQ_160MHZ (1 << 16)
1759 #define DP_PLL_FREQ_MASK (3 << 16)
1761 /** locked once port is enabled */
1762 #define DP_PORT_REVERSAL (1 << 15)
1765 #define DP_PLL_ENABLE (1 << 14)
1767 /** sends the clock on lane 15 of the PEG for debug */
1768 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1770 #define DP_SCRAMBLING_DISABLE (1 << 12)
1771 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
1773 /** limit RGB values to avoid confusing TVs */
1774 #define DP_COLOR_RANGE_16_235 (1 << 8)
1776 /** Turn on the audio link */
1777 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1779 /** vs and hs sync polarity */
1780 #define DP_SYNC_VS_HIGH (1 << 4)
1781 #define DP_SYNC_HS_HIGH (1 << 3)
1784 #define DP_DETECTED (1 << 2)
1786 /** The aux channel provides a way to talk to the
1787 * signal sink for DDC etc. Max packet size supported
1788 * is 20 bytes in each direction, hence the 5 fixed
1791 #define DPA_AUX_CH_CTL 0x64010
1792 #define DPA_AUX_CH_DATA1 0x64014
1793 #define DPA_AUX_CH_DATA2 0x64018
1794 #define DPA_AUX_CH_DATA3 0x6401c
1795 #define DPA_AUX_CH_DATA4 0x64020
1796 #define DPA_AUX_CH_DATA5 0x64024
1798 #define DPB_AUX_CH_CTL 0x64110
1799 #define DPB_AUX_CH_DATA1 0x64114
1800 #define DPB_AUX_CH_DATA2 0x64118
1801 #define DPB_AUX_CH_DATA3 0x6411c
1802 #define DPB_AUX_CH_DATA4 0x64120
1803 #define DPB_AUX_CH_DATA5 0x64124
1805 #define DPC_AUX_CH_CTL 0x64210
1806 #define DPC_AUX_CH_DATA1 0x64214
1807 #define DPC_AUX_CH_DATA2 0x64218
1808 #define DPC_AUX_CH_DATA3 0x6421c
1809 #define DPC_AUX_CH_DATA4 0x64220
1810 #define DPC_AUX_CH_DATA5 0x64224
1812 #define DPD_AUX_CH_CTL 0x64310
1813 #define DPD_AUX_CH_DATA1 0x64314
1814 #define DPD_AUX_CH_DATA2 0x64318
1815 #define DPD_AUX_CH_DATA3 0x6431c
1816 #define DPD_AUX_CH_DATA4 0x64320
1817 #define DPD_AUX_CH_DATA5 0x64324
1819 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1820 #define DP_AUX_CH_CTL_DONE (1 << 30)
1821 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
1822 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
1823 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1824 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
1825 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
1826 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
1827 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
1828 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
1829 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1830 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
1831 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1832 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
1833 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
1834 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
1835 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
1836 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
1837 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
1838 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1839 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1842 * Computing GMCH M and N values for the Display Port link
1844 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1846 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1848 * The GMCH value is used internally
1850 * bytes_per_pixel is the number of bytes coming out of the plane,
1851 * which is after the LUTs, so we want the bytes for our color format.
1852 * For our current usage, this is always 3, one byte for R, G and B.
1854 #define PIPEA_GMCH_DATA_M 0x70050
1855 #define PIPEB_GMCH_DATA_M 0x71050
1857 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1858 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1859 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
1861 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
1863 #define PIPEA_GMCH_DATA_N 0x70054
1864 #define PIPEB_GMCH_DATA_N 0x71054
1865 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
1868 * Computing Link M and N values for the Display Port link
1870 * Link M / N = pixel_clock / ls_clk
1872 * (the DP spec calls pixel_clock the 'strm_clk')
1874 * The Link value is transmitted in the Main Stream
1875 * Attributes and VB-ID.
1878 #define PIPEA_DP_LINK_M 0x70060
1879 #define PIPEB_DP_LINK_M 0x71060
1880 #define PIPEA_DP_LINK_M_MASK (0xffffff)
1882 #define PIPEA_DP_LINK_N 0x70064
1883 #define PIPEB_DP_LINK_N 0x71064
1884 #define PIPEA_DP_LINK_N_MASK (0xffffff)
1886 /* Display & cursor control */
1888 /* dithering flag on Ironlake */
1889 #define PIPE_ENABLE_DITHER (1 << 4)
1891 #define PIPEADSL 0x70000
1892 #define PIPEACONF 0x70008
1893 #define PIPEACONF_ENABLE (1<<31)
1894 #define PIPEACONF_DISABLE 0
1895 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1896 #define I965_PIPECONF_ACTIVE (1<<30)
1897 #define PIPEACONF_SINGLE_WIDE 0
1898 #define PIPEACONF_PIPE_UNLOCKED 0
1899 #define PIPEACONF_PIPE_LOCKED (1<<25)
1900 #define PIPEACONF_PALETTE 0
1901 #define PIPEACONF_GAMMA (1<<24)
1902 #define PIPECONF_FORCE_BORDER (1<<25)
1903 #define PIPECONF_PROGRESSIVE (0 << 21)
1904 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1905 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1906 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
1907 #define PIPEASTAT 0x70024
1908 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1909 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1910 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
1911 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1912 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1913 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1914 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1915 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1916 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1917 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1918 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1919 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1920 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1921 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1922 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1923 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1924 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1925 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1926 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1927 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1928 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1929 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
1930 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1931 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1932 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1933 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1934 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1935 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1936 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1937 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
1938 #define PIPE_8BPC (0 << 5)
1939 #define PIPE_10BPC (1 << 5)
1940 #define PIPE_6BPC (2 << 5)
1941 #define PIPE_12BPC (3 << 5)
1943 #define DSPARB 0x70030
1944 #define DSPARB_CSTART_MASK (0x7f << 7)
1945 #define DSPARB_CSTART_SHIFT 7
1946 #define DSPARB_BSTART_MASK (0x7f)
1947 #define DSPARB_BSTART_SHIFT 0
1948 #define DSPARB_BEND_SHIFT 9 /* on 855 */
1949 #define DSPARB_AEND_SHIFT 0
1951 #define DSPFW1 0x70034
1952 #define DSPFW_SR_SHIFT 23
1953 #define DSPFW_CURSORB_SHIFT 16
1954 #define DSPFW_PLANEB_SHIFT 8
1955 #define DSPFW2 0x70038
1956 #define DSPFW_CURSORA_MASK 0x00003f00
1957 #define DSPFW_CURSORA_SHIFT 8
1958 #define DSPFW3 0x7003c
1959 #define DSPFW_HPLL_SR_EN (1<<31)
1960 #define DSPFW_CURSOR_SR_SHIFT 24
1961 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
1963 /* FIFO watermark sizes etc */
1964 #define G4X_FIFO_LINE_SIZE 64
1965 #define I915_FIFO_LINE_SIZE 64
1966 #define I830_FIFO_LINE_SIZE 32
1968 #define G4X_FIFO_SIZE 127
1969 #define I945_FIFO_SIZE 127 /* 945 & 965 */
1970 #define I915_FIFO_SIZE 95
1971 #define I855GM_FIFO_SIZE 127 /* In cachelines */
1972 #define I830_FIFO_SIZE 95
1974 #define G4X_MAX_WM 0x3f
1975 #define I915_MAX_WM 0x3f
1977 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
1978 #define PINEVIEW_FIFO_LINE_SIZE 64
1979 #define PINEVIEW_MAX_WM 0x1ff
1980 #define PINEVIEW_DFT_WM 0x3f
1981 #define PINEVIEW_DFT_HPLLOFF_WM 0
1982 #define PINEVIEW_GUARD_WM 10
1983 #define PINEVIEW_CURSOR_FIFO 64
1984 #define PINEVIEW_CURSOR_MAX_WM 0x3f
1985 #define PINEVIEW_CURSOR_DFT_WM 0
1986 #define PINEVIEW_CURSOR_GUARD_WM 5
1989 * The two pipe frame counter registers are not synchronized, so
1990 * reading a stable value is somewhat tricky. The following code
1994 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1995 * PIPE_FRAME_HIGH_SHIFT;
1996 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1997 * PIPE_FRAME_LOW_SHIFT);
1998 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1999 * PIPE_FRAME_HIGH_SHIFT);
2000 * } while (high1 != high2);
2001 * frame = (high1 << 8) | low1;
2003 #define PIPEAFRAMEHIGH 0x70040
2004 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2005 #define PIPE_FRAME_HIGH_SHIFT 0
2006 #define PIPEAFRAMEPIXEL 0x70044
2007 #define PIPE_FRAME_LOW_MASK 0xff000000
2008 #define PIPE_FRAME_LOW_SHIFT 24
2009 #define PIPE_PIXEL_MASK 0x00ffffff
2010 #define PIPE_PIXEL_SHIFT 0
2011 /* GM45+ just has to be different */
2012 #define PIPEA_FRMCOUNT_GM45 0x70040
2013 #define PIPEA_FLIPCOUNT_GM45 0x70044
2015 /* Cursor A & B regs */
2016 #define CURACNTR 0x70080
2017 /* Old style CUR*CNTR flags (desktop 8xx) */
2018 #define CURSOR_ENABLE 0x80000000
2019 #define CURSOR_GAMMA_ENABLE 0x40000000
2020 #define CURSOR_STRIDE_MASK 0x30000000
2021 #define CURSOR_FORMAT_SHIFT 24
2022 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2023 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2024 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2025 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2026 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2027 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2028 /* New style CUR*CNTR flags */
2029 #define CURSOR_MODE 0x27
2030 #define CURSOR_MODE_DISABLE 0x00
2031 #define CURSOR_MODE_64_32B_AX 0x07
2032 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2033 #define MCURSOR_PIPE_SELECT (1 << 28)
2034 #define MCURSOR_PIPE_A 0x00
2035 #define MCURSOR_PIPE_B (1 << 28)
2036 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2037 #define CURABASE 0x70084
2038 #define CURAPOS 0x70088
2039 #define CURSOR_POS_MASK 0x007FF
2040 #define CURSOR_POS_SIGN 0x8000
2041 #define CURSOR_X_SHIFT 0
2042 #define CURSOR_Y_SHIFT 16
2043 #define CURSIZE 0x700a0
2044 #define CURBCNTR 0x700c0
2045 #define CURBBASE 0x700c4
2046 #define CURBPOS 0x700c8
2048 /* Display A control */
2049 #define DSPACNTR 0x70180
2050 #define DISPLAY_PLANE_ENABLE (1<<31)
2051 #define DISPLAY_PLANE_DISABLE 0
2052 #define DISPPLANE_GAMMA_ENABLE (1<<30)
2053 #define DISPPLANE_GAMMA_DISABLE 0
2054 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2055 #define DISPPLANE_8BPP (0x2<<26)
2056 #define DISPPLANE_15_16BPP (0x4<<26)
2057 #define DISPPLANE_16BPP (0x5<<26)
2058 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2059 #define DISPPLANE_32BPP (0x7<<26)
2060 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2061 #define DISPPLANE_STEREO_ENABLE (1<<25)
2062 #define DISPPLANE_STEREO_DISABLE 0
2063 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
2064 #define DISPPLANE_SEL_PIPE_A 0
2065 #define DISPPLANE_SEL_PIPE_B (1<<24)
2066 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2067 #define DISPPLANE_SRC_KEY_DISABLE 0
2068 #define DISPPLANE_LINE_DOUBLE (1<<20)
2069 #define DISPPLANE_NO_LINE_DOUBLE 0
2070 #define DISPPLANE_STEREO_POLARITY_FIRST 0
2071 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2072 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2073 #define DISPPLANE_TILED (1<<10)
2074 #define DSPAADDR 0x70184
2075 #define DSPASTRIDE 0x70188
2076 #define DSPAPOS 0x7018C /* reserved */
2077 #define DSPASIZE 0x70190
2078 #define DSPASURF 0x7019C /* 965+ only */
2079 #define DSPATILEOFF 0x701A4 /* 965+ only */
2082 #define SWF00 0x71410
2083 #define SWF01 0x71414
2084 #define SWF02 0x71418
2085 #define SWF03 0x7141c
2086 #define SWF04 0x71420
2087 #define SWF05 0x71424
2088 #define SWF06 0x71428
2089 #define SWF10 0x70410
2090 #define SWF11 0x70414
2091 #define SWF14 0x71420
2092 #define SWF30 0x72414
2093 #define SWF31 0x72418
2094 #define SWF32 0x7241c
2097 #define PIPEBDSL 0x71000
2098 #define PIPEBCONF 0x71008
2099 #define PIPEBSTAT 0x71024
2100 #define PIPEBFRAMEHIGH 0x71040
2101 #define PIPEBFRAMEPIXEL 0x71044
2102 #define PIPEB_FRMCOUNT_GM45 0x71040
2103 #define PIPEB_FLIPCOUNT_GM45 0x71044
2106 /* Display B control */
2107 #define DSPBCNTR 0x71180
2108 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2109 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
2110 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2111 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2112 #define DSPBADDR 0x71184
2113 #define DSPBSTRIDE 0x71188
2114 #define DSPBPOS 0x7118C
2115 #define DSPBSIZE 0x71190
2116 #define DSPBSURF 0x7119C
2117 #define DSPBTILEOFF 0x711A4
2120 #define VGACNTRL 0x71400
2121 # define VGA_DISP_DISABLE (1 << 31)
2122 # define VGA_2X_MODE (1 << 30)
2123 # define VGA_PIPE_B_SELECT (1 << 29)
2127 #define CPU_VGACNTRL 0x41000
2129 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2130 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2131 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2132 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2133 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2134 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2135 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
2136 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2137 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2139 /* refresh rate hardware control */
2140 #define RR_HW_CTL 0x45300
2141 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2142 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2144 #define FDI_PLL_BIOS_0 0x46000
2145 #define FDI_PLL_BIOS_1 0x46004
2146 #define FDI_PLL_BIOS_2 0x46008
2147 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2148 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
2149 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
2151 #define FDI_PLL_FREQ_CTL 0x46030
2152 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2153 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2154 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2157 #define PIPEA_DATA_M1 0x60030
2158 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2159 #define TU_SIZE_MASK 0x7e000000
2160 #define PIPEA_DATA_M1_OFFSET 0
2161 #define PIPEA_DATA_N1 0x60034
2162 #define PIPEA_DATA_N1_OFFSET 0
2164 #define PIPEA_DATA_M2 0x60038
2165 #define PIPEA_DATA_M2_OFFSET 0
2166 #define PIPEA_DATA_N2 0x6003c
2167 #define PIPEA_DATA_N2_OFFSET 0
2169 #define PIPEA_LINK_M1 0x60040
2170 #define PIPEA_LINK_M1_OFFSET 0
2171 #define PIPEA_LINK_N1 0x60044
2172 #define PIPEA_LINK_N1_OFFSET 0
2174 #define PIPEA_LINK_M2 0x60048
2175 #define PIPEA_LINK_M2_OFFSET 0
2176 #define PIPEA_LINK_N2 0x6004c
2177 #define PIPEA_LINK_N2_OFFSET 0
2179 /* PIPEB timing regs are same start from 0x61000 */
2181 #define PIPEB_DATA_M1 0x61030
2182 #define PIPEB_DATA_M1_OFFSET 0
2183 #define PIPEB_DATA_N1 0x61034
2184 #define PIPEB_DATA_N1_OFFSET 0
2186 #define PIPEB_DATA_M2 0x61038
2187 #define PIPEB_DATA_M2_OFFSET 0
2188 #define PIPEB_DATA_N2 0x6103c
2189 #define PIPEB_DATA_N2_OFFSET 0
2191 #define PIPEB_LINK_M1 0x61040
2192 #define PIPEB_LINK_M1_OFFSET 0
2193 #define PIPEB_LINK_N1 0x61044
2194 #define PIPEB_LINK_N1_OFFSET 0
2196 #define PIPEB_LINK_M2 0x61048
2197 #define PIPEB_LINK_M2_OFFSET 0
2198 #define PIPEB_LINK_N2 0x6104c
2199 #define PIPEB_LINK_N2_OFFSET 0
2201 /* CPU panel fitter */
2202 #define PFA_CTL_1 0x68080
2203 #define PFB_CTL_1 0x68880
2204 #define PF_ENABLE (1<<31)
2205 #define PF_FILTER_MASK (3<<23)
2206 #define PF_FILTER_PROGRAMMED (0<<23)
2207 #define PF_FILTER_MED_3x3 (1<<23)
2208 #define PF_FILTER_EDGE_ENHANCE (2<<23)
2209 #define PF_FILTER_EDGE_SOFTEN (3<<23)
2210 #define PFA_WIN_SZ 0x68074
2211 #define PFB_WIN_SZ 0x68874
2212 #define PFA_WIN_POS 0x68070
2213 #define PFB_WIN_POS 0x68870
2215 /* legacy palette */
2216 #define LGC_PALETTE_A 0x4a000
2217 #define LGC_PALETTE_B 0x4a800
2220 #define DE_MASTER_IRQ_CONTROL (1 << 31)
2221 #define DE_SPRITEB_FLIP_DONE (1 << 29)
2222 #define DE_SPRITEA_FLIP_DONE (1 << 28)
2223 #define DE_PLANEB_FLIP_DONE (1 << 27)
2224 #define DE_PLANEA_FLIP_DONE (1 << 26)
2225 #define DE_PCU_EVENT (1 << 25)
2226 #define DE_GTT_FAULT (1 << 24)
2227 #define DE_POISON (1 << 23)
2228 #define DE_PERFORM_COUNTER (1 << 22)
2229 #define DE_PCH_EVENT (1 << 21)
2230 #define DE_AUX_CHANNEL_A (1 << 20)
2231 #define DE_DP_A_HOTPLUG (1 << 19)
2232 #define DE_GSE (1 << 18)
2233 #define DE_PIPEB_VBLANK (1 << 15)
2234 #define DE_PIPEB_EVEN_FIELD (1 << 14)
2235 #define DE_PIPEB_ODD_FIELD (1 << 13)
2236 #define DE_PIPEB_LINE_COMPARE (1 << 12)
2237 #define DE_PIPEB_VSYNC (1 << 11)
2238 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2239 #define DE_PIPEA_VBLANK (1 << 7)
2240 #define DE_PIPEA_EVEN_FIELD (1 << 6)
2241 #define DE_PIPEA_ODD_FIELD (1 << 5)
2242 #define DE_PIPEA_LINE_COMPARE (1 << 4)
2243 #define DE_PIPEA_VSYNC (1 << 3)
2244 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2246 #define DEISR 0x44000
2247 #define DEIMR 0x44004
2248 #define DEIIR 0x44008
2249 #define DEIER 0x4400c
2252 #define GT_SYNC_STATUS (1 << 2)
2253 #define GT_USER_INTERRUPT (1 << 0)
2255 #define GTISR 0x44010
2256 #define GTIMR 0x44014
2257 #define GTIIR 0x44018
2258 #define GTIER 0x4401c
2260 #define DISP_ARB_CTL 0x45000
2261 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2265 /* south display engine interrupt */
2266 #define SDE_CRT_HOTPLUG (1 << 11)
2267 #define SDE_PORTD_HOTPLUG (1 << 10)
2268 #define SDE_PORTC_HOTPLUG (1 << 9)
2269 #define SDE_PORTB_HOTPLUG (1 << 8)
2270 #define SDE_SDVOB_HOTPLUG (1 << 6)
2271 #define SDE_HOTPLUG_MASK (0xf << 8)
2273 #define SDEISR 0xc4000
2274 #define SDEIMR 0xc4004
2275 #define SDEIIR 0xc4008
2276 #define SDEIER 0xc400c
2278 /* digital port hotplug */
2279 #define PCH_PORT_HOTPLUG 0xc4030
2280 #define PORTD_HOTPLUG_ENABLE (1 << 20)
2281 #define PORTD_PULSE_DURATION_2ms (0)
2282 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2283 #define PORTD_PULSE_DURATION_6ms (2 << 18)
2284 #define PORTD_PULSE_DURATION_100ms (3 << 18)
2285 #define PORTD_HOTPLUG_NO_DETECT (0)
2286 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2287 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2288 #define PORTC_HOTPLUG_ENABLE (1 << 12)
2289 #define PORTC_PULSE_DURATION_2ms (0)
2290 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2291 #define PORTC_PULSE_DURATION_6ms (2 << 10)
2292 #define PORTC_PULSE_DURATION_100ms (3 << 10)
2293 #define PORTC_HOTPLUG_NO_DETECT (0)
2294 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2295 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2296 #define PORTB_HOTPLUG_ENABLE (1 << 4)
2297 #define PORTB_PULSE_DURATION_2ms (0)
2298 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2299 #define PORTB_PULSE_DURATION_6ms (2 << 2)
2300 #define PORTB_PULSE_DURATION_100ms (3 << 2)
2301 #define PORTB_HOTPLUG_NO_DETECT (0)
2302 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2303 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2305 #define PCH_GPIOA 0xc5010
2306 #define PCH_GPIOB 0xc5014
2307 #define PCH_GPIOC 0xc5018
2308 #define PCH_GPIOD 0xc501c
2309 #define PCH_GPIOE 0xc5020
2310 #define PCH_GPIOF 0xc5024
2312 #define PCH_GMBUS0 0xc5100
2313 #define PCH_GMBUS1 0xc5104
2314 #define PCH_GMBUS2 0xc5108
2315 #define PCH_GMBUS3 0xc510c
2316 #define PCH_GMBUS4 0xc5110
2317 #define PCH_GMBUS5 0xc5120
2319 #define PCH_DPLL_A 0xc6014
2320 #define PCH_DPLL_B 0xc6018
2322 #define PCH_FPA0 0xc6040
2323 #define PCH_FPA1 0xc6044
2324 #define PCH_FPB0 0xc6048
2325 #define PCH_FPB1 0xc604c
2327 #define PCH_DPLL_TEST 0xc606c
2329 #define PCH_DREF_CONTROL 0xC6200
2330 #define DREF_CONTROL_MASK 0x7fc3
2331 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2332 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2333 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2334 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2335 #define DREF_SSC_SOURCE_DISABLE (0<<11)
2336 #define DREF_SSC_SOURCE_ENABLE (2<<11)
2337 #define DREF_SSC_SOURCE_MASK (3<<11)
2338 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2339 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2340 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2341 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2342 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2343 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2344 #define DREF_SSC4_DOWNSPREAD (0<<6)
2345 #define DREF_SSC4_CENTERSPREAD (1<<6)
2346 #define DREF_SSC1_DISABLE (0<<1)
2347 #define DREF_SSC1_ENABLE (1<<1)
2348 #define DREF_SSC4_DISABLE (0)
2349 #define DREF_SSC4_ENABLE (1)
2351 #define PCH_RAWCLK_FREQ 0xc6204
2352 #define FDL_TP1_TIMER_SHIFT 12
2353 #define FDL_TP1_TIMER_MASK (3<<12)
2354 #define FDL_TP2_TIMER_SHIFT 10
2355 #define FDL_TP2_TIMER_MASK (3<<10)
2356 #define RAWCLK_FREQ_MASK 0x3ff
2358 #define PCH_DPLL_TMR_CFG 0xc6208
2360 #define PCH_SSC4_PARMS 0xc6210
2361 #define PCH_SSC4_AUX_PARMS 0xc6214
2365 #define TRANS_HTOTAL_A 0xe0000
2366 #define TRANS_HTOTAL_SHIFT 16
2367 #define TRANS_HACTIVE_SHIFT 0
2368 #define TRANS_HBLANK_A 0xe0004
2369 #define TRANS_HBLANK_END_SHIFT 16
2370 #define TRANS_HBLANK_START_SHIFT 0
2371 #define TRANS_HSYNC_A 0xe0008
2372 #define TRANS_HSYNC_END_SHIFT 16
2373 #define TRANS_HSYNC_START_SHIFT 0
2374 #define TRANS_VTOTAL_A 0xe000c
2375 #define TRANS_VTOTAL_SHIFT 16
2376 #define TRANS_VACTIVE_SHIFT 0
2377 #define TRANS_VBLANK_A 0xe0010
2378 #define TRANS_VBLANK_END_SHIFT 16
2379 #define TRANS_VBLANK_START_SHIFT 0
2380 #define TRANS_VSYNC_A 0xe0014
2381 #define TRANS_VSYNC_END_SHIFT 16
2382 #define TRANS_VSYNC_START_SHIFT 0
2384 #define TRANSA_DATA_M1 0xe0030
2385 #define TRANSA_DATA_N1 0xe0034
2386 #define TRANSA_DATA_M2 0xe0038
2387 #define TRANSA_DATA_N2 0xe003c
2388 #define TRANSA_DP_LINK_M1 0xe0040
2389 #define TRANSA_DP_LINK_N1 0xe0044
2390 #define TRANSA_DP_LINK_M2 0xe0048
2391 #define TRANSA_DP_LINK_N2 0xe004c
2393 #define TRANS_HTOTAL_B 0xe1000
2394 #define TRANS_HBLANK_B 0xe1004
2395 #define TRANS_HSYNC_B 0xe1008
2396 #define TRANS_VTOTAL_B 0xe100c
2397 #define TRANS_VBLANK_B 0xe1010
2398 #define TRANS_VSYNC_B 0xe1014
2400 #define TRANSB_DATA_M1 0xe1030
2401 #define TRANSB_DATA_N1 0xe1034
2402 #define TRANSB_DATA_M2 0xe1038
2403 #define TRANSB_DATA_N2 0xe103c
2404 #define TRANSB_DP_LINK_M1 0xe1040
2405 #define TRANSB_DP_LINK_N1 0xe1044
2406 #define TRANSB_DP_LINK_M2 0xe1048
2407 #define TRANSB_DP_LINK_N2 0xe104c
2409 #define TRANSACONF 0xf0008
2410 #define TRANSBCONF 0xf1008
2411 #define TRANS_DISABLE (0<<31)
2412 #define TRANS_ENABLE (1<<31)
2413 #define TRANS_STATE_MASK (1<<30)
2414 #define TRANS_STATE_DISABLE (0<<30)
2415 #define TRANS_STATE_ENABLE (1<<30)
2416 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
2417 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
2418 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
2419 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
2420 #define TRANS_DP_AUDIO_ONLY (1<<26)
2421 #define TRANS_DP_VIDEO_AUDIO (0<<26)
2422 #define TRANS_PROGRESSIVE (0<<21)
2423 #define TRANS_8BPC (0<<5)
2424 #define TRANS_10BPC (1<<5)
2425 #define TRANS_6BPC (2<<5)
2426 #define TRANS_12BPC (3<<5)
2428 #define FDI_RXA_CHICKEN 0xc200c
2429 #define FDI_RXB_CHICKEN 0xc2010
2430 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
2433 #define FDI_TXA_CTL 0x60100
2434 #define FDI_TXB_CTL 0x61100
2435 #define FDI_TX_DISABLE (0<<31)
2436 #define FDI_TX_ENABLE (1<<31)
2437 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
2438 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
2439 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
2440 #define FDI_LINK_TRAIN_NONE (3<<28)
2441 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
2442 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
2443 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
2444 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
2445 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
2446 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
2447 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
2448 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
2449 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
2450 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
2451 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
2452 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
2453 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2454 /* Ironlake: hardwired to 1 */
2455 #define FDI_TX_PLL_ENABLE (1<<14)
2456 /* both Tx and Rx */
2457 #define FDI_SCRAMBLING_ENABLE (0<<7)
2458 #define FDI_SCRAMBLING_DISABLE (1<<7)
2460 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2461 #define FDI_RXA_CTL 0xf000c
2462 #define FDI_RXB_CTL 0xf100c
2463 #define FDI_RX_ENABLE (1<<31)
2464 #define FDI_RX_DISABLE (0<<31)
2465 /* train, dp width same as FDI_TX */
2466 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
2467 #define FDI_8BPC (0<<16)
2468 #define FDI_10BPC (1<<16)
2469 #define FDI_6BPC (2<<16)
2470 #define FDI_12BPC (3<<16)
2471 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
2472 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
2473 #define FDI_RX_PLL_ENABLE (1<<13)
2474 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
2475 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
2476 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2477 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2478 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2479 #define FDI_SEL_RAWCLK (0<<4)
2480 #define FDI_SEL_PCDCLK (1<<4)
2482 #define FDI_RXA_MISC 0xf0010
2483 #define FDI_RXB_MISC 0xf1010
2484 #define FDI_RXA_TUSIZE1 0xf0030
2485 #define FDI_RXA_TUSIZE2 0xf0038
2486 #define FDI_RXB_TUSIZE1 0xf1030
2487 #define FDI_RXB_TUSIZE2 0xf1038
2489 /* FDI_RX interrupt register format */
2490 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
2491 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
2492 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
2493 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
2494 #define FDI_RX_FS_CODE_ERR (1<<6)
2495 #define FDI_RX_FE_CODE_ERR (1<<5)
2496 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
2497 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
2498 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
2499 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
2500 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
2502 #define FDI_RXA_IIR 0xf0014
2503 #define FDI_RXA_IMR 0xf0018
2504 #define FDI_RXB_IIR 0xf1014
2505 #define FDI_RXB_IMR 0xf1018
2507 #define FDI_PLL_CTL_1 0xfe000
2508 #define FDI_PLL_CTL_2 0xfe004
2511 #define PCH_ADPA 0xe1100
2512 #define ADPA_TRANS_SELECT_MASK (1<<30)
2513 #define ADPA_TRANS_A_SELECT 0
2514 #define ADPA_TRANS_B_SELECT (1<<30)
2515 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2516 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2517 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2518 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2519 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2520 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2521 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2522 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2523 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2524 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2525 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2526 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2527 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2528 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2529 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2530 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2531 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2532 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2533 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2536 #define HDMIB 0xe1140
2537 #define PORT_ENABLE (1 << 31)
2538 #define TRANSCODER_A (0)
2539 #define TRANSCODER_B (1 << 30)
2540 #define COLOR_FORMAT_8bpc (0)
2541 #define COLOR_FORMAT_12bpc (3 << 26)
2542 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
2543 #define SDVO_ENCODING (0)
2544 #define TMDS_ENCODING (2 << 10)
2545 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
2546 #define SDVOB_BORDER_ENABLE (1 << 7)
2547 #define AUDIO_ENABLE (1 << 6)
2548 #define VSYNC_ACTIVE_HIGH (1 << 4)
2549 #define HSYNC_ACTIVE_HIGH (1 << 3)
2550 #define PORT_DETECTED (1 << 2)
2552 #define HDMIC 0xe1150
2553 #define HDMID 0xe1160
2555 #define PCH_LVDS 0xe1180
2556 #define LVDS_DETECTED (1 << 1)
2558 #define BLC_PWM_CPU_CTL2 0x48250
2559 #define PWM_ENABLE (1 << 31)
2560 #define PWM_PIPE_A (0 << 29)
2561 #define PWM_PIPE_B (1 << 29)
2562 #define BLC_PWM_CPU_CTL 0x48254
2564 #define BLC_PWM_PCH_CTL1 0xc8250
2565 #define PWM_PCH_ENABLE (1 << 31)
2566 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
2567 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
2568 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
2569 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
2571 #define BLC_PWM_PCH_CTL2 0xc8254
2573 #define PCH_PP_STATUS 0xc7200
2574 #define PCH_PP_CONTROL 0xc7204
2575 #define EDP_FORCE_VDD (1 << 3)
2576 #define EDP_BLC_ENABLE (1 << 2)
2577 #define PANEL_POWER_RESET (1 << 1)
2578 #define PANEL_POWER_OFF (0 << 0)
2579 #define PANEL_POWER_ON (1 << 0)
2580 #define PCH_PP_ON_DELAYS 0xc7208
2581 #define EDP_PANEL (1 << 30)
2582 #define PCH_PP_OFF_DELAYS 0xc720c
2583 #define PCH_PP_DIVISOR 0xc7210
2585 #define PCH_DP_B 0xe4100
2586 #define PCH_DPB_AUX_CH_CTL 0xe4110
2587 #define PCH_DPB_AUX_CH_DATA1 0xe4114
2588 #define PCH_DPB_AUX_CH_DATA2 0xe4118
2589 #define PCH_DPB_AUX_CH_DATA3 0xe411c
2590 #define PCH_DPB_AUX_CH_DATA4 0xe4120
2591 #define PCH_DPB_AUX_CH_DATA5 0xe4124
2593 #define PCH_DP_C 0xe4200
2594 #define PCH_DPC_AUX_CH_CTL 0xe4210
2595 #define PCH_DPC_AUX_CH_DATA1 0xe4214
2596 #define PCH_DPC_AUX_CH_DATA2 0xe4218
2597 #define PCH_DPC_AUX_CH_DATA3 0xe421c
2598 #define PCH_DPC_AUX_CH_DATA4 0xe4220
2599 #define PCH_DPC_AUX_CH_DATA5 0xe4224
2601 #define PCH_DP_D 0xe4300
2602 #define PCH_DPD_AUX_CH_CTL 0xe4310
2603 #define PCH_DPD_AUX_CH_DATA1 0xe4314
2604 #define PCH_DPD_AUX_CH_DATA2 0xe4318
2605 #define PCH_DPD_AUX_CH_DATA3 0xe431c
2606 #define PCH_DPD_AUX_CH_DATA4 0xe4320
2607 #define PCH_DPD_AUX_CH_DATA5 0xe4324
2609 #endif /* _I915_REG_H_ */