SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #define MAX_NOPID ((u32)~0)
  38
  39 /**
  40  * Interrupts that are always left unmasked.
  41  *
  42  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  43  * we leave them always unmasked in IMR and then control enabling them through
  44  * PIPESTAT alone.
  45  */
  46 #define I915_INTERRUPT_ENABLE_FIX                       \
  47         (I915_ASLE_INTERRUPT |                          \
  48          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  49          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  51          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  52          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  53
  54 /** Interrupts that we mask and unmask at runtime. */
  55 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  56
  57 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  58                                  PIPE_VBLANK_INTERRUPT_STATUS)
  59
  60 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  61                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  62
  63 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  64                                          DRM_I915_VBLANK_PIPE_B)
  65
  66 void
  67 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  68 {
  69         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  70                 dev_priv->gt_irq_mask_reg &= ~mask;
  71                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  72                 (void) I915_READ(GTIMR);
  73         }
  74 }
  75
  76 static inline void
  77 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  78 {
  79         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  80                 dev_priv->gt_irq_mask_reg |= mask;
  81                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  82                 (void) I915_READ(GTIMR);
  83         }
  84 }
  85
  86 /* For display hotplug interrupt */
  87 void
  88 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  89 {
  90         if ((dev_priv->irq_mask_reg & mask) != 0) {
  91                 dev_priv->irq_mask_reg &= ~mask;
  92                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  93                 (void) I915_READ(DEIMR);
  94         }
  95 }
  96
  97 static inline void
  98 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  99 {
 100         if ((dev_priv->irq_mask_reg & mask) != mask) {
 101                 dev_priv->irq_mask_reg |= mask;
 102                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 103                 (void) I915_READ(DEIMR);
 104         }
 105 }
 106
 107 void
 108 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 109 {
 110         if ((dev_priv->irq_mask_reg & mask) != 0) {
 111                 dev_priv->irq_mask_reg &= ~mask;
 112                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 113                 (void) I915_READ(IMR);
 114         }
 115 }
 116
 117 static inline void
 118 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 119 {
 120         if ((dev_priv->irq_mask_reg & mask) != mask) {
 121                 dev_priv->irq_mask_reg |= mask;
 122                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 123                 (void) I915_READ(IMR);
 124         }
 125 }
 126
 127 static inline u32
 128 i915_pipestat(int pipe)
 129 {
 130         if (pipe == 0)
 131                 return PIPEASTAT;
 132         if (pipe == 1)
 133                 return PIPEBSTAT;
 134         BUG();
 135 }
 136
 137 void
 138 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 139 {
 140         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 141                 u32 reg = i915_pipestat(pipe);
 142
 143                 dev_priv->pipestat[pipe] |= mask;
 144                 /* Enable the interrupt, clear any pending status */
 145                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 146                 (void) I915_READ(reg);
 147         }
 148 }
 149
 150 void
 151 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 152 {
 153         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 154                 u32 reg = i915_pipestat(pipe);
 155
 156                 dev_priv->pipestat[pipe] &= ~mask;
 157                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 158                 (void) I915_READ(reg);
 159         }
 160 }
 161
 162 /**
 163  * intel_enable_asle - enable ASLE interrupt for OpRegion
 164  */
 165 void intel_enable_asle (struct drm_device *dev)
 166 {
 167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 168
 169         if (IS_IRONLAKE(dev))
 170                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 171         else
 172                 i915_enable_pipestat(dev_priv, 1,
 173                                      I915_LEGACY_BLC_EVENT_ENABLE);
 174 }
 175
 176 /**
 177  * i915_pipe_enabled - check if a pipe is enabled
 178  * @dev: DRM device
 179  * @pipe: pipe to check
 180  *
 181  * Reading certain registers when the pipe is disabled can hang the chip.
 182  * Use this routine to make sure the PLL is running and the pipe is active
 183  * before reading such registers if unsure.
 184  */
 185 static int
 186 i915_pipe_enabled(struct drm_device *dev, int pipe)
 187 {
 188         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 189         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 190
 191         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 192                 return 1;
 193
 194         return 0;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low, count;
 206
 207         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 208         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 212                                 "pipe %d\n", pipe);
 213                 return 0;
 214         }
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 223                          PIPE_FRAME_HIGH_SHIFT);
 224                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 225                         PIPE_FRAME_LOW_SHIFT);
 226                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 227                          PIPE_FRAME_HIGH_SHIFT);
 228         } while (high1 != high2);
 229
 230         count = (high1 << 8) | low;
 231
 232         return count;
 233 }
 234
 235 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 236 {
 237         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 238         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 239
 240         if (!i915_pipe_enabled(dev, pipe)) {
 241                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 242                                         "pipe %d\n", pipe);
 243                 return 0;
 244         }
 245
 246         return I915_READ(reg);
 247 }
 248
 249 /*
 250  * Handle hotplug events outside the interrupt handler proper.
 251  */
 252 static void i915_hotplug_work_func(struct work_struct *work)
 253 {
 254         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 255                                                     hotplug_work);
 256         struct drm_device *dev = dev_priv->dev;
 257         struct drm_mode_config *mode_config = &dev->mode_config;
 258         struct drm_connector *connector;
 259
 260         if (mode_config->num_connector) {
 261                 list_for_each_entry(connector, &mode_config->connector_list, head) {
 262                         struct intel_output *intel_output = to_intel_output(connector);
 263
 264                         if (intel_output->hot_plug)
 265                                 (*intel_output->hot_plug) (intel_output);
 266                 }
 267         }
 268         /* Just fire off a uevent and let userspace tell us what to do */
 269         drm_sysfs_hotplug_event(dev);
 270 }
 271
 272 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 273 {
 274         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 275         int ret = IRQ_NONE;
 276         u32 de_iir, gt_iir, de_ier, pch_iir;
 277         u32 new_de_iir, new_gt_iir, new_pch_iir;
 278         struct drm_i915_master_private *master_priv;
 279
 280         /* disable master interrupt before clearing iir  */
 281         de_ier = I915_READ(DEIER);
 282         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 283         (void)I915_READ(DEIER);
 284
 285         de_iir = I915_READ(DEIIR);
 286         gt_iir = I915_READ(GTIIR);
 287         pch_iir = I915_READ(SDEIIR);
 288
 289         for (;;) {
 290                 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 291                         break;
 292
 293                 ret = IRQ_HANDLED;
 294
 295                 /* should clear PCH hotplug event before clear CPU irq */
 296                 I915_WRITE(SDEIIR, pch_iir);
 297                 new_pch_iir = I915_READ(SDEIIR);
 298
 299                 I915_WRITE(DEIIR, de_iir);
 300                 new_de_iir = I915_READ(DEIIR);
 301                 I915_WRITE(GTIIR, gt_iir);
 302                 new_gt_iir = I915_READ(GTIIR);
 303
 304                 if (dev->primary->master) {
 305                         master_priv = dev->primary->master->driver_priv;
 306                         if (master_priv->sarea_priv)
 307                                 master_priv->sarea_priv->last_dispatch =
 308                                         READ_BREADCRUMB(dev_priv);
 309                 }
 310
 311                 if (gt_iir & GT_USER_INTERRUPT) {
 312                         u32 seqno = i915_get_gem_seqno(dev);
 313                         dev_priv->mm.irq_gem_seqno = seqno;
 314                         trace_i915_gem_request_complete(dev, seqno);
 315                         DRM_WAKEUP(&dev_priv->irq_queue);
 316                 }
 317
 318                 if (de_iir & DE_GSE)
 319                         ironlake_opregion_gse_intr(dev);
 320
 321                 /* check event from PCH */
 322                 if ((de_iir & DE_PCH_EVENT) &&
 323                         (pch_iir & SDE_HOTPLUG_MASK)) {
 324                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 325                 }
 326
 327                 de_iir = new_de_iir;
 328                 gt_iir = new_gt_iir;
 329                 pch_iir = new_pch_iir;
 330         }
 331
 332         I915_WRITE(DEIER, de_ier);
 333         (void)I915_READ(DEIER);
 334
 335         return ret;
 336 }
 337
 338 /**
 339  * i915_error_work_func - do process context error handling work
 340  * @work: work struct
 341  *
 342  * Fire an error uevent so userspace can see that a hang or error
 343  * was detected.
 344  */
 345 static void i915_error_work_func(struct work_struct *work)
 346 {
 347         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 348                                                     error_work);
 349         struct drm_device *dev = dev_priv->dev;
 350         char *error_event[] = { "ERROR=1", NULL };
 351         char *reset_event[] = { "RESET=1", NULL };
 352         char *reset_done_event[] = { "ERROR=0", NULL };
 353
 354         DRM_DEBUG_DRIVER("generating error event\n");
 355         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 356
 357         if (atomic_read(&dev_priv->mm.wedged)) {
 358                 if (IS_I965G(dev)) {
 359                         DRM_DEBUG_DRIVER("resetting chip\n");
 360                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 361                         if (!i965_reset(dev, GDRST_RENDER)) {
 362                                 atomic_set(&dev_priv->mm.wedged, 0);
 363                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 364                         }
 365                 } else {
 366                         DRM_DEBUG_DRIVER("reboot required\n");
 367                 }
 368         }
 369 }
 370
 371 /**
 372  * i915_capture_error_state - capture an error record for later analysis
 373  * @dev: drm device
 374  *
 375  * Should be called when an error is detected (either a hang or an error
 376  * interrupt) to capture error state from the time of the error.  Fills
 377  * out a structure which becomes available in debugfs for user level tools
 378  * to pick up.
 379  */
 380 static void i915_capture_error_state(struct drm_device *dev)
 381 {
 382         struct drm_i915_private *dev_priv = dev->dev_private;
 383         struct drm_i915_error_state *error;
 384         unsigned long flags;
 385
 386         spin_lock_irqsave(&dev_priv->error_lock, flags);
 387         if (dev_priv->first_error)
 388                 goto out;
 389
 390         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 391         if (!error) {
 392                 DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n");
 393                 goto out;
 394         }
 395
 396         error->eir = I915_READ(EIR);
 397         error->pgtbl_er = I915_READ(PGTBL_ER);
 398         error->pipeastat = I915_READ(PIPEASTAT);
 399         error->pipebstat = I915_READ(PIPEBSTAT);
 400         error->instpm = I915_READ(INSTPM);
 401         if (!IS_I965G(dev)) {
 402                 error->ipeir = I915_READ(IPEIR);
 403                 error->ipehr = I915_READ(IPEHR);
 404                 error->instdone = I915_READ(INSTDONE);
 405                 error->acthd = I915_READ(ACTHD);
 406         } else {
 407                 error->ipeir = I915_READ(IPEIR_I965);
 408                 error->ipehr = I915_READ(IPEHR_I965);
 409                 error->instdone = I915_READ(INSTDONE_I965);
 410                 error->instps = I915_READ(INSTPS);
 411                 error->instdone1 = I915_READ(INSTDONE1);
 412                 error->acthd = I915_READ(ACTHD_I965);
 413         }
 414
 415         do_gettimeofday(&error->time);
 416
 417         dev_priv->first_error = error;
 418
 419 out:
 420         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 421 }
 422
 423 /**
 424  * i915_handle_error - handle an error interrupt
 425  * @dev: drm device
 426  *
 427  * Do some basic checking of regsiter state at error interrupt time and
 428  * dump it to the syslog.  Also call i915_capture_error_state() to make
 429  * sure we get a record and make it available in debugfs.  Fire a uevent
 430  * so userspace knows something bad happened (should trigger collection
 431  * of a ring dump etc.).
 432  */
 433 static void i915_handle_error(struct drm_device *dev, bool wedged)
 434 {
 435         struct drm_i915_private *dev_priv = dev->dev_private;
 436         u32 eir = I915_READ(EIR);
 437         u32 pipea_stats = I915_READ(PIPEASTAT);
 438         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 439
 440         i915_capture_error_state(dev);
 441
 442         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 443                eir);
 444
 445         if (IS_G4X(dev)) {
 446                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 447                         u32 ipeir = I915_READ(IPEIR_I965);
 448
 449                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 450                                I915_READ(IPEIR_I965));
 451                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 452                                I915_READ(IPEHR_I965));
 453                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 454                                I915_READ(INSTDONE_I965));
 455                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 456                                I915_READ(INSTPS));
 457                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 458                                I915_READ(INSTDONE1));
 459                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 460                                I915_READ(ACTHD_I965));
 461                         I915_WRITE(IPEIR_I965, ipeir);
 462                         (void)I915_READ(IPEIR_I965);
 463                 }
 464                 if (eir & GM45_ERROR_PAGE_TABLE) {
 465                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 466                         printk(KERN_ERR "page table error\n");
 467                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 468                                pgtbl_err);
 469                         I915_WRITE(PGTBL_ER, pgtbl_err);
 470                         (void)I915_READ(PGTBL_ER);
 471                 }
 472         }
 473
 474         if (IS_I9XX(dev)) {
 475                 if (eir & I915_ERROR_PAGE_TABLE) {
 476                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 477                         printk(KERN_ERR "page table error\n");
 478                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 479                                pgtbl_err);
 480                         I915_WRITE(PGTBL_ER, pgtbl_err);
 481                         (void)I915_READ(PGTBL_ER);
 482                 }
 483         }
 484
 485         if (eir & I915_ERROR_MEMORY_REFRESH) {
 486                 printk(KERN_ERR "memory refresh error\n");
 487                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 488                        pipea_stats);
 489                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 490                        pipeb_stats);
 491                 /* pipestat has already been acked */
 492         }
 493         if (eir & I915_ERROR_INSTRUCTION) {
 494                 printk(KERN_ERR "instruction error\n");
 495                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 496                        I915_READ(INSTPM));
 497                 if (!IS_I965G(dev)) {
 498                         u32 ipeir = I915_READ(IPEIR);
 499
 500                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 501                                I915_READ(IPEIR));
 502                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 503                                I915_READ(IPEHR));
 504                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 505                                I915_READ(INSTDONE));
 506                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 507                                I915_READ(ACTHD));
 508                         I915_WRITE(IPEIR, ipeir);
 509                         (void)I915_READ(IPEIR);
 510                 } else {
 511                         u32 ipeir = I915_READ(IPEIR_I965);
 512
 513                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 514                                I915_READ(IPEIR_I965));
 515                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 516                                I915_READ(IPEHR_I965));
 517                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 518                                I915_READ(INSTDONE_I965));
 519                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 520                                I915_READ(INSTPS));
 521                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 522                                I915_READ(INSTDONE1));
 523                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 524                                I915_READ(ACTHD_I965));
 525                         I915_WRITE(IPEIR_I965, ipeir);
 526                         (void)I915_READ(IPEIR_I965);
 527                 }
 528         }
 529
 530         I915_WRITE(EIR, eir);
 531         (void)I915_READ(EIR);
 532         eir = I915_READ(EIR);
 533         if (eir) {
 534                 /*
 535                  * some errors might have become stuck,
 536                  * mask them.
 537                  */
 538                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 539                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 540                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 541         }
 542
 543         if (wedged) {
 544                 atomic_set(&dev_priv->mm.wedged, 1);
 545
 546                 /*
 547                  * Wakeup waiting processes so they don't hang
 548                  */
 549                 printk("i915: Waking up sleeping processes\n");
 550                 DRM_WAKEUP(&dev_priv->irq_queue);
 551         }
 552
 553         queue_work(dev_priv->wq, &dev_priv->error_work);
 554 }
 555
 556 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 557 {
 558         struct drm_device *dev = (struct drm_device *) arg;
 559         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 560         struct drm_i915_master_private *master_priv;
 561         u32 iir, new_iir;
 562         u32 pipea_stats, pipeb_stats;
 563         u32 vblank_status;
 564         u32 vblank_enable;
 565         int vblank = 0;
 566         unsigned long irqflags;
 567         int irq_received;
 568         int ret = IRQ_NONE;
 569
 570         atomic_inc(&dev_priv->irq_received);
 571
 572         if (IS_IRONLAKE(dev))
 573                 return ironlake_irq_handler(dev);
 574
 575         iir = I915_READ(IIR);
 576
 577         if (IS_I965G(dev)) {
 578                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 579                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 580         } else {
 581                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 582                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 583         }
 584
 585         for (;;) {
 586                 irq_received = iir != 0;
 587
 588                 /* Can't rely on pipestat interrupt bit in iir as it might
 589                  * have been cleared after the pipestat interrupt was received.
 590                  * It doesn't set the bit in iir again, but it still produces
 591                  * interrupts (for non-MSI).
 592                  */
 593                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 594                 pipea_stats = I915_READ(PIPEASTAT);
 595                 pipeb_stats = I915_READ(PIPEBSTAT);
 596
 597                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 598                         i915_handle_error(dev, false);
 599
 600                 /*
 601                  * Clear the PIPE(A|B)STAT regs before the IIR
 602                  */
 603                 if (pipea_stats & 0x8000ffff) {
 604                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 605                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 606                         I915_WRITE(PIPEASTAT, pipea_stats);
 607                         irq_received = 1;
 608                 }
 609
 610                 if (pipeb_stats & 0x8000ffff) {
 611                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 612                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 613                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 614                         irq_received = 1;
 615                 }
 616                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 617
 618                 if (!irq_received)
 619                         break;
 620
 621                 ret = IRQ_HANDLED;
 622
 623                 /* Consume port.  Then clear IIR or we'll miss events */
 624                 if ((I915_HAS_HOTPLUG(dev)) &&
 625                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 626                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 627
 628                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 629                                   hotplug_status);
 630                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 631                                 queue_work(dev_priv->wq,
 632                                            &dev_priv->hotplug_work);
 633
 634                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 635                         I915_READ(PORT_HOTPLUG_STAT);
 636                 }
 637
 638                 I915_WRITE(IIR, iir);
 639                 new_iir = I915_READ(IIR); /* Flush posted writes */
 640
 641                 if (dev->primary->master) {
 642                         master_priv = dev->primary->master->driver_priv;
 643                         if (master_priv->sarea_priv)
 644                                 master_priv->sarea_priv->last_dispatch =
 645                                         READ_BREADCRUMB(dev_priv);
 646                 }
 647
 648                 if (iir & I915_USER_INTERRUPT) {
 649                         u32 seqno = i915_get_gem_seqno(dev);
 650                         dev_priv->mm.irq_gem_seqno = seqno;
 651                         trace_i915_gem_request_complete(dev, seqno);
 652                         DRM_WAKEUP(&dev_priv->irq_queue);
 653                         dev_priv->hangcheck_count = 0;
 654                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 655                 }
 656
 657                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 658                         intel_prepare_page_flip(dev, 0);
 659
 660                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 661                         intel_prepare_page_flip(dev, 1);
 662
 663                 if (pipea_stats & vblank_status) {
 664                         vblank++;
 665                         drm_handle_vblank(dev, 0);
 666                         intel_finish_page_flip(dev, 0);
 667                 }
 668
 669                 if (pipeb_stats & vblank_status) {
 670                         vblank++;
 671                         drm_handle_vblank(dev, 1);
 672                         intel_finish_page_flip(dev, 1);
 673                 }
 674
 675                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 676                     (iir & I915_ASLE_INTERRUPT))
 677                         opregion_asle_intr(dev);
 678
 679                 /* With MSI, interrupts are only generated when iir
 680                  * transitions from zero to nonzero.  If another bit got
 681                  * set while we were handling the existing iir bits, then
 682                  * we would never get another interrupt.
 683                  *
 684                  * This is fine on non-MSI as well, as if we hit this path
 685                  * we avoid exiting the interrupt handler only to generate
 686                  * another one.
 687                  *
 688                  * Note that for MSI this could cause a stray interrupt report
 689                  * if an interrupt landed in the time between writing IIR and
 690                  * the posting read.  This should be rare enough to never
 691                  * trigger the 99% of 100,000 interrupts test for disabling
 692                  * stray interrupts.
 693                  */
 694                 iir = new_iir;
 695         }
 696
 697         return ret;
 698 }
 699
 700 static int i915_emit_irq(struct drm_device * dev)
 701 {
 702         drm_i915_private_t *dev_priv = dev->dev_private;
 703         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 704         RING_LOCALS;
 705
 706         i915_kernel_lost_context(dev);
 707
 708         DRM_DEBUG_DRIVER("\n");
 709
 710         dev_priv->counter++;
 711         if (dev_priv->counter > 0x7FFFFFFFUL)
 712                 dev_priv->counter = 1;
 713         if (master_priv->sarea_priv)
 714                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 715
 716         BEGIN_LP_RING(4);
 717         OUT_RING(MI_STORE_DWORD_INDEX);
 718         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 719         OUT_RING(dev_priv->counter);
 720         OUT_RING(MI_USER_INTERRUPT);
 721         ADVANCE_LP_RING();
 722
 723         return dev_priv->counter;
 724 }
 725
 726 void i915_user_irq_get(struct drm_device *dev)
 727 {
 728         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 729         unsigned long irqflags;
 730
 731         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 732         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
 733                 if (IS_IRONLAKE(dev))
 734                         ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 735                 else
 736                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 737         }
 738         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 739 }
 740
 741 void i915_user_irq_put(struct drm_device *dev)
 742 {
 743         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 744         unsigned long irqflags;
 745
 746         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 747         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 748         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
 749                 if (IS_IRONLAKE(dev))
 750                         ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 751                 else
 752                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 753         }
 754         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 755 }
 756
 757 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
 758 {
 759         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 760
 761         if (dev_priv->trace_irq_seqno == 0)
 762                 i915_user_irq_get(dev);
 763
 764         dev_priv->trace_irq_seqno = seqno;
 765 }
 766
 767 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 768 {
 769         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 770         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 771         int ret = 0;
 772
 773         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 774                   READ_BREADCRUMB(dev_priv));
 775
 776         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 777                 if (master_priv->sarea_priv)
 778                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 779                 return 0;
 780         }
 781
 782         if (master_priv->sarea_priv)
 783                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 784
 785         i915_user_irq_get(dev);
 786         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 787                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 788         i915_user_irq_put(dev);
 789
 790         if (ret == -EBUSY) {
 791                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 792                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 793         }
 794
 795         return ret;
 796 }
 797
 798 /* Needs the lock as it touches the ring.
 799  */
 800 int i915_irq_emit(struct drm_device *dev, void *data,
 801                          struct drm_file *file_priv)
 802 {
 803         drm_i915_private_t *dev_priv = dev->dev_private;
 804         drm_i915_irq_emit_t *emit = data;
 805         int result;
 806
 807         if (!dev_priv || !dev_priv->ring.virtual_start) {
 808                 DRM_ERROR("called with no initialization\n");
 809                 return -EINVAL;
 810         }
 811
 812         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 813
 814         mutex_lock(&dev->struct_mutex);
 815         result = i915_emit_irq(dev);
 816         mutex_unlock(&dev->struct_mutex);
 817
 818         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 819                 DRM_ERROR("copy_to_user\n");
 820                 return -EFAULT;
 821         }
 822
 823         return 0;
 824 }
 825
 826 /* Doesn't need the hardware lock.
 827  */
 828 int i915_irq_wait(struct drm_device *dev, void *data,
 829                          struct drm_file *file_priv)
 830 {
 831         drm_i915_private_t *dev_priv = dev->dev_private;
 832         drm_i915_irq_wait_t *irqwait = data;
 833
 834         if (!dev_priv) {
 835                 DRM_ERROR("called with no initialization\n");
 836                 return -EINVAL;
 837         }
 838
 839         return i915_wait_irq(dev, irqwait->irq_seq);
 840 }
 841
 842 /* Called from drm generic code, passed 'crtc' which
 843  * we use as a pipe index
 844  */
 845 int i915_enable_vblank(struct drm_device *dev, int pipe)
 846 {
 847         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 848         unsigned long irqflags;
 849         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 850         u32 pipeconf;
 851
 852         pipeconf = I915_READ(pipeconf_reg);
 853         if (!(pipeconf & PIPEACONF_ENABLE))
 854                 return -EINVAL;
 855
 856         if (IS_IRONLAKE(dev))
 857                 return 0;
 858
 859         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 860         if (IS_I965G(dev))
 861                 i915_enable_pipestat(dev_priv, pipe,
 862                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 863         else
 864                 i915_enable_pipestat(dev_priv, pipe,
 865                                      PIPE_VBLANK_INTERRUPT_ENABLE);
 866         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 867         return 0;
 868 }
 869
 870 /* Called from drm generic code, passed 'crtc' which
 871  * we use as a pipe index
 872  */
 873 void i915_disable_vblank(struct drm_device *dev, int pipe)
 874 {
 875         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 876         unsigned long irqflags;
 877
 878         if (IS_IRONLAKE(dev))
 879                 return;
 880
 881         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 882         i915_disable_pipestat(dev_priv, pipe,
 883                               PIPE_VBLANK_INTERRUPT_ENABLE |
 884                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
 885         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 886 }
 887
 888 void i915_enable_interrupt (struct drm_device *dev)
 889 {
 890         struct drm_i915_private *dev_priv = dev->dev_private;
 891
 892         if (!IS_IRONLAKE(dev))
 893                 opregion_enable_asle(dev);
 894         dev_priv->irq_enabled = 1;
 895 }
 896
 897
 898 /* Set the vblank monitor pipe
 899  */
 900 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 901                          struct drm_file *file_priv)
 902 {
 903         drm_i915_private_t *dev_priv = dev->dev_private;
 904
 905         if (!dev_priv) {
 906                 DRM_ERROR("called with no initialization\n");
 907                 return -EINVAL;
 908         }
 909
 910         return 0;
 911 }
 912
 913 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 914                          struct drm_file *file_priv)
 915 {
 916         drm_i915_private_t *dev_priv = dev->dev_private;
 917         drm_i915_vblank_pipe_t *pipe = data;
 918
 919         if (!dev_priv) {
 920                 DRM_ERROR("called with no initialization\n");
 921                 return -EINVAL;
 922         }
 923
 924         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 925
 926         return 0;
 927 }
 928
 929 /**
 930  * Schedule buffer swap at given vertical blank.
 931  */
 932 int i915_vblank_swap(struct drm_device *dev, void *data,
 933                      struct drm_file *file_priv)
 934 {
 935         /* The delayed swap mechanism was fundamentally racy, and has been
 936          * removed.  The model was that the client requested a delayed flip/swap
 937          * from the kernel, then waited for vblank before continuing to perform
 938          * rendering.  The problem was that the kernel might wake the client
 939          * up before it dispatched the vblank swap (since the lock has to be
 940          * held while touching the ringbuffer), in which case the client would
 941          * clear and start the next frame before the swap occurred, and
 942          * flicker would occur in addition to likely missing the vblank.
 943          *
 944          * In the absence of this ioctl, userland falls back to a correct path
 945          * of waiting for a vblank, then dispatching the swap on its own.
 946          * Context switching to userland and back is plenty fast enough for
 947          * meeting the requirements of vblank swapping.
 948          */
 949         return -EINVAL;
 950 }
 951
 952 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
 953         drm_i915_private_t *dev_priv = dev->dev_private;
 954         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
 955 }
 956
 957 /**
 958  * This is called when the chip hasn't reported back with completed
 959  * batchbuffers in a long time. The first time this is called we simply record
 960  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
 961  * again, we assume the chip is wedged and try to fix it.
 962  */
 963 void i915_hangcheck_elapsed(unsigned long data)
 964 {
 965         struct drm_device *dev = (struct drm_device *)data;
 966         drm_i915_private_t *dev_priv = dev->dev_private;
 967         uint32_t acthd;
 968
 969         if (!IS_I965G(dev))
 970                 acthd = I915_READ(ACTHD);
 971         else
 972                 acthd = I915_READ(ACTHD_I965);
 973
 974         /* If all work is done then ACTHD clearly hasn't advanced. */
 975         if (list_empty(&dev_priv->mm.request_list) ||
 976                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
 977                 dev_priv->hangcheck_count = 0;
 978                 return;
 979         }
 980
 981         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
 982                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
 983                 i915_handle_error(dev, true);
 984                 return;
 985         }
 986
 987         /* Reset timer case chip hangs without another request being added */
 988         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 989
 990         if (acthd != dev_priv->last_acthd)
 991                 dev_priv->hangcheck_count = 0;
 992         else
 993                 dev_priv->hangcheck_count++;
 994
 995         dev_priv->last_acthd = acthd;
 996 }
 997
 998 /* drm_dma.h hooks
 999 */
1000 static void ironlake_irq_preinstall(struct drm_device *dev)
1001 {
1002         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1003
1004         I915_WRITE(HWSTAM, 0xeffe);
1005
1006         /* XXX hotplug from PCH */
1007
1008         I915_WRITE(DEIMR, 0xffffffff);
1009         I915_WRITE(DEIER, 0x0);
1010         (void) I915_READ(DEIER);
1011
1012         /* and GT */
1013         I915_WRITE(GTIMR, 0xffffffff);
1014         I915_WRITE(GTIER, 0x0);
1015         (void) I915_READ(GTIER);
1016
1017         /* south display irq */
1018         I915_WRITE(SDEIMR, 0xffffffff);
1019         I915_WRITE(SDEIER, 0x0);
1020         (void) I915_READ(SDEIER);
1021 }
1022
1023 static int ironlake_irq_postinstall(struct drm_device *dev)
1024 {
1025         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1026         /* enable kind of interrupts always enabled */
1027         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT;
1028         u32 render_mask = GT_USER_INTERRUPT;
1029         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1030                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1031
1032         dev_priv->irq_mask_reg = ~display_mask;
1033         dev_priv->de_irq_enable_reg = display_mask;
1034
1035         /* should always can generate irq */
1036         I915_WRITE(DEIIR, I915_READ(DEIIR));
1037         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1038         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1039         (void) I915_READ(DEIER);
1040
1041         /* user interrupt should be enabled, but masked initial */
1042         dev_priv->gt_irq_mask_reg = 0xffffffff;
1043         dev_priv->gt_irq_enable_reg = render_mask;
1044
1045         I915_WRITE(GTIIR, I915_READ(GTIIR));
1046         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1047         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1048         (void) I915_READ(GTIER);
1049
1050         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1051         dev_priv->pch_irq_enable_reg = hotplug_mask;
1052
1053         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1054         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1055         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1056         (void) I915_READ(SDEIER);
1057
1058         return 0;
1059 }
1060
1061 void i915_driver_irq_preinstall(struct drm_device * dev)
1062 {
1063         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1064
1065         atomic_set(&dev_priv->irq_received, 0);
1066
1067         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1068         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1069
1070         if (IS_IRONLAKE(dev)) {
1071                 ironlake_irq_preinstall(dev);
1072                 return;
1073         }
1074
1075         if (I915_HAS_HOTPLUG(dev)) {
1076                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1077                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1078         }
1079
1080         I915_WRITE(HWSTAM, 0xeffe);
1081         I915_WRITE(PIPEASTAT, 0);
1082         I915_WRITE(PIPEBSTAT, 0);
1083         I915_WRITE(IMR, 0xffffffff);
1084         I915_WRITE(IER, 0x0);
1085         (void) I915_READ(IER);
1086 }
1087
1088 int i915_driver_irq_postinstall(struct drm_device *dev)
1089 {
1090         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1091         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1092         u32 error_mask;
1093
1094         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1095
1096         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1097
1098         if (IS_IRONLAKE(dev))
1099                 return ironlake_irq_postinstall(dev);
1100
1101         /* Unmask the interrupts that we always want on. */
1102         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1103
1104         dev_priv->pipestat[0] = 0;
1105         dev_priv->pipestat[1] = 0;
1106
1107         if (I915_HAS_HOTPLUG(dev)) {
1108                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1109
1110                 /* Leave other bits alone */
1111                 hotplug_en |= HOTPLUG_EN_MASK;
1112                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1113
1114                 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
1115                         TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
1116                         SDVOB_HOTPLUG_INT_STATUS;
1117                 if (IS_G4X(dev)) {
1118                         dev_priv->hotplug_supported_mask |=
1119                                 HDMIB_HOTPLUG_INT_STATUS |
1120                                 HDMIC_HOTPLUG_INT_STATUS |
1121                                 HDMID_HOTPLUG_INT_STATUS;
1122                 }
1123                 /* Enable in IER... */
1124                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1125                 /* and unmask in IMR */
1126                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1127         }
1128
1129         /*
1130          * Enable some error detection, note the instruction error mask
1131          * bit is reserved, so we leave it masked.
1132          */
1133         if (IS_G4X(dev)) {
1134                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1135                                GM45_ERROR_MEM_PRIV |
1136                                GM45_ERROR_CP_PRIV |
1137                                I915_ERROR_MEMORY_REFRESH);
1138         } else {
1139                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1140                                I915_ERROR_MEMORY_REFRESH);
1141         }
1142         I915_WRITE(EMR, error_mask);
1143
1144         /* Disable pipe interrupt enables, clear pending pipe status */
1145         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1146         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1147         /* Clear pending interrupt status */
1148         I915_WRITE(IIR, I915_READ(IIR));
1149
1150         I915_WRITE(IER, enable_mask);
1151         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1152         (void) I915_READ(IER);
1153
1154         opregion_enable_asle(dev);
1155
1156         return 0;
1157 }
1158
1159 static void ironlake_irq_uninstall(struct drm_device *dev)
1160 {
1161         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1162         I915_WRITE(HWSTAM, 0xffffffff);
1163
1164         I915_WRITE(DEIMR, 0xffffffff);
1165         I915_WRITE(DEIER, 0x0);
1166         I915_WRITE(DEIIR, I915_READ(DEIIR));
1167
1168         I915_WRITE(GTIMR, 0xffffffff);
1169         I915_WRITE(GTIER, 0x0);
1170         I915_WRITE(GTIIR, I915_READ(GTIIR));
1171 }
1172
1173 void i915_driver_irq_uninstall(struct drm_device * dev)
1174 {
1175         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1176
1177         if (!dev_priv)
1178                 return;
1179
1180         dev_priv->vblank_pipe = 0;
1181
1182         if (IS_IRONLAKE(dev)) {
1183                 ironlake_irq_uninstall(dev);
1184                 return;
1185         }
1186
1187         if (I915_HAS_HOTPLUG(dev)) {
1188                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1189                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1190         }
1191
1192         I915_WRITE(HWSTAM, 0xffffffff);
1193         I915_WRITE(PIPEASTAT, 0);
1194         I915_WRITE(PIPEBSTAT, 0);
1195         I915_WRITE(IMR, 0xffffffff);
1196         I915_WRITE(IER, 0x0);
1197
1198         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1199         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1200         I915_WRITE(IIR, I915_READ(IIR));
1201 }