SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      I915_LEGACY_BLC_EVENT_ENABLE);
 175                 if (IS_I965G(dev))
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              I915_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 195
 196         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 197                 return 1;
 198
 199         return 0;
 200 }
 201
 202 /* Called from drm generic code, passed a 'crtc', which
 203  * we use as a pipe index
 204  */
 205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 206 {
 207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 208         unsigned long high_frame;
 209         unsigned long low_frame;
 210         u32 high1, high2, low, count;
 211
 212         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 213         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 214
 215         if (!i915_pipe_enabled(dev, pipe)) {
 216                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 217                                 "pipe %d\n", pipe);
 218                 return 0;
 219         }
 220
 221         /*
 222          * High & low register fields aren't synchronized, so make sure
 223          * we get a low value that's stable across two reads of the high
 224          * register.
 225          */
 226         do {
 227                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 228                          PIPE_FRAME_HIGH_SHIFT);
 229                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 230                         PIPE_FRAME_LOW_SHIFT);
 231                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 232                          PIPE_FRAME_HIGH_SHIFT);
 233         } while (high1 != high2);
 234
 235         count = (high1 << 8) | low;
 236
 237         return count;
 238 }
 239
 240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 241 {
 242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 243         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 244
 245         if (!i915_pipe_enabled(dev, pipe)) {
 246                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 247                                         "pipe %d\n", pipe);
 248                 return 0;
 249         }
 250
 251         return I915_READ(reg);
 252 }
 253
 254 /*
 255  * Handle hotplug events outside the interrupt handler proper.
 256  */
 257 static void i915_hotplug_work_func(struct work_struct *work)
 258 {
 259         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 260                                                     hotplug_work);
 261         struct drm_device *dev = dev_priv->dev;
 262         struct drm_mode_config *mode_config = &dev->mode_config;
 263         struct drm_encoder *encoder;
 264
 265         if (mode_config->num_encoder) {
 266                 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 267                         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 268
 269                         if (intel_encoder->hot_plug)
 270                                 (*intel_encoder->hot_plug) (intel_encoder);
 271                 }
 272         }
 273         /* Just fire off a uevent and let userspace tell us what to do */
 274         drm_helper_hpd_irq_event(dev);
 275 }
 276
 277 static void i915_handle_rps_change(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         u32 busy_up, busy_down, max_avg, min_avg;
 281         u16 rgvswctl;
 282         u8 new_delay = dev_priv->cur_delay;
 283
 284         I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
 285         busy_up = I915_READ(RCPREVBSYTUPAVG);
 286         busy_down = I915_READ(RCPREVBSYTDNAVG);
 287         max_avg = I915_READ(RCBMAXAVG);
 288         min_avg = I915_READ(RCBMINAVG);
 289
 290         /* Handle RCS change request from hw */
 291         if (busy_up > max_avg) {
 292                 if (dev_priv->cur_delay != dev_priv->max_delay)
 293                         new_delay = dev_priv->cur_delay - 1;
 294                 if (new_delay < dev_priv->max_delay)
 295                         new_delay = dev_priv->max_delay;
 296         } else if (busy_down < min_avg) {
 297                 if (dev_priv->cur_delay != dev_priv->min_delay)
 298                         new_delay = dev_priv->cur_delay + 1;
 299                 if (new_delay > dev_priv->min_delay)
 300                         new_delay = dev_priv->min_delay;
 301         }
 302
 303         DRM_DEBUG("rps change requested: %d -> %d\n",
 304                   dev_priv->cur_delay, new_delay);
 305
 306         rgvswctl = I915_READ(MEMSWCTL);
 307         if (rgvswctl & MEMCTL_CMD_STS) {
 308                 DRM_ERROR("gpu busy, RCS change rejected\n");
 309                 return; /* still busy with another command */
 310         }
 311
 312         /* Program the new state */
 313         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
 314                 (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
 315         I915_WRITE(MEMSWCTL, rgvswctl);
 316         POSTING_READ(MEMSWCTL);
 317
 318         rgvswctl |= MEMCTL_CMD_STS;
 319         I915_WRITE(MEMSWCTL, rgvswctl);
 320
 321         dev_priv->cur_delay = new_delay;
 322
 323         DRM_DEBUG("rps changed\n");
 324
 325         return;
 326 }
 327
 328 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 329 {
 330         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 331         int ret = IRQ_NONE;
 332         u32 de_iir, gt_iir, de_ier, pch_iir;
 333         struct drm_i915_master_private *master_priv;
 334
 335         /* disable master interrupt before clearing iir  */
 336         de_ier = I915_READ(DEIER);
 337         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 338         (void)I915_READ(DEIER);
 339
 340         de_iir = I915_READ(DEIIR);
 341         gt_iir = I915_READ(GTIIR);
 342         pch_iir = I915_READ(SDEIIR);
 343
 344         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 345                 goto done;
 346
 347         ret = IRQ_HANDLED;
 348
 349         if (dev->primary->master) {
 350                 master_priv = dev->primary->master->driver_priv;
 351                 if (master_priv->sarea_priv)
 352                         master_priv->sarea_priv->last_dispatch =
 353                                 READ_BREADCRUMB(dev_priv);
 354         }
 355
 356         if (gt_iir & GT_PIPE_NOTIFY) {
 357                 u32 seqno = i915_get_gem_seqno(dev);
 358                 dev_priv->mm.irq_gem_seqno = seqno;
 359                 trace_i915_gem_request_complete(dev, seqno);
 360                 DRM_WAKEUP(&dev_priv->irq_queue);
 361                 dev_priv->hangcheck_count = 0;
 362                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 363         }
 364
 365         if (de_iir & DE_GSE)
 366                 ironlake_opregion_gse_intr(dev);
 367
 368         if (de_iir & DE_PLANEA_FLIP_DONE) {
 369                 intel_prepare_page_flip(dev, 0);
 370                 intel_finish_page_flip(dev, 0);
 371         }
 372
 373         if (de_iir & DE_PLANEB_FLIP_DONE) {
 374                 intel_prepare_page_flip(dev, 1);
 375                 intel_finish_page_flip(dev, 1);
 376         }
 377
 378         if (de_iir & DE_PIPEA_VBLANK)
 379                 drm_handle_vblank(dev, 0);
 380
 381         if (de_iir & DE_PIPEB_VBLANK)
 382                 drm_handle_vblank(dev, 1);
 383
 384         /* check event from PCH */
 385         if ((de_iir & DE_PCH_EVENT) &&
 386             (pch_iir & SDE_HOTPLUG_MASK)) {
 387                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 388         }
 389
 390         if (de_iir & DE_PCU_EVENT) {
 391                 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
 392                 i915_handle_rps_change(dev);
 393         }
 394
 395         /* should clear PCH hotplug event before clear CPU irq */
 396         I915_WRITE(SDEIIR, pch_iir);
 397         I915_WRITE(GTIIR, gt_iir);
 398         I915_WRITE(DEIIR, de_iir);
 399
 400 done:
 401         I915_WRITE(DEIER, de_ier);
 402         (void)I915_READ(DEIER);
 403
 404         return ret;
 405 }
 406
 407 /**
 408  * i915_error_work_func - do process context error handling work
 409  * @work: work struct
 410  *
 411  * Fire an error uevent so userspace can see that a hang or error
 412  * was detected.
 413  */
 414 static void i915_error_work_func(struct work_struct *work)
 415 {
 416         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 417                                                     error_work);
 418         struct drm_device *dev = dev_priv->dev;
 419         char *error_event[] = { "ERROR=1", NULL };
 420         char *reset_event[] = { "RESET=1", NULL };
 421         char *reset_done_event[] = { "ERROR=0", NULL };
 422
 423         DRM_DEBUG_DRIVER("generating error event\n");
 424         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 425
 426         if (atomic_read(&dev_priv->mm.wedged)) {
 427                 if (IS_I965G(dev)) {
 428                         DRM_DEBUG_DRIVER("resetting chip\n");
 429                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 430                         if (!i965_reset(dev, GDRST_RENDER)) {
 431                                 atomic_set(&dev_priv->mm.wedged, 0);
 432                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 433                         }
 434                 } else {
 435                         DRM_DEBUG_DRIVER("reboot required\n");
 436                 }
 437         }
 438 }
 439
 440 static struct drm_i915_error_object *
 441 i915_error_object_create(struct drm_device *dev,
 442                          struct drm_gem_object *src)
 443 {
 444         struct drm_i915_error_object *dst;
 445         struct drm_i915_gem_object *src_priv;
 446         int page, page_count;
 447
 448         if (src == NULL)
 449                 return NULL;
 450
 451         src_priv = to_intel_bo(src);
 452         if (src_priv->pages == NULL)
 453                 return NULL;
 454
 455         page_count = src->size / PAGE_SIZE;
 456
 457         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 458         if (dst == NULL)
 459                 return NULL;
 460
 461         for (page = 0; page < page_count; page++) {
 462                 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 463                 unsigned long flags;
 464
 465                 if (d == NULL)
 466                         goto unwind;
 467                 local_irq_save(flags);
 468                 s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
 469                 memcpy(d, s, PAGE_SIZE);
 470                 kunmap_atomic(s, KM_IRQ0);
 471                 local_irq_restore(flags);
 472                 dst->pages[page] = d;
 473         }
 474         dst->page_count = page_count;
 475         dst->gtt_offset = src_priv->gtt_offset;
 476
 477         return dst;
 478
 479 unwind:
 480         while (page--)
 481                 kfree(dst->pages[page]);
 482         kfree(dst);
 483         return NULL;
 484 }
 485
 486 static void
 487 i915_error_object_free(struct drm_i915_error_object *obj)
 488 {
 489         int page;
 490
 491         if (obj == NULL)
 492                 return;
 493
 494         for (page = 0; page < obj->page_count; page++)
 495                 kfree(obj->pages[page]);
 496
 497         kfree(obj);
 498 }
 499
 500 static void
 501 i915_error_state_free(struct drm_device *dev,
 502                       struct drm_i915_error_state *error)
 503 {
 504         i915_error_object_free(error->batchbuffer[0]);
 505         i915_error_object_free(error->batchbuffer[1]);
 506         i915_error_object_free(error->ringbuffer);
 507         kfree(error->active_bo);
 508         kfree(error);
 509 }
 510
 511 static u32
 512 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 513 {
 514         u32 cmd;
 515
 516         if (IS_I830(dev) || IS_845G(dev))
 517                 cmd = MI_BATCH_BUFFER;
 518         else if (IS_I965G(dev))
 519                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 520                        MI_BATCH_NON_SECURE_I965);
 521         else
 522                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 523
 524         return ring[0] == cmd ? ring[1] : 0;
 525 }
 526
 527 static u32
 528 i915_ringbuffer_last_batch(struct drm_device *dev)
 529 {
 530         struct drm_i915_private *dev_priv = dev->dev_private;
 531         u32 head, bbaddr;
 532         u32 *ring;
 533
 534         /* Locate the current position in the ringbuffer and walk back
 535          * to find the most recently dispatched batch buffer.
 536          */
 537         bbaddr = 0;
 538         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 539         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 540
 541         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 542                 bbaddr = i915_get_bbaddr(dev, ring);
 543                 if (bbaddr)
 544                         break;
 545         }
 546
 547         if (bbaddr == 0) {
 548                 ring = (u32 *)(dev_priv->render_ring.virtual_start + dev_priv->render_ring.Size);
 549                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 550                         bbaddr = i915_get_bbaddr(dev, ring);
 551                         if (bbaddr)
 552                                 break;
 553                 }
 554         }
 555
 556         return bbaddr;
 557 }
 558
 559 /**
 560  * i915_capture_error_state - capture an error record for later analysis
 561  * @dev: drm device
 562  *
 563  * Should be called when an error is detected (either a hang or an error
 564  * interrupt) to capture error state from the time of the error.  Fills
 565  * out a structure which becomes available in debugfs for user level tools
 566  * to pick up.
 567  */
 568 static void i915_capture_error_state(struct drm_device *dev)
 569 {
 570         struct drm_i915_private *dev_priv = dev->dev_private;
 571         struct drm_i915_gem_object *obj_priv;
 572         struct drm_i915_error_state *error;
 573         struct drm_gem_object *batchbuffer[2];
 574         unsigned long flags;
 575         u32 bbaddr;
 576         int count;
 577
 578         spin_lock_irqsave(&dev_priv->error_lock, flags);
 579         error = dev_priv->first_error;
 580         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 581         if (error)
 582                 return;
 583
 584         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 585         if (!error) {
 586                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 587                 return;
 588         }
 589
 590         error->seqno = i915_get_gem_seqno(dev);
 591         error->eir = I915_READ(EIR);
 592         error->pgtbl_er = I915_READ(PGTBL_ER);
 593         error->pipeastat = I915_READ(PIPEASTAT);
 594         error->pipebstat = I915_READ(PIPEBSTAT);
 595         error->instpm = I915_READ(INSTPM);
 596         if (!IS_I965G(dev)) {
 597                 error->ipeir = I915_READ(IPEIR);
 598                 error->ipehr = I915_READ(IPEHR);
 599                 error->instdone = I915_READ(INSTDONE);
 600                 error->acthd = I915_READ(ACTHD);
 601                 error->bbaddr = 0;
 602         } else {
 603                 error->ipeir = I915_READ(IPEIR_I965);
 604                 error->ipehr = I915_READ(IPEHR_I965);
 605                 error->instdone = I915_READ(INSTDONE_I965);
 606                 error->instps = I915_READ(INSTPS);
 607                 error->instdone1 = I915_READ(INSTDONE1);
 608                 error->acthd = I915_READ(ACTHD_I965);
 609                 error->bbaddr = I915_READ64(BB_ADDR);
 610         }
 611
 612         bbaddr = i915_ringbuffer_last_batch(dev);
 613
 614         /* Grab the current batchbuffer, most likely to have crashed. */
 615         batchbuffer[0] = NULL;
 616         batchbuffer[1] = NULL;
 617         count = 0;
 618         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
 619                 struct drm_gem_object *obj = &obj_priv->base;
 620
 621                 if (batchbuffer[0] == NULL &&
 622                     bbaddr >= obj_priv->gtt_offset &&
 623                     bbaddr < obj_priv->gtt_offset + obj->size)
 624                         batchbuffer[0] = obj;
 625
 626                 if (batchbuffer[1] == NULL &&
 627                     error->acthd >= obj_priv->gtt_offset &&
 628                     error->acthd < obj_priv->gtt_offset + obj->size &&
 629                     batchbuffer[0] != obj)
 630                         batchbuffer[1] = obj;
 631
 632                 count++;
 633         }
 634
 635         /* We need to copy these to an anonymous buffer as the simplest
 636          * method to avoid being overwritten by userpace.
 637          */
 638         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 639         error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 640
 641         /* Record the ringbuffer */
 642         error->ringbuffer = i915_error_object_create(dev, dev_priv->render_ring.ring_obj);
 643
 644         /* Record buffers on the active list. */
 645         error->active_bo = NULL;
 646         error->active_bo_count = 0;
 647
 648         if (count)
 649                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 650                                            GFP_ATOMIC);
 651
 652         if (error->active_bo) {
 653                 int i = 0;
 654                 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
 655                         struct drm_gem_object *obj = &obj_priv->base;
 656
 657                         error->active_bo[i].size = obj->size;
 658                         error->active_bo[i].name = obj->name;
 659                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 660                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 661                         error->active_bo[i].read_domains = obj->read_domains;
 662                         error->active_bo[i].write_domain = obj->write_domain;
 663                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 664                         error->active_bo[i].pinned = 0;
 665                         if (obj_priv->pin_count > 0)
 666                                 error->active_bo[i].pinned = 1;
 667                         if (obj_priv->user_pin_count > 0)
 668                                 error->active_bo[i].pinned = -1;
 669                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 670                         error->active_bo[i].dirty = obj_priv->dirty;
 671                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 672
 673                         if (++i == count)
 674                                 break;
 675                 }
 676                 error->active_bo_count = i;
 677         }
 678
 679         do_gettimeofday(&error->time);
 680
 681         spin_lock_irqsave(&dev_priv->error_lock, flags);
 682         if (dev_priv->first_error == NULL) {
 683                 dev_priv->first_error = error;
 684                 error = NULL;
 685         }
 686         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 687
 688         if (error)
 689                 i915_error_state_free(dev, error);
 690 }
 691
 692 void i915_destroy_error_state(struct drm_device *dev)
 693 {
 694         struct drm_i915_private *dev_priv = dev->dev_private;
 695         struct drm_i915_error_state *error;
 696
 697         spin_lock(&dev_priv->error_lock);
 698         error = dev_priv->first_error;
 699         dev_priv->first_error = NULL;
 700         spin_unlock(&dev_priv->error_lock);
 701
 702         if (error)
 703                 i915_error_state_free(dev, error);
 704 }
 705
 706 /**
 707  * i915_handle_error - handle an error interrupt
 708  * @dev: drm device
 709  *
 710  * Do some basic checking of regsiter state at error interrupt time and
 711  * dump it to the syslog.  Also call i915_capture_error_state() to make
 712  * sure we get a record and make it available in debugfs.  Fire a uevent
 713  * so userspace knows something bad happened (should trigger collection
 714  * of a ring dump etc.).
 715  */
 716 static void i915_handle_error(struct drm_device *dev, bool wedged)
 717 {
 718         struct drm_i915_private *dev_priv = dev->dev_private;
 719         u32 eir = I915_READ(EIR);
 720         u32 pipea_stats = I915_READ(PIPEASTAT);
 721         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 722
 723         i915_capture_error_state(dev);
 724
 725         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 726                eir);
 727
 728         if (IS_G4X(dev)) {
 729                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 730                         u32 ipeir = I915_READ(IPEIR_I965);
 731
 732                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 733                                I915_READ(IPEIR_I965));
 734                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 735                                I915_READ(IPEHR_I965));
 736                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 737                                I915_READ(INSTDONE_I965));
 738                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 739                                I915_READ(INSTPS));
 740                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 741                                I915_READ(INSTDONE1));
 742                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 743                                I915_READ(ACTHD_I965));
 744                         I915_WRITE(IPEIR_I965, ipeir);
 745                         (void)I915_READ(IPEIR_I965);
 746                 }
 747                 if (eir & GM45_ERROR_PAGE_TABLE) {
 748                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 749                         printk(KERN_ERR "page table error\n");
 750                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 751                                pgtbl_err);
 752                         I915_WRITE(PGTBL_ER, pgtbl_err);
 753                         (void)I915_READ(PGTBL_ER);
 754                 }
 755         }
 756
 757         if (IS_I9XX(dev)) {
 758                 if (eir & I915_ERROR_PAGE_TABLE) {
 759                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 760                         printk(KERN_ERR "page table error\n");
 761                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 762                                pgtbl_err);
 763                         I915_WRITE(PGTBL_ER, pgtbl_err);
 764                         (void)I915_READ(PGTBL_ER);
 765                 }
 766         }
 767
 768         if (eir & I915_ERROR_MEMORY_REFRESH) {
 769                 printk(KERN_ERR "memory refresh error\n");
 770                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 771                        pipea_stats);
 772                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 773                        pipeb_stats);
 774                 /* pipestat has already been acked */
 775         }
 776         if (eir & I915_ERROR_INSTRUCTION) {
 777                 printk(KERN_ERR "instruction error\n");
 778                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 779                        I915_READ(INSTPM));
 780                 if (!IS_I965G(dev)) {
 781                         u32 ipeir = I915_READ(IPEIR);
 782
 783                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 784                                I915_READ(IPEIR));
 785                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 786                                I915_READ(IPEHR));
 787                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 788                                I915_READ(INSTDONE));
 789                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 790                                I915_READ(ACTHD));
 791                         I915_WRITE(IPEIR, ipeir);
 792                         (void)I915_READ(IPEIR);
 793                 } else {
 794                         u32 ipeir = I915_READ(IPEIR_I965);
 795
 796                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 797                                I915_READ(IPEIR_I965));
 798                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 799                                I915_READ(IPEHR_I965));
 800                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 801                                I915_READ(INSTDONE_I965));
 802                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 803                                I915_READ(INSTPS));
 804                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 805                                I915_READ(INSTDONE1));
 806                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 807                                I915_READ(ACTHD_I965));
 808                         I915_WRITE(IPEIR_I965, ipeir);
 809                         (void)I915_READ(IPEIR_I965);
 810                 }
 811         }
 812
 813         I915_WRITE(EIR, eir);
 814         (void)I915_READ(EIR);
 815         eir = I915_READ(EIR);
 816         if (eir) {
 817                 /*
 818                  * some errors might have become stuck,
 819                  * mask them.
 820                  */
 821                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 822                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 823                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 824         }
 825
 826         if (wedged) {
 827                 atomic_set(&dev_priv->mm.wedged, 1);
 828
 829                 /*
 830                  * Wakeup waiting processes so they don't hang
 831                  */
 832                 DRM_WAKEUP(&dev_priv->irq_queue);
 833         }
 834
 835         queue_work(dev_priv->wq, &dev_priv->error_work);
 836 }
 837
 838 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 839 {
 840         struct drm_device *dev = (struct drm_device *) arg;
 841         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 842         struct drm_i915_master_private *master_priv;
 843         u32 iir, new_iir;
 844         u32 pipea_stats, pipeb_stats;
 845         u32 vblank_status;
 846         u32 vblank_enable;
 847         int vblank = 0;
 848         unsigned long irqflags;
 849         int irq_received;
 850         int ret = IRQ_NONE;
 851
 852         atomic_inc(&dev_priv->irq_received);
 853
 854         if (HAS_PCH_SPLIT(dev))
 855                 return ironlake_irq_handler(dev);
 856
 857         iir = I915_READ(IIR);
 858
 859         if (IS_I965G(dev)) {
 860                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 861                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 862         } else {
 863                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 864                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 865         }
 866
 867         for (;;) {
 868                 irq_received = iir != 0;
 869
 870                 /* Can't rely on pipestat interrupt bit in iir as it might
 871                  * have been cleared after the pipestat interrupt was received.
 872                  * It doesn't set the bit in iir again, but it still produces
 873                  * interrupts (for non-MSI).
 874                  */
 875                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 876                 pipea_stats = I915_READ(PIPEASTAT);
 877                 pipeb_stats = I915_READ(PIPEBSTAT);
 878
 879                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 880                         i915_handle_error(dev, false);
 881
 882                 /*
 883                  * Clear the PIPE(A|B)STAT regs before the IIR
 884                  */
 885                 if (pipea_stats & 0x8000ffff) {
 886                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 887                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 888                         I915_WRITE(PIPEASTAT, pipea_stats);
 889                         irq_received = 1;
 890                 }
 891
 892                 if (pipeb_stats & 0x8000ffff) {
 893                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 894                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 895                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 896                         irq_received = 1;
 897                 }
 898                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 899
 900                 if (!irq_received)
 901                         break;
 902
 903                 ret = IRQ_HANDLED;
 904
 905                 /* Consume port.  Then clear IIR or we'll miss events */
 906                 if ((I915_HAS_HOTPLUG(dev)) &&
 907                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 908                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 909
 910                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 911                                   hotplug_status);
 912                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 913                                 queue_work(dev_priv->wq,
 914                                            &dev_priv->hotplug_work);
 915
 916                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 917                         I915_READ(PORT_HOTPLUG_STAT);
 918                 }
 919
 920                 I915_WRITE(IIR, iir);
 921                 new_iir = I915_READ(IIR); /* Flush posted writes */
 922
 923                 if (dev->primary->master) {
 924                         master_priv = dev->primary->master->driver_priv;
 925                         if (master_priv->sarea_priv)
 926                                 master_priv->sarea_priv->last_dispatch =
 927                                         READ_BREADCRUMB(dev_priv);
 928                 }
 929
 930                 if (iir & I915_USER_INTERRUPT) {
 931                         u32 seqno = i915_get_gem_seqno(dev);
 932                         dev_priv->mm.irq_gem_seqno = seqno;
 933                         trace_i915_gem_request_complete(dev, seqno);
 934                         DRM_WAKEUP(&dev_priv->irq_queue);
 935                         dev_priv->hangcheck_count = 0;
 936                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 937                 }
 938
 939                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 940                         intel_prepare_page_flip(dev, 0);
 941
 942                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 943                         intel_prepare_page_flip(dev, 1);
 944
 945                 if (pipea_stats & vblank_status) {
 946                         vblank++;
 947                         drm_handle_vblank(dev, 0);
 948                         intel_finish_page_flip(dev, 0);
 949                 }
 950
 951                 if (pipeb_stats & vblank_status) {
 952                         vblank++;
 953                         drm_handle_vblank(dev, 1);
 954                         intel_finish_page_flip(dev, 1);
 955                 }
 956
 957                 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 958                     (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 959                     (iir & I915_ASLE_INTERRUPT))
 960                         opregion_asle_intr(dev);
 961
 962                 /* With MSI, interrupts are only generated when iir
 963                  * transitions from zero to nonzero.  If another bit got
 964                  * set while we were handling the existing iir bits, then
 965                  * we would never get another interrupt.
 966                  *
 967                  * This is fine on non-MSI as well, as if we hit this path
 968                  * we avoid exiting the interrupt handler only to generate
 969                  * another one.
 970                  *
 971                  * Note that for MSI this could cause a stray interrupt report
 972                  * if an interrupt landed in the time between writing IIR and
 973                  * the posting read.  This should be rare enough to never
 974                  * trigger the 99% of 100,000 interrupts test for disabling
 975                  * stray interrupts.
 976                  */
 977                 iir = new_iir;
 978         }
 979
 980         return ret;
 981 }
 982
 983 static int i915_emit_irq(struct drm_device * dev)
 984 {
 985         drm_i915_private_t *dev_priv = dev->dev_private;
 986         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 987         RING_LOCALS;
 988
 989         i915_kernel_lost_context(dev);
 990
 991         DRM_DEBUG_DRIVER("\n");
 992
 993         dev_priv->counter++;
 994         if (dev_priv->counter > 0x7FFFFFFFUL)
 995                 dev_priv->counter = 1;
 996         if (master_priv->sarea_priv)
 997                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 998
 999         BEGIN_LP_RING(4);
1000         OUT_RING(MI_STORE_DWORD_INDEX);
1001         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1002         OUT_RING(dev_priv->counter);
1003         OUT_RING(MI_USER_INTERRUPT);
1004         ADVANCE_LP_RING();
1005
1006         return dev_priv->counter;
1007 }
1008
1009 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1010 {
1011         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1012
1013         if (dev_priv->trace_irq_seqno == 0)
1014                 i915_user_irq_get(dev);
1015
1016         dev_priv->trace_irq_seqno = seqno;
1017 }
1018
1019 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1020 {
1021         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1022         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1023         int ret = 0;
1024
1025         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1026                   READ_BREADCRUMB(dev_priv));
1027
1028         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1029                 if (master_priv->sarea_priv)
1030                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1031                 return 0;
1032         }
1033
1034         if (master_priv->sarea_priv)
1035                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1036
1037         i915_user_irq_get(dev);
1038         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
1039                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1040         i915_user_irq_put(dev);
1041
1042         if (ret == -EBUSY) {
1043                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1044                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1045         }
1046
1047         return ret;
1048 }
1049
1050 /* Needs the lock as it touches the ring.
1051  */
1052 int i915_irq_emit(struct drm_device *dev, void *data,
1053                          struct drm_file *file_priv)
1054 {
1055         drm_i915_private_t *dev_priv = dev->dev_private;
1056         drm_i915_irq_emit_t *emit = data;
1057         int result;
1058
1059         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1060                 DRM_ERROR("called with no initialization\n");
1061                 return -EINVAL;
1062         }
1063
1064         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1065
1066         mutex_lock(&dev->struct_mutex);
1067         result = i915_emit_irq(dev);
1068         mutex_unlock(&dev->struct_mutex);
1069
1070         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1071                 DRM_ERROR("copy_to_user\n");
1072                 return -EFAULT;
1073         }
1074
1075         return 0;
1076 }
1077
1078 /* Doesn't need the hardware lock.
1079  */
1080 int i915_irq_wait(struct drm_device *dev, void *data,
1081                          struct drm_file *file_priv)
1082 {
1083         drm_i915_private_t *dev_priv = dev->dev_private;
1084         drm_i915_irq_wait_t *irqwait = data;
1085
1086         if (!dev_priv) {
1087                 DRM_ERROR("called with no initialization\n");
1088                 return -EINVAL;
1089         }
1090
1091         return i915_wait_irq(dev, irqwait->irq_seq);
1092 }
1093
1094 /* Called from drm generic code, passed 'crtc' which
1095  * we use as a pipe index
1096  */
1097 int i915_enable_vblank(struct drm_device *dev, int pipe)
1098 {
1099         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1100         unsigned long irqflags;
1101         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1102         u32 pipeconf;
1103
1104         pipeconf = I915_READ(pipeconf_reg);
1105         if (!(pipeconf & PIPEACONF_ENABLE))
1106                 return -EINVAL;
1107
1108         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1109         if (HAS_PCH_SPLIT(dev))
1110                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1111                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1112         else if (IS_I965G(dev))
1113                 i915_enable_pipestat(dev_priv, pipe,
1114                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1115         else
1116                 i915_enable_pipestat(dev_priv, pipe,
1117                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1118         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1119         return 0;
1120 }
1121
1122 /* Called from drm generic code, passed 'crtc' which
1123  * we use as a pipe index
1124  */
1125 void i915_disable_vblank(struct drm_device *dev, int pipe)
1126 {
1127         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1128         unsigned long irqflags;
1129
1130         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1131         if (HAS_PCH_SPLIT(dev))
1132                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1133                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1134         else
1135                 i915_disable_pipestat(dev_priv, pipe,
1136                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1137                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1138         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1139 }
1140
1141 void i915_enable_interrupt (struct drm_device *dev)
1142 {
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144
1145         if (!HAS_PCH_SPLIT(dev))
1146                 opregion_enable_asle(dev);
1147         dev_priv->irq_enabled = 1;
1148 }
1149
1150
1151 /* Set the vblank monitor pipe
1152  */
1153 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1154                          struct drm_file *file_priv)
1155 {
1156         drm_i915_private_t *dev_priv = dev->dev_private;
1157
1158         if (!dev_priv) {
1159                 DRM_ERROR("called with no initialization\n");
1160                 return -EINVAL;
1161         }
1162
1163         return 0;
1164 }
1165
1166 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1167                          struct drm_file *file_priv)
1168 {
1169         drm_i915_private_t *dev_priv = dev->dev_private;
1170         drm_i915_vblank_pipe_t *pipe = data;
1171
1172         if (!dev_priv) {
1173                 DRM_ERROR("called with no initialization\n");
1174                 return -EINVAL;
1175         }
1176
1177         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1178
1179         return 0;
1180 }
1181
1182 /**
1183  * Schedule buffer swap at given vertical blank.
1184  */
1185 int i915_vblank_swap(struct drm_device *dev, void *data,
1186                      struct drm_file *file_priv)
1187 {
1188         /* The delayed swap mechanism was fundamentally racy, and has been
1189          * removed.  The model was that the client requested a delayed flip/swap
1190          * from the kernel, then waited for vblank before continuing to perform
1191          * rendering.  The problem was that the kernel might wake the client
1192          * up before it dispatched the vblank swap (since the lock has to be
1193          * held while touching the ringbuffer), in which case the client would
1194          * clear and start the next frame before the swap occurred, and
1195          * flicker would occur in addition to likely missing the vblank.
1196          *
1197          * In the absence of this ioctl, userland falls back to a correct path
1198          * of waiting for a vblank, then dispatching the swap on its own.
1199          * Context switching to userland and back is plenty fast enough for
1200          * meeting the requirements of vblank swapping.
1201          */
1202         return -EINVAL;
1203 }
1204
1205 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
1206         drm_i915_private_t *dev_priv = dev->dev_private;
1207         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
1208 }
1209
1210 /**
1211  * This is called when the chip hasn't reported back with completed
1212  * batchbuffers in a long time. The first time this is called we simply record
1213  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1214  * again, we assume the chip is wedged and try to fix it.
1215  */
1216 void i915_hangcheck_elapsed(unsigned long data)
1217 {
1218         struct drm_device *dev = (struct drm_device *)data;
1219         drm_i915_private_t *dev_priv = dev->dev_private;
1220         uint32_t acthd;
1221
1222         /* No reset support on this chip yet. */
1223         if (IS_GEN6(dev))
1224                 return;
1225
1226         if (!IS_I965G(dev))
1227                 acthd = I915_READ(ACTHD);
1228         else
1229                 acthd = I915_READ(ACTHD_I965);
1230
1231         /* If all work is done then ACTHD clearly hasn't advanced. */
1232         if (list_empty(&dev_priv->mm.request_list) ||
1233                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
1234                 dev_priv->hangcheck_count = 0;
1235                 return;
1236         }
1237
1238         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1239                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1240                 i915_handle_error(dev, true);
1241                 return;
1242         }
1243
1244         /* Reset timer case chip hangs without another request being added */
1245         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1246
1247         if (acthd != dev_priv->last_acthd)
1248                 dev_priv->hangcheck_count = 0;
1249         else
1250                 dev_priv->hangcheck_count++;
1251
1252         dev_priv->last_acthd = acthd;
1253 }
1254
1255 /* drm_dma.h hooks
1256 */
1257 static void ironlake_irq_preinstall(struct drm_device *dev)
1258 {
1259         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1260
1261         I915_WRITE(HWSTAM, 0xeffe);
1262
1263         /* XXX hotplug from PCH */
1264
1265         I915_WRITE(DEIMR, 0xffffffff);
1266         I915_WRITE(DEIER, 0x0);
1267         (void) I915_READ(DEIER);
1268
1269         /* and GT */
1270         I915_WRITE(GTIMR, 0xffffffff);
1271         I915_WRITE(GTIER, 0x0);
1272         (void) I915_READ(GTIER);
1273
1274         /* south display irq */
1275         I915_WRITE(SDEIMR, 0xffffffff);
1276         I915_WRITE(SDEIER, 0x0);
1277         (void) I915_READ(SDEIER);
1278 }
1279
1280 static int ironlake_irq_postinstall(struct drm_device *dev)
1281 {
1282         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1283         /* enable kind of interrupts always enabled */
1284         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1285                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1286         u32 render_mask = GT_PIPE_NOTIFY;
1287         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1288                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1289
1290         dev_priv->irq_mask_reg = ~display_mask;
1291         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1292
1293         /* should always can generate irq */
1294         I915_WRITE(DEIIR, I915_READ(DEIIR));
1295         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1296         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1297         (void) I915_READ(DEIER);
1298
1299         /* user interrupt should be enabled, but masked initial */
1300         dev_priv->gt_irq_mask_reg = 0xffffffff;
1301         dev_priv->gt_irq_enable_reg = render_mask;
1302
1303         I915_WRITE(GTIIR, I915_READ(GTIIR));
1304         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1305         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1306         (void) I915_READ(GTIER);
1307
1308         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1309         dev_priv->pch_irq_enable_reg = hotplug_mask;
1310
1311         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1312         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1313         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1314         (void) I915_READ(SDEIER);
1315
1316         if (IS_IRONLAKE_M(dev)) {
1317                 /* Clear & enable PCU event interrupts */
1318                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1319                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1320                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1321         }
1322
1323         return 0;
1324 }
1325
1326 void i915_driver_irq_preinstall(struct drm_device * dev)
1327 {
1328         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1329
1330         atomic_set(&dev_priv->irq_received, 0);
1331
1332         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1333         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1334
1335         if (HAS_PCH_SPLIT(dev)) {
1336                 ironlake_irq_preinstall(dev);
1337                 return;
1338         }
1339
1340         if (I915_HAS_HOTPLUG(dev)) {
1341                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1342                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1343         }
1344
1345         I915_WRITE(HWSTAM, 0xeffe);
1346         I915_WRITE(PIPEASTAT, 0);
1347         I915_WRITE(PIPEBSTAT, 0);
1348         I915_WRITE(IMR, 0xffffffff);
1349         I915_WRITE(IER, 0x0);
1350         (void) I915_READ(IER);
1351 }
1352
1353 /*
1354  * Must be called after intel_modeset_init or hotplug interrupts won't be
1355  * enabled correctly.
1356  */
1357 int i915_driver_irq_postinstall(struct drm_device *dev)
1358 {
1359         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1360         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1361         u32 error_mask;
1362
1363         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1364
1365         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1366
1367         if (HAS_PCH_SPLIT(dev))
1368                 return ironlake_irq_postinstall(dev);
1369
1370         /* Unmask the interrupts that we always want on. */
1371         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1372
1373         dev_priv->pipestat[0] = 0;
1374         dev_priv->pipestat[1] = 0;
1375
1376         if (I915_HAS_HOTPLUG(dev)) {
1377                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1378
1379                 /* Note HDMI and DP share bits */
1380                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1381                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1382                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1383                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1384                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1385                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1386                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1387                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1388                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1389                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1390                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1391                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1392                 /* Ignore TV since it's buggy */
1393
1394                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1395
1396                 /* Enable in IER... */
1397                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1398                 /* and unmask in IMR */
1399                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1400         }
1401
1402         /*
1403          * Enable some error detection, note the instruction error mask
1404          * bit is reserved, so we leave it masked.
1405          */
1406         if (IS_G4X(dev)) {
1407                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1408                                GM45_ERROR_MEM_PRIV |
1409                                GM45_ERROR_CP_PRIV |
1410                                I915_ERROR_MEMORY_REFRESH);
1411         } else {
1412                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1413                                I915_ERROR_MEMORY_REFRESH);
1414         }
1415         I915_WRITE(EMR, error_mask);
1416
1417         /* Disable pipe interrupt enables, clear pending pipe status */
1418         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1419         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1420         /* Clear pending interrupt status */
1421         I915_WRITE(IIR, I915_READ(IIR));
1422
1423         I915_WRITE(IER, enable_mask);
1424         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1425         (void) I915_READ(IER);
1426
1427         opregion_enable_asle(dev);
1428
1429         return 0;
1430 }
1431
1432 static void ironlake_irq_uninstall(struct drm_device *dev)
1433 {
1434         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1435         I915_WRITE(HWSTAM, 0xffffffff);
1436
1437         I915_WRITE(DEIMR, 0xffffffff);
1438         I915_WRITE(DEIER, 0x0);
1439         I915_WRITE(DEIIR, I915_READ(DEIIR));
1440
1441         I915_WRITE(GTIMR, 0xffffffff);
1442         I915_WRITE(GTIER, 0x0);
1443         I915_WRITE(GTIIR, I915_READ(GTIIR));
1444 }
1445
1446 void i915_driver_irq_uninstall(struct drm_device * dev)
1447 {
1448         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1449
1450         if (!dev_priv)
1451                 return;
1452
1453         dev_priv->vblank_pipe = 0;
1454
1455         if (HAS_PCH_SPLIT(dev)) {
1456                 ironlake_irq_uninstall(dev);
1457                 return;
1458         }
1459
1460         if (I915_HAS_HOTPLUG(dev)) {
1461                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1462                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1463         }
1464
1465         I915_WRITE(HWSTAM, 0xffffffff);
1466         I915_WRITE(PIPEASTAT, 0);
1467         I915_WRITE(PIPEBSTAT, 0);
1468         I915_WRITE(IMR, 0xffffffff);
1469         I915_WRITE(IER, 0x0);
1470
1471         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1472         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1473         I915_WRITE(IIR, I915_READ(IIR));
1474 }