SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define MAX_NOPID ((u32)~0)
  35
  36 /** These are the interrupts used by the driver */
  37 #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT |               \
  38                                     I915_ASLE_INTERRUPT |               \
  39                                     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  40                                     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
  41
  42 void
  43 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  44 {
  45         if ((dev_priv->irq_mask_reg & mask) != 0) {
  46                 dev_priv->irq_mask_reg &= ~mask;
  47                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  48                 (void) I915_READ(IMR);
  49         }
  50 }
  51
  52 static inline void
  53 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  54 {
  55         if ((dev_priv->irq_mask_reg & mask) != mask) {
  56                 dev_priv->irq_mask_reg |= mask;
  57                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  58                 (void) I915_READ(IMR);
  59         }
  60 }
  61
  62 /**
  63  * i915_pipe_enabled - check if a pipe is enabled
  64  * @dev: DRM device
  65  * @pipe: pipe to check
  66  *
  67  * Reading certain registers when the pipe is disabled can hang the chip.
  68  * Use this routine to make sure the PLL is running and the pipe is active
  69  * before reading such registers if unsure.
  70  */
  71 static int
  72 i915_pipe_enabled(struct drm_device *dev, int pipe)
  73 {
  74         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  75         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
  76
  77         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
  78                 return 1;
  79
  80         return 0;
  81 }
  82
  83 /* Called from drm generic code, passed a 'crtc', which
  84  * we use as a pipe index
  85  */
  86 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  87 {
  88         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  89         unsigned long high_frame;
  90         unsigned long low_frame;
  91         u32 high1, high2, low, count;
  92
  93         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
  94         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
  95
  96         if (!i915_pipe_enabled(dev, pipe)) {
  97                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
  98                 return 0;
  99         }
 100
 101         /*
 102          * High & low register fields aren't synchronized, so make sure
 103          * we get a low value that's stable across two reads of the high
 104          * register.
 105          */
 106         do {
 107                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 108                          PIPE_FRAME_HIGH_SHIFT);
 109                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 110                         PIPE_FRAME_LOW_SHIFT);
 111                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 112                          PIPE_FRAME_HIGH_SHIFT);
 113         } while (high1 != high2);
 114
 115         count = (high1 << 8) | low;
 116
 117         return count;
 118 }
 119
 120 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 121 {
 122         struct drm_device *dev = (struct drm_device *) arg;
 123         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 124         u32 iir;
 125         u32 pipea_stats, pipeb_stats;
 126         int vblank = 0;
 127
 128         atomic_inc(&dev_priv->irq_received);
 129
 130         if (dev->pdev->msi_enabled)
 131                 I915_WRITE(IMR, ~0);
 132         iir = I915_READ(IIR);
 133
 134         if (iir == 0) {
 135                 if (dev->pdev->msi_enabled) {
 136                         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 137                         (void) I915_READ(IMR);
 138                 }
 139                 return IRQ_NONE;
 140         }
 141
 142         /*
 143          * Clear the PIPE(A|B)STAT regs before the IIR otherwise
 144          * we may get extra interrupts.
 145          */
 146         if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
 147                 pipea_stats = I915_READ(PIPEASTAT);
 148                 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A))
 149                         pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
 150                                          PIPE_VBLANK_INTERRUPT_ENABLE);
 151                 else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
 152                                         PIPE_VBLANK_INTERRUPT_STATUS)) {
 153                         vblank++;
 154                         drm_handle_vblank(dev, 0);
 155                 }
 156
 157                 I915_WRITE(PIPEASTAT, pipea_stats);
 158         }
 159         if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
 160                 pipeb_stats = I915_READ(PIPEBSTAT);
 161                 /* Ack the event */
 162                 I915_WRITE(PIPEBSTAT, pipeb_stats);
 163
 164                 /* The vblank interrupt gets enabled even if we didn't ask for
 165                    it, so make sure it's shut down again */
 166                 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B))
 167                         pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
 168                                          PIPE_VBLANK_INTERRUPT_ENABLE);
 169                 else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
 170                                         PIPE_VBLANK_INTERRUPT_STATUS)) {
 171                         vblank++;
 172                         drm_handle_vblank(dev, 1);
 173                 }
 174
 175                 if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS)
 176                         opregion_asle_intr(dev);
 177                 I915_WRITE(PIPEBSTAT, pipeb_stats);
 178         }
 179
 180         I915_WRITE(IIR, iir);
 181         if (dev->pdev->msi_enabled)
 182                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 183         (void) I915_READ(IIR); /* Flush posted writes */
 184
 185         if (dev_priv->sarea_priv)
 186                 dev_priv->sarea_priv->last_dispatch =
 187                         READ_BREADCRUMB(dev_priv);
 188
 189         if (iir & I915_USER_INTERRUPT) {
 190                 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
 191                 DRM_WAKEUP(&dev_priv->irq_queue);
 192         }
 193
 194         if (iir & I915_ASLE_INTERRUPT)
 195                 opregion_asle_intr(dev);
 196
 197         return IRQ_HANDLED;
 198 }
 199
 200 static int i915_emit_irq(struct drm_device * dev)
 201 {
 202         drm_i915_private_t *dev_priv = dev->dev_private;
 203         RING_LOCALS;
 204
 205         i915_kernel_lost_context(dev);
 206
 207         DRM_DEBUG("\n");
 208
 209         dev_priv->counter++;
 210         if (dev_priv->counter > 0x7FFFFFFFUL)
 211                 dev_priv->counter = 1;
 212         if (dev_priv->sarea_priv)
 213                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 214
 215         BEGIN_LP_RING(6);
 216         OUT_RING(MI_STORE_DWORD_INDEX);
 217         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 218         OUT_RING(dev_priv->counter);
 219         OUT_RING(0);
 220         OUT_RING(0);
 221         OUT_RING(MI_USER_INTERRUPT);
 222         ADVANCE_LP_RING();
 223
 224         return dev_priv->counter;
 225 }
 226
 227 void i915_user_irq_get(struct drm_device *dev)
 228 {
 229         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 230         unsigned long irqflags;
 231
 232         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 233         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
 234                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 235         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 236 }
 237
 238 void i915_user_irq_put(struct drm_device *dev)
 239 {
 240         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 241         unsigned long irqflags;
 242
 243         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 244         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 245         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
 246                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 247         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 248 }
 249
 250 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 251 {
 252         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 253         int ret = 0;
 254
 255         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 256                   READ_BREADCRUMB(dev_priv));
 257
 258         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 259                 if (dev_priv->sarea_priv) {
 260                         dev_priv->sarea_priv->last_dispatch =
 261                                 READ_BREADCRUMB(dev_priv);
 262                 }
 263                 return 0;
 264         }
 265
 266         if (dev_priv->sarea_priv)
 267                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 268
 269         i915_user_irq_get(dev);
 270         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 271                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 272         i915_user_irq_put(dev);
 273
 274         if (ret == -EBUSY) {
 275                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 276                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 277         }
 278
 279         if (dev_priv->sarea_priv)
 280                 dev_priv->sarea_priv->last_dispatch =
 281                         READ_BREADCRUMB(dev_priv);
 282
 283         return ret;
 284 }
 285
 286 /* Needs the lock as it touches the ring.
 287  */
 288 int i915_irq_emit(struct drm_device *dev, void *data,
 289                          struct drm_file *file_priv)
 290 {
 291         drm_i915_private_t *dev_priv = dev->dev_private;
 292         drm_i915_irq_emit_t *emit = data;
 293         int result;
 294
 295         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 296
 297         if (!dev_priv) {
 298                 DRM_ERROR("called with no initialization\n");
 299                 return -EINVAL;
 300         }
 301         mutex_lock(&dev->struct_mutex);
 302         result = i915_emit_irq(dev);
 303         mutex_unlock(&dev->struct_mutex);
 304
 305         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 306                 DRM_ERROR("copy_to_user\n");
 307                 return -EFAULT;
 308         }
 309
 310         return 0;
 311 }
 312
 313 /* Doesn't need the hardware lock.
 314  */
 315 int i915_irq_wait(struct drm_device *dev, void *data,
 316                          struct drm_file *file_priv)
 317 {
 318         drm_i915_private_t *dev_priv = dev->dev_private;
 319         drm_i915_irq_wait_t *irqwait = data;
 320
 321         if (!dev_priv) {
 322                 DRM_ERROR("called with no initialization\n");
 323                 return -EINVAL;
 324         }
 325
 326         return i915_wait_irq(dev, irqwait->irq_seq);
 327 }
 328
 329 /* Called from drm generic code, passed 'crtc' which
 330  * we use as a pipe index
 331  */
 332 int i915_enable_vblank(struct drm_device *dev, int pipe)
 333 {
 334         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 335         u32     pipestat_reg = 0;
 336         u32     pipestat;
 337         u32     interrupt = 0;
 338         unsigned long irqflags;
 339
 340         switch (pipe) {
 341         case 0:
 342                 pipestat_reg = PIPEASTAT;
 343                 interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 344                 break;
 345         case 1:
 346                 pipestat_reg = PIPEBSTAT;
 347                 interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 348                 break;
 349         default:
 350                 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
 351                           pipe);
 352                 return 0;
 353         }
 354
 355         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 356         /* Enabling vblank events in IMR comes before PIPESTAT write, or
 357          * there's a race where the PIPESTAT vblank bit gets set to 1, so
 358          * the OR of enabled PIPESTAT bits goes to 1, so the PIPExEVENT in
 359          * ISR flashes to 1, but the IIR bit doesn't get set to 1 because
 360          * IMR masks it.  It doesn't ever get set after we clear the masking
 361          * in IMR because the ISR bit is edge, not level-triggered, on the
 362          * OR of PIPESTAT bits.
 363          */
 364         i915_enable_irq(dev_priv, interrupt);
 365         pipestat = I915_READ(pipestat_reg);
 366         if (IS_I965G(dev))
 367                 pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
 368         else
 369                 pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
 370         /* Clear any stale interrupt status */
 371         pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
 372                      PIPE_VBLANK_INTERRUPT_STATUS);
 373         I915_WRITE(pipestat_reg, pipestat);
 374         (void) I915_READ(pipestat_reg); /* Posting read */
 375         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 376
 377         return 0;
 378 }
 379
 380 /* Called from drm generic code, passed 'crtc' which
 381  * we use as a pipe index
 382  */
 383 void i915_disable_vblank(struct drm_device *dev, int pipe)
 384 {
 385         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 386         u32     pipestat_reg = 0;
 387         u32     pipestat;
 388         u32     interrupt = 0;
 389         unsigned long irqflags;
 390
 391         switch (pipe) {
 392         case 0:
 393                 pipestat_reg = PIPEASTAT;
 394                 interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 395                 break;
 396         case 1:
 397                 pipestat_reg = PIPEBSTAT;
 398                 interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 399                 break;
 400         default:
 401                 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
 402                           pipe);
 403                 return;
 404                 break;
 405         }
 406
 407         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 408         i915_disable_irq(dev_priv, interrupt);
 409         pipestat = I915_READ(pipestat_reg);
 410         pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
 411                       PIPE_VBLANK_INTERRUPT_ENABLE);
 412         /* Clear any stale interrupt status */
 413         pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
 414                      PIPE_VBLANK_INTERRUPT_STATUS);
 415         I915_WRITE(pipestat_reg, pipestat);
 416         (void) I915_READ(pipestat_reg); /* Posting read */
 417         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 418 }
 419
 420 /* Set the vblank monitor pipe
 421  */
 422 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 423                          struct drm_file *file_priv)
 424 {
 425         drm_i915_private_t *dev_priv = dev->dev_private;
 426
 427         if (!dev_priv) {
 428                 DRM_ERROR("called with no initialization\n");
 429                 return -EINVAL;
 430         }
 431
 432         return 0;
 433 }
 434
 435 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 436                          struct drm_file *file_priv)
 437 {
 438         drm_i915_private_t *dev_priv = dev->dev_private;
 439         drm_i915_vblank_pipe_t *pipe = data;
 440
 441         if (!dev_priv) {
 442                 DRM_ERROR("called with no initialization\n");
 443                 return -EINVAL;
 444         }
 445
 446         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 447
 448         return 0;
 449 }
 450
 451 /**
 452  * Schedule buffer swap at given vertical blank.
 453  */
 454 int i915_vblank_swap(struct drm_device *dev, void *data,
 455                      struct drm_file *file_priv)
 456 {
 457         /* The delayed swap mechanism was fundamentally racy, and has been
 458          * removed.  The model was that the client requested a delayed flip/swap
 459          * from the kernel, then waited for vblank before continuing to perform
 460          * rendering.  The problem was that the kernel might wake the client
 461          * up before it dispatched the vblank swap (since the lock has to be
 462          * held while touching the ringbuffer), in which case the client would
 463          * clear and start the next frame before the swap occurred, and
 464          * flicker would occur in addition to likely missing the vblank.
 465          *
 466          * In the absence of this ioctl, userland falls back to a correct path
 467          * of waiting for a vblank, then dispatching the swap on its own.
 468          * Context switching to userland and back is plenty fast enough for
 469          * meeting the requirements of vblank swapping.
 470          */
 471         return -EINVAL;
 472 }
 473
 474 /* drm_dma.h hooks
 475 */
 476 void i915_driver_irq_preinstall(struct drm_device * dev)
 477 {
 478         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 479
 480         I915_WRITE(HWSTAM, 0xeffe);
 481         I915_WRITE(IMR, 0xffffffff);
 482         I915_WRITE(IER, 0x0);
 483 }
 484
 485 int i915_driver_irq_postinstall(struct drm_device *dev)
 486 {
 487         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 488         int ret, num_pipes = 2;
 489
 490         /* Set initial unmasked IRQs to just the selected vblank pipes. */
 491         dev_priv->irq_mask_reg = ~0;
 492
 493         ret = drm_vblank_init(dev, num_pipes);
 494         if (ret)
 495                 return ret;
 496
 497         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 498         dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
 499         dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 500
 501         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 502
 503         dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK;
 504
 505         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 506         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
 507         (void) I915_READ(IER);
 508
 509         opregion_enable_asle(dev);
 510         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
 511
 512         return 0;
 513 }
 514
 515 void i915_driver_irq_uninstall(struct drm_device * dev)
 516 {
 517         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 518         u32 temp;
 519
 520         if (!dev_priv)
 521                 return;
 522
 523         dev_priv->vblank_pipe = 0;
 524
 525         I915_WRITE(HWSTAM, 0xffffffff);
 526         I915_WRITE(IMR, 0xffffffff);
 527         I915_WRITE(IER, 0x0);
 528
 529         temp = I915_READ(PIPEASTAT);
 530         I915_WRITE(PIPEASTAT, temp);
 531         temp = I915_READ(PIPEBSTAT);
 532         I915_WRITE(PIPEBSTAT, temp);
 533         temp = I915_READ(IIR);
 534         I915_WRITE(IIR, temp);
 535 }