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   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 #define MAX_NOPID ((u32)~0)
  36
  37 /**
  38  * Interrupts that are always left unmasked.
  39  *
  40  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  41  * we leave them always unmasked in IMR and then control enabling them through
  42  * PIPESTAT alone.
  43  */
  44 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
  45                                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |  \
  46                                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
  47
  48 /** Interrupts that we mask and unmask at runtime. */
  49 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  50
  51 /** These are all of the interrupts used by the driver */
  52 #define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \
  53                                     I915_INTERRUPT_ENABLE_VAR)
  54
  55 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  56                                  PIPE_VBLANK_INTERRUPT_STATUS)
  57
  58 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  59                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  60
  61 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  62                                          DRM_I915_VBLANK_PIPE_B)
  63
  64 void
  65 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  66 {
  67         if ((dev_priv->irq_mask_reg & mask) != 0) {
  68                 dev_priv->irq_mask_reg &= ~mask;
  69                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  70                 (void) I915_READ(IMR);
  71         }
  72 }
  73
  74 static inline void
  75 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  76 {
  77         if ((dev_priv->irq_mask_reg & mask) != mask) {
  78                 dev_priv->irq_mask_reg |= mask;
  79                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  80                 (void) I915_READ(IMR);
  81         }
  82 }
  83
  84 static inline u32
  85 i915_pipestat(int pipe)
  86 {
  87         if (pipe == 0)
  88                 return PIPEASTAT;
  89         if (pipe == 1)
  90                 return PIPEBSTAT;
  91         BUG();
  92 }
  93
  94 void
  95 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  96 {
  97         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  98                 u32 reg = i915_pipestat(pipe);
  99
 100                 dev_priv->pipestat[pipe] |= mask;
 101                 /* Enable the interrupt, clear any pending status */
 102                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 103                 (void) I915_READ(reg);
 104         }
 105 }
 106
 107 void
 108 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 109 {
 110         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 111                 u32 reg = i915_pipestat(pipe);
 112
 113                 dev_priv->pipestat[pipe] &= ~mask;
 114                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 115                 (void) I915_READ(reg);
 116         }
 117 }
 118
 119 /**
 120  * i915_pipe_enabled - check if a pipe is enabled
 121  * @dev: DRM device
 122  * @pipe: pipe to check
 123  *
 124  * Reading certain registers when the pipe is disabled can hang the chip.
 125  * Use this routine to make sure the PLL is running and the pipe is active
 126  * before reading such registers if unsure.
 127  */
 128 static int
 129 i915_pipe_enabled(struct drm_device *dev, int pipe)
 130 {
 131         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 132         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 133
 134         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 135                 return 1;
 136
 137         return 0;
 138 }
 139
 140 /* Called from drm generic code, passed a 'crtc', which
 141  * we use as a pipe index
 142  */
 143 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 144 {
 145         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 146         unsigned long high_frame;
 147         unsigned long low_frame;
 148         u32 high1, high2, low, count;
 149
 150         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 151         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 152
 153         if (!i915_pipe_enabled(dev, pipe)) {
 154                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 155                 return 0;
 156         }
 157
 158         /*
 159          * High & low register fields aren't synchronized, so make sure
 160          * we get a low value that's stable across two reads of the high
 161          * register.
 162          */
 163         do {
 164                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 165                          PIPE_FRAME_HIGH_SHIFT);
 166                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 167                         PIPE_FRAME_LOW_SHIFT);
 168                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 169                          PIPE_FRAME_HIGH_SHIFT);
 170         } while (high1 != high2);
 171
 172         count = (high1 << 8) | low;
 173
 174         return count;
 175 }
 176
 177 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 178 {
 179         struct drm_device *dev = (struct drm_device *) arg;
 180         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 181         struct drm_i915_master_private *master_priv;
 182         u32 iir, new_iir;
 183         u32 pipea_stats, pipeb_stats;
 184         u32 vblank_status;
 185         u32 vblank_enable;
 186         int vblank = 0;
 187         unsigned long irqflags;
 188         int irq_received;
 189         int ret = IRQ_NONE;
 190
 191         atomic_inc(&dev_priv->irq_received);
 192
 193         iir = I915_READ(IIR);
 194
 195         if (IS_I965G(dev)) {
 196                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 197                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 198         } else {
 199                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 200                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 201         }
 202
 203         for (;;) {
 204                 irq_received = iir != 0;
 205
 206                 /* Can't rely on pipestat interrupt bit in iir as it might
 207                  * have been cleared after the pipestat interrupt was received.
 208                  * It doesn't set the bit in iir again, but it still produces
 209                  * interrupts (for non-MSI).
 210                  */
 211                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 212                 pipea_stats = I915_READ(PIPEASTAT);
 213                 pipeb_stats = I915_READ(PIPEBSTAT);
 214
 215                 /*
 216                  * Clear the PIPE(A|B)STAT regs before the IIR
 217                  */
 218                 if (pipea_stats & 0x8000ffff) {
 219                         I915_WRITE(PIPEASTAT, pipea_stats);
 220                         irq_received = 1;
 221                 }
 222
 223                 if (pipeb_stats & 0x8000ffff) {
 224                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 225                         irq_received = 1;
 226                 }
 227                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 228
 229                 if (!irq_received)
 230                         break;
 231
 232                 ret = IRQ_HANDLED;
 233
 234                 I915_WRITE(IIR, iir);
 235                 new_iir = I915_READ(IIR); /* Flush posted writes */
 236
 237                 if (dev->primary->master) {
 238                         master_priv = dev->primary->master->driver_priv;
 239                         if (master_priv->sarea_priv)
 240                                 master_priv->sarea_priv->last_dispatch =
 241                                         READ_BREADCRUMB(dev_priv);
 242                 }
 243
 244                 if (iir & I915_USER_INTERRUPT) {
 245                         dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
 246                         DRM_WAKEUP(&dev_priv->irq_queue);
 247                 }
 248
 249                 if (pipea_stats & vblank_status) {
 250                         vblank++;
 251                         drm_handle_vblank(dev, 0);
 252                 }
 253
 254                 if (pipeb_stats & vblank_status) {
 255                         vblank++;
 256                         drm_handle_vblank(dev, 1);
 257                 }
 258
 259                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 260                     (iir & I915_ASLE_INTERRUPT))
 261                         opregion_asle_intr(dev);
 262
 263                 /* With MSI, interrupts are only generated when iir
 264                  * transitions from zero to nonzero.  If another bit got
 265                  * set while we were handling the existing iir bits, then
 266                  * we would never get another interrupt.
 267                  *
 268                  * This is fine on non-MSI as well, as if we hit this path
 269                  * we avoid exiting the interrupt handler only to generate
 270                  * another one.
 271                  *
 272                  * Note that for MSI this could cause a stray interrupt report
 273                  * if an interrupt landed in the time between writing IIR and
 274                  * the posting read.  This should be rare enough to never
 275                  * trigger the 99% of 100,000 interrupts test for disabling
 276                  * stray interrupts.
 277                  */
 278                 iir = new_iir;
 279         }
 280
 281         return ret;
 282 }
 283
 284 static int i915_emit_irq(struct drm_device * dev)
 285 {
 286         drm_i915_private_t *dev_priv = dev->dev_private;
 287         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 288         RING_LOCALS;
 289
 290         i915_kernel_lost_context(dev);
 291
 292         DRM_DEBUG("\n");
 293
 294         dev_priv->counter++;
 295         if (dev_priv->counter > 0x7FFFFFFFUL)
 296                 dev_priv->counter = 1;
 297         if (master_priv->sarea_priv)
 298                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 299
 300         BEGIN_LP_RING(4);
 301         OUT_RING(MI_STORE_DWORD_INDEX);
 302         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 303         OUT_RING(dev_priv->counter);
 304         OUT_RING(MI_USER_INTERRUPT);
 305         ADVANCE_LP_RING();
 306
 307         return dev_priv->counter;
 308 }
 309
 310 void i915_user_irq_get(struct drm_device *dev)
 311 {
 312         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 313         unsigned long irqflags;
 314
 315         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 316         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
 317                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 318         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 319 }
 320
 321 void i915_user_irq_put(struct drm_device *dev)
 322 {
 323         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 324         unsigned long irqflags;
 325
 326         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 327         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 328         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
 329                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 330         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 331 }
 332
 333 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 334 {
 335         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 336         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 337         int ret = 0;
 338
 339         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 340                   READ_BREADCRUMB(dev_priv));
 341
 342         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 343                 if (master_priv->sarea_priv)
 344                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 345                 return 0;
 346         }
 347
 348         if (master_priv->sarea_priv)
 349                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 350
 351         i915_user_irq_get(dev);
 352         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 353                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 354         i915_user_irq_put(dev);
 355
 356         if (ret == -EBUSY) {
 357                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 358                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 359         }
 360
 361         return ret;
 362 }
 363
 364 /* Needs the lock as it touches the ring.
 365  */
 366 int i915_irq_emit(struct drm_device *dev, void *data,
 367                          struct drm_file *file_priv)
 368 {
 369         drm_i915_private_t *dev_priv = dev->dev_private;
 370         drm_i915_irq_emit_t *emit = data;
 371         int result;
 372
 373         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 374
 375         if (!dev_priv) {
 376                 DRM_ERROR("called with no initialization\n");
 377                 return -EINVAL;
 378         }
 379         mutex_lock(&dev->struct_mutex);
 380         result = i915_emit_irq(dev);
 381         mutex_unlock(&dev->struct_mutex);
 382
 383         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 384                 DRM_ERROR("copy_to_user\n");
 385                 return -EFAULT;
 386         }
 387
 388         return 0;
 389 }
 390
 391 /* Doesn't need the hardware lock.
 392  */
 393 int i915_irq_wait(struct drm_device *dev, void *data,
 394                          struct drm_file *file_priv)
 395 {
 396         drm_i915_private_t *dev_priv = dev->dev_private;
 397         drm_i915_irq_wait_t *irqwait = data;
 398
 399         if (!dev_priv) {
 400                 DRM_ERROR("called with no initialization\n");
 401                 return -EINVAL;
 402         }
 403
 404         return i915_wait_irq(dev, irqwait->irq_seq);
 405 }
 406
 407 /* Called from drm generic code, passed 'crtc' which
 408  * we use as a pipe index
 409  */
 410 int i915_enable_vblank(struct drm_device *dev, int pipe)
 411 {
 412         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 413         unsigned long irqflags;
 414         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 415         u32 pipeconf;
 416
 417         pipeconf = I915_READ(pipeconf_reg);
 418         if (!(pipeconf & PIPEACONF_ENABLE))
 419                 return -EINVAL;
 420
 421         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 422         if (IS_I965G(dev))
 423                 i915_enable_pipestat(dev_priv, pipe,
 424                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 425         else
 426                 i915_enable_pipestat(dev_priv, pipe,
 427                                      PIPE_VBLANK_INTERRUPT_ENABLE);
 428         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 429         return 0;
 430 }
 431
 432 /* Called from drm generic code, passed 'crtc' which
 433  * we use as a pipe index
 434  */
 435 void i915_disable_vblank(struct drm_device *dev, int pipe)
 436 {
 437         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 438         unsigned long irqflags;
 439
 440         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 441         i915_disable_pipestat(dev_priv, pipe,
 442                               PIPE_VBLANK_INTERRUPT_ENABLE |
 443                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
 444         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 445 }
 446
 447 void i915_enable_interrupt (struct drm_device *dev)
 448 {
 449         struct drm_i915_private *dev_priv = dev->dev_private;
 450         opregion_enable_asle(dev);
 451         dev_priv->irq_enabled = 1;
 452 }
 453
 454
 455 /* Set the vblank monitor pipe
 456  */
 457 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 458                          struct drm_file *file_priv)
 459 {
 460         drm_i915_private_t *dev_priv = dev->dev_private;
 461
 462         if (!dev_priv) {
 463                 DRM_ERROR("called with no initialization\n");
 464                 return -EINVAL;
 465         }
 466
 467         return 0;
 468 }
 469
 470 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 471                          struct drm_file *file_priv)
 472 {
 473         drm_i915_private_t *dev_priv = dev->dev_private;
 474         drm_i915_vblank_pipe_t *pipe = data;
 475
 476         if (!dev_priv) {
 477                 DRM_ERROR("called with no initialization\n");
 478                 return -EINVAL;
 479         }
 480
 481         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 482
 483         return 0;
 484 }
 485
 486 /**
 487  * Schedule buffer swap at given vertical blank.
 488  */
 489 int i915_vblank_swap(struct drm_device *dev, void *data,
 490                      struct drm_file *file_priv)
 491 {
 492         /* The delayed swap mechanism was fundamentally racy, and has been
 493          * removed.  The model was that the client requested a delayed flip/swap
 494          * from the kernel, then waited for vblank before continuing to perform
 495          * rendering.  The problem was that the kernel might wake the client
 496          * up before it dispatched the vblank swap (since the lock has to be
 497          * held while touching the ringbuffer), in which case the client would
 498          * clear and start the next frame before the swap occurred, and
 499          * flicker would occur in addition to likely missing the vblank.
 500          *
 501          * In the absence of this ioctl, userland falls back to a correct path
 502          * of waiting for a vblank, then dispatching the swap on its own.
 503          * Context switching to userland and back is plenty fast enough for
 504          * meeting the requirements of vblank swapping.
 505          */
 506         return -EINVAL;
 507 }
 508
 509 /* drm_dma.h hooks
 510 */
 511 void i915_driver_irq_preinstall(struct drm_device * dev)
 512 {
 513         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 514
 515         atomic_set(&dev_priv->irq_received, 0);
 516
 517         I915_WRITE(HWSTAM, 0xeffe);
 518         I915_WRITE(PIPEASTAT, 0);
 519         I915_WRITE(PIPEBSTAT, 0);
 520         I915_WRITE(IMR, 0xffffffff);
 521         I915_WRITE(IER, 0x0);
 522         (void) I915_READ(IER);
 523 }
 524
 525 int i915_driver_irq_postinstall(struct drm_device *dev)
 526 {
 527         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 528
 529         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 530
 531         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 532
 533         /* Unmask the interrupts that we always want on. */
 534         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
 535
 536         dev_priv->pipestat[0] = 0;
 537         dev_priv->pipestat[1] = 0;
 538
 539         /* Disable pipe interrupt enables, clear pending pipe status */
 540         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 541         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 542         /* Clear pending interrupt status */
 543         I915_WRITE(IIR, I915_READ(IIR));
 544
 545         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
 546         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 547         (void) I915_READ(IER);
 548
 549         opregion_enable_asle(dev);
 550         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
 551
 552         return 0;
 553 }
 554
 555 void i915_driver_irq_uninstall(struct drm_device * dev)
 556 {
 557         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 558
 559         if (!dev_priv)
 560                 return;
 561
 562         dev_priv->vblank_pipe = 0;
 563
 564         I915_WRITE(HWSTAM, 0xffffffff);
 565         I915_WRITE(PIPEASTAT, 0);
 566         I915_WRITE(PIPEBSTAT, 0);
 567         I915_WRITE(IMR, 0xffffffff);
 568         I915_WRITE(IER, 0x0);
 569
 570         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 571         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 572         I915_WRITE(IIR, I915_READ(IIR));
 573 }