2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "intel_drv.h"
33 #include <linux/swap.h>
34 #include <linux/pci.h>
36 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51 static int i915_gem_evict_something(struct drm_device *dev);
52 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
53 struct drm_i915_gem_pwrite *args,
54 struct drm_file *file_priv);
56 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
59 drm_i915_private_t *dev_priv = dev->dev_private;
62 (start & (PAGE_SIZE - 1)) != 0 ||
63 (end & (PAGE_SIZE - 1)) != 0) {
67 drm_mm_init(&dev_priv->mm.gtt_space, start,
70 dev->gtt_total = (uint32_t) (end - start);
76 i915_gem_init_ioctl(struct drm_device *dev, void *data,
77 struct drm_file *file_priv)
79 struct drm_i915_gem_init *args = data;
82 mutex_lock(&dev->struct_mutex);
83 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
84 mutex_unlock(&dev->struct_mutex);
90 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
91 struct drm_file *file_priv)
93 struct drm_i915_gem_get_aperture *args = data;
95 if (!(dev->driver->driver_features & DRIVER_GEM))
98 args->aper_size = dev->gtt_total;
99 args->aper_available_size = (args->aper_size -
100 atomic_read(&dev->pin_memory));
107 * Creates a new mm object and returns a handle to it.
110 i915_gem_create_ioctl(struct drm_device *dev, void *data,
111 struct drm_file *file_priv)
113 struct drm_i915_gem_create *args = data;
114 struct drm_gem_object *obj;
118 args->size = roundup(args->size, PAGE_SIZE);
120 /* Allocate the new object */
121 obj = drm_gem_object_alloc(dev, args->size);
125 ret = drm_gem_handle_create(file_priv, obj, &handle);
126 mutex_lock(&dev->struct_mutex);
127 drm_gem_object_handle_unreference(obj);
128 mutex_unlock(&dev->struct_mutex);
133 args->handle = handle;
139 fast_shmem_read(struct page **pages,
140 loff_t page_base, int page_offset,
147 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
150 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
151 kunmap_atomic(vaddr, KM_USER0);
159 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
161 drm_i915_private_t *dev_priv = obj->dev->dev_private;
162 struct drm_i915_gem_object *obj_priv = obj->driver_private;
164 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
165 obj_priv->tiling_mode != I915_TILING_NONE;
169 slow_shmem_copy(struct page *dst_page,
171 struct page *src_page,
175 char *dst_vaddr, *src_vaddr;
177 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
178 if (dst_vaddr == NULL)
181 src_vaddr = kmap_atomic(src_page, KM_USER1);
182 if (src_vaddr == NULL) {
183 kunmap_atomic(dst_vaddr, KM_USER0);
187 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
189 kunmap_atomic(src_vaddr, KM_USER1);
190 kunmap_atomic(dst_vaddr, KM_USER0);
196 slow_shmem_bit17_copy(struct page *gpu_page,
198 struct page *cpu_page,
203 char *gpu_vaddr, *cpu_vaddr;
205 /* Use the unswizzled path if this page isn't affected. */
206 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
208 return slow_shmem_copy(cpu_page, cpu_offset,
209 gpu_page, gpu_offset, length);
211 return slow_shmem_copy(gpu_page, gpu_offset,
212 cpu_page, cpu_offset, length);
215 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
216 if (gpu_vaddr == NULL)
219 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
220 if (cpu_vaddr == NULL) {
221 kunmap_atomic(gpu_vaddr, KM_USER0);
225 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
226 * XORing with the other bits (A9 for Y, A9 and A10 for X)
229 int cacheline_end = ALIGN(gpu_offset + 1, 64);
230 int this_length = min(cacheline_end - gpu_offset, length);
231 int swizzled_gpu_offset = gpu_offset ^ 64;
234 memcpy(cpu_vaddr + cpu_offset,
235 gpu_vaddr + swizzled_gpu_offset,
238 memcpy(gpu_vaddr + swizzled_gpu_offset,
239 cpu_vaddr + cpu_offset,
242 cpu_offset += this_length;
243 gpu_offset += this_length;
244 length -= this_length;
247 kunmap_atomic(cpu_vaddr, KM_USER1);
248 kunmap_atomic(gpu_vaddr, KM_USER0);
254 * This is the fast shmem pread path, which attempts to copy_from_user directly
255 * from the backing pages of the object to the user's address space. On a
256 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
259 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
260 struct drm_i915_gem_pread *args,
261 struct drm_file *file_priv)
263 struct drm_i915_gem_object *obj_priv = obj->driver_private;
265 loff_t offset, page_base;
266 char __user *user_data;
267 int page_offset, page_length;
270 user_data = (char __user *) (uintptr_t) args->data_ptr;
273 mutex_lock(&dev->struct_mutex);
275 ret = i915_gem_object_get_pages(obj);
279 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
284 obj_priv = obj->driver_private;
285 offset = args->offset;
288 /* Operation in this page
290 * page_base = page offset within aperture
291 * page_offset = offset within page
292 * page_length = bytes to copy for this page
294 page_base = (offset & ~(PAGE_SIZE-1));
295 page_offset = offset & (PAGE_SIZE-1);
296 page_length = remain;
297 if ((page_offset + remain) > PAGE_SIZE)
298 page_length = PAGE_SIZE - page_offset;
300 ret = fast_shmem_read(obj_priv->pages,
301 page_base, page_offset,
302 user_data, page_length);
306 remain -= page_length;
307 user_data += page_length;
308 offset += page_length;
312 i915_gem_object_put_pages(obj);
314 mutex_unlock(&dev->struct_mutex);
320 * This is the fallback shmem pread path, which allocates temporary storage
321 * in kernel space to copy_to_user into outside of the struct_mutex, so we
322 * can copy out of the object's backing pages while holding the struct mutex
323 * and not take page faults.
326 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
327 struct drm_i915_gem_pread *args,
328 struct drm_file *file_priv)
330 struct drm_i915_gem_object *obj_priv = obj->driver_private;
331 struct mm_struct *mm = current->mm;
332 struct page **user_pages;
334 loff_t offset, pinned_pages, i;
335 loff_t first_data_page, last_data_page, num_pages;
336 int shmem_page_index, shmem_page_offset;
337 int data_page_index, data_page_offset;
340 uint64_t data_ptr = args->data_ptr;
341 int do_bit17_swizzling;
345 /* Pin the user pages containing the data. We can't fault while
346 * holding the struct mutex, yet we want to hold it while
347 * dereferencing the user data.
349 first_data_page = data_ptr / PAGE_SIZE;
350 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
351 num_pages = last_data_page - first_data_page + 1;
353 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
354 if (user_pages == NULL)
357 down_read(&mm->mmap_sem);
358 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
359 num_pages, 1, 0, user_pages, NULL);
360 up_read(&mm->mmap_sem);
361 if (pinned_pages < num_pages) {
363 goto fail_put_user_pages;
366 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
368 mutex_lock(&dev->struct_mutex);
370 ret = i915_gem_object_get_pages(obj);
374 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
379 obj_priv = obj->driver_private;
380 offset = args->offset;
383 /* Operation in this page
385 * shmem_page_index = page number within shmem file
386 * shmem_page_offset = offset within page in shmem file
387 * data_page_index = page number in get_user_pages return
388 * data_page_offset = offset with data_page_index page.
389 * page_length = bytes to copy for this page
391 shmem_page_index = offset / PAGE_SIZE;
392 shmem_page_offset = offset & ~PAGE_MASK;
393 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
394 data_page_offset = data_ptr & ~PAGE_MASK;
396 page_length = remain;
397 if ((shmem_page_offset + page_length) > PAGE_SIZE)
398 page_length = PAGE_SIZE - shmem_page_offset;
399 if ((data_page_offset + page_length) > PAGE_SIZE)
400 page_length = PAGE_SIZE - data_page_offset;
402 if (do_bit17_swizzling) {
403 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
405 user_pages[data_page_index],
410 ret = slow_shmem_copy(user_pages[data_page_index],
412 obj_priv->pages[shmem_page_index],
419 remain -= page_length;
420 data_ptr += page_length;
421 offset += page_length;
425 i915_gem_object_put_pages(obj);
427 mutex_unlock(&dev->struct_mutex);
429 for (i = 0; i < pinned_pages; i++) {
430 SetPageDirty(user_pages[i]);
431 page_cache_release(user_pages[i]);
433 drm_free_large(user_pages);
439 * Reads data from the object referenced by handle.
441 * On error, the contents of *data are undefined.
444 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
445 struct drm_file *file_priv)
447 struct drm_i915_gem_pread *args = data;
448 struct drm_gem_object *obj;
449 struct drm_i915_gem_object *obj_priv;
452 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
455 obj_priv = obj->driver_private;
457 /* Bounds check source.
459 * XXX: This could use review for overflow issues...
461 if (args->offset > obj->size || args->size > obj->size ||
462 args->offset + args->size > obj->size) {
463 drm_gem_object_unreference(obj);
467 if (i915_gem_object_needs_bit17_swizzle(obj)) {
468 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
470 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
472 ret = i915_gem_shmem_pread_slow(dev, obj, args,
476 drm_gem_object_unreference(obj);
481 /* This is the fast write path which cannot handle
482 * page faults in the source data
486 fast_user_write(struct io_mapping *mapping,
487 loff_t page_base, int page_offset,
488 char __user *user_data,
492 unsigned long unwritten;
494 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
495 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
497 io_mapping_unmap_atomic(vaddr_atomic);
503 /* Here's the write path which can sleep for
508 slow_kernel_write(struct io_mapping *mapping,
509 loff_t gtt_base, int gtt_offset,
510 struct page *user_page, int user_offset,
513 char *src_vaddr, *dst_vaddr;
514 unsigned long unwritten;
516 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
517 src_vaddr = kmap_atomic(user_page, KM_USER1);
518 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
519 src_vaddr + user_offset,
521 kunmap_atomic(src_vaddr, KM_USER1);
522 io_mapping_unmap_atomic(dst_vaddr);
529 fast_shmem_write(struct page **pages,
530 loff_t page_base, int page_offset,
535 unsigned long unwritten;
537 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
540 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
541 kunmap_atomic(vaddr, KM_USER0);
549 * This is the fast pwrite path, where we copy the data directly from the
550 * user into the GTT, uncached.
553 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
554 struct drm_i915_gem_pwrite *args,
555 struct drm_file *file_priv)
557 struct drm_i915_gem_object *obj_priv = obj->driver_private;
558 drm_i915_private_t *dev_priv = dev->dev_private;
560 loff_t offset, page_base;
561 char __user *user_data;
562 int page_offset, page_length;
565 user_data = (char __user *) (uintptr_t) args->data_ptr;
567 if (!access_ok(VERIFY_READ, user_data, remain))
571 mutex_lock(&dev->struct_mutex);
572 ret = i915_gem_object_pin(obj, 0);
574 mutex_unlock(&dev->struct_mutex);
577 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
581 obj_priv = obj->driver_private;
582 offset = obj_priv->gtt_offset + args->offset;
585 /* Operation in this page
587 * page_base = page offset within aperture
588 * page_offset = offset within page
589 * page_length = bytes to copy for this page
591 page_base = (offset & ~(PAGE_SIZE-1));
592 page_offset = offset & (PAGE_SIZE-1);
593 page_length = remain;
594 if ((page_offset + remain) > PAGE_SIZE)
595 page_length = PAGE_SIZE - page_offset;
597 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
598 page_offset, user_data, page_length);
600 /* If we get a fault while copying data, then (presumably) our
601 * source page isn't available. Return the error and we'll
602 * retry in the slow path.
607 remain -= page_length;
608 user_data += page_length;
609 offset += page_length;
613 i915_gem_object_unpin(obj);
614 mutex_unlock(&dev->struct_mutex);
620 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
621 * the memory and maps it using kmap_atomic for copying.
623 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
624 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
627 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
628 struct drm_i915_gem_pwrite *args,
629 struct drm_file *file_priv)
631 struct drm_i915_gem_object *obj_priv = obj->driver_private;
632 drm_i915_private_t *dev_priv = dev->dev_private;
634 loff_t gtt_page_base, offset;
635 loff_t first_data_page, last_data_page, num_pages;
636 loff_t pinned_pages, i;
637 struct page **user_pages;
638 struct mm_struct *mm = current->mm;
639 int gtt_page_offset, data_page_offset, data_page_index, page_length;
641 uint64_t data_ptr = args->data_ptr;
645 /* Pin the user pages containing the data. We can't fault while
646 * holding the struct mutex, and all of the pwrite implementations
647 * want to hold it while dereferencing the user data.
649 first_data_page = data_ptr / PAGE_SIZE;
650 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
651 num_pages = last_data_page - first_data_page + 1;
653 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
654 if (user_pages == NULL)
657 down_read(&mm->mmap_sem);
658 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
659 num_pages, 0, 0, user_pages, NULL);
660 up_read(&mm->mmap_sem);
661 if (pinned_pages < num_pages) {
663 goto out_unpin_pages;
666 mutex_lock(&dev->struct_mutex);
667 ret = i915_gem_object_pin(obj, 0);
671 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673 goto out_unpin_object;
675 obj_priv = obj->driver_private;
676 offset = obj_priv->gtt_offset + args->offset;
679 /* Operation in this page
681 * gtt_page_base = page offset within aperture
682 * gtt_page_offset = offset within page in aperture
683 * data_page_index = page number in get_user_pages return
684 * data_page_offset = offset with data_page_index page.
685 * page_length = bytes to copy for this page
687 gtt_page_base = offset & PAGE_MASK;
688 gtt_page_offset = offset & ~PAGE_MASK;
689 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
690 data_page_offset = data_ptr & ~PAGE_MASK;
692 page_length = remain;
693 if ((gtt_page_offset + page_length) > PAGE_SIZE)
694 page_length = PAGE_SIZE - gtt_page_offset;
695 if ((data_page_offset + page_length) > PAGE_SIZE)
696 page_length = PAGE_SIZE - data_page_offset;
698 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
699 gtt_page_base, gtt_page_offset,
700 user_pages[data_page_index],
704 /* If we get a fault while copying data, then (presumably) our
705 * source page isn't available. Return the error and we'll
706 * retry in the slow path.
709 goto out_unpin_object;
711 remain -= page_length;
712 offset += page_length;
713 data_ptr += page_length;
717 i915_gem_object_unpin(obj);
719 mutex_unlock(&dev->struct_mutex);
721 for (i = 0; i < pinned_pages; i++)
722 page_cache_release(user_pages[i]);
723 drm_free_large(user_pages);
729 * This is the fast shmem pwrite path, which attempts to directly
730 * copy_from_user into the kmapped pages backing the object.
733 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
734 struct drm_i915_gem_pwrite *args,
735 struct drm_file *file_priv)
737 struct drm_i915_gem_object *obj_priv = obj->driver_private;
739 loff_t offset, page_base;
740 char __user *user_data;
741 int page_offset, page_length;
744 user_data = (char __user *) (uintptr_t) args->data_ptr;
747 mutex_lock(&dev->struct_mutex);
749 ret = i915_gem_object_get_pages(obj);
753 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
757 obj_priv = obj->driver_private;
758 offset = args->offset;
762 /* Operation in this page
764 * page_base = page offset within aperture
765 * page_offset = offset within page
766 * page_length = bytes to copy for this page
768 page_base = (offset & ~(PAGE_SIZE-1));
769 page_offset = offset & (PAGE_SIZE-1);
770 page_length = remain;
771 if ((page_offset + remain) > PAGE_SIZE)
772 page_length = PAGE_SIZE - page_offset;
774 ret = fast_shmem_write(obj_priv->pages,
775 page_base, page_offset,
776 user_data, page_length);
780 remain -= page_length;
781 user_data += page_length;
782 offset += page_length;
786 i915_gem_object_put_pages(obj);
788 mutex_unlock(&dev->struct_mutex);
794 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
795 * the memory and maps it using kmap_atomic for copying.
797 * This avoids taking mmap_sem for faulting on the user's address while the
798 * struct_mutex is held.
801 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
802 struct drm_i915_gem_pwrite *args,
803 struct drm_file *file_priv)
805 struct drm_i915_gem_object *obj_priv = obj->driver_private;
806 struct mm_struct *mm = current->mm;
807 struct page **user_pages;
809 loff_t offset, pinned_pages, i;
810 loff_t first_data_page, last_data_page, num_pages;
811 int shmem_page_index, shmem_page_offset;
812 int data_page_index, data_page_offset;
815 uint64_t data_ptr = args->data_ptr;
816 int do_bit17_swizzling;
820 /* Pin the user pages containing the data. We can't fault while
821 * holding the struct mutex, and all of the pwrite implementations
822 * want to hold it while dereferencing the user data.
824 first_data_page = data_ptr / PAGE_SIZE;
825 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
826 num_pages = last_data_page - first_data_page + 1;
828 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
829 if (user_pages == NULL)
832 down_read(&mm->mmap_sem);
833 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
834 num_pages, 0, 0, user_pages, NULL);
835 up_read(&mm->mmap_sem);
836 if (pinned_pages < num_pages) {
838 goto fail_put_user_pages;
841 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
843 mutex_lock(&dev->struct_mutex);
845 ret = i915_gem_object_get_pages(obj);
849 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
853 obj_priv = obj->driver_private;
854 offset = args->offset;
858 /* Operation in this page
860 * shmem_page_index = page number within shmem file
861 * shmem_page_offset = offset within page in shmem file
862 * data_page_index = page number in get_user_pages return
863 * data_page_offset = offset with data_page_index page.
864 * page_length = bytes to copy for this page
866 shmem_page_index = offset / PAGE_SIZE;
867 shmem_page_offset = offset & ~PAGE_MASK;
868 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
869 data_page_offset = data_ptr & ~PAGE_MASK;
871 page_length = remain;
872 if ((shmem_page_offset + page_length) > PAGE_SIZE)
873 page_length = PAGE_SIZE - shmem_page_offset;
874 if ((data_page_offset + page_length) > PAGE_SIZE)
875 page_length = PAGE_SIZE - data_page_offset;
877 if (do_bit17_swizzling) {
878 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
880 user_pages[data_page_index],
885 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
887 user_pages[data_page_index],
894 remain -= page_length;
895 data_ptr += page_length;
896 offset += page_length;
900 i915_gem_object_put_pages(obj);
902 mutex_unlock(&dev->struct_mutex);
904 for (i = 0; i < pinned_pages; i++)
905 page_cache_release(user_pages[i]);
906 drm_free_large(user_pages);
912 * Writes data to the object referenced by handle.
914 * On error, the contents of the buffer that were to be modified are undefined.
917 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
918 struct drm_file *file_priv)
920 struct drm_i915_gem_pwrite *args = data;
921 struct drm_gem_object *obj;
922 struct drm_i915_gem_object *obj_priv;
925 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
928 obj_priv = obj->driver_private;
930 /* Bounds check destination.
932 * XXX: This could use review for overflow issues...
934 if (args->offset > obj->size || args->size > obj->size ||
935 args->offset + args->size > obj->size) {
936 drm_gem_object_unreference(obj);
940 /* We can only do the GTT pwrite on untiled buffers, as otherwise
941 * it would end up going through the fenced access, and we'll get
942 * different detiling behavior between reading and writing.
943 * pread/pwrite currently are reading and writing from the CPU
944 * perspective, requiring manual detiling by the client.
946 if (obj_priv->phys_obj)
947 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
948 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
949 dev->gtt_total != 0) {
950 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
951 if (ret == -EFAULT) {
952 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
955 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
956 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
958 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
959 if (ret == -EFAULT) {
960 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
967 DRM_INFO("pwrite failed %d\n", ret);
970 drm_gem_object_unreference(obj);
976 * Called when user space prepares to use an object with the CPU, either
977 * through the mmap ioctl's mapping or a GTT mapping.
980 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
981 struct drm_file *file_priv)
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct drm_i915_gem_set_domain *args = data;
985 struct drm_gem_object *obj;
986 struct drm_i915_gem_object *obj_priv;
987 uint32_t read_domains = args->read_domains;
988 uint32_t write_domain = args->write_domain;
991 if (!(dev->driver->driver_features & DRIVER_GEM))
994 /* Only handle setting domains to types used by the CPU. */
995 if (write_domain & I915_GEM_GPU_DOMAINS)
998 if (read_domains & I915_GEM_GPU_DOMAINS)
1001 /* Having something in the write domain implies it's in the read
1002 * domain, and only that read domain. Enforce that in the request.
1004 if (write_domain != 0 && read_domains != write_domain)
1007 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1010 obj_priv = obj->driver_private;
1012 mutex_lock(&dev->struct_mutex);
1014 intel_mark_busy(dev, obj);
1017 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1018 obj, obj->size, read_domains, write_domain);
1020 if (read_domains & I915_GEM_DOMAIN_GTT) {
1021 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1023 /* Update the LRU on the fence for the CPU access that's
1026 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1027 list_move_tail(&obj_priv->fence_list,
1028 &dev_priv->mm.fence_list);
1031 /* Silently promote "you're not bound, there was nothing to do"
1032 * to success, since the client was just asking us to
1033 * make sure everything was done.
1038 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1041 drm_gem_object_unreference(obj);
1042 mutex_unlock(&dev->struct_mutex);
1047 * Called when user space has done writes to this buffer
1050 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv)
1053 struct drm_i915_gem_sw_finish *args = data;
1054 struct drm_gem_object *obj;
1055 struct drm_i915_gem_object *obj_priv;
1058 if (!(dev->driver->driver_features & DRIVER_GEM))
1061 mutex_lock(&dev->struct_mutex);
1062 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1064 mutex_unlock(&dev->struct_mutex);
1069 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1070 __func__, args->handle, obj, obj->size);
1072 obj_priv = obj->driver_private;
1074 /* Pinned buffers may be scanout, so flush the cache */
1075 if (obj_priv->pin_count)
1076 i915_gem_object_flush_cpu_write_domain(obj);
1078 drm_gem_object_unreference(obj);
1079 mutex_unlock(&dev->struct_mutex);
1084 * Maps the contents of an object, returning the address it is mapped
1087 * While the mapping holds a reference on the contents of the object, it doesn't
1088 * imply a ref on the object itself.
1091 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1092 struct drm_file *file_priv)
1094 struct drm_i915_gem_mmap *args = data;
1095 struct drm_gem_object *obj;
1099 if (!(dev->driver->driver_features & DRIVER_GEM))
1102 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1106 offset = args->offset;
1108 down_write(¤t->mm->mmap_sem);
1109 addr = do_mmap(obj->filp, 0, args->size,
1110 PROT_READ | PROT_WRITE, MAP_SHARED,
1112 up_write(¤t->mm->mmap_sem);
1113 mutex_lock(&dev->struct_mutex);
1114 drm_gem_object_unreference(obj);
1115 mutex_unlock(&dev->struct_mutex);
1116 if (IS_ERR((void *)addr))
1119 args->addr_ptr = (uint64_t) addr;
1125 * i915_gem_fault - fault a page into the GTT
1126 * vma: VMA in question
1129 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1130 * from userspace. The fault handler takes care of binding the object to
1131 * the GTT (if needed), allocating and programming a fence register (again,
1132 * only if needed based on whether the old reg is still valid or the object
1133 * is tiled) and inserting a new PTE into the faulting process.
1135 * Note that the faulting process may involve evicting existing objects
1136 * from the GTT and/or fence registers to make room. So performance may
1137 * suffer if the GTT working set is large or there are few fence registers
1140 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1142 struct drm_gem_object *obj = vma->vm_private_data;
1143 struct drm_device *dev = obj->dev;
1144 struct drm_i915_private *dev_priv = dev->dev_private;
1145 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1146 pgoff_t page_offset;
1149 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1151 /* We don't use vmf->pgoff since that has the fake offset */
1152 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1155 /* Now bind it into the GTT if needed */
1156 mutex_lock(&dev->struct_mutex);
1157 if (!obj_priv->gtt_space) {
1158 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1160 mutex_unlock(&dev->struct_mutex);
1161 return VM_FAULT_SIGBUS;
1163 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1165 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1167 mutex_unlock(&dev->struct_mutex);
1168 return VM_FAULT_SIGBUS;
1172 /* Need a new fence register? */
1173 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1174 ret = i915_gem_object_get_fence_reg(obj);
1176 mutex_unlock(&dev->struct_mutex);
1177 return VM_FAULT_SIGBUS;
1181 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1184 /* Finally, remap it using the new GTT offset */
1185 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1187 mutex_unlock(&dev->struct_mutex);
1192 return VM_FAULT_OOM;
1195 return VM_FAULT_SIGBUS;
1197 return VM_FAULT_NOPAGE;
1202 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1203 * @obj: obj in question
1205 * GEM memory mapping works by handing back to userspace a fake mmap offset
1206 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1207 * up the object based on the offset and sets up the various memory mapping
1210 * This routine allocates and attaches a fake offset for @obj.
1213 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1215 struct drm_device *dev = obj->dev;
1216 struct drm_gem_mm *mm = dev->mm_private;
1217 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1218 struct drm_map_list *list;
1219 struct drm_local_map *map;
1222 /* Set the object up for mmap'ing */
1223 list = &obj->map_list;
1224 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1229 map->type = _DRM_GEM;
1230 map->size = obj->size;
1233 /* Get a DRM GEM mmap offset allocated... */
1234 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1235 obj->size / PAGE_SIZE, 0, 0);
1236 if (!list->file_offset_node) {
1237 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1242 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1243 obj->size / PAGE_SIZE, 0);
1244 if (!list->file_offset_node) {
1249 list->hash.key = list->file_offset_node->start;
1250 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1251 DRM_ERROR("failed to add to map hash\n");
1255 /* By now we should be all set, any drm_mmap request on the offset
1256 * below will get to our mmap & fault handler */
1257 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1262 drm_mm_put_block(list->file_offset_node);
1270 * i915_gem_release_mmap - remove physical page mappings
1271 * @obj: obj in question
1273 * Preserve the reservation of the mmaping with the DRM core code, but
1274 * relinquish ownership of the pages back to the system.
1276 * It is vital that we remove the page mapping if we have mapped a tiled
1277 * object through the GTT and then lose the fence register due to
1278 * resource pressure. Similarly if the object has been moved out of the
1279 * aperture, than pages mapped into userspace must be revoked. Removing the
1280 * mapping will then trigger a page fault on the next user access, allowing
1281 * fixup by i915_gem_fault().
1284 i915_gem_release_mmap(struct drm_gem_object *obj)
1286 struct drm_device *dev = obj->dev;
1287 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1289 if (dev->dev_mapping)
1290 unmap_mapping_range(dev->dev_mapping,
1291 obj_priv->mmap_offset, obj->size, 1);
1295 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1297 struct drm_device *dev = obj->dev;
1298 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1299 struct drm_gem_mm *mm = dev->mm_private;
1300 struct drm_map_list *list;
1302 list = &obj->map_list;
1303 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1305 if (list->file_offset_node) {
1306 drm_mm_put_block(list->file_offset_node);
1307 list->file_offset_node = NULL;
1315 obj_priv->mmap_offset = 0;
1319 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1320 * @obj: object to check
1322 * Return the required GTT alignment for an object, taking into account
1323 * potential fence register mapping if needed.
1326 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1328 struct drm_device *dev = obj->dev;
1329 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1333 * Minimum alignment is 4k (GTT page size), but might be greater
1334 * if a fence register is needed for the object.
1336 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1340 * Previous chips need to be aligned to the size of the smallest
1341 * fence register that can contain the object.
1348 for (i = start; i < obj->size; i <<= 1)
1355 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1357 * @data: GTT mapping ioctl data
1358 * @file_priv: GEM object info
1360 * Simply returns the fake offset to userspace so it can mmap it.
1361 * The mmap call will end up in drm_gem_mmap(), which will set things
1362 * up so we can get faults in the handler above.
1364 * The fault handler will take care of binding the object into the GTT
1365 * (since it may have been evicted to make room for something), allocating
1366 * a fence register, and mapping the appropriate aperture address into
1370 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1371 struct drm_file *file_priv)
1373 struct drm_i915_gem_mmap_gtt *args = data;
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 struct drm_gem_object *obj;
1376 struct drm_i915_gem_object *obj_priv;
1379 if (!(dev->driver->driver_features & DRIVER_GEM))
1382 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1386 mutex_lock(&dev->struct_mutex);
1388 obj_priv = obj->driver_private;
1390 if (!obj_priv->mmap_offset) {
1391 ret = i915_gem_create_mmap_offset(obj);
1393 drm_gem_object_unreference(obj);
1394 mutex_unlock(&dev->struct_mutex);
1399 args->offset = obj_priv->mmap_offset;
1401 obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
1403 /* Make sure the alignment is correct for fence regs etc */
1404 if (obj_priv->agp_mem &&
1405 (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
1406 drm_gem_object_unreference(obj);
1407 mutex_unlock(&dev->struct_mutex);
1412 * Pull it into the GTT so that we have a page list (makes the
1413 * initial fault faster and any subsequent flushing possible).
1415 if (!obj_priv->agp_mem) {
1416 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1418 drm_gem_object_unreference(obj);
1419 mutex_unlock(&dev->struct_mutex);
1422 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1425 drm_gem_object_unreference(obj);
1426 mutex_unlock(&dev->struct_mutex);
1432 i915_gem_object_put_pages(struct drm_gem_object *obj)
1434 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1435 int page_count = obj->size / PAGE_SIZE;
1438 BUG_ON(obj_priv->pages_refcount == 0);
1440 if (--obj_priv->pages_refcount != 0)
1443 if (obj_priv->tiling_mode != I915_TILING_NONE)
1444 i915_gem_object_save_bit_17_swizzle(obj);
1446 for (i = 0; i < page_count; i++)
1447 if (obj_priv->pages[i] != NULL) {
1448 if (obj_priv->dirty)
1449 set_page_dirty(obj_priv->pages[i]);
1450 mark_page_accessed(obj_priv->pages[i]);
1451 page_cache_release(obj_priv->pages[i]);
1453 obj_priv->dirty = 0;
1455 drm_free_large(obj_priv->pages);
1456 obj_priv->pages = NULL;
1460 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1462 struct drm_device *dev = obj->dev;
1463 drm_i915_private_t *dev_priv = dev->dev_private;
1464 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1466 /* Add a reference if we're newly entering the active list. */
1467 if (!obj_priv->active) {
1468 drm_gem_object_reference(obj);
1469 obj_priv->active = 1;
1471 /* Move from whatever list we were on to the tail of execution. */
1472 spin_lock(&dev_priv->mm.active_list_lock);
1473 list_move_tail(&obj_priv->list,
1474 &dev_priv->mm.active_list);
1475 spin_unlock(&dev_priv->mm.active_list_lock);
1476 obj_priv->last_rendering_seqno = seqno;
1480 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1482 struct drm_device *dev = obj->dev;
1483 drm_i915_private_t *dev_priv = dev->dev_private;
1484 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1486 BUG_ON(!obj_priv->active);
1487 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1488 obj_priv->last_rendering_seqno = 0;
1492 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1494 struct drm_device *dev = obj->dev;
1495 drm_i915_private_t *dev_priv = dev->dev_private;
1496 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1498 i915_verify_inactive(dev, __FILE__, __LINE__);
1499 if (obj_priv->pin_count != 0)
1500 list_del_init(&obj_priv->list);
1502 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1504 obj_priv->last_rendering_seqno = 0;
1505 if (obj_priv->active) {
1506 obj_priv->active = 0;
1507 drm_gem_object_unreference(obj);
1509 i915_verify_inactive(dev, __FILE__, __LINE__);
1513 * Creates a new sequence number, emitting a write of it to the status page
1514 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1516 * Must be called with struct_lock held.
1518 * Returned sequence numbers are nonzero on success.
1521 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1522 uint32_t flush_domains)
1524 drm_i915_private_t *dev_priv = dev->dev_private;
1525 struct drm_i915_file_private *i915_file_priv = NULL;
1526 struct drm_i915_gem_request *request;
1531 if (file_priv != NULL)
1532 i915_file_priv = file_priv->driver_priv;
1534 request = kzalloc(sizeof(*request), GFP_KERNEL);
1535 if (request == NULL)
1538 /* Grab the seqno we're going to make this request be, and bump the
1539 * next (skipping 0 so it can be the reserved no-seqno value).
1541 seqno = dev_priv->mm.next_gem_seqno;
1542 dev_priv->mm.next_gem_seqno++;
1543 if (dev_priv->mm.next_gem_seqno == 0)
1544 dev_priv->mm.next_gem_seqno++;
1547 OUT_RING(MI_STORE_DWORD_INDEX);
1548 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1551 OUT_RING(MI_USER_INTERRUPT);
1554 DRM_DEBUG("%d\n", seqno);
1556 request->seqno = seqno;
1557 request->emitted_jiffies = jiffies;
1558 was_empty = list_empty(&dev_priv->mm.request_list);
1559 list_add_tail(&request->list, &dev_priv->mm.request_list);
1560 if (i915_file_priv) {
1561 list_add_tail(&request->client_list,
1562 &i915_file_priv->mm.request_list);
1564 INIT_LIST_HEAD(&request->client_list);
1567 /* Associate any objects on the flushing list matching the write
1568 * domain we're flushing with our flush.
1570 if (flush_domains != 0) {
1571 struct drm_i915_gem_object *obj_priv, *next;
1573 list_for_each_entry_safe(obj_priv, next,
1574 &dev_priv->mm.flushing_list, list) {
1575 struct drm_gem_object *obj = obj_priv->obj;
1577 if ((obj->write_domain & flush_domains) ==
1578 obj->write_domain) {
1579 obj->write_domain = 0;
1580 i915_gem_object_move_to_active(obj, seqno);
1586 if (!dev_priv->mm.suspended) {
1587 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1589 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1595 * Command execution barrier
1597 * Ensures that all commands in the ring are finished
1598 * before signalling the CPU
1601 i915_retire_commands(struct drm_device *dev)
1603 drm_i915_private_t *dev_priv = dev->dev_private;
1604 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1605 uint32_t flush_domains = 0;
1608 /* The sampler always gets flushed on i965 (sigh) */
1610 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1613 OUT_RING(0); /* noop */
1615 return flush_domains;
1619 * Moves buffers associated only with the given active seqno from the active
1620 * to inactive list, potentially freeing them.
1623 i915_gem_retire_request(struct drm_device *dev,
1624 struct drm_i915_gem_request *request)
1626 drm_i915_private_t *dev_priv = dev->dev_private;
1628 /* Move any buffers on the active list that are no longer referenced
1629 * by the ringbuffer to the flushing/inactive lists as appropriate.
1631 spin_lock(&dev_priv->mm.active_list_lock);
1632 while (!list_empty(&dev_priv->mm.active_list)) {
1633 struct drm_gem_object *obj;
1634 struct drm_i915_gem_object *obj_priv;
1636 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1637 struct drm_i915_gem_object,
1639 obj = obj_priv->obj;
1641 /* If the seqno being retired doesn't match the oldest in the
1642 * list, then the oldest in the list must still be newer than
1645 if (obj_priv->last_rendering_seqno != request->seqno)
1649 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1650 __func__, request->seqno, obj);
1653 if (obj->write_domain != 0)
1654 i915_gem_object_move_to_flushing(obj);
1656 /* Take a reference on the object so it won't be
1657 * freed while the spinlock is held. The list
1658 * protection for this spinlock is safe when breaking
1659 * the lock like this since the next thing we do
1660 * is just get the head of the list again.
1662 drm_gem_object_reference(obj);
1663 i915_gem_object_move_to_inactive(obj);
1664 spin_unlock(&dev_priv->mm.active_list_lock);
1665 drm_gem_object_unreference(obj);
1666 spin_lock(&dev_priv->mm.active_list_lock);
1670 spin_unlock(&dev_priv->mm.active_list_lock);
1674 * Returns true if seq1 is later than seq2.
1677 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1679 return (int32_t)(seq1 - seq2) >= 0;
1683 i915_get_gem_seqno(struct drm_device *dev)
1685 drm_i915_private_t *dev_priv = dev->dev_private;
1687 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1691 * This function clears the request list as sequence numbers are passed.
1694 i915_gem_retire_requests(struct drm_device *dev)
1696 drm_i915_private_t *dev_priv = dev->dev_private;
1699 if (!dev_priv->hw_status_page)
1702 seqno = i915_get_gem_seqno(dev);
1704 while (!list_empty(&dev_priv->mm.request_list)) {
1705 struct drm_i915_gem_request *request;
1706 uint32_t retiring_seqno;
1708 request = list_first_entry(&dev_priv->mm.request_list,
1709 struct drm_i915_gem_request,
1711 retiring_seqno = request->seqno;
1713 if (i915_seqno_passed(seqno, retiring_seqno) ||
1714 atomic_read(&dev_priv->mm.wedged)) {
1715 i915_gem_retire_request(dev, request);
1717 list_del(&request->list);
1718 list_del(&request->client_list);
1726 i915_gem_retire_work_handler(struct work_struct *work)
1728 drm_i915_private_t *dev_priv;
1729 struct drm_device *dev;
1731 dev_priv = container_of(work, drm_i915_private_t,
1732 mm.retire_work.work);
1733 dev = dev_priv->dev;
1735 mutex_lock(&dev->struct_mutex);
1736 i915_gem_retire_requests(dev);
1737 if (!dev_priv->mm.suspended &&
1738 !list_empty(&dev_priv->mm.request_list))
1739 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1740 mutex_unlock(&dev->struct_mutex);
1744 * Waits for a sequence number to be signaled, and cleans up the
1745 * request and object lists appropriately for that event.
1748 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1750 drm_i915_private_t *dev_priv = dev->dev_private;
1756 if (atomic_read(&dev_priv->mm.wedged))
1759 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1761 ier = I915_READ(DEIER) | I915_READ(GTIER);
1763 ier = I915_READ(IER);
1765 DRM_ERROR("something (likely vbetool) disabled "
1766 "interrupts, re-enabling\n");
1767 i915_driver_irq_preinstall(dev);
1768 i915_driver_irq_postinstall(dev);
1771 dev_priv->mm.waiting_gem_seqno = seqno;
1772 i915_user_irq_get(dev);
1773 ret = wait_event_interruptible(dev_priv->irq_queue,
1774 i915_seqno_passed(i915_get_gem_seqno(dev),
1776 atomic_read(&dev_priv->mm.wedged));
1777 i915_user_irq_put(dev);
1778 dev_priv->mm.waiting_gem_seqno = 0;
1780 if (atomic_read(&dev_priv->mm.wedged))
1783 if (ret && ret != -ERESTARTSYS)
1784 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1785 __func__, ret, seqno, i915_get_gem_seqno(dev));
1787 /* Directly dispatch request retiring. While we have the work queue
1788 * to handle this, the waiter on a request often wants an associated
1789 * buffer to have made it to the inactive list, and we would need
1790 * a separate wait queue to handle that.
1793 i915_gem_retire_requests(dev);
1799 i915_gem_flush(struct drm_device *dev,
1800 uint32_t invalidate_domains,
1801 uint32_t flush_domains)
1803 drm_i915_private_t *dev_priv = dev->dev_private;
1808 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1809 invalidate_domains, flush_domains);
1812 if (flush_domains & I915_GEM_DOMAIN_CPU)
1813 drm_agp_chipset_flush(dev);
1815 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1817 * read/write caches:
1819 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1820 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1821 * also flushed at 2d versus 3d pipeline switches.
1825 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1826 * MI_READ_FLUSH is set, and is always flushed on 965.
1828 * I915_GEM_DOMAIN_COMMAND may not exist?
1830 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1831 * invalidated when MI_EXE_FLUSH is set.
1833 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1834 * invalidated with every MI_FLUSH.
1838 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1839 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1840 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1841 * are flushed at any MI_FLUSH.
1844 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1845 if ((invalidate_domains|flush_domains) &
1846 I915_GEM_DOMAIN_RENDER)
1847 cmd &= ~MI_NO_WRITE_FLUSH;
1848 if (!IS_I965G(dev)) {
1850 * On the 965, the sampler cache always gets flushed
1851 * and this bit is reserved.
1853 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1854 cmd |= MI_READ_FLUSH;
1856 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1857 cmd |= MI_EXE_FLUSH;
1860 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1864 OUT_RING(0); /* noop */
1870 * Ensures that all rendering to the object has completed and the object is
1871 * safe to unbind from the GTT or access from the CPU.
1874 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1876 struct drm_device *dev = obj->dev;
1877 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1880 /* This function only exists to support waiting for existing rendering,
1881 * not for emitting required flushes.
1883 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1885 /* If there is rendering queued on the buffer being evicted, wait for
1888 if (obj_priv->active) {
1890 DRM_INFO("%s: object %p wait for seqno %08x\n",
1891 __func__, obj, obj_priv->last_rendering_seqno);
1893 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1902 * Unbinds an object from the GTT aperture.
1905 i915_gem_object_unbind(struct drm_gem_object *obj)
1907 struct drm_device *dev = obj->dev;
1908 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1912 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1913 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1915 if (obj_priv->gtt_space == NULL)
1918 if (obj_priv->pin_count != 0) {
1919 DRM_ERROR("Attempting to unbind pinned buffer\n");
1923 /* blow away mappings if mapped through GTT */
1924 i915_gem_release_mmap(obj);
1926 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1927 i915_gem_clear_fence_reg(obj);
1929 /* Move the object to the CPU domain to ensure that
1930 * any possible CPU writes while it's not in the GTT
1931 * are flushed when we go to remap it. This will
1932 * also ensure that all pending GPU writes are finished
1935 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1937 if (ret != -ERESTARTSYS)
1938 DRM_ERROR("set_domain failed: %d\n", ret);
1942 BUG_ON(obj_priv->active);
1944 if (obj_priv->agp_mem != NULL) {
1945 drm_unbind_agp(obj_priv->agp_mem);
1946 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1947 obj_priv->agp_mem = NULL;
1950 i915_gem_object_put_pages(obj);
1952 if (obj_priv->gtt_space) {
1953 atomic_dec(&dev->gtt_count);
1954 atomic_sub(obj->size, &dev->gtt_memory);
1956 drm_mm_put_block(obj_priv->gtt_space);
1957 obj_priv->gtt_space = NULL;
1960 /* Remove ourselves from the LRU list if present. */
1961 if (!list_empty(&obj_priv->list))
1962 list_del_init(&obj_priv->list);
1968 i915_gem_evict_something(struct drm_device *dev)
1970 drm_i915_private_t *dev_priv = dev->dev_private;
1971 struct drm_gem_object *obj;
1972 struct drm_i915_gem_object *obj_priv;
1976 /* If there's an inactive buffer available now, grab it
1979 if (!list_empty(&dev_priv->mm.inactive_list)) {
1980 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1981 struct drm_i915_gem_object,
1983 obj = obj_priv->obj;
1984 BUG_ON(obj_priv->pin_count != 0);
1986 DRM_INFO("%s: evicting %p\n", __func__, obj);
1988 BUG_ON(obj_priv->active);
1990 /* Wait on the rendering and unbind the buffer. */
1991 ret = i915_gem_object_unbind(obj);
1995 /* If we didn't get anything, but the ring is still processing
1996 * things, wait for one of those things to finish and hopefully
1997 * leave us a buffer to evict.
1999 if (!list_empty(&dev_priv->mm.request_list)) {
2000 struct drm_i915_gem_request *request;
2002 request = list_first_entry(&dev_priv->mm.request_list,
2003 struct drm_i915_gem_request,
2006 ret = i915_wait_request(dev, request->seqno);
2010 /* if waiting caused an object to become inactive,
2011 * then loop around and wait for it. Otherwise, we
2012 * assume that waiting freed and unbound something,
2013 * so there should now be some space in the GTT
2015 if (!list_empty(&dev_priv->mm.inactive_list))
2020 /* If we didn't have anything on the request list but there
2021 * are buffers awaiting a flush, emit one and try again.
2022 * When we wait on it, those buffers waiting for that flush
2023 * will get moved to inactive.
2025 if (!list_empty(&dev_priv->mm.flushing_list)) {
2026 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2027 struct drm_i915_gem_object,
2029 obj = obj_priv->obj;
2034 i915_add_request(dev, NULL, obj->write_domain);
2040 DRM_ERROR("inactive empty %d request empty %d "
2041 "flushing empty %d\n",
2042 list_empty(&dev_priv->mm.inactive_list),
2043 list_empty(&dev_priv->mm.request_list),
2044 list_empty(&dev_priv->mm.flushing_list));
2045 /* If we didn't do any of the above, there's nothing to be done
2046 * and we just can't fit it in.
2054 i915_gem_evict_everything(struct drm_device *dev)
2059 ret = i915_gem_evict_something(dev);
2069 i915_gem_object_get_pages(struct drm_gem_object *obj)
2071 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2073 struct address_space *mapping;
2074 struct inode *inode;
2078 if (obj_priv->pages_refcount++ != 0)
2081 /* Get the list of pages out of our struct file. They'll be pinned
2082 * at this point until we release them.
2084 page_count = obj->size / PAGE_SIZE;
2085 BUG_ON(obj_priv->pages != NULL);
2086 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2087 if (obj_priv->pages == NULL) {
2088 DRM_ERROR("Faled to allocate page list\n");
2089 obj_priv->pages_refcount--;
2093 inode = obj->filp->f_path.dentry->d_inode;
2094 mapping = inode->i_mapping;
2095 for (i = 0; i < page_count; i++) {
2096 page = read_mapping_page(mapping, i, NULL);
2098 ret = PTR_ERR(page);
2099 DRM_ERROR("read_mapping_page failed: %d\n", ret);
2100 i915_gem_object_put_pages(obj);
2103 obj_priv->pages[i] = page;
2106 if (obj_priv->tiling_mode != I915_TILING_NONE)
2107 i915_gem_object_do_bit_17_swizzle(obj);
2112 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2114 struct drm_gem_object *obj = reg->obj;
2115 struct drm_device *dev = obj->dev;
2116 drm_i915_private_t *dev_priv = dev->dev_private;
2117 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2118 int regnum = obj_priv->fence_reg;
2121 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2123 val |= obj_priv->gtt_offset & 0xfffff000;
2124 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2125 if (obj_priv->tiling_mode == I915_TILING_Y)
2126 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2127 val |= I965_FENCE_REG_VALID;
2129 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2132 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2134 struct drm_gem_object *obj = reg->obj;
2135 struct drm_device *dev = obj->dev;
2136 drm_i915_private_t *dev_priv = dev->dev_private;
2137 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2138 int regnum = obj_priv->fence_reg;
2140 uint32_t fence_reg, val;
2143 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2144 (obj_priv->gtt_offset & (obj->size - 1))) {
2145 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2146 __func__, obj_priv->gtt_offset, obj->size);
2150 if (obj_priv->tiling_mode == I915_TILING_Y &&
2151 HAS_128_BYTE_Y_TILING(dev))
2156 /* Note: pitch better be a power of two tile widths */
2157 pitch_val = obj_priv->stride / tile_width;
2158 pitch_val = ffs(pitch_val) - 1;
2160 val = obj_priv->gtt_offset;
2161 if (obj_priv->tiling_mode == I915_TILING_Y)
2162 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2163 val |= I915_FENCE_SIZE_BITS(obj->size);
2164 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2165 val |= I830_FENCE_REG_VALID;
2168 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2170 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2171 I915_WRITE(fence_reg, val);
2174 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2176 struct drm_gem_object *obj = reg->obj;
2177 struct drm_device *dev = obj->dev;
2178 drm_i915_private_t *dev_priv = dev->dev_private;
2179 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2180 int regnum = obj_priv->fence_reg;
2183 uint32_t fence_size_bits;
2185 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2186 (obj_priv->gtt_offset & (obj->size - 1))) {
2187 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2188 __func__, obj_priv->gtt_offset);
2192 pitch_val = obj_priv->stride / 128;
2193 pitch_val = ffs(pitch_val) - 1;
2194 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2196 val = obj_priv->gtt_offset;
2197 if (obj_priv->tiling_mode == I915_TILING_Y)
2198 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2199 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2200 WARN_ON(fence_size_bits & ~0x00000f00);
2201 val |= fence_size_bits;
2202 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2203 val |= I830_FENCE_REG_VALID;
2205 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2209 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2210 * @obj: object to map through a fence reg
2212 * When mapping objects through the GTT, userspace wants to be able to write
2213 * to them without having to worry about swizzling if the object is tiled.
2215 * This function walks the fence regs looking for a free one for @obj,
2216 * stealing one if it can't find any.
2218 * It then sets up the reg based on the object's properties: address, pitch
2219 * and tiling format.
2222 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2224 struct drm_device *dev = obj->dev;
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2227 struct drm_i915_fence_reg *reg = NULL;
2228 struct drm_i915_gem_object *old_obj_priv = NULL;
2231 /* Just update our place in the LRU if our fence is getting used. */
2232 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2233 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2237 switch (obj_priv->tiling_mode) {
2238 case I915_TILING_NONE:
2239 WARN(1, "allocating a fence for non-tiled object?\n");
2242 if (!obj_priv->stride)
2244 WARN((obj_priv->stride & (512 - 1)),
2245 "object 0x%08x is X tiled but has non-512B pitch\n",
2246 obj_priv->gtt_offset);
2249 if (!obj_priv->stride)
2251 WARN((obj_priv->stride & (128 - 1)),
2252 "object 0x%08x is Y tiled but has non-128B pitch\n",
2253 obj_priv->gtt_offset);
2257 /* First try to find a free reg */
2259 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2260 reg = &dev_priv->fence_regs[i];
2264 old_obj_priv = reg->obj->driver_private;
2265 if (!old_obj_priv->pin_count)
2269 /* None available, try to steal one or wait for a user to finish */
2270 if (i == dev_priv->num_fence_regs) {
2271 struct drm_gem_object *old_obj = NULL;
2276 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2278 old_obj = old_obj_priv->obj;
2280 if (old_obj_priv->pin_count)
2283 /* Take a reference, as otherwise the wait_rendering
2284 * below may cause the object to get freed out from
2287 drm_gem_object_reference(old_obj);
2289 /* i915 uses fences for GPU access to tiled buffers */
2290 if (IS_I965G(dev) || !old_obj_priv->active)
2293 /* This brings the object to the head of the LRU if it
2294 * had been written to. The only way this should
2295 * result in us waiting longer than the expected
2296 * optimal amount of time is if there was a
2297 * fence-using buffer later that was read-only.
2299 i915_gem_object_flush_gpu_write_domain(old_obj);
2300 ret = i915_gem_object_wait_rendering(old_obj);
2302 drm_gem_object_unreference(old_obj);
2310 * Zap this virtual mapping so we can set up a fence again
2311 * for this object next time we need it.
2313 i915_gem_release_mmap(old_obj);
2315 i = old_obj_priv->fence_reg;
2316 reg = &dev_priv->fence_regs[i];
2318 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2319 list_del_init(&old_obj_priv->fence_list);
2321 drm_gem_object_unreference(old_obj);
2324 obj_priv->fence_reg = i;
2325 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2330 i965_write_fence_reg(reg);
2331 else if (IS_I9XX(dev))
2332 i915_write_fence_reg(reg);
2334 i830_write_fence_reg(reg);
2340 * i915_gem_clear_fence_reg - clear out fence register info
2341 * @obj: object to clear
2343 * Zeroes out the fence register itself and clears out the associated
2344 * data structures in dev_priv and obj_priv.
2347 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2349 struct drm_device *dev = obj->dev;
2350 drm_i915_private_t *dev_priv = dev->dev_private;
2351 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2354 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2358 if (obj_priv->fence_reg < 8)
2359 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2361 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2364 I915_WRITE(fence_reg, 0);
2367 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2368 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2369 list_del_init(&obj_priv->fence_list);
2373 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2374 * to the buffer to finish, and then resets the fence register.
2375 * @obj: tiled object holding a fence register.
2377 * Zeroes out the fence register itself and clears out the associated
2378 * data structures in dev_priv and obj_priv.
2381 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2383 struct drm_device *dev = obj->dev;
2384 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2386 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2389 /* On the i915, GPU access to tiled buffers is via a fence,
2390 * therefore we must wait for any outstanding access to complete
2391 * before clearing the fence.
2393 if (!IS_I965G(dev)) {
2396 i915_gem_object_flush_gpu_write_domain(obj);
2397 i915_gem_object_flush_gtt_write_domain(obj);
2398 ret = i915_gem_object_wait_rendering(obj);
2403 i915_gem_clear_fence_reg (obj);
2409 * Finds free space in the GTT aperture and binds the object there.
2412 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2414 struct drm_device *dev = obj->dev;
2415 drm_i915_private_t *dev_priv = dev->dev_private;
2416 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2417 struct drm_mm_node *free_space;
2418 int page_count, ret;
2420 if (dev_priv->mm.suspended)
2423 alignment = i915_gem_get_gtt_alignment(obj);
2424 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2425 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2430 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2431 obj->size, alignment, 0);
2432 if (free_space != NULL) {
2433 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2435 if (obj_priv->gtt_space != NULL) {
2436 obj_priv->gtt_space->private = obj;
2437 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2440 if (obj_priv->gtt_space == NULL) {
2443 /* If the gtt is empty and we're still having trouble
2444 * fitting our object in, we're out of memory.
2447 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2449 spin_lock(&dev_priv->mm.active_list_lock);
2450 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2451 list_empty(&dev_priv->mm.flushing_list) &&
2452 list_empty(&dev_priv->mm.active_list));
2453 spin_unlock(&dev_priv->mm.active_list_lock);
2455 DRM_ERROR("GTT full, but LRU list empty\n");
2459 ret = i915_gem_evict_something(dev);
2461 if (ret != -ERESTARTSYS)
2462 DRM_ERROR("Failed to evict a buffer %d\n", ret);
2469 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2470 obj->size, obj_priv->gtt_offset);
2472 ret = i915_gem_object_get_pages(obj);
2474 drm_mm_put_block(obj_priv->gtt_space);
2475 obj_priv->gtt_space = NULL;
2479 page_count = obj->size / PAGE_SIZE;
2480 /* Create an AGP memory structure pointing at our pages, and bind it
2483 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2486 obj_priv->gtt_offset,
2487 obj_priv->agp_type);
2488 if (obj_priv->agp_mem == NULL) {
2489 i915_gem_object_put_pages(obj);
2490 drm_mm_put_block(obj_priv->gtt_space);
2491 obj_priv->gtt_space = NULL;
2494 atomic_inc(&dev->gtt_count);
2495 atomic_add(obj->size, &dev->gtt_memory);
2497 /* Assert that the object is not currently in any GPU domain. As it
2498 * wasn't in the GTT, there shouldn't be any way it could have been in
2501 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2502 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2508 i915_gem_clflush_object(struct drm_gem_object *obj)
2510 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2512 /* If we don't have a page list set up, then we're not pinned
2513 * to GPU, and we can ignore the cache flush because it'll happen
2514 * again at bind time.
2516 if (obj_priv->pages == NULL)
2519 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2522 /** Flushes any GPU write domain for the object if it's dirty. */
2524 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2526 struct drm_device *dev = obj->dev;
2529 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2532 /* Queue the GPU write cache flushing we need. */
2533 i915_gem_flush(dev, 0, obj->write_domain);
2534 seqno = i915_add_request(dev, NULL, obj->write_domain);
2535 obj->write_domain = 0;
2536 i915_gem_object_move_to_active(obj, seqno);
2539 /** Flushes the GTT write domain for the object if it's dirty. */
2541 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2543 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2546 /* No actual flushing is required for the GTT write domain. Writes
2547 * to it immediately go to main memory as far as we know, so there's
2548 * no chipset flush. It also doesn't land in render cache.
2550 obj->write_domain = 0;
2553 /** Flushes the CPU write domain for the object if it's dirty. */
2555 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2557 struct drm_device *dev = obj->dev;
2559 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2562 i915_gem_clflush_object(obj);
2563 drm_agp_chipset_flush(dev);
2564 obj->write_domain = 0;
2568 * Moves a single object to the GTT read, and possibly write domain.
2570 * This function returns when the move is complete, including waiting on
2574 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2576 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2579 /* Not valid to be called on unbound objects. */
2580 if (obj_priv->gtt_space == NULL)
2583 i915_gem_object_flush_gpu_write_domain(obj);
2584 /* Wait on any GPU rendering and flushing to occur. */
2585 ret = i915_gem_object_wait_rendering(obj);
2589 /* If we're writing through the GTT domain, then CPU and GPU caches
2590 * will need to be invalidated at next use.
2593 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2595 i915_gem_object_flush_cpu_write_domain(obj);
2597 /* It should now be out of any other write domains, and we can update
2598 * the domain values for our changes.
2600 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2601 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2603 obj->write_domain = I915_GEM_DOMAIN_GTT;
2604 obj_priv->dirty = 1;
2611 * Moves a single object to the CPU read, and possibly write domain.
2613 * This function returns when the move is complete, including waiting on
2617 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2621 i915_gem_object_flush_gpu_write_domain(obj);
2622 /* Wait on any GPU rendering and flushing to occur. */
2623 ret = i915_gem_object_wait_rendering(obj);
2627 i915_gem_object_flush_gtt_write_domain(obj);
2629 /* If we have a partially-valid cache of the object in the CPU,
2630 * finish invalidating it and free the per-page flags.
2632 i915_gem_object_set_to_full_cpu_read_domain(obj);
2634 /* Flush the CPU cache if it's still invalid. */
2635 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2636 i915_gem_clflush_object(obj);
2638 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2641 /* It should now be out of any other write domains, and we can update
2642 * the domain values for our changes.
2644 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2646 /* If we're writing through the CPU, then the GPU read domains will
2647 * need to be invalidated at next use.
2650 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2651 obj->write_domain = I915_GEM_DOMAIN_CPU;
2658 * Set the next domain for the specified object. This
2659 * may not actually perform the necessary flushing/invaliding though,
2660 * as that may want to be batched with other set_domain operations
2662 * This is (we hope) the only really tricky part of gem. The goal
2663 * is fairly simple -- track which caches hold bits of the object
2664 * and make sure they remain coherent. A few concrete examples may
2665 * help to explain how it works. For shorthand, we use the notation
2666 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2667 * a pair of read and write domain masks.
2669 * Case 1: the batch buffer
2675 * 5. Unmapped from GTT
2678 * Let's take these a step at a time
2681 * Pages allocated from the kernel may still have
2682 * cache contents, so we set them to (CPU, CPU) always.
2683 * 2. Written by CPU (using pwrite)
2684 * The pwrite function calls set_domain (CPU, CPU) and
2685 * this function does nothing (as nothing changes)
2687 * This function asserts that the object is not
2688 * currently in any GPU-based read or write domains
2690 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2691 * As write_domain is zero, this function adds in the
2692 * current read domains (CPU+COMMAND, 0).
2693 * flush_domains is set to CPU.
2694 * invalidate_domains is set to COMMAND
2695 * clflush is run to get data out of the CPU caches
2696 * then i915_dev_set_domain calls i915_gem_flush to
2697 * emit an MI_FLUSH and drm_agp_chipset_flush
2698 * 5. Unmapped from GTT
2699 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2700 * flush_domains and invalidate_domains end up both zero
2701 * so no flushing/invalidating happens
2705 * Case 2: The shared render buffer
2709 * 3. Read/written by GPU
2710 * 4. set_domain to (CPU,CPU)
2711 * 5. Read/written by CPU
2712 * 6. Read/written by GPU
2715 * Same as last example, (CPU, CPU)
2717 * Nothing changes (assertions find that it is not in the GPU)
2718 * 3. Read/written by GPU
2719 * execbuffer calls set_domain (RENDER, RENDER)
2720 * flush_domains gets CPU
2721 * invalidate_domains gets GPU
2723 * MI_FLUSH and drm_agp_chipset_flush
2724 * 4. set_domain (CPU, CPU)
2725 * flush_domains gets GPU
2726 * invalidate_domains gets CPU
2727 * wait_rendering (obj) to make sure all drawing is complete.
2728 * This will include an MI_FLUSH to get the data from GPU
2730 * clflush (obj) to invalidate the CPU cache
2731 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2732 * 5. Read/written by CPU
2733 * cache lines are loaded and dirtied
2734 * 6. Read written by GPU
2735 * Same as last GPU access
2737 * Case 3: The constant buffer
2742 * 4. Updated (written) by CPU again
2751 * flush_domains = CPU
2752 * invalidate_domains = RENDER
2755 * drm_agp_chipset_flush
2756 * 4. Updated (written) by CPU again
2758 * flush_domains = 0 (no previous write domain)
2759 * invalidate_domains = 0 (no new read domains)
2762 * flush_domains = CPU
2763 * invalidate_domains = RENDER
2766 * drm_agp_chipset_flush
2769 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2771 struct drm_device *dev = obj->dev;
2772 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2773 uint32_t invalidate_domains = 0;
2774 uint32_t flush_domains = 0;
2776 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2777 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2779 intel_mark_busy(dev, obj);
2782 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2784 obj->read_domains, obj->pending_read_domains,
2785 obj->write_domain, obj->pending_write_domain);
2788 * If the object isn't moving to a new write domain,
2789 * let the object stay in multiple read domains
2791 if (obj->pending_write_domain == 0)
2792 obj->pending_read_domains |= obj->read_domains;
2794 obj_priv->dirty = 1;
2797 * Flush the current write domain if
2798 * the new read domains don't match. Invalidate
2799 * any read domains which differ from the old
2802 if (obj->write_domain &&
2803 obj->write_domain != obj->pending_read_domains) {
2804 flush_domains |= obj->write_domain;
2805 invalidate_domains |=
2806 obj->pending_read_domains & ~obj->write_domain;
2809 * Invalidate any read caches which may have
2810 * stale data. That is, any new read domains.
2812 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2813 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2815 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2816 __func__, flush_domains, invalidate_domains);
2818 i915_gem_clflush_object(obj);
2821 /* The actual obj->write_domain will be updated with
2822 * pending_write_domain after we emit the accumulated flush for all
2823 * of our domain changes in execbuffers (which clears objects'
2824 * write_domains). So if we have a current write domain that we
2825 * aren't changing, set pending_write_domain to that.
2827 if (flush_domains == 0 && obj->pending_write_domain == 0)
2828 obj->pending_write_domain = obj->write_domain;
2829 obj->read_domains = obj->pending_read_domains;
2831 dev->invalidate_domains |= invalidate_domains;
2832 dev->flush_domains |= flush_domains;
2834 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2836 obj->read_domains, obj->write_domain,
2837 dev->invalidate_domains, dev->flush_domains);
2842 * Moves the object from a partially CPU read to a full one.
2844 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2845 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2848 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2850 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2852 if (!obj_priv->page_cpu_valid)
2855 /* If we're partially in the CPU read domain, finish moving it in.
2857 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2860 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2861 if (obj_priv->page_cpu_valid[i])
2863 drm_clflush_pages(obj_priv->pages + i, 1);
2867 /* Free the page_cpu_valid mappings which are now stale, whether
2868 * or not we've got I915_GEM_DOMAIN_CPU.
2870 kfree(obj_priv->page_cpu_valid);
2871 obj_priv->page_cpu_valid = NULL;
2875 * Set the CPU read domain on a range of the object.
2877 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2878 * not entirely valid. The page_cpu_valid member of the object flags which
2879 * pages have been flushed, and will be respected by
2880 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2881 * of the whole object.
2883 * This function returns when the move is complete, including waiting on
2887 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2888 uint64_t offset, uint64_t size)
2890 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2893 if (offset == 0 && size == obj->size)
2894 return i915_gem_object_set_to_cpu_domain(obj, 0);
2896 i915_gem_object_flush_gpu_write_domain(obj);
2897 /* Wait on any GPU rendering and flushing to occur. */
2898 ret = i915_gem_object_wait_rendering(obj);
2901 i915_gem_object_flush_gtt_write_domain(obj);
2903 /* If we're already fully in the CPU read domain, we're done. */
2904 if (obj_priv->page_cpu_valid == NULL &&
2905 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2908 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2909 * newly adding I915_GEM_DOMAIN_CPU
2911 if (obj_priv->page_cpu_valid == NULL) {
2912 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
2914 if (obj_priv->page_cpu_valid == NULL)
2916 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2917 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2919 /* Flush the cache on any pages that are still invalid from the CPU's
2922 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2924 if (obj_priv->page_cpu_valid[i])
2927 drm_clflush_pages(obj_priv->pages + i, 1);
2929 obj_priv->page_cpu_valid[i] = 1;
2932 /* It should now be out of any other write domains, and we can update
2933 * the domain values for our changes.
2935 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2937 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2943 * Pin an object to the GTT and evaluate the relocations landing in it.
2946 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2947 struct drm_file *file_priv,
2948 struct drm_i915_gem_exec_object *entry,
2949 struct drm_i915_gem_relocation_entry *relocs)
2951 struct drm_device *dev = obj->dev;
2952 drm_i915_private_t *dev_priv = dev->dev_private;
2953 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2955 void __iomem *reloc_page;
2957 /* Choose the GTT offset for our buffer and put it there. */
2958 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2962 entry->offset = obj_priv->gtt_offset;
2964 /* Apply the relocations, using the GTT aperture to avoid cache
2965 * flushing requirements.
2967 for (i = 0; i < entry->relocation_count; i++) {
2968 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
2969 struct drm_gem_object *target_obj;
2970 struct drm_i915_gem_object *target_obj_priv;
2971 uint32_t reloc_val, reloc_offset;
2972 uint32_t __iomem *reloc_entry;
2974 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2975 reloc->target_handle);
2976 if (target_obj == NULL) {
2977 i915_gem_object_unpin(obj);
2980 target_obj_priv = target_obj->driver_private;
2982 /* The target buffer should have appeared before us in the
2983 * exec_object list, so it should have a GTT space bound by now.
2985 if (target_obj_priv->gtt_space == NULL) {
2986 DRM_ERROR("No GTT space found for object %d\n",
2987 reloc->target_handle);
2988 drm_gem_object_unreference(target_obj);
2989 i915_gem_object_unpin(obj);
2993 if (reloc->offset > obj->size - 4) {
2994 DRM_ERROR("Relocation beyond object bounds: "
2995 "obj %p target %d offset %d size %d.\n",
2996 obj, reloc->target_handle,
2997 (int) reloc->offset, (int) obj->size);
2998 drm_gem_object_unreference(target_obj);
2999 i915_gem_object_unpin(obj);
3002 if (reloc->offset & 3) {
3003 DRM_ERROR("Relocation not 4-byte aligned: "
3004 "obj %p target %d offset %d.\n",
3005 obj, reloc->target_handle,
3006 (int) reloc->offset);
3007 drm_gem_object_unreference(target_obj);
3008 i915_gem_object_unpin(obj);
3012 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3013 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3014 DRM_ERROR("reloc with read/write CPU domains: "
3015 "obj %p target %d offset %d "
3016 "read %08x write %08x",
3017 obj, reloc->target_handle,
3018 (int) reloc->offset,
3019 reloc->read_domains,
3020 reloc->write_domain);
3021 drm_gem_object_unreference(target_obj);
3022 i915_gem_object_unpin(obj);
3026 if (reloc->write_domain && target_obj->pending_write_domain &&
3027 reloc->write_domain != target_obj->pending_write_domain) {
3028 DRM_ERROR("Write domain conflict: "
3029 "obj %p target %d offset %d "
3030 "new %08x old %08x\n",
3031 obj, reloc->target_handle,
3032 (int) reloc->offset,
3033 reloc->write_domain,
3034 target_obj->pending_write_domain);
3035 drm_gem_object_unreference(target_obj);
3036 i915_gem_object_unpin(obj);
3041 DRM_INFO("%s: obj %p offset %08x target %d "
3042 "read %08x write %08x gtt %08x "
3043 "presumed %08x delta %08x\n",
3046 (int) reloc->offset,
3047 (int) reloc->target_handle,
3048 (int) reloc->read_domains,
3049 (int) reloc->write_domain,
3050 (int) target_obj_priv->gtt_offset,
3051 (int) reloc->presumed_offset,
3055 target_obj->pending_read_domains |= reloc->read_domains;
3056 target_obj->pending_write_domain |= reloc->write_domain;
3058 /* If the relocation already has the right value in it, no
3059 * more work needs to be done.
3061 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3062 drm_gem_object_unreference(target_obj);
3066 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3068 drm_gem_object_unreference(target_obj);
3069 i915_gem_object_unpin(obj);
3073 /* Map the page containing the relocation we're going to
3076 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3077 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3080 reloc_entry = (uint32_t __iomem *)(reloc_page +
3081 (reloc_offset & (PAGE_SIZE - 1)));
3082 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3085 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3086 obj, (unsigned int) reloc->offset,
3087 readl(reloc_entry), reloc_val);
3089 writel(reloc_val, reloc_entry);
3090 io_mapping_unmap_atomic(reloc_page);
3092 /* The updated presumed offset for this entry will be
3093 * copied back out to the user.
3095 reloc->presumed_offset = target_obj_priv->gtt_offset;
3097 drm_gem_object_unreference(target_obj);
3102 i915_gem_dump_object(obj, 128, __func__, ~0);
3107 /** Dispatch a batchbuffer to the ring
3110 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3111 struct drm_i915_gem_execbuffer *exec,
3112 struct drm_clip_rect *cliprects,
3113 uint64_t exec_offset)
3115 drm_i915_private_t *dev_priv = dev->dev_private;
3116 int nbox = exec->num_cliprects;
3118 uint32_t exec_start, exec_len;
3121 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3122 exec_len = (uint32_t) exec->batch_len;
3124 count = nbox ? nbox : 1;
3126 for (i = 0; i < count; i++) {
3128 int ret = i915_emit_box(dev, cliprects, i,
3129 exec->DR1, exec->DR4);
3134 if (IS_I830(dev) || IS_845G(dev)) {
3136 OUT_RING(MI_BATCH_BUFFER);
3137 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3138 OUT_RING(exec_start + exec_len - 4);
3143 if (IS_I965G(dev)) {
3144 OUT_RING(MI_BATCH_BUFFER_START |
3146 MI_BATCH_NON_SECURE_I965);
3147 OUT_RING(exec_start);
3149 OUT_RING(MI_BATCH_BUFFER_START |
3151 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3157 /* XXX breadcrumb */
3161 /* Throttle our rendering by waiting until the ring has completed our requests
3162 * emitted over 20 msec ago.
3164 * Note that if we were to use the current jiffies each time around the loop,
3165 * we wouldn't escape the function with any frames outstanding if the time to
3166 * render a frame was over 20ms.
3168 * This should get us reasonable parallelism between CPU and GPU but also
3169 * relatively low latency when blocking on a particular request to finish.
3172 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3174 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3176 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3178 mutex_lock(&dev->struct_mutex);
3179 while (!list_empty(&i915_file_priv->mm.request_list)) {
3180 struct drm_i915_gem_request *request;
3182 request = list_first_entry(&i915_file_priv->mm.request_list,
3183 struct drm_i915_gem_request,
3186 if (time_after_eq(request->emitted_jiffies, recent_enough))
3189 ret = i915_wait_request(dev, request->seqno);
3193 mutex_unlock(&dev->struct_mutex);
3199 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3200 uint32_t buffer_count,
3201 struct drm_i915_gem_relocation_entry **relocs)
3203 uint32_t reloc_count = 0, reloc_index = 0, i;
3207 for (i = 0; i < buffer_count; i++) {
3208 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3210 reloc_count += exec_list[i].relocation_count;
3213 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3214 if (*relocs == NULL)
3217 for (i = 0; i < buffer_count; i++) {
3218 struct drm_i915_gem_relocation_entry __user *user_relocs;
3220 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3222 ret = copy_from_user(&(*relocs)[reloc_index],
3224 exec_list[i].relocation_count *
3227 drm_free_large(*relocs);
3232 reloc_index += exec_list[i].relocation_count;
3239 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3240 uint32_t buffer_count,
3241 struct drm_i915_gem_relocation_entry *relocs)
3243 uint32_t reloc_count = 0, i;
3246 for (i = 0; i < buffer_count; i++) {
3247 struct drm_i915_gem_relocation_entry __user *user_relocs;
3250 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3252 unwritten = copy_to_user(user_relocs,
3253 &relocs[reloc_count],
3254 exec_list[i].relocation_count *
3262 reloc_count += exec_list[i].relocation_count;
3266 drm_free_large(relocs);
3272 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3273 uint64_t exec_offset)
3275 uint32_t exec_start, exec_len;
3277 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3278 exec_len = (uint32_t) exec->batch_len;
3280 if ((exec_start | exec_len) & 0x7)
3290 i915_gem_execbuffer(struct drm_device *dev, void *data,
3291 struct drm_file *file_priv)
3293 drm_i915_private_t *dev_priv = dev->dev_private;
3294 struct drm_i915_gem_execbuffer *args = data;
3295 struct drm_i915_gem_exec_object *exec_list = NULL;
3296 struct drm_gem_object **object_list = NULL;
3297 struct drm_gem_object *batch_obj;
3298 struct drm_i915_gem_object *obj_priv;
3299 struct drm_clip_rect *cliprects = NULL;
3300 struct drm_i915_gem_relocation_entry *relocs;
3301 int ret, ret2, i, pinned = 0;
3302 uint64_t exec_offset;
3303 uint32_t seqno, flush_domains, reloc_index;
3307 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3308 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3311 if (args->buffer_count < 1) {
3312 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3315 /* Copy in the exec list from userland */
3316 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3317 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3318 if (exec_list == NULL || object_list == NULL) {
3319 DRM_ERROR("Failed to allocate exec or object list "
3321 args->buffer_count);
3325 ret = copy_from_user(exec_list,
3326 (struct drm_i915_relocation_entry __user *)
3327 (uintptr_t) args->buffers_ptr,
3328 sizeof(*exec_list) * args->buffer_count);
3330 DRM_ERROR("copy %d exec entries failed %d\n",
3331 args->buffer_count, ret);
3335 if (args->num_cliprects != 0) {
3336 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3338 if (cliprects == NULL)
3341 ret = copy_from_user(cliprects,
3342 (struct drm_clip_rect __user *)
3343 (uintptr_t) args->cliprects_ptr,
3344 sizeof(*cliprects) * args->num_cliprects);
3346 DRM_ERROR("copy %d cliprects failed: %d\n",
3347 args->num_cliprects, ret);
3352 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3357 mutex_lock(&dev->struct_mutex);
3359 i915_verify_inactive(dev, __FILE__, __LINE__);
3361 if (atomic_read(&dev_priv->mm.wedged)) {
3362 DRM_ERROR("Execbuf while wedged\n");
3363 mutex_unlock(&dev->struct_mutex);
3368 if (dev_priv->mm.suspended) {
3369 DRM_ERROR("Execbuf while VT-switched.\n");
3370 mutex_unlock(&dev->struct_mutex);
3375 /* Look up object handles */
3376 for (i = 0; i < args->buffer_count; i++) {
3377 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3378 exec_list[i].handle);
3379 if (object_list[i] == NULL) {
3380 DRM_ERROR("Invalid object handle %d at index %d\n",
3381 exec_list[i].handle, i);
3386 obj_priv = object_list[i]->driver_private;
3387 if (obj_priv->in_execbuffer) {
3388 DRM_ERROR("Object %p appears more than once in object list\n",
3393 obj_priv->in_execbuffer = true;
3396 /* Pin and relocate */
3397 for (pin_tries = 0; ; pin_tries++) {
3401 for (i = 0; i < args->buffer_count; i++) {
3402 object_list[i]->pending_read_domains = 0;
3403 object_list[i]->pending_write_domain = 0;
3404 ret = i915_gem_object_pin_and_relocate(object_list[i],
3407 &relocs[reloc_index]);
3411 reloc_index += exec_list[i].relocation_count;
3417 /* error other than GTT full, or we've already tried again */
3418 if (ret != -ENOSPC || pin_tries >= 1) {
3419 if (ret != -ERESTARTSYS)
3420 DRM_ERROR("Failed to pin buffers %d\n", ret);
3424 /* unpin all of our buffers */
3425 for (i = 0; i < pinned; i++)
3426 i915_gem_object_unpin(object_list[i]);
3429 /* evict everyone we can from the aperture */
3430 ret = i915_gem_evict_everything(dev);
3435 /* Set the pending read domains for the batch buffer to COMMAND */
3436 batch_obj = object_list[args->buffer_count-1];
3437 if (batch_obj->pending_write_domain) {
3438 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3442 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3444 /* Sanity check the batch buffer, prior to moving objects */
3445 exec_offset = exec_list[args->buffer_count - 1].offset;
3446 ret = i915_gem_check_execbuffer (args, exec_offset);
3448 DRM_ERROR("execbuf with invalid offset/length\n");
3452 i915_verify_inactive(dev, __FILE__, __LINE__);
3454 /* Zero the global flush/invalidate flags. These
3455 * will be modified as new domains are computed
3458 dev->invalidate_domains = 0;
3459 dev->flush_domains = 0;
3461 for (i = 0; i < args->buffer_count; i++) {
3462 struct drm_gem_object *obj = object_list[i];
3464 /* Compute new gpu domains and update invalidate/flush */
3465 i915_gem_object_set_to_gpu_domain(obj);
3468 i915_verify_inactive(dev, __FILE__, __LINE__);
3470 if (dev->invalidate_domains | dev->flush_domains) {
3472 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3474 dev->invalidate_domains,
3475 dev->flush_domains);
3478 dev->invalidate_domains,
3479 dev->flush_domains);
3480 if (dev->flush_domains)
3481 (void)i915_add_request(dev, file_priv,
3482 dev->flush_domains);
3485 for (i = 0; i < args->buffer_count; i++) {
3486 struct drm_gem_object *obj = object_list[i];
3488 obj->write_domain = obj->pending_write_domain;
3491 i915_verify_inactive(dev, __FILE__, __LINE__);
3494 for (i = 0; i < args->buffer_count; i++) {
3495 i915_gem_object_check_coherency(object_list[i],
3496 exec_list[i].handle);
3501 i915_gem_dump_object(batch_obj,
3507 /* Exec the batchbuffer */
3508 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3510 DRM_ERROR("dispatch failed %d\n", ret);
3515 * Ensure that the commands in the batch buffer are
3516 * finished before the interrupt fires
3518 flush_domains = i915_retire_commands(dev);
3520 i915_verify_inactive(dev, __FILE__, __LINE__);
3523 * Get a seqno representing the execution of the current buffer,
3524 * which we can wait on. We would like to mitigate these interrupts,
3525 * likely by only creating seqnos occasionally (so that we have
3526 * *some* interrupts representing completion of buffers that we can
3527 * wait on when trying to clear up gtt space).
3529 seqno = i915_add_request(dev, file_priv, flush_domains);
3531 for (i = 0; i < args->buffer_count; i++) {
3532 struct drm_gem_object *obj = object_list[i];
3534 i915_gem_object_move_to_active(obj, seqno);
3536 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3540 i915_dump_lru(dev, __func__);
3543 i915_verify_inactive(dev, __FILE__, __LINE__);
3546 for (i = 0; i < pinned; i++)
3547 i915_gem_object_unpin(object_list[i]);
3549 for (i = 0; i < args->buffer_count; i++) {
3550 if (object_list[i]) {
3551 obj_priv = object_list[i]->driver_private;
3552 obj_priv->in_execbuffer = false;
3554 drm_gem_object_unreference(object_list[i]);
3557 mutex_unlock(&dev->struct_mutex);
3560 /* Copy the new buffer offsets back to the user's exec list. */
3561 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3562 (uintptr_t) args->buffers_ptr,
3564 sizeof(*exec_list) * args->buffer_count);
3567 DRM_ERROR("failed to copy %d exec entries "
3568 "back to user (%d)\n",
3569 args->buffer_count, ret);
3573 /* Copy the updated relocations out regardless of current error
3574 * state. Failure to update the relocs would mean that the next
3575 * time userland calls execbuf, it would do so with presumed offset
3576 * state that didn't match the actual object state.
3578 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3581 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3588 drm_free_large(object_list);
3589 drm_free_large(exec_list);
3596 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3598 struct drm_device *dev = obj->dev;
3599 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3602 i915_verify_inactive(dev, __FILE__, __LINE__);
3603 if (obj_priv->gtt_space == NULL) {
3604 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3606 if (ret != -EBUSY && ret != -ERESTARTSYS)
3607 DRM_ERROR("Failure to bind: %d\n", ret);
3612 * Pre-965 chips need a fence register set up in order to
3613 * properly handle tiled surfaces.
3615 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3616 ret = i915_gem_object_get_fence_reg(obj);
3618 if (ret != -EBUSY && ret != -ERESTARTSYS)
3619 DRM_ERROR("Failure to install fence: %d\n",
3624 obj_priv->pin_count++;
3626 /* If the object is not active and not pending a flush,
3627 * remove it from the inactive list
3629 if (obj_priv->pin_count == 1) {
3630 atomic_inc(&dev->pin_count);
3631 atomic_add(obj->size, &dev->pin_memory);
3632 if (!obj_priv->active &&
3633 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3634 !list_empty(&obj_priv->list))
3635 list_del_init(&obj_priv->list);
3637 i915_verify_inactive(dev, __FILE__, __LINE__);
3643 i915_gem_object_unpin(struct drm_gem_object *obj)
3645 struct drm_device *dev = obj->dev;
3646 drm_i915_private_t *dev_priv = dev->dev_private;
3647 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3649 i915_verify_inactive(dev, __FILE__, __LINE__);
3650 obj_priv->pin_count--;
3651 BUG_ON(obj_priv->pin_count < 0);
3652 BUG_ON(obj_priv->gtt_space == NULL);
3654 /* If the object is no longer pinned, and is
3655 * neither active nor being flushed, then stick it on
3658 if (obj_priv->pin_count == 0) {
3659 if (!obj_priv->active &&
3660 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3661 list_move_tail(&obj_priv->list,
3662 &dev_priv->mm.inactive_list);
3663 atomic_dec(&dev->pin_count);
3664 atomic_sub(obj->size, &dev->pin_memory);
3666 i915_verify_inactive(dev, __FILE__, __LINE__);
3670 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3671 struct drm_file *file_priv)
3673 struct drm_i915_gem_pin *args = data;
3674 struct drm_gem_object *obj;
3675 struct drm_i915_gem_object *obj_priv;
3678 mutex_lock(&dev->struct_mutex);
3680 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3682 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3684 mutex_unlock(&dev->struct_mutex);
3687 obj_priv = obj->driver_private;
3689 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3690 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3692 drm_gem_object_unreference(obj);
3693 mutex_unlock(&dev->struct_mutex);
3697 obj_priv->user_pin_count++;
3698 obj_priv->pin_filp = file_priv;
3699 if (obj_priv->user_pin_count == 1) {
3700 ret = i915_gem_object_pin(obj, args->alignment);
3702 drm_gem_object_unreference(obj);
3703 mutex_unlock(&dev->struct_mutex);
3708 /* XXX - flush the CPU caches for pinned objects
3709 * as the X server doesn't manage domains yet
3711 i915_gem_object_flush_cpu_write_domain(obj);
3712 args->offset = obj_priv->gtt_offset;
3713 drm_gem_object_unreference(obj);
3714 mutex_unlock(&dev->struct_mutex);
3720 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3721 struct drm_file *file_priv)
3723 struct drm_i915_gem_pin *args = data;
3724 struct drm_gem_object *obj;
3725 struct drm_i915_gem_object *obj_priv;
3727 mutex_lock(&dev->struct_mutex);
3729 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3731 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3733 mutex_unlock(&dev->struct_mutex);
3737 obj_priv = obj->driver_private;
3738 if (obj_priv->pin_filp != file_priv) {
3739 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3741 drm_gem_object_unreference(obj);
3742 mutex_unlock(&dev->struct_mutex);
3745 obj_priv->user_pin_count--;
3746 if (obj_priv->user_pin_count == 0) {
3747 obj_priv->pin_filp = NULL;
3748 i915_gem_object_unpin(obj);
3751 drm_gem_object_unreference(obj);
3752 mutex_unlock(&dev->struct_mutex);
3757 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3758 struct drm_file *file_priv)
3760 struct drm_i915_gem_busy *args = data;
3761 struct drm_gem_object *obj;
3762 struct drm_i915_gem_object *obj_priv;
3764 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3766 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3771 mutex_lock(&dev->struct_mutex);
3772 /* Update the active list for the hardware's current position.
3773 * Otherwise this only updates on a delayed timer or when irqs are
3774 * actually unmasked, and our working set ends up being larger than
3777 i915_gem_retire_requests(dev);
3779 obj_priv = obj->driver_private;
3780 /* Don't count being on the flushing list against the object being
3781 * done. Otherwise, a buffer left on the flushing list but not getting
3782 * flushed (because nobody's flushing that domain) won't ever return
3783 * unbusy and get reused by libdrm's bo cache. The other expected
3784 * consumer of this interface, OpenGL's occlusion queries, also specs
3785 * that the objects get unbusy "eventually" without any interference.
3787 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
3789 drm_gem_object_unreference(obj);
3790 mutex_unlock(&dev->struct_mutex);
3795 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3796 struct drm_file *file_priv)
3798 return i915_gem_ring_throttle(dev, file_priv);
3801 int i915_gem_init_object(struct drm_gem_object *obj)
3803 struct drm_i915_gem_object *obj_priv;
3805 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
3806 if (obj_priv == NULL)
3810 * We've just allocated pages from the kernel,
3811 * so they've just been written by the CPU with
3812 * zeros. They'll need to be clflushed before we
3813 * use them with the GPU.
3815 obj->write_domain = I915_GEM_DOMAIN_CPU;
3816 obj->read_domains = I915_GEM_DOMAIN_CPU;
3818 obj_priv->agp_type = AGP_USER_MEMORY;
3820 obj->driver_private = obj_priv;
3821 obj_priv->obj = obj;
3822 obj_priv->fence_reg = I915_FENCE_REG_NONE;
3823 INIT_LIST_HEAD(&obj_priv->list);
3824 INIT_LIST_HEAD(&obj_priv->fence_list);
3829 void i915_gem_free_object(struct drm_gem_object *obj)
3831 struct drm_device *dev = obj->dev;
3832 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3834 while (obj_priv->pin_count > 0)
3835 i915_gem_object_unpin(obj);
3837 if (obj_priv->phys_obj)
3838 i915_gem_detach_phys_object(dev, obj);
3840 i915_gem_object_unbind(obj);
3842 if (obj_priv->mmap_offset)
3843 i915_gem_free_mmap_offset(obj);
3845 kfree(obj_priv->page_cpu_valid);
3846 kfree(obj_priv->bit_17);
3847 kfree(obj->driver_private);
3850 /** Unbinds all objects that are on the given buffer list. */
3852 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3854 struct drm_gem_object *obj;
3855 struct drm_i915_gem_object *obj_priv;
3858 while (!list_empty(head)) {
3859 obj_priv = list_first_entry(head,
3860 struct drm_i915_gem_object,
3862 obj = obj_priv->obj;
3864 if (obj_priv->pin_count != 0) {
3865 DRM_ERROR("Pinned object in unbind list\n");
3866 mutex_unlock(&dev->struct_mutex);
3870 ret = i915_gem_object_unbind(obj);
3872 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3874 mutex_unlock(&dev->struct_mutex);
3884 i915_gem_idle(struct drm_device *dev)
3886 drm_i915_private_t *dev_priv = dev->dev_private;
3887 uint32_t seqno, cur_seqno, last_seqno;
3890 mutex_lock(&dev->struct_mutex);
3892 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3893 mutex_unlock(&dev->struct_mutex);
3897 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3898 * We need to replace this with a semaphore, or something.
3900 dev_priv->mm.suspended = 1;
3901 del_timer(&dev_priv->hangcheck_timer);
3903 /* Cancel the retire work handler, wait for it to finish if running
3905 mutex_unlock(&dev->struct_mutex);
3906 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3907 mutex_lock(&dev->struct_mutex);
3909 i915_kernel_lost_context(dev);
3911 /* Flush the GPU along with all non-CPU write domains
3913 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
3914 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
3917 mutex_unlock(&dev->struct_mutex);
3921 dev_priv->mm.waiting_gem_seqno = seqno;
3925 cur_seqno = i915_get_gem_seqno(dev);
3926 if (i915_seqno_passed(cur_seqno, seqno))
3928 if (last_seqno == cur_seqno) {
3929 if (stuck++ > 100) {
3930 DRM_ERROR("hardware wedged\n");
3931 atomic_set(&dev_priv->mm.wedged, 1);
3932 DRM_WAKEUP(&dev_priv->irq_queue);
3937 last_seqno = cur_seqno;
3939 dev_priv->mm.waiting_gem_seqno = 0;
3941 i915_gem_retire_requests(dev);
3943 spin_lock(&dev_priv->mm.active_list_lock);
3944 if (!atomic_read(&dev_priv->mm.wedged)) {
3945 /* Active and flushing should now be empty as we've
3946 * waited for a sequence higher than any pending execbuffer
3948 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3949 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3950 /* Request should now be empty as we've also waited
3951 * for the last request in the list
3953 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3956 /* Empty the active and flushing lists to inactive. If there's
3957 * anything left at this point, it means that we're wedged and
3958 * nothing good's going to happen by leaving them there. So strip
3959 * the GPU domains and just stuff them onto inactive.
3961 while (!list_empty(&dev_priv->mm.active_list)) {
3962 struct drm_i915_gem_object *obj_priv;
3964 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3965 struct drm_i915_gem_object,
3967 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3968 i915_gem_object_move_to_inactive(obj_priv->obj);
3970 spin_unlock(&dev_priv->mm.active_list_lock);
3972 while (!list_empty(&dev_priv->mm.flushing_list)) {
3973 struct drm_i915_gem_object *obj_priv;
3975 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3976 struct drm_i915_gem_object,
3978 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3979 i915_gem_object_move_to_inactive(obj_priv->obj);
3983 /* Move all inactive buffers out of the GTT. */
3984 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3985 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3987 mutex_unlock(&dev->struct_mutex);
3991 i915_gem_cleanup_ringbuffer(dev);
3992 mutex_unlock(&dev->struct_mutex);
3998 i915_gem_init_hws(struct drm_device *dev)
4000 drm_i915_private_t *dev_priv = dev->dev_private;
4001 struct drm_gem_object *obj;
4002 struct drm_i915_gem_object *obj_priv;
4005 /* If we need a physical address for the status page, it's already
4006 * initialized at driver load time.
4008 if (!I915_NEED_GFX_HWS(dev))
4011 obj = drm_gem_object_alloc(dev, 4096);
4013 DRM_ERROR("Failed to allocate status page\n");
4016 obj_priv = obj->driver_private;
4017 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4019 ret = i915_gem_object_pin(obj, 4096);
4021 drm_gem_object_unreference(obj);
4025 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4027 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4028 if (dev_priv->hw_status_page == NULL) {
4029 DRM_ERROR("Failed to map status page.\n");
4030 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4031 i915_gem_object_unpin(obj);
4032 drm_gem_object_unreference(obj);
4035 dev_priv->hws_obj = obj;
4036 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4037 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4038 I915_READ(HWS_PGA); /* posting read */
4039 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4045 i915_gem_cleanup_hws(struct drm_device *dev)
4047 drm_i915_private_t *dev_priv = dev->dev_private;
4048 struct drm_gem_object *obj;
4049 struct drm_i915_gem_object *obj_priv;
4051 if (dev_priv->hws_obj == NULL)
4054 obj = dev_priv->hws_obj;
4055 obj_priv = obj->driver_private;
4057 kunmap(obj_priv->pages[0]);
4058 i915_gem_object_unpin(obj);
4059 drm_gem_object_unreference(obj);
4060 dev_priv->hws_obj = NULL;
4062 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4063 dev_priv->hw_status_page = NULL;
4065 /* Write high address into HWS_PGA when disabling. */
4066 I915_WRITE(HWS_PGA, 0x1ffff000);
4070 i915_gem_init_ringbuffer(struct drm_device *dev)
4072 drm_i915_private_t *dev_priv = dev->dev_private;
4073 struct drm_gem_object *obj;
4074 struct drm_i915_gem_object *obj_priv;
4075 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4079 ret = i915_gem_init_hws(dev);
4083 obj = drm_gem_object_alloc(dev, 128 * 1024);
4085 DRM_ERROR("Failed to allocate ringbuffer\n");
4086 i915_gem_cleanup_hws(dev);
4089 obj_priv = obj->driver_private;
4091 ret = i915_gem_object_pin(obj, 4096);
4093 drm_gem_object_unreference(obj);
4094 i915_gem_cleanup_hws(dev);
4098 /* Set up the kernel mapping for the ring. */
4099 ring->Size = obj->size;
4101 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4102 ring->map.size = obj->size;
4104 ring->map.flags = 0;
4107 drm_core_ioremap_wc(&ring->map, dev);
4108 if (ring->map.handle == NULL) {
4109 DRM_ERROR("Failed to map ringbuffer.\n");
4110 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4111 i915_gem_object_unpin(obj);
4112 drm_gem_object_unreference(obj);
4113 i915_gem_cleanup_hws(dev);
4116 ring->ring_obj = obj;
4117 ring->virtual_start = ring->map.handle;
4119 /* Stop the ring if it's running. */
4120 I915_WRITE(PRB0_CTL, 0);
4121 I915_WRITE(PRB0_TAIL, 0);
4122 I915_WRITE(PRB0_HEAD, 0);
4124 /* Initialize the ring. */
4125 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4126 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4128 /* G45 ring initialization fails to reset head to zero */
4130 DRM_ERROR("Ring head not reset to zero "
4131 "ctl %08x head %08x tail %08x start %08x\n",
4132 I915_READ(PRB0_CTL),
4133 I915_READ(PRB0_HEAD),
4134 I915_READ(PRB0_TAIL),
4135 I915_READ(PRB0_START));
4136 I915_WRITE(PRB0_HEAD, 0);
4138 DRM_ERROR("Ring head forced to zero "
4139 "ctl %08x head %08x tail %08x start %08x\n",
4140 I915_READ(PRB0_CTL),
4141 I915_READ(PRB0_HEAD),
4142 I915_READ(PRB0_TAIL),
4143 I915_READ(PRB0_START));
4146 I915_WRITE(PRB0_CTL,
4147 ((obj->size - 4096) & RING_NR_PAGES) |
4151 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4153 /* If the head is still not zero, the ring is dead */
4155 DRM_ERROR("Ring initialization failed "
4156 "ctl %08x head %08x tail %08x start %08x\n",
4157 I915_READ(PRB0_CTL),
4158 I915_READ(PRB0_HEAD),
4159 I915_READ(PRB0_TAIL),
4160 I915_READ(PRB0_START));
4164 /* Update our cache of the ring state */
4165 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4166 i915_kernel_lost_context(dev);
4168 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4169 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4170 ring->space = ring->head - (ring->tail + 8);
4171 if (ring->space < 0)
4172 ring->space += ring->Size;
4179 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4181 drm_i915_private_t *dev_priv = dev->dev_private;
4183 if (dev_priv->ring.ring_obj == NULL)
4186 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4188 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4189 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4190 dev_priv->ring.ring_obj = NULL;
4191 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4193 i915_gem_cleanup_hws(dev);
4197 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4198 struct drm_file *file_priv)
4200 drm_i915_private_t *dev_priv = dev->dev_private;
4203 if (drm_core_check_feature(dev, DRIVER_MODESET))
4206 if (atomic_read(&dev_priv->mm.wedged)) {
4207 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4208 atomic_set(&dev_priv->mm.wedged, 0);
4211 mutex_lock(&dev->struct_mutex);
4212 dev_priv->mm.suspended = 0;
4214 ret = i915_gem_init_ringbuffer(dev);
4216 mutex_unlock(&dev->struct_mutex);
4220 spin_lock(&dev_priv->mm.active_list_lock);
4221 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4222 spin_unlock(&dev_priv->mm.active_list_lock);
4224 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4225 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4226 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4227 mutex_unlock(&dev->struct_mutex);
4229 drm_irq_install(dev);
4235 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4236 struct drm_file *file_priv)
4240 if (drm_core_check_feature(dev, DRIVER_MODESET))
4243 ret = i915_gem_idle(dev);
4244 drm_irq_uninstall(dev);
4250 i915_gem_lastclose(struct drm_device *dev)
4254 if (drm_core_check_feature(dev, DRIVER_MODESET))
4257 ret = i915_gem_idle(dev);
4259 DRM_ERROR("failed to idle hardware: %d\n", ret);
4263 i915_gem_load(struct drm_device *dev)
4266 drm_i915_private_t *dev_priv = dev->dev_private;
4268 spin_lock_init(&dev_priv->mm.active_list_lock);
4269 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4270 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4271 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4272 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4273 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4274 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4275 i915_gem_retire_work_handler);
4276 dev_priv->mm.next_gem_seqno = 1;
4278 /* Old X drivers will take 0-2 for front, back, depth buffers */
4279 dev_priv->fence_reg_start = 3;
4281 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4282 dev_priv->num_fence_regs = 16;
4284 dev_priv->num_fence_regs = 8;
4286 /* Initialize fence registers to zero */
4287 if (IS_I965G(dev)) {
4288 for (i = 0; i < 16; i++)
4289 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4291 for (i = 0; i < 8; i++)
4292 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4293 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4294 for (i = 0; i < 8; i++)
4295 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4298 i915_gem_detect_bit_6_swizzle(dev);
4302 * Create a physically contiguous memory object for this object
4303 * e.g. for cursor + overlay regs
4305 int i915_gem_init_phys_object(struct drm_device *dev,
4308 drm_i915_private_t *dev_priv = dev->dev_private;
4309 struct drm_i915_gem_phys_object *phys_obj;
4312 if (dev_priv->mm.phys_objs[id - 1] || !size)
4315 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4321 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4322 if (!phys_obj->handle) {
4327 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4330 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4338 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4340 drm_i915_private_t *dev_priv = dev->dev_private;
4341 struct drm_i915_gem_phys_object *phys_obj;
4343 if (!dev_priv->mm.phys_objs[id - 1])
4346 phys_obj = dev_priv->mm.phys_objs[id - 1];
4347 if (phys_obj->cur_obj) {
4348 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4352 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4354 drm_pci_free(dev, phys_obj->handle);
4356 dev_priv->mm.phys_objs[id - 1] = NULL;
4359 void i915_gem_free_all_phys_object(struct drm_device *dev)
4363 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4364 i915_gem_free_phys_object(dev, i);
4367 void i915_gem_detach_phys_object(struct drm_device *dev,
4368 struct drm_gem_object *obj)
4370 struct drm_i915_gem_object *obj_priv;
4375 obj_priv = obj->driver_private;
4376 if (!obj_priv->phys_obj)
4379 ret = i915_gem_object_get_pages(obj);
4383 page_count = obj->size / PAGE_SIZE;
4385 for (i = 0; i < page_count; i++) {
4386 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4387 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4389 memcpy(dst, src, PAGE_SIZE);
4390 kunmap_atomic(dst, KM_USER0);
4392 drm_clflush_pages(obj_priv->pages, page_count);
4393 drm_agp_chipset_flush(dev);
4395 i915_gem_object_put_pages(obj);
4397 obj_priv->phys_obj->cur_obj = NULL;
4398 obj_priv->phys_obj = NULL;
4402 i915_gem_attach_phys_object(struct drm_device *dev,
4403 struct drm_gem_object *obj, int id)
4405 drm_i915_private_t *dev_priv = dev->dev_private;
4406 struct drm_i915_gem_object *obj_priv;
4411 if (id > I915_MAX_PHYS_OBJECT)
4414 obj_priv = obj->driver_private;
4416 if (obj_priv->phys_obj) {
4417 if (obj_priv->phys_obj->id == id)
4419 i915_gem_detach_phys_object(dev, obj);
4423 /* create a new object */
4424 if (!dev_priv->mm.phys_objs[id - 1]) {
4425 ret = i915_gem_init_phys_object(dev, id,
4428 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4433 /* bind to the object */
4434 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4435 obj_priv->phys_obj->cur_obj = obj;
4437 ret = i915_gem_object_get_pages(obj);
4439 DRM_ERROR("failed to get page list\n");
4443 page_count = obj->size / PAGE_SIZE;
4445 for (i = 0; i < page_count; i++) {
4446 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4447 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4449 memcpy(dst, src, PAGE_SIZE);
4450 kunmap_atomic(src, KM_USER0);
4453 i915_gem_object_put_pages(obj);
4461 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4462 struct drm_i915_gem_pwrite *args,
4463 struct drm_file *file_priv)
4465 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4468 char __user *user_data;
4470 user_data = (char __user *) (uintptr_t) args->data_ptr;
4471 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4473 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4474 ret = copy_from_user(obj_addr, user_data, args->size);
4478 drm_agp_chipset_flush(dev);
4482 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4484 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4486 /* Clean up our request list when the client is going away, so that
4487 * later retire_requests won't dereference our soon-to-be-gone
4490 mutex_lock(&dev->struct_mutex);
4491 while (!list_empty(&i915_file_priv->mm.request_list))
4492 list_del_init(i915_file_priv->mm.request_list.next);
4493 mutex_unlock(&dev->struct_mutex);