2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 drm_gem_object_handle_unreference_unlocked(obj);
136 args->handle = handle;
142 fast_shmem_read(struct page **pages,
143 loff_t page_base, int page_offset,
150 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
154 kunmap_atomic(vaddr, KM_USER0);
162 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
164 drm_i915_private_t *dev_priv = obj->dev->dev_private;
165 struct drm_i915_gem_object *obj_priv = obj->driver_private;
167 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
168 obj_priv->tiling_mode != I915_TILING_NONE;
172 slow_shmem_copy(struct page *dst_page,
174 struct page *src_page,
178 char *dst_vaddr, *src_vaddr;
180 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
181 if (dst_vaddr == NULL)
184 src_vaddr = kmap_atomic(src_page, KM_USER1);
185 if (src_vaddr == NULL) {
186 kunmap_atomic(dst_vaddr, KM_USER0);
190 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
192 kunmap_atomic(src_vaddr, KM_USER1);
193 kunmap_atomic(dst_vaddr, KM_USER0);
199 slow_shmem_bit17_copy(struct page *gpu_page,
201 struct page *cpu_page,
206 char *gpu_vaddr, *cpu_vaddr;
208 /* Use the unswizzled path if this page isn't affected. */
209 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
211 return slow_shmem_copy(cpu_page, cpu_offset,
212 gpu_page, gpu_offset, length);
214 return slow_shmem_copy(gpu_page, gpu_offset,
215 cpu_page, cpu_offset, length);
218 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
219 if (gpu_vaddr == NULL)
222 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
223 if (cpu_vaddr == NULL) {
224 kunmap_atomic(gpu_vaddr, KM_USER0);
228 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
229 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 int cacheline_end = ALIGN(gpu_offset + 1, 64);
233 int this_length = min(cacheline_end - gpu_offset, length);
234 int swizzled_gpu_offset = gpu_offset ^ 64;
237 memcpy(cpu_vaddr + cpu_offset,
238 gpu_vaddr + swizzled_gpu_offset,
241 memcpy(gpu_vaddr + swizzled_gpu_offset,
242 cpu_vaddr + cpu_offset,
245 cpu_offset += this_length;
246 gpu_offset += this_length;
247 length -= this_length;
250 kunmap_atomic(cpu_vaddr, KM_USER1);
251 kunmap_atomic(gpu_vaddr, KM_USER0);
257 * This is the fast shmem pread path, which attempts to copy_from_user directly
258 * from the backing pages of the object to the user's address space. On a
259 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
263 struct drm_i915_gem_pread *args,
264 struct drm_file *file_priv)
266 struct drm_i915_gem_object *obj_priv = obj->driver_private;
268 loff_t offset, page_base;
269 char __user *user_data;
270 int page_offset, page_length;
273 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 mutex_lock(&dev->struct_mutex);
278 ret = i915_gem_object_get_pages(obj, 0);
282 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
287 obj_priv = obj->driver_private;
288 offset = args->offset;
291 /* Operation in this page
293 * page_base = page offset within aperture
294 * page_offset = offset within page
295 * page_length = bytes to copy for this page
297 page_base = (offset & ~(PAGE_SIZE-1));
298 page_offset = offset & (PAGE_SIZE-1);
299 page_length = remain;
300 if ((page_offset + remain) > PAGE_SIZE)
301 page_length = PAGE_SIZE - page_offset;
303 ret = fast_shmem_read(obj_priv->pages,
304 page_base, page_offset,
305 user_data, page_length);
309 remain -= page_length;
310 user_data += page_length;
311 offset += page_length;
315 i915_gem_object_put_pages(obj);
317 mutex_unlock(&dev->struct_mutex);
323 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
327 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
329 /* If we've insufficient memory to map in the pages, attempt
330 * to make some space by throwing out some old buffers.
332 if (ret == -ENOMEM) {
333 struct drm_device *dev = obj->dev;
335 ret = i915_gem_evict_something(dev, obj->size);
339 ret = i915_gem_object_get_pages(obj, 0);
346 * This is the fallback shmem pread path, which allocates temporary storage
347 * in kernel space to copy_to_user into outside of the struct_mutex, so we
348 * can copy out of the object's backing pages while holding the struct mutex
349 * and not take page faults.
352 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
353 struct drm_i915_gem_pread *args,
354 struct drm_file *file_priv)
356 struct drm_i915_gem_object *obj_priv = obj->driver_private;
357 struct mm_struct *mm = current->mm;
358 struct page **user_pages;
360 loff_t offset, pinned_pages, i;
361 loff_t first_data_page, last_data_page, num_pages;
362 int shmem_page_index, shmem_page_offset;
363 int data_page_index, data_page_offset;
366 uint64_t data_ptr = args->data_ptr;
367 int do_bit17_swizzling;
371 /* Pin the user pages containing the data. We can't fault while
372 * holding the struct mutex, yet we want to hold it while
373 * dereferencing the user data.
375 first_data_page = data_ptr / PAGE_SIZE;
376 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
377 num_pages = last_data_page - first_data_page + 1;
379 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
380 if (user_pages == NULL)
383 down_read(&mm->mmap_sem);
384 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
385 num_pages, 1, 0, user_pages, NULL);
386 up_read(&mm->mmap_sem);
387 if (pinned_pages < num_pages) {
389 goto fail_put_user_pages;
392 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
394 mutex_lock(&dev->struct_mutex);
396 ret = i915_gem_object_get_pages_or_evict(obj);
400 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
405 obj_priv = obj->driver_private;
406 offset = args->offset;
409 /* Operation in this page
411 * shmem_page_index = page number within shmem file
412 * shmem_page_offset = offset within page in shmem file
413 * data_page_index = page number in get_user_pages return
414 * data_page_offset = offset with data_page_index page.
415 * page_length = bytes to copy for this page
417 shmem_page_index = offset / PAGE_SIZE;
418 shmem_page_offset = offset & ~PAGE_MASK;
419 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
420 data_page_offset = data_ptr & ~PAGE_MASK;
422 page_length = remain;
423 if ((shmem_page_offset + page_length) > PAGE_SIZE)
424 page_length = PAGE_SIZE - shmem_page_offset;
425 if ((data_page_offset + page_length) > PAGE_SIZE)
426 page_length = PAGE_SIZE - data_page_offset;
428 if (do_bit17_swizzling) {
429 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
431 user_pages[data_page_index],
436 ret = slow_shmem_copy(user_pages[data_page_index],
438 obj_priv->pages[shmem_page_index],
445 remain -= page_length;
446 data_ptr += page_length;
447 offset += page_length;
451 i915_gem_object_put_pages(obj);
453 mutex_unlock(&dev->struct_mutex);
455 for (i = 0; i < pinned_pages; i++) {
456 SetPageDirty(user_pages[i]);
457 page_cache_release(user_pages[i]);
459 drm_free_large(user_pages);
465 * Reads data from the object referenced by handle.
467 * On error, the contents of *data are undefined.
470 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
471 struct drm_file *file_priv)
473 struct drm_i915_gem_pread *args = data;
474 struct drm_gem_object *obj;
475 struct drm_i915_gem_object *obj_priv;
478 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
481 obj_priv = obj->driver_private;
483 /* Bounds check source.
485 * XXX: This could use review for overflow issues...
487 if (args->offset > obj->size || args->size > obj->size ||
488 args->offset + args->size > obj->size) {
489 drm_gem_object_unreference_unlocked(obj);
493 if (i915_gem_object_needs_bit17_swizzle(obj)) {
494 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
496 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
498 ret = i915_gem_shmem_pread_slow(dev, obj, args,
502 drm_gem_object_unreference_unlocked(obj);
507 /* This is the fast write path which cannot handle
508 * page faults in the source data
512 fast_user_write(struct io_mapping *mapping,
513 loff_t page_base, int page_offset,
514 char __user *user_data,
518 unsigned long unwritten;
520 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
521 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
523 io_mapping_unmap_atomic(vaddr_atomic);
529 /* Here's the write path which can sleep for
534 slow_kernel_write(struct io_mapping *mapping,
535 loff_t gtt_base, int gtt_offset,
536 struct page *user_page, int user_offset,
539 char *src_vaddr, *dst_vaddr;
540 unsigned long unwritten;
542 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
543 src_vaddr = kmap_atomic(user_page, KM_USER1);
544 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
545 src_vaddr + user_offset,
547 kunmap_atomic(src_vaddr, KM_USER1);
548 io_mapping_unmap_atomic(dst_vaddr);
555 fast_shmem_write(struct page **pages,
556 loff_t page_base, int page_offset,
561 unsigned long unwritten;
563 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
566 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
567 kunmap_atomic(vaddr, KM_USER0);
575 * This is the fast pwrite path, where we copy the data directly from the
576 * user into the GTT, uncached.
579 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
580 struct drm_i915_gem_pwrite *args,
581 struct drm_file *file_priv)
583 struct drm_i915_gem_object *obj_priv = obj->driver_private;
584 drm_i915_private_t *dev_priv = dev->dev_private;
586 loff_t offset, page_base;
587 char __user *user_data;
588 int page_offset, page_length;
591 user_data = (char __user *) (uintptr_t) args->data_ptr;
593 if (!access_ok(VERIFY_READ, user_data, remain))
597 mutex_lock(&dev->struct_mutex);
598 ret = i915_gem_object_pin(obj, 0);
600 mutex_unlock(&dev->struct_mutex);
603 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
607 obj_priv = obj->driver_private;
608 offset = obj_priv->gtt_offset + args->offset;
611 /* Operation in this page
613 * page_base = page offset within aperture
614 * page_offset = offset within page
615 * page_length = bytes to copy for this page
617 page_base = (offset & ~(PAGE_SIZE-1));
618 page_offset = offset & (PAGE_SIZE-1);
619 page_length = remain;
620 if ((page_offset + remain) > PAGE_SIZE)
621 page_length = PAGE_SIZE - page_offset;
623 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
624 page_offset, user_data, page_length);
626 /* If we get a fault while copying data, then (presumably) our
627 * source page isn't available. Return the error and we'll
628 * retry in the slow path.
633 remain -= page_length;
634 user_data += page_length;
635 offset += page_length;
639 i915_gem_object_unpin(obj);
640 mutex_unlock(&dev->struct_mutex);
646 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
647 * the memory and maps it using kmap_atomic for copying.
649 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
650 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
653 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
654 struct drm_i915_gem_pwrite *args,
655 struct drm_file *file_priv)
657 struct drm_i915_gem_object *obj_priv = obj->driver_private;
658 drm_i915_private_t *dev_priv = dev->dev_private;
660 loff_t gtt_page_base, offset;
661 loff_t first_data_page, last_data_page, num_pages;
662 loff_t pinned_pages, i;
663 struct page **user_pages;
664 struct mm_struct *mm = current->mm;
665 int gtt_page_offset, data_page_offset, data_page_index, page_length;
667 uint64_t data_ptr = args->data_ptr;
671 /* Pin the user pages containing the data. We can't fault while
672 * holding the struct mutex, and all of the pwrite implementations
673 * want to hold it while dereferencing the user data.
675 first_data_page = data_ptr / PAGE_SIZE;
676 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
677 num_pages = last_data_page - first_data_page + 1;
679 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
680 if (user_pages == NULL)
683 down_read(&mm->mmap_sem);
684 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
685 num_pages, 0, 0, user_pages, NULL);
686 up_read(&mm->mmap_sem);
687 if (pinned_pages < num_pages) {
689 goto out_unpin_pages;
692 mutex_lock(&dev->struct_mutex);
693 ret = i915_gem_object_pin(obj, 0);
697 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
699 goto out_unpin_object;
701 obj_priv = obj->driver_private;
702 offset = obj_priv->gtt_offset + args->offset;
705 /* Operation in this page
707 * gtt_page_base = page offset within aperture
708 * gtt_page_offset = offset within page in aperture
709 * data_page_index = page number in get_user_pages return
710 * data_page_offset = offset with data_page_index page.
711 * page_length = bytes to copy for this page
713 gtt_page_base = offset & PAGE_MASK;
714 gtt_page_offset = offset & ~PAGE_MASK;
715 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
716 data_page_offset = data_ptr & ~PAGE_MASK;
718 page_length = remain;
719 if ((gtt_page_offset + page_length) > PAGE_SIZE)
720 page_length = PAGE_SIZE - gtt_page_offset;
721 if ((data_page_offset + page_length) > PAGE_SIZE)
722 page_length = PAGE_SIZE - data_page_offset;
724 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
725 gtt_page_base, gtt_page_offset,
726 user_pages[data_page_index],
730 /* If we get a fault while copying data, then (presumably) our
731 * source page isn't available. Return the error and we'll
732 * retry in the slow path.
735 goto out_unpin_object;
737 remain -= page_length;
738 offset += page_length;
739 data_ptr += page_length;
743 i915_gem_object_unpin(obj);
745 mutex_unlock(&dev->struct_mutex);
747 for (i = 0; i < pinned_pages; i++)
748 page_cache_release(user_pages[i]);
749 drm_free_large(user_pages);
755 * This is the fast shmem pwrite path, which attempts to directly
756 * copy_from_user into the kmapped pages backing the object.
759 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
760 struct drm_i915_gem_pwrite *args,
761 struct drm_file *file_priv)
763 struct drm_i915_gem_object *obj_priv = obj->driver_private;
765 loff_t offset, page_base;
766 char __user *user_data;
767 int page_offset, page_length;
770 user_data = (char __user *) (uintptr_t) args->data_ptr;
773 mutex_lock(&dev->struct_mutex);
775 ret = i915_gem_object_get_pages(obj, 0);
779 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
783 obj_priv = obj->driver_private;
784 offset = args->offset;
788 /* Operation in this page
790 * page_base = page offset within aperture
791 * page_offset = offset within page
792 * page_length = bytes to copy for this page
794 page_base = (offset & ~(PAGE_SIZE-1));
795 page_offset = offset & (PAGE_SIZE-1);
796 page_length = remain;
797 if ((page_offset + remain) > PAGE_SIZE)
798 page_length = PAGE_SIZE - page_offset;
800 ret = fast_shmem_write(obj_priv->pages,
801 page_base, page_offset,
802 user_data, page_length);
806 remain -= page_length;
807 user_data += page_length;
808 offset += page_length;
812 i915_gem_object_put_pages(obj);
814 mutex_unlock(&dev->struct_mutex);
820 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
821 * the memory and maps it using kmap_atomic for copying.
823 * This avoids taking mmap_sem for faulting on the user's address while the
824 * struct_mutex is held.
827 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
828 struct drm_i915_gem_pwrite *args,
829 struct drm_file *file_priv)
831 struct drm_i915_gem_object *obj_priv = obj->driver_private;
832 struct mm_struct *mm = current->mm;
833 struct page **user_pages;
835 loff_t offset, pinned_pages, i;
836 loff_t first_data_page, last_data_page, num_pages;
837 int shmem_page_index, shmem_page_offset;
838 int data_page_index, data_page_offset;
841 uint64_t data_ptr = args->data_ptr;
842 int do_bit17_swizzling;
846 /* Pin the user pages containing the data. We can't fault while
847 * holding the struct mutex, and all of the pwrite implementations
848 * want to hold it while dereferencing the user data.
850 first_data_page = data_ptr / PAGE_SIZE;
851 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
852 num_pages = last_data_page - first_data_page + 1;
854 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
855 if (user_pages == NULL)
858 down_read(&mm->mmap_sem);
859 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
860 num_pages, 0, 0, user_pages, NULL);
861 up_read(&mm->mmap_sem);
862 if (pinned_pages < num_pages) {
864 goto fail_put_user_pages;
867 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
869 mutex_lock(&dev->struct_mutex);
871 ret = i915_gem_object_get_pages_or_evict(obj);
875 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
879 obj_priv = obj->driver_private;
880 offset = args->offset;
884 /* Operation in this page
886 * shmem_page_index = page number within shmem file
887 * shmem_page_offset = offset within page in shmem file
888 * data_page_index = page number in get_user_pages return
889 * data_page_offset = offset with data_page_index page.
890 * page_length = bytes to copy for this page
892 shmem_page_index = offset / PAGE_SIZE;
893 shmem_page_offset = offset & ~PAGE_MASK;
894 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
895 data_page_offset = data_ptr & ~PAGE_MASK;
897 page_length = remain;
898 if ((shmem_page_offset + page_length) > PAGE_SIZE)
899 page_length = PAGE_SIZE - shmem_page_offset;
900 if ((data_page_offset + page_length) > PAGE_SIZE)
901 page_length = PAGE_SIZE - data_page_offset;
903 if (do_bit17_swizzling) {
904 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
906 user_pages[data_page_index],
911 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
913 user_pages[data_page_index],
920 remain -= page_length;
921 data_ptr += page_length;
922 offset += page_length;
926 i915_gem_object_put_pages(obj);
928 mutex_unlock(&dev->struct_mutex);
930 for (i = 0; i < pinned_pages; i++)
931 page_cache_release(user_pages[i]);
932 drm_free_large(user_pages);
938 * Writes data to the object referenced by handle.
940 * On error, the contents of the buffer that were to be modified are undefined.
943 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
944 struct drm_file *file_priv)
946 struct drm_i915_gem_pwrite *args = data;
947 struct drm_gem_object *obj;
948 struct drm_i915_gem_object *obj_priv;
951 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
954 obj_priv = obj->driver_private;
956 /* Bounds check destination.
958 * XXX: This could use review for overflow issues...
960 if (args->offset > obj->size || args->size > obj->size ||
961 args->offset + args->size > obj->size) {
962 drm_gem_object_unreference_unlocked(obj);
966 /* We can only do the GTT pwrite on untiled buffers, as otherwise
967 * it would end up going through the fenced access, and we'll get
968 * different detiling behavior between reading and writing.
969 * pread/pwrite currently are reading and writing from the CPU
970 * perspective, requiring manual detiling by the client.
972 if (obj_priv->phys_obj)
973 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
974 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
975 dev->gtt_total != 0) {
976 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
977 if (ret == -EFAULT) {
978 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
981 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
982 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
984 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
985 if (ret == -EFAULT) {
986 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
993 DRM_INFO("pwrite failed %d\n", ret);
996 drm_gem_object_unreference_unlocked(obj);
1002 * Called when user space prepares to use an object with the CPU, either
1003 * through the mmap ioctl's mapping or a GTT mapping.
1006 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1007 struct drm_file *file_priv)
1009 struct drm_i915_private *dev_priv = dev->dev_private;
1010 struct drm_i915_gem_set_domain *args = data;
1011 struct drm_gem_object *obj;
1012 struct drm_i915_gem_object *obj_priv;
1013 uint32_t read_domains = args->read_domains;
1014 uint32_t write_domain = args->write_domain;
1017 if (!(dev->driver->driver_features & DRIVER_GEM))
1020 /* Only handle setting domains to types used by the CPU. */
1021 if (write_domain & I915_GEM_GPU_DOMAINS)
1024 if (read_domains & I915_GEM_GPU_DOMAINS)
1027 /* Having something in the write domain implies it's in the read
1028 * domain, and only that read domain. Enforce that in the request.
1030 if (write_domain != 0 && read_domains != write_domain)
1033 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1036 obj_priv = obj->driver_private;
1038 mutex_lock(&dev->struct_mutex);
1040 intel_mark_busy(dev, obj);
1043 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1044 obj, obj->size, read_domains, write_domain);
1046 if (read_domains & I915_GEM_DOMAIN_GTT) {
1047 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1049 /* Update the LRU on the fence for the CPU access that's
1052 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1053 list_move_tail(&obj_priv->fence_list,
1054 &dev_priv->mm.fence_list);
1057 /* Silently promote "you're not bound, there was nothing to do"
1058 * to success, since the client was just asking us to
1059 * make sure everything was done.
1064 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1067 drm_gem_object_unreference(obj);
1068 mutex_unlock(&dev->struct_mutex);
1073 * Called when user space has done writes to this buffer
1076 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv)
1079 struct drm_i915_gem_sw_finish *args = data;
1080 struct drm_gem_object *obj;
1081 struct drm_i915_gem_object *obj_priv;
1084 if (!(dev->driver->driver_features & DRIVER_GEM))
1087 mutex_lock(&dev->struct_mutex);
1088 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1090 mutex_unlock(&dev->struct_mutex);
1095 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1096 __func__, args->handle, obj, obj->size);
1098 obj_priv = obj->driver_private;
1100 /* Pinned buffers may be scanout, so flush the cache */
1101 if (obj_priv->pin_count)
1102 i915_gem_object_flush_cpu_write_domain(obj);
1104 drm_gem_object_unreference(obj);
1105 mutex_unlock(&dev->struct_mutex);
1110 * Maps the contents of an object, returning the address it is mapped
1113 * While the mapping holds a reference on the contents of the object, it doesn't
1114 * imply a ref on the object itself.
1117 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1118 struct drm_file *file_priv)
1120 struct drm_i915_gem_mmap *args = data;
1121 struct drm_gem_object *obj;
1125 if (!(dev->driver->driver_features & DRIVER_GEM))
1128 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1132 offset = args->offset;
1134 down_write(¤t->mm->mmap_sem);
1135 addr = do_mmap(obj->filp, 0, args->size,
1136 PROT_READ | PROT_WRITE, MAP_SHARED,
1138 up_write(¤t->mm->mmap_sem);
1139 drm_gem_object_unreference_unlocked(obj);
1140 if (IS_ERR((void *)addr))
1143 args->addr_ptr = (uint64_t) addr;
1149 * i915_gem_fault - fault a page into the GTT
1150 * vma: VMA in question
1153 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1154 * from userspace. The fault handler takes care of binding the object to
1155 * the GTT (if needed), allocating and programming a fence register (again,
1156 * only if needed based on whether the old reg is still valid or the object
1157 * is tiled) and inserting a new PTE into the faulting process.
1159 * Note that the faulting process may involve evicting existing objects
1160 * from the GTT and/or fence registers to make room. So performance may
1161 * suffer if the GTT working set is large or there are few fence registers
1164 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1166 struct drm_gem_object *obj = vma->vm_private_data;
1167 struct drm_device *dev = obj->dev;
1168 struct drm_i915_private *dev_priv = dev->dev_private;
1169 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1170 pgoff_t page_offset;
1173 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1175 /* We don't use vmf->pgoff since that has the fake offset */
1176 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1179 /* Now bind it into the GTT if needed */
1180 mutex_lock(&dev->struct_mutex);
1181 if (!obj_priv->gtt_space) {
1182 ret = i915_gem_object_bind_to_gtt(obj, 0);
1186 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1188 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1193 /* Need a new fence register? */
1194 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1195 ret = i915_gem_object_get_fence_reg(obj);
1200 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1203 /* Finally, remap it using the new GTT offset */
1204 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1206 mutex_unlock(&dev->struct_mutex);
1211 return VM_FAULT_NOPAGE;
1214 return VM_FAULT_OOM;
1216 return VM_FAULT_SIGBUS;
1221 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1222 * @obj: obj in question
1224 * GEM memory mapping works by handing back to userspace a fake mmap offset
1225 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1226 * up the object based on the offset and sets up the various memory mapping
1229 * This routine allocates and attaches a fake offset for @obj.
1232 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1234 struct drm_device *dev = obj->dev;
1235 struct drm_gem_mm *mm = dev->mm_private;
1236 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1237 struct drm_map_list *list;
1238 struct drm_local_map *map;
1241 /* Set the object up for mmap'ing */
1242 list = &obj->map_list;
1243 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1248 map->type = _DRM_GEM;
1249 map->size = obj->size;
1252 /* Get a DRM GEM mmap offset allocated... */
1253 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1254 obj->size / PAGE_SIZE, 0, 0);
1255 if (!list->file_offset_node) {
1256 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1261 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1262 obj->size / PAGE_SIZE, 0);
1263 if (!list->file_offset_node) {
1268 list->hash.key = list->file_offset_node->start;
1269 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1270 DRM_ERROR("failed to add to map hash\n");
1275 /* By now we should be all set, any drm_mmap request on the offset
1276 * below will get to our mmap & fault handler */
1277 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1282 drm_mm_put_block(list->file_offset_node);
1290 * i915_gem_release_mmap - remove physical page mappings
1291 * @obj: obj in question
1293 * Preserve the reservation of the mmapping with the DRM core code, but
1294 * relinquish ownership of the pages back to the system.
1296 * It is vital that we remove the page mapping if we have mapped a tiled
1297 * object through the GTT and then lose the fence register due to
1298 * resource pressure. Similarly if the object has been moved out of the
1299 * aperture, than pages mapped into userspace must be revoked. Removing the
1300 * mapping will then trigger a page fault on the next user access, allowing
1301 * fixup by i915_gem_fault().
1304 i915_gem_release_mmap(struct drm_gem_object *obj)
1306 struct drm_device *dev = obj->dev;
1307 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1309 if (dev->dev_mapping)
1310 unmap_mapping_range(dev->dev_mapping,
1311 obj_priv->mmap_offset, obj->size, 1);
1315 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1317 struct drm_device *dev = obj->dev;
1318 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1319 struct drm_gem_mm *mm = dev->mm_private;
1320 struct drm_map_list *list;
1322 list = &obj->map_list;
1323 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1325 if (list->file_offset_node) {
1326 drm_mm_put_block(list->file_offset_node);
1327 list->file_offset_node = NULL;
1335 obj_priv->mmap_offset = 0;
1339 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1340 * @obj: object to check
1342 * Return the required GTT alignment for an object, taking into account
1343 * potential fence register mapping if needed.
1346 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1348 struct drm_device *dev = obj->dev;
1349 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1353 * Minimum alignment is 4k (GTT page size), but might be greater
1354 * if a fence register is needed for the object.
1356 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1360 * Previous chips need to be aligned to the size of the smallest
1361 * fence register that can contain the object.
1368 for (i = start; i < obj->size; i <<= 1)
1375 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1377 * @data: GTT mapping ioctl data
1378 * @file_priv: GEM object info
1380 * Simply returns the fake offset to userspace so it can mmap it.
1381 * The mmap call will end up in drm_gem_mmap(), which will set things
1382 * up so we can get faults in the handler above.
1384 * The fault handler will take care of binding the object into the GTT
1385 * (since it may have been evicted to make room for something), allocating
1386 * a fence register, and mapping the appropriate aperture address into
1390 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1391 struct drm_file *file_priv)
1393 struct drm_i915_gem_mmap_gtt *args = data;
1394 struct drm_i915_private *dev_priv = dev->dev_private;
1395 struct drm_gem_object *obj;
1396 struct drm_i915_gem_object *obj_priv;
1399 if (!(dev->driver->driver_features & DRIVER_GEM))
1402 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1406 mutex_lock(&dev->struct_mutex);
1408 obj_priv = obj->driver_private;
1410 if (obj_priv->madv != I915_MADV_WILLNEED) {
1411 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1412 drm_gem_object_unreference(obj);
1413 mutex_unlock(&dev->struct_mutex);
1418 if (!obj_priv->mmap_offset) {
1419 ret = i915_gem_create_mmap_offset(obj);
1421 drm_gem_object_unreference(obj);
1422 mutex_unlock(&dev->struct_mutex);
1427 args->offset = obj_priv->mmap_offset;
1430 * Pull it into the GTT so that we have a page list (makes the
1431 * initial fault faster and any subsequent flushing possible).
1433 if (!obj_priv->agp_mem) {
1434 ret = i915_gem_object_bind_to_gtt(obj, 0);
1436 drm_gem_object_unreference(obj);
1437 mutex_unlock(&dev->struct_mutex);
1440 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1443 drm_gem_object_unreference(obj);
1444 mutex_unlock(&dev->struct_mutex);
1450 i915_gem_object_put_pages(struct drm_gem_object *obj)
1452 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1453 int page_count = obj->size / PAGE_SIZE;
1456 BUG_ON(obj_priv->pages_refcount == 0);
1457 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1459 if (--obj_priv->pages_refcount != 0)
1462 if (obj_priv->tiling_mode != I915_TILING_NONE)
1463 i915_gem_object_save_bit_17_swizzle(obj);
1465 if (obj_priv->madv == I915_MADV_DONTNEED)
1466 obj_priv->dirty = 0;
1468 for (i = 0; i < page_count; i++) {
1469 if (obj_priv->pages[i] == NULL)
1472 if (obj_priv->dirty)
1473 set_page_dirty(obj_priv->pages[i]);
1475 if (obj_priv->madv == I915_MADV_WILLNEED)
1476 mark_page_accessed(obj_priv->pages[i]);
1478 page_cache_release(obj_priv->pages[i]);
1480 obj_priv->dirty = 0;
1482 drm_free_large(obj_priv->pages);
1483 obj_priv->pages = NULL;
1487 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1489 struct drm_device *dev = obj->dev;
1490 drm_i915_private_t *dev_priv = dev->dev_private;
1491 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1493 /* Add a reference if we're newly entering the active list. */
1494 if (!obj_priv->active) {
1495 drm_gem_object_reference(obj);
1496 obj_priv->active = 1;
1498 /* Move from whatever list we were on to the tail of execution. */
1499 spin_lock(&dev_priv->mm.active_list_lock);
1500 list_move_tail(&obj_priv->list,
1501 &dev_priv->mm.active_list);
1502 spin_unlock(&dev_priv->mm.active_list_lock);
1503 obj_priv->last_rendering_seqno = seqno;
1507 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1509 struct drm_device *dev = obj->dev;
1510 drm_i915_private_t *dev_priv = dev->dev_private;
1511 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1513 BUG_ON(!obj_priv->active);
1514 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1515 obj_priv->last_rendering_seqno = 0;
1518 /* Immediately discard the backing storage */
1520 i915_gem_object_truncate(struct drm_gem_object *obj)
1522 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1523 struct inode *inode;
1525 inode = obj->filp->f_path.dentry->d_inode;
1526 if (inode->i_op->truncate)
1527 inode->i_op->truncate (inode);
1529 obj_priv->madv = __I915_MADV_PURGED;
1533 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1535 return obj_priv->madv == I915_MADV_DONTNEED;
1539 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1541 struct drm_device *dev = obj->dev;
1542 drm_i915_private_t *dev_priv = dev->dev_private;
1543 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1545 i915_verify_inactive(dev, __FILE__, __LINE__);
1546 if (obj_priv->pin_count != 0)
1547 list_del_init(&obj_priv->list);
1549 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1551 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1553 obj_priv->last_rendering_seqno = 0;
1554 if (obj_priv->active) {
1555 obj_priv->active = 0;
1556 drm_gem_object_unreference(obj);
1558 i915_verify_inactive(dev, __FILE__, __LINE__);
1562 i915_gem_process_flushing_list(struct drm_device *dev,
1563 uint32_t flush_domains, uint32_t seqno)
1565 drm_i915_private_t *dev_priv = dev->dev_private;
1566 struct drm_i915_gem_object *obj_priv, *next;
1568 list_for_each_entry_safe(obj_priv, next,
1569 &dev_priv->mm.gpu_write_list,
1571 struct drm_gem_object *obj = obj_priv->obj;
1573 if ((obj->write_domain & flush_domains) ==
1574 obj->write_domain) {
1575 uint32_t old_write_domain = obj->write_domain;
1577 obj->write_domain = 0;
1578 list_del_init(&obj_priv->gpu_write_list);
1579 i915_gem_object_move_to_active(obj, seqno);
1581 /* update the fence lru list */
1582 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1583 list_move_tail(&obj_priv->fence_list,
1584 &dev_priv->mm.fence_list);
1586 trace_i915_gem_object_change_domain(obj,
1594 * Creates a new sequence number, emitting a write of it to the status page
1595 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1597 * Must be called with struct_lock held.
1599 * Returned sequence numbers are nonzero on success.
1602 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1603 uint32_t flush_domains)
1605 drm_i915_private_t *dev_priv = dev->dev_private;
1606 struct drm_i915_file_private *i915_file_priv = NULL;
1607 struct drm_i915_gem_request *request;
1612 if (file_priv != NULL)
1613 i915_file_priv = file_priv->driver_priv;
1615 request = kzalloc(sizeof(*request), GFP_KERNEL);
1616 if (request == NULL)
1619 /* Grab the seqno we're going to make this request be, and bump the
1620 * next (skipping 0 so it can be the reserved no-seqno value).
1622 seqno = dev_priv->mm.next_gem_seqno;
1623 dev_priv->mm.next_gem_seqno++;
1624 if (dev_priv->mm.next_gem_seqno == 0)
1625 dev_priv->mm.next_gem_seqno++;
1628 OUT_RING(MI_STORE_DWORD_INDEX);
1629 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1632 OUT_RING(MI_USER_INTERRUPT);
1635 DRM_DEBUG_DRIVER("%d\n", seqno);
1637 request->seqno = seqno;
1638 request->emitted_jiffies = jiffies;
1639 was_empty = list_empty(&dev_priv->mm.request_list);
1640 list_add_tail(&request->list, &dev_priv->mm.request_list);
1641 if (i915_file_priv) {
1642 list_add_tail(&request->client_list,
1643 &i915_file_priv->mm.request_list);
1645 INIT_LIST_HEAD(&request->client_list);
1648 /* Associate any objects on the flushing list matching the write
1649 * domain we're flushing with our flush.
1651 if (flush_domains != 0)
1652 i915_gem_process_flushing_list(dev, flush_domains, seqno);
1654 if (!dev_priv->mm.suspended) {
1655 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1657 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1663 * Command execution barrier
1665 * Ensures that all commands in the ring are finished
1666 * before signalling the CPU
1669 i915_retire_commands(struct drm_device *dev)
1671 drm_i915_private_t *dev_priv = dev->dev_private;
1672 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1673 uint32_t flush_domains = 0;
1676 /* The sampler always gets flushed on i965 (sigh) */
1678 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1681 OUT_RING(0); /* noop */
1683 return flush_domains;
1687 * Moves buffers associated only with the given active seqno from the active
1688 * to inactive list, potentially freeing them.
1691 i915_gem_retire_request(struct drm_device *dev,
1692 struct drm_i915_gem_request *request)
1694 drm_i915_private_t *dev_priv = dev->dev_private;
1696 trace_i915_gem_request_retire(dev, request->seqno);
1698 /* Move any buffers on the active list that are no longer referenced
1699 * by the ringbuffer to the flushing/inactive lists as appropriate.
1701 spin_lock(&dev_priv->mm.active_list_lock);
1702 while (!list_empty(&dev_priv->mm.active_list)) {
1703 struct drm_gem_object *obj;
1704 struct drm_i915_gem_object *obj_priv;
1706 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1707 struct drm_i915_gem_object,
1709 obj = obj_priv->obj;
1711 /* If the seqno being retired doesn't match the oldest in the
1712 * list, then the oldest in the list must still be newer than
1715 if (obj_priv->last_rendering_seqno != request->seqno)
1719 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1720 __func__, request->seqno, obj);
1723 if (obj->write_domain != 0)
1724 i915_gem_object_move_to_flushing(obj);
1726 /* Take a reference on the object so it won't be
1727 * freed while the spinlock is held. The list
1728 * protection for this spinlock is safe when breaking
1729 * the lock like this since the next thing we do
1730 * is just get the head of the list again.
1732 drm_gem_object_reference(obj);
1733 i915_gem_object_move_to_inactive(obj);
1734 spin_unlock(&dev_priv->mm.active_list_lock);
1735 drm_gem_object_unreference(obj);
1736 spin_lock(&dev_priv->mm.active_list_lock);
1740 spin_unlock(&dev_priv->mm.active_list_lock);
1744 * Returns true if seq1 is later than seq2.
1747 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1749 return (int32_t)(seq1 - seq2) >= 0;
1753 i915_get_gem_seqno(struct drm_device *dev)
1755 drm_i915_private_t *dev_priv = dev->dev_private;
1757 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1761 * This function clears the request list as sequence numbers are passed.
1764 i915_gem_retire_requests(struct drm_device *dev)
1766 drm_i915_private_t *dev_priv = dev->dev_private;
1769 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1772 seqno = i915_get_gem_seqno(dev);
1774 while (!list_empty(&dev_priv->mm.request_list)) {
1775 struct drm_i915_gem_request *request;
1776 uint32_t retiring_seqno;
1778 request = list_first_entry(&dev_priv->mm.request_list,
1779 struct drm_i915_gem_request,
1781 retiring_seqno = request->seqno;
1783 if (i915_seqno_passed(seqno, retiring_seqno) ||
1784 atomic_read(&dev_priv->mm.wedged)) {
1785 i915_gem_retire_request(dev, request);
1787 list_del(&request->list);
1788 list_del(&request->client_list);
1794 if (unlikely (dev_priv->trace_irq_seqno &&
1795 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1796 i915_user_irq_put(dev);
1797 dev_priv->trace_irq_seqno = 0;
1802 i915_gem_retire_work_handler(struct work_struct *work)
1804 drm_i915_private_t *dev_priv;
1805 struct drm_device *dev;
1807 dev_priv = container_of(work, drm_i915_private_t,
1808 mm.retire_work.work);
1809 dev = dev_priv->dev;
1811 mutex_lock(&dev->struct_mutex);
1812 i915_gem_retire_requests(dev);
1813 if (!dev_priv->mm.suspended &&
1814 !list_empty(&dev_priv->mm.request_list))
1815 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1816 mutex_unlock(&dev->struct_mutex);
1820 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1822 drm_i915_private_t *dev_priv = dev->dev_private;
1828 if (atomic_read(&dev_priv->mm.wedged))
1831 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1832 if (HAS_PCH_SPLIT(dev))
1833 ier = I915_READ(DEIER) | I915_READ(GTIER);
1835 ier = I915_READ(IER);
1837 DRM_ERROR("something (likely vbetool) disabled "
1838 "interrupts, re-enabling\n");
1839 i915_driver_irq_preinstall(dev);
1840 i915_driver_irq_postinstall(dev);
1843 trace_i915_gem_request_wait_begin(dev, seqno);
1845 dev_priv->mm.waiting_gem_seqno = seqno;
1846 i915_user_irq_get(dev);
1848 ret = wait_event_interruptible(dev_priv->irq_queue,
1849 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1850 atomic_read(&dev_priv->mm.wedged));
1852 wait_event(dev_priv->irq_queue,
1853 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1854 atomic_read(&dev_priv->mm.wedged));
1856 i915_user_irq_put(dev);
1857 dev_priv->mm.waiting_gem_seqno = 0;
1859 trace_i915_gem_request_wait_end(dev, seqno);
1861 if (atomic_read(&dev_priv->mm.wedged))
1864 if (ret && ret != -ERESTARTSYS)
1865 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1866 __func__, ret, seqno, i915_get_gem_seqno(dev));
1868 /* Directly dispatch request retiring. While we have the work queue
1869 * to handle this, the waiter on a request often wants an associated
1870 * buffer to have made it to the inactive list, and we would need
1871 * a separate wait queue to handle that.
1874 i915_gem_retire_requests(dev);
1880 * Waits for a sequence number to be signaled, and cleans up the
1881 * request and object lists appropriately for that event.
1884 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1886 return i915_do_wait_request(dev, seqno, 1);
1890 i915_gem_flush(struct drm_device *dev,
1891 uint32_t invalidate_domains,
1892 uint32_t flush_domains)
1894 drm_i915_private_t *dev_priv = dev->dev_private;
1899 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1900 invalidate_domains, flush_domains);
1902 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1903 invalidate_domains, flush_domains);
1905 if (flush_domains & I915_GEM_DOMAIN_CPU)
1906 drm_agp_chipset_flush(dev);
1908 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1910 * read/write caches:
1912 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1913 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1914 * also flushed at 2d versus 3d pipeline switches.
1918 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1919 * MI_READ_FLUSH is set, and is always flushed on 965.
1921 * I915_GEM_DOMAIN_COMMAND may not exist?
1923 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1924 * invalidated when MI_EXE_FLUSH is set.
1926 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1927 * invalidated with every MI_FLUSH.
1931 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1932 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1933 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1934 * are flushed at any MI_FLUSH.
1937 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1938 if ((invalidate_domains|flush_domains) &
1939 I915_GEM_DOMAIN_RENDER)
1940 cmd &= ~MI_NO_WRITE_FLUSH;
1941 if (!IS_I965G(dev)) {
1943 * On the 965, the sampler cache always gets flushed
1944 * and this bit is reserved.
1946 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1947 cmd |= MI_READ_FLUSH;
1949 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1950 cmd |= MI_EXE_FLUSH;
1953 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1963 * Ensures that all rendering to the object has completed and the object is
1964 * safe to unbind from the GTT or access from the CPU.
1967 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1969 struct drm_device *dev = obj->dev;
1970 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1973 /* This function only exists to support waiting for existing rendering,
1974 * not for emitting required flushes.
1976 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1978 /* If there is rendering queued on the buffer being evicted, wait for
1981 if (obj_priv->active) {
1983 DRM_INFO("%s: object %p wait for seqno %08x\n",
1984 __func__, obj, obj_priv->last_rendering_seqno);
1986 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1995 * Unbinds an object from the GTT aperture.
1998 i915_gem_object_unbind(struct drm_gem_object *obj)
2000 struct drm_device *dev = obj->dev;
2001 drm_i915_private_t *dev_priv = dev->dev_private;
2002 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2006 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2007 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2009 if (obj_priv->gtt_space == NULL)
2012 if (obj_priv->pin_count != 0) {
2013 DRM_ERROR("Attempting to unbind pinned buffer\n");
2017 /* blow away mappings if mapped through GTT */
2018 i915_gem_release_mmap(obj);
2020 /* Move the object to the CPU domain to ensure that
2021 * any possible CPU writes while it's not in the GTT
2022 * are flushed when we go to remap it. This will
2023 * also ensure that all pending GPU writes are finished
2026 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2028 if (ret != -ERESTARTSYS)
2029 DRM_ERROR("set_domain failed: %d\n", ret);
2033 BUG_ON(obj_priv->active);
2035 /* release the fence reg _after_ flushing */
2036 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2037 i915_gem_clear_fence_reg(obj);
2039 if (obj_priv->agp_mem != NULL) {
2040 drm_unbind_agp(obj_priv->agp_mem);
2041 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2042 obj_priv->agp_mem = NULL;
2045 i915_gem_object_put_pages(obj);
2046 BUG_ON(obj_priv->pages_refcount);
2048 if (obj_priv->gtt_space) {
2049 atomic_dec(&dev->gtt_count);
2050 atomic_sub(obj->size, &dev->gtt_memory);
2052 drm_mm_put_block(obj_priv->gtt_space);
2053 obj_priv->gtt_space = NULL;
2056 /* Remove ourselves from the LRU list if present. */
2057 spin_lock(&dev_priv->mm.active_list_lock);
2058 if (!list_empty(&obj_priv->list))
2059 list_del_init(&obj_priv->list);
2060 spin_unlock(&dev_priv->mm.active_list_lock);
2062 if (i915_gem_object_is_purgeable(obj_priv))
2063 i915_gem_object_truncate(obj);
2065 trace_i915_gem_object_unbind(obj);
2070 static struct drm_gem_object *
2071 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2073 drm_i915_private_t *dev_priv = dev->dev_private;
2074 struct drm_i915_gem_object *obj_priv;
2075 struct drm_gem_object *best = NULL;
2076 struct drm_gem_object *first = NULL;
2078 /* Try to find the smallest clean object */
2079 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2080 struct drm_gem_object *obj = obj_priv->obj;
2081 if (obj->size >= min_size) {
2082 if ((!obj_priv->dirty ||
2083 i915_gem_object_is_purgeable(obj_priv)) &&
2084 (!best || obj->size < best->size)) {
2086 if (best->size == min_size)
2094 return best ? best : first;
2098 i915_gpu_idle(struct drm_device *dev)
2100 drm_i915_private_t *dev_priv = dev->dev_private;
2104 spin_lock(&dev_priv->mm.active_list_lock);
2105 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
2106 list_empty(&dev_priv->mm.active_list);
2107 spin_unlock(&dev_priv->mm.active_list_lock);
2112 /* Flush everything onto the inactive list. */
2113 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2114 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2118 return i915_wait_request(dev, seqno);
2122 i915_gem_evict_everything(struct drm_device *dev)
2124 drm_i915_private_t *dev_priv = dev->dev_private;
2128 spin_lock(&dev_priv->mm.active_list_lock);
2129 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2130 list_empty(&dev_priv->mm.flushing_list) &&
2131 list_empty(&dev_priv->mm.active_list));
2132 spin_unlock(&dev_priv->mm.active_list_lock);
2137 /* Flush everything (on to the inactive lists) and evict */
2138 ret = i915_gpu_idle(dev);
2142 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2144 ret = i915_gem_evict_from_inactive_list(dev);
2148 spin_lock(&dev_priv->mm.active_list_lock);
2149 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2150 list_empty(&dev_priv->mm.flushing_list) &&
2151 list_empty(&dev_priv->mm.active_list));
2152 spin_unlock(&dev_priv->mm.active_list_lock);
2153 BUG_ON(!lists_empty);
2159 i915_gem_evict_something(struct drm_device *dev, int min_size)
2161 drm_i915_private_t *dev_priv = dev->dev_private;
2162 struct drm_gem_object *obj;
2166 i915_gem_retire_requests(dev);
2168 /* If there's an inactive buffer available now, grab it
2171 obj = i915_gem_find_inactive_object(dev, min_size);
2173 struct drm_i915_gem_object *obj_priv;
2176 DRM_INFO("%s: evicting %p\n", __func__, obj);
2178 obj_priv = obj->driver_private;
2179 BUG_ON(obj_priv->pin_count != 0);
2180 BUG_ON(obj_priv->active);
2182 /* Wait on the rendering and unbind the buffer. */
2183 return i915_gem_object_unbind(obj);
2186 /* If we didn't get anything, but the ring is still processing
2187 * things, wait for the next to finish and hopefully leave us
2188 * a buffer to evict.
2190 if (!list_empty(&dev_priv->mm.request_list)) {
2191 struct drm_i915_gem_request *request;
2193 request = list_first_entry(&dev_priv->mm.request_list,
2194 struct drm_i915_gem_request,
2197 ret = i915_wait_request(dev, request->seqno);
2204 /* If we didn't have anything on the request list but there
2205 * are buffers awaiting a flush, emit one and try again.
2206 * When we wait on it, those buffers waiting for that flush
2207 * will get moved to inactive.
2209 if (!list_empty(&dev_priv->mm.flushing_list)) {
2210 struct drm_i915_gem_object *obj_priv;
2212 /* Find an object that we can immediately reuse */
2213 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2214 obj = obj_priv->obj;
2215 if (obj->size >= min_size)
2227 seqno = i915_add_request(dev, NULL, obj->write_domain);
2231 ret = i915_wait_request(dev, seqno);
2239 /* If we didn't do any of the above, there's no single buffer
2240 * large enough to swap out for the new one, so just evict
2241 * everything and start again. (This should be rare.)
2243 if (!list_empty (&dev_priv->mm.inactive_list))
2244 return i915_gem_evict_from_inactive_list(dev);
2246 return i915_gem_evict_everything(dev);
2251 i915_gem_object_get_pages(struct drm_gem_object *obj,
2254 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2256 struct address_space *mapping;
2257 struct inode *inode;
2261 if (obj_priv->pages_refcount++ != 0)
2264 /* Get the list of pages out of our struct file. They'll be pinned
2265 * at this point until we release them.
2267 page_count = obj->size / PAGE_SIZE;
2268 BUG_ON(obj_priv->pages != NULL);
2269 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2270 if (obj_priv->pages == NULL) {
2271 obj_priv->pages_refcount--;
2275 inode = obj->filp->f_path.dentry->d_inode;
2276 mapping = inode->i_mapping;
2277 for (i = 0; i < page_count; i++) {
2278 page = read_cache_page_gfp(mapping, i,
2279 mapping_gfp_mask (mapping) |
2283 ret = PTR_ERR(page);
2284 i915_gem_object_put_pages(obj);
2287 obj_priv->pages[i] = page;
2290 if (obj_priv->tiling_mode != I915_TILING_NONE)
2291 i915_gem_object_do_bit_17_swizzle(obj);
2296 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2298 struct drm_gem_object *obj = reg->obj;
2299 struct drm_device *dev = obj->dev;
2300 drm_i915_private_t *dev_priv = dev->dev_private;
2301 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2302 int regnum = obj_priv->fence_reg;
2305 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2307 val |= obj_priv->gtt_offset & 0xfffff000;
2308 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2309 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2311 if (obj_priv->tiling_mode == I915_TILING_Y)
2312 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2313 val |= I965_FENCE_REG_VALID;
2315 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2318 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2320 struct drm_gem_object *obj = reg->obj;
2321 struct drm_device *dev = obj->dev;
2322 drm_i915_private_t *dev_priv = dev->dev_private;
2323 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2324 int regnum = obj_priv->fence_reg;
2327 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2329 val |= obj_priv->gtt_offset & 0xfffff000;
2330 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2331 if (obj_priv->tiling_mode == I915_TILING_Y)
2332 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2333 val |= I965_FENCE_REG_VALID;
2335 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2338 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2340 struct drm_gem_object *obj = reg->obj;
2341 struct drm_device *dev = obj->dev;
2342 drm_i915_private_t *dev_priv = dev->dev_private;
2343 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2344 int regnum = obj_priv->fence_reg;
2346 uint32_t fence_reg, val;
2349 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2350 (obj_priv->gtt_offset & (obj->size - 1))) {
2351 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2352 __func__, obj_priv->gtt_offset, obj->size);
2356 if (obj_priv->tiling_mode == I915_TILING_Y &&
2357 HAS_128_BYTE_Y_TILING(dev))
2362 /* Note: pitch better be a power of two tile widths */
2363 pitch_val = obj_priv->stride / tile_width;
2364 pitch_val = ffs(pitch_val) - 1;
2366 val = obj_priv->gtt_offset;
2367 if (obj_priv->tiling_mode == I915_TILING_Y)
2368 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2369 val |= I915_FENCE_SIZE_BITS(obj->size);
2370 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2371 val |= I830_FENCE_REG_VALID;
2374 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2376 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2377 I915_WRITE(fence_reg, val);
2380 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2382 struct drm_gem_object *obj = reg->obj;
2383 struct drm_device *dev = obj->dev;
2384 drm_i915_private_t *dev_priv = dev->dev_private;
2385 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2386 int regnum = obj_priv->fence_reg;
2389 uint32_t fence_size_bits;
2391 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2392 (obj_priv->gtt_offset & (obj->size - 1))) {
2393 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2394 __func__, obj_priv->gtt_offset);
2398 pitch_val = obj_priv->stride / 128;
2399 pitch_val = ffs(pitch_val) - 1;
2400 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2402 val = obj_priv->gtt_offset;
2403 if (obj_priv->tiling_mode == I915_TILING_Y)
2404 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2405 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2406 WARN_ON(fence_size_bits & ~0x00000f00);
2407 val |= fence_size_bits;
2408 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2409 val |= I830_FENCE_REG_VALID;
2411 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2414 static int i915_find_fence_reg(struct drm_device *dev)
2416 struct drm_i915_fence_reg *reg = NULL;
2417 struct drm_i915_gem_object *obj_priv = NULL;
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 struct drm_gem_object *obj = NULL;
2422 /* First try to find a free reg */
2424 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2425 reg = &dev_priv->fence_regs[i];
2429 obj_priv = reg->obj->driver_private;
2430 if (!obj_priv->pin_count)
2437 /* None available, try to steal one or wait for a user to finish */
2438 i = I915_FENCE_REG_NONE;
2439 list_for_each_entry(obj_priv, &dev_priv->mm.fence_list,
2441 obj = obj_priv->obj;
2443 if (obj_priv->pin_count)
2447 i = obj_priv->fence_reg;
2451 BUG_ON(i == I915_FENCE_REG_NONE);
2453 /* We only have a reference on obj from the active list. put_fence_reg
2454 * might drop that one, causing a use-after-free in it. So hold a
2455 * private reference to obj like the other callers of put_fence_reg
2456 * (set_tiling ioctl) do. */
2457 drm_gem_object_reference(obj);
2458 ret = i915_gem_object_put_fence_reg(obj);
2459 drm_gem_object_unreference(obj);
2467 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2468 * @obj: object to map through a fence reg
2470 * When mapping objects through the GTT, userspace wants to be able to write
2471 * to them without having to worry about swizzling if the object is tiled.
2473 * This function walks the fence regs looking for a free one for @obj,
2474 * stealing one if it can't find any.
2476 * It then sets up the reg based on the object's properties: address, pitch
2477 * and tiling format.
2480 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2482 struct drm_device *dev = obj->dev;
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2485 struct drm_i915_fence_reg *reg = NULL;
2488 /* Just update our place in the LRU if our fence is getting used. */
2489 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2490 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2494 switch (obj_priv->tiling_mode) {
2495 case I915_TILING_NONE:
2496 WARN(1, "allocating a fence for non-tiled object?\n");
2499 if (!obj_priv->stride)
2501 WARN((obj_priv->stride & (512 - 1)),
2502 "object 0x%08x is X tiled but has non-512B pitch\n",
2503 obj_priv->gtt_offset);
2506 if (!obj_priv->stride)
2508 WARN((obj_priv->stride & (128 - 1)),
2509 "object 0x%08x is Y tiled but has non-128B pitch\n",
2510 obj_priv->gtt_offset);
2514 ret = i915_find_fence_reg(dev);
2518 obj_priv->fence_reg = ret;
2519 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2520 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2525 sandybridge_write_fence_reg(reg);
2526 else if (IS_I965G(dev))
2527 i965_write_fence_reg(reg);
2528 else if (IS_I9XX(dev))
2529 i915_write_fence_reg(reg);
2531 i830_write_fence_reg(reg);
2533 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2534 obj_priv->tiling_mode);
2540 * i915_gem_clear_fence_reg - clear out fence register info
2541 * @obj: object to clear
2543 * Zeroes out the fence register itself and clears out the associated
2544 * data structures in dev_priv and obj_priv.
2547 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2549 struct drm_device *dev = obj->dev;
2550 drm_i915_private_t *dev_priv = dev->dev_private;
2551 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2554 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2555 (obj_priv->fence_reg * 8), 0);
2556 } else if (IS_I965G(dev)) {
2557 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2561 if (obj_priv->fence_reg < 8)
2562 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2564 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2567 I915_WRITE(fence_reg, 0);
2570 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2571 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2572 list_del_init(&obj_priv->fence_list);
2576 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2577 * to the buffer to finish, and then resets the fence register.
2578 * @obj: tiled object holding a fence register.
2580 * Zeroes out the fence register itself and clears out the associated
2581 * data structures in dev_priv and obj_priv.
2584 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2586 struct drm_device *dev = obj->dev;
2587 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2589 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2592 /* If we've changed tiling, GTT-mappings of the object
2593 * need to re-fault to ensure that the correct fence register
2594 * setup is in place.
2596 i915_gem_release_mmap(obj);
2598 /* On the i915, GPU access to tiled buffers is via a fence,
2599 * therefore we must wait for any outstanding access to complete
2600 * before clearing the fence.
2602 if (!IS_I965G(dev)) {
2605 i915_gem_object_flush_gpu_write_domain(obj);
2606 ret = i915_gem_object_wait_rendering(obj);
2611 i915_gem_object_flush_gtt_write_domain(obj);
2612 i915_gem_clear_fence_reg (obj);
2618 * Finds free space in the GTT aperture and binds the object there.
2621 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2623 struct drm_device *dev = obj->dev;
2624 drm_i915_private_t *dev_priv = dev->dev_private;
2625 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2626 struct drm_mm_node *free_space;
2627 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2630 if (obj_priv->madv != I915_MADV_WILLNEED) {
2631 DRM_ERROR("Attempting to bind a purgeable object\n");
2636 alignment = i915_gem_get_gtt_alignment(obj);
2637 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2638 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2643 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2644 obj->size, alignment, 0);
2645 if (free_space != NULL) {
2646 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2648 if (obj_priv->gtt_space != NULL) {
2649 obj_priv->gtt_space->private = obj;
2650 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2653 if (obj_priv->gtt_space == NULL) {
2654 /* If the gtt is empty and we're still having trouble
2655 * fitting our object in, we're out of memory.
2658 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2660 ret = i915_gem_evict_something(dev, obj->size);
2668 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2669 obj->size, obj_priv->gtt_offset);
2671 ret = i915_gem_object_get_pages(obj, gfpmask);
2673 drm_mm_put_block(obj_priv->gtt_space);
2674 obj_priv->gtt_space = NULL;
2676 if (ret == -ENOMEM) {
2677 /* first try to clear up some space from the GTT */
2678 ret = i915_gem_evict_something(dev, obj->size);
2680 /* now try to shrink everyone else */
2695 /* Create an AGP memory structure pointing at our pages, and bind it
2698 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2700 obj->size >> PAGE_SHIFT,
2701 obj_priv->gtt_offset,
2702 obj_priv->agp_type);
2703 if (obj_priv->agp_mem == NULL) {
2704 i915_gem_object_put_pages(obj);
2705 drm_mm_put_block(obj_priv->gtt_space);
2706 obj_priv->gtt_space = NULL;
2708 ret = i915_gem_evict_something(dev, obj->size);
2714 atomic_inc(&dev->gtt_count);
2715 atomic_add(obj->size, &dev->gtt_memory);
2717 /* Assert that the object is not currently in any GPU domain. As it
2718 * wasn't in the GTT, there shouldn't be any way it could have been in
2721 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2722 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2724 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2730 i915_gem_clflush_object(struct drm_gem_object *obj)
2732 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2734 /* If we don't have a page list set up, then we're not pinned
2735 * to GPU, and we can ignore the cache flush because it'll happen
2736 * again at bind time.
2738 if (obj_priv->pages == NULL)
2741 trace_i915_gem_object_clflush(obj);
2743 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2746 /** Flushes any GPU write domain for the object if it's dirty. */
2748 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2750 struct drm_device *dev = obj->dev;
2752 uint32_t old_write_domain;
2754 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2757 /* Queue the GPU write cache flushing we need. */
2758 old_write_domain = obj->write_domain;
2759 i915_gem_flush(dev, 0, obj->write_domain);
2760 seqno = i915_add_request(dev, NULL, obj->write_domain);
2761 BUG_ON(obj->write_domain);
2762 i915_gem_object_move_to_active(obj, seqno);
2764 trace_i915_gem_object_change_domain(obj,
2769 /** Flushes the GTT write domain for the object if it's dirty. */
2771 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2773 uint32_t old_write_domain;
2775 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2778 /* No actual flushing is required for the GTT write domain. Writes
2779 * to it immediately go to main memory as far as we know, so there's
2780 * no chipset flush. It also doesn't land in render cache.
2782 old_write_domain = obj->write_domain;
2783 obj->write_domain = 0;
2785 trace_i915_gem_object_change_domain(obj,
2790 /** Flushes the CPU write domain for the object if it's dirty. */
2792 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2794 struct drm_device *dev = obj->dev;
2795 uint32_t old_write_domain;
2797 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2800 i915_gem_clflush_object(obj);
2801 drm_agp_chipset_flush(dev);
2802 old_write_domain = obj->write_domain;
2803 obj->write_domain = 0;
2805 trace_i915_gem_object_change_domain(obj,
2811 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2813 switch (obj->write_domain) {
2814 case I915_GEM_DOMAIN_GTT:
2815 i915_gem_object_flush_gtt_write_domain(obj);
2817 case I915_GEM_DOMAIN_CPU:
2818 i915_gem_object_flush_cpu_write_domain(obj);
2821 i915_gem_object_flush_gpu_write_domain(obj);
2827 * Moves a single object to the GTT read, and possibly write domain.
2829 * This function returns when the move is complete, including waiting on
2833 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2835 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2836 uint32_t old_write_domain, old_read_domains;
2839 /* Not valid to be called on unbound objects. */
2840 if (obj_priv->gtt_space == NULL)
2843 i915_gem_object_flush_gpu_write_domain(obj);
2844 /* Wait on any GPU rendering and flushing to occur. */
2845 ret = i915_gem_object_wait_rendering(obj);
2849 old_write_domain = obj->write_domain;
2850 old_read_domains = obj->read_domains;
2852 /* If we're writing through the GTT domain, then CPU and GPU caches
2853 * will need to be invalidated at next use.
2856 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2858 i915_gem_object_flush_cpu_write_domain(obj);
2860 /* It should now be out of any other write domains, and we can update
2861 * the domain values for our changes.
2863 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2864 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2866 obj->write_domain = I915_GEM_DOMAIN_GTT;
2867 obj_priv->dirty = 1;
2870 trace_i915_gem_object_change_domain(obj,
2878 * Prepare buffer for display plane. Use uninterruptible for possible flush
2879 * wait, as in modesetting process we're not supposed to be interrupted.
2882 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2884 struct drm_device *dev = obj->dev;
2885 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2886 uint32_t old_write_domain, old_read_domains;
2889 /* Not valid to be called on unbound objects. */
2890 if (obj_priv->gtt_space == NULL)
2893 i915_gem_object_flush_gpu_write_domain(obj);
2895 /* Wait on any GPU rendering and flushing to occur. */
2896 if (obj_priv->active) {
2898 DRM_INFO("%s: object %p wait for seqno %08x\n",
2899 __func__, obj, obj_priv->last_rendering_seqno);
2901 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2906 old_write_domain = obj->write_domain;
2907 old_read_domains = obj->read_domains;
2909 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2911 i915_gem_object_flush_cpu_write_domain(obj);
2913 /* It should now be out of any other write domains, and we can update
2914 * the domain values for our changes.
2916 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2917 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2918 obj->write_domain = I915_GEM_DOMAIN_GTT;
2919 obj_priv->dirty = 1;
2921 trace_i915_gem_object_change_domain(obj,
2929 * Moves a single object to the CPU read, and possibly write domain.
2931 * This function returns when the move is complete, including waiting on
2935 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2937 uint32_t old_write_domain, old_read_domains;
2940 i915_gem_object_flush_gpu_write_domain(obj);
2941 /* Wait on any GPU rendering and flushing to occur. */
2942 ret = i915_gem_object_wait_rendering(obj);
2946 i915_gem_object_flush_gtt_write_domain(obj);
2948 /* If we have a partially-valid cache of the object in the CPU,
2949 * finish invalidating it and free the per-page flags.
2951 i915_gem_object_set_to_full_cpu_read_domain(obj);
2953 old_write_domain = obj->write_domain;
2954 old_read_domains = obj->read_domains;
2956 /* Flush the CPU cache if it's still invalid. */
2957 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2958 i915_gem_clflush_object(obj);
2960 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2963 /* It should now be out of any other write domains, and we can update
2964 * the domain values for our changes.
2966 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2968 /* If we're writing through the CPU, then the GPU read domains will
2969 * need to be invalidated at next use.
2972 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2973 obj->write_domain = I915_GEM_DOMAIN_CPU;
2976 trace_i915_gem_object_change_domain(obj,
2984 * Set the next domain for the specified object. This
2985 * may not actually perform the necessary flushing/invaliding though,
2986 * as that may want to be batched with other set_domain operations
2988 * This is (we hope) the only really tricky part of gem. The goal
2989 * is fairly simple -- track which caches hold bits of the object
2990 * and make sure they remain coherent. A few concrete examples may
2991 * help to explain how it works. For shorthand, we use the notation
2992 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2993 * a pair of read and write domain masks.
2995 * Case 1: the batch buffer
3001 * 5. Unmapped from GTT
3004 * Let's take these a step at a time
3007 * Pages allocated from the kernel may still have
3008 * cache contents, so we set them to (CPU, CPU) always.
3009 * 2. Written by CPU (using pwrite)
3010 * The pwrite function calls set_domain (CPU, CPU) and
3011 * this function does nothing (as nothing changes)
3013 * This function asserts that the object is not
3014 * currently in any GPU-based read or write domains
3016 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3017 * As write_domain is zero, this function adds in the
3018 * current read domains (CPU+COMMAND, 0).
3019 * flush_domains is set to CPU.
3020 * invalidate_domains is set to COMMAND
3021 * clflush is run to get data out of the CPU caches
3022 * then i915_dev_set_domain calls i915_gem_flush to
3023 * emit an MI_FLUSH and drm_agp_chipset_flush
3024 * 5. Unmapped from GTT
3025 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3026 * flush_domains and invalidate_domains end up both zero
3027 * so no flushing/invalidating happens
3031 * Case 2: The shared render buffer
3035 * 3. Read/written by GPU
3036 * 4. set_domain to (CPU,CPU)
3037 * 5. Read/written by CPU
3038 * 6. Read/written by GPU
3041 * Same as last example, (CPU, CPU)
3043 * Nothing changes (assertions find that it is not in the GPU)
3044 * 3. Read/written by GPU
3045 * execbuffer calls set_domain (RENDER, RENDER)
3046 * flush_domains gets CPU
3047 * invalidate_domains gets GPU
3049 * MI_FLUSH and drm_agp_chipset_flush
3050 * 4. set_domain (CPU, CPU)
3051 * flush_domains gets GPU
3052 * invalidate_domains gets CPU
3053 * wait_rendering (obj) to make sure all drawing is complete.
3054 * This will include an MI_FLUSH to get the data from GPU
3056 * clflush (obj) to invalidate the CPU cache
3057 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3058 * 5. Read/written by CPU
3059 * cache lines are loaded and dirtied
3060 * 6. Read written by GPU
3061 * Same as last GPU access
3063 * Case 3: The constant buffer
3068 * 4. Updated (written) by CPU again
3077 * flush_domains = CPU
3078 * invalidate_domains = RENDER
3081 * drm_agp_chipset_flush
3082 * 4. Updated (written) by CPU again
3084 * flush_domains = 0 (no previous write domain)
3085 * invalidate_domains = 0 (no new read domains)
3088 * flush_domains = CPU
3089 * invalidate_domains = RENDER
3092 * drm_agp_chipset_flush
3095 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3097 struct drm_device *dev = obj->dev;
3098 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3099 uint32_t invalidate_domains = 0;
3100 uint32_t flush_domains = 0;
3101 uint32_t old_read_domains;
3103 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3104 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3106 intel_mark_busy(dev, obj);
3109 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3111 obj->read_domains, obj->pending_read_domains,
3112 obj->write_domain, obj->pending_write_domain);
3115 * If the object isn't moving to a new write domain,
3116 * let the object stay in multiple read domains
3118 if (obj->pending_write_domain == 0)
3119 obj->pending_read_domains |= obj->read_domains;
3121 obj_priv->dirty = 1;
3124 * Flush the current write domain if
3125 * the new read domains don't match. Invalidate
3126 * any read domains which differ from the old
3129 if (obj->write_domain &&
3130 obj->write_domain != obj->pending_read_domains) {
3131 flush_domains |= obj->write_domain;
3132 invalidate_domains |=
3133 obj->pending_read_domains & ~obj->write_domain;
3136 * Invalidate any read caches which may have
3137 * stale data. That is, any new read domains.
3139 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3140 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3142 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3143 __func__, flush_domains, invalidate_domains);
3145 i915_gem_clflush_object(obj);
3148 old_read_domains = obj->read_domains;
3150 /* The actual obj->write_domain will be updated with
3151 * pending_write_domain after we emit the accumulated flush for all
3152 * of our domain changes in execbuffers (which clears objects'
3153 * write_domains). So if we have a current write domain that we
3154 * aren't changing, set pending_write_domain to that.
3156 if (flush_domains == 0 && obj->pending_write_domain == 0)
3157 obj->pending_write_domain = obj->write_domain;
3158 obj->read_domains = obj->pending_read_domains;
3160 dev->invalidate_domains |= invalidate_domains;
3161 dev->flush_domains |= flush_domains;
3163 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3165 obj->read_domains, obj->write_domain,
3166 dev->invalidate_domains, dev->flush_domains);
3169 trace_i915_gem_object_change_domain(obj,
3175 * Moves the object from a partially CPU read to a full one.
3177 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3178 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3181 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3183 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3185 if (!obj_priv->page_cpu_valid)
3188 /* If we're partially in the CPU read domain, finish moving it in.
3190 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3193 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3194 if (obj_priv->page_cpu_valid[i])
3196 drm_clflush_pages(obj_priv->pages + i, 1);
3200 /* Free the page_cpu_valid mappings which are now stale, whether
3201 * or not we've got I915_GEM_DOMAIN_CPU.
3203 kfree(obj_priv->page_cpu_valid);
3204 obj_priv->page_cpu_valid = NULL;
3208 * Set the CPU read domain on a range of the object.
3210 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3211 * not entirely valid. The page_cpu_valid member of the object flags which
3212 * pages have been flushed, and will be respected by
3213 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3214 * of the whole object.
3216 * This function returns when the move is complete, including waiting on
3220 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3221 uint64_t offset, uint64_t size)
3223 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3224 uint32_t old_read_domains;
3227 if (offset == 0 && size == obj->size)
3228 return i915_gem_object_set_to_cpu_domain(obj, 0);
3230 i915_gem_object_flush_gpu_write_domain(obj);
3231 /* Wait on any GPU rendering and flushing to occur. */
3232 ret = i915_gem_object_wait_rendering(obj);
3235 i915_gem_object_flush_gtt_write_domain(obj);
3237 /* If we're already fully in the CPU read domain, we're done. */
3238 if (obj_priv->page_cpu_valid == NULL &&
3239 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3242 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3243 * newly adding I915_GEM_DOMAIN_CPU
3245 if (obj_priv->page_cpu_valid == NULL) {
3246 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3248 if (obj_priv->page_cpu_valid == NULL)
3250 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3251 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3253 /* Flush the cache on any pages that are still invalid from the CPU's
3256 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3258 if (obj_priv->page_cpu_valid[i])
3261 drm_clflush_pages(obj_priv->pages + i, 1);
3263 obj_priv->page_cpu_valid[i] = 1;
3266 /* It should now be out of any other write domains, and we can update
3267 * the domain values for our changes.
3269 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3271 old_read_domains = obj->read_domains;
3272 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3274 trace_i915_gem_object_change_domain(obj,
3282 * Pin an object to the GTT and evaluate the relocations landing in it.
3285 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3286 struct drm_file *file_priv,
3287 struct drm_i915_gem_exec_object2 *entry,
3288 struct drm_i915_gem_relocation_entry *relocs)
3290 struct drm_device *dev = obj->dev;
3291 drm_i915_private_t *dev_priv = dev->dev_private;
3292 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3294 void __iomem *reloc_page;
3297 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3298 obj_priv->tiling_mode != I915_TILING_NONE;
3300 /* Check fence reg constraints and rebind if necessary */
3301 if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3302 obj_priv->tiling_mode))
3303 i915_gem_object_unbind(obj);
3305 /* Choose the GTT offset for our buffer and put it there. */
3306 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3311 * Pre-965 chips need a fence register set up in order to
3312 * properly handle blits to/from tiled surfaces.
3315 ret = i915_gem_object_get_fence_reg(obj);
3317 if (ret != -EBUSY && ret != -ERESTARTSYS)
3318 DRM_ERROR("Failure to install fence: %d\n",
3320 i915_gem_object_unpin(obj);
3325 entry->offset = obj_priv->gtt_offset;
3327 /* Apply the relocations, using the GTT aperture to avoid cache
3328 * flushing requirements.
3330 for (i = 0; i < entry->relocation_count; i++) {
3331 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3332 struct drm_gem_object *target_obj;
3333 struct drm_i915_gem_object *target_obj_priv;
3334 uint32_t reloc_val, reloc_offset;
3335 uint32_t __iomem *reloc_entry;
3337 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3338 reloc->target_handle);
3339 if (target_obj == NULL) {
3340 i915_gem_object_unpin(obj);
3343 target_obj_priv = target_obj->driver_private;
3346 DRM_INFO("%s: obj %p offset %08x target %d "
3347 "read %08x write %08x gtt %08x "
3348 "presumed %08x delta %08x\n",
3351 (int) reloc->offset,
3352 (int) reloc->target_handle,
3353 (int) reloc->read_domains,
3354 (int) reloc->write_domain,
3355 (int) target_obj_priv->gtt_offset,
3356 (int) reloc->presumed_offset,
3360 /* The target buffer should have appeared before us in the
3361 * exec_object list, so it should have a GTT space bound by now.
3363 if (target_obj_priv->gtt_space == NULL) {
3364 DRM_ERROR("No GTT space found for object %d\n",
3365 reloc->target_handle);
3366 drm_gem_object_unreference(target_obj);
3367 i915_gem_object_unpin(obj);
3371 /* Validate that the target is in a valid r/w GPU domain */
3372 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3373 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3374 DRM_ERROR("reloc with read/write CPU domains: "
3375 "obj %p target %d offset %d "
3376 "read %08x write %08x",
3377 obj, reloc->target_handle,
3378 (int) reloc->offset,
3379 reloc->read_domains,
3380 reloc->write_domain);
3381 drm_gem_object_unreference(target_obj);
3382 i915_gem_object_unpin(obj);
3385 if (reloc->write_domain && target_obj->pending_write_domain &&
3386 reloc->write_domain != target_obj->pending_write_domain) {
3387 DRM_ERROR("Write domain conflict: "
3388 "obj %p target %d offset %d "
3389 "new %08x old %08x\n",
3390 obj, reloc->target_handle,
3391 (int) reloc->offset,
3392 reloc->write_domain,
3393 target_obj->pending_write_domain);
3394 drm_gem_object_unreference(target_obj);
3395 i915_gem_object_unpin(obj);
3399 target_obj->pending_read_domains |= reloc->read_domains;
3400 target_obj->pending_write_domain |= reloc->write_domain;
3402 /* If the relocation already has the right value in it, no
3403 * more work needs to be done.
3405 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3406 drm_gem_object_unreference(target_obj);
3410 /* Check that the relocation address is valid... */
3411 if (reloc->offset > obj->size - 4) {
3412 DRM_ERROR("Relocation beyond object bounds: "
3413 "obj %p target %d offset %d size %d.\n",
3414 obj, reloc->target_handle,
3415 (int) reloc->offset, (int) obj->size);
3416 drm_gem_object_unreference(target_obj);
3417 i915_gem_object_unpin(obj);
3420 if (reloc->offset & 3) {
3421 DRM_ERROR("Relocation not 4-byte aligned: "
3422 "obj %p target %d offset %d.\n",
3423 obj, reloc->target_handle,
3424 (int) reloc->offset);
3425 drm_gem_object_unreference(target_obj);
3426 i915_gem_object_unpin(obj);
3430 /* and points to somewhere within the target object. */
3431 if (reloc->delta >= target_obj->size) {
3432 DRM_ERROR("Relocation beyond target object bounds: "
3433 "obj %p target %d delta %d size %d.\n",
3434 obj, reloc->target_handle,
3435 (int) reloc->delta, (int) target_obj->size);
3436 drm_gem_object_unreference(target_obj);
3437 i915_gem_object_unpin(obj);
3441 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3443 drm_gem_object_unreference(target_obj);
3444 i915_gem_object_unpin(obj);
3448 /* Map the page containing the relocation we're going to
3451 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3452 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3455 reloc_entry = (uint32_t __iomem *)(reloc_page +
3456 (reloc_offset & (PAGE_SIZE - 1)));
3457 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3460 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3461 obj, (unsigned int) reloc->offset,
3462 readl(reloc_entry), reloc_val);
3464 writel(reloc_val, reloc_entry);
3465 io_mapping_unmap_atomic(reloc_page);
3467 /* The updated presumed offset for this entry will be
3468 * copied back out to the user.
3470 reloc->presumed_offset = target_obj_priv->gtt_offset;
3472 drm_gem_object_unreference(target_obj);
3477 i915_gem_dump_object(obj, 128, __func__, ~0);
3482 /** Dispatch a batchbuffer to the ring
3485 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3486 struct drm_i915_gem_execbuffer2 *exec,
3487 struct drm_clip_rect *cliprects,
3488 uint64_t exec_offset)
3490 drm_i915_private_t *dev_priv = dev->dev_private;
3491 int nbox = exec->num_cliprects;
3493 uint32_t exec_start, exec_len;
3496 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3497 exec_len = (uint32_t) exec->batch_len;
3499 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3501 count = nbox ? nbox : 1;
3503 for (i = 0; i < count; i++) {
3505 int ret = i915_emit_box(dev, cliprects, i,
3506 exec->DR1, exec->DR4);
3511 if (IS_I830(dev) || IS_845G(dev)) {
3513 OUT_RING(MI_BATCH_BUFFER);
3514 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3515 OUT_RING(exec_start + exec_len - 4);
3520 if (IS_I965G(dev)) {
3521 OUT_RING(MI_BATCH_BUFFER_START |
3523 MI_BATCH_NON_SECURE_I965);
3524 OUT_RING(exec_start);
3526 OUT_RING(MI_BATCH_BUFFER_START |
3528 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3534 /* XXX breadcrumb */
3538 /* Throttle our rendering by waiting until the ring has completed our requests
3539 * emitted over 20 msec ago.
3541 * Note that if we were to use the current jiffies each time around the loop,
3542 * we wouldn't escape the function with any frames outstanding if the time to
3543 * render a frame was over 20ms.
3545 * This should get us reasonable parallelism between CPU and GPU but also
3546 * relatively low latency when blocking on a particular request to finish.
3549 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3551 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3553 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3555 mutex_lock(&dev->struct_mutex);
3556 while (!list_empty(&i915_file_priv->mm.request_list)) {
3557 struct drm_i915_gem_request *request;
3559 request = list_first_entry(&i915_file_priv->mm.request_list,
3560 struct drm_i915_gem_request,
3563 if (time_after_eq(request->emitted_jiffies, recent_enough))
3566 ret = i915_wait_request(dev, request->seqno);
3570 mutex_unlock(&dev->struct_mutex);
3576 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3577 uint32_t buffer_count,
3578 struct drm_i915_gem_relocation_entry **relocs)
3580 uint32_t reloc_count = 0, reloc_index = 0, i;
3584 for (i = 0; i < buffer_count; i++) {
3585 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3587 reloc_count += exec_list[i].relocation_count;
3590 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3591 if (*relocs == NULL) {
3592 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3596 for (i = 0; i < buffer_count; i++) {
3597 struct drm_i915_gem_relocation_entry __user *user_relocs;
3599 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3601 ret = copy_from_user(&(*relocs)[reloc_index],
3603 exec_list[i].relocation_count *
3606 drm_free_large(*relocs);
3611 reloc_index += exec_list[i].relocation_count;
3618 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3619 uint32_t buffer_count,
3620 struct drm_i915_gem_relocation_entry *relocs)
3622 uint32_t reloc_count = 0, i;
3628 for (i = 0; i < buffer_count; i++) {
3629 struct drm_i915_gem_relocation_entry __user *user_relocs;
3632 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3634 unwritten = copy_to_user(user_relocs,
3635 &relocs[reloc_count],
3636 exec_list[i].relocation_count *
3644 reloc_count += exec_list[i].relocation_count;
3648 drm_free_large(relocs);
3654 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3655 uint64_t exec_offset)
3657 uint32_t exec_start, exec_len;
3659 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3660 exec_len = (uint32_t) exec->batch_len;
3662 if ((exec_start | exec_len) & 0x7)
3672 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3673 struct drm_gem_object **object_list,
3676 drm_i915_private_t *dev_priv = dev->dev_private;
3677 struct drm_i915_gem_object *obj_priv;
3682 prepare_to_wait(&dev_priv->pending_flip_queue,
3683 &wait, TASK_INTERRUPTIBLE);
3684 for (i = 0; i < count; i++) {
3685 obj_priv = object_list[i]->driver_private;
3686 if (atomic_read(&obj_priv->pending_flip) > 0)
3692 if (!signal_pending(current)) {
3693 mutex_unlock(&dev->struct_mutex);
3695 mutex_lock(&dev->struct_mutex);
3701 finish_wait(&dev_priv->pending_flip_queue, &wait);
3707 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3708 struct drm_file *file_priv,
3709 struct drm_i915_gem_execbuffer2 *args,
3710 struct drm_i915_gem_exec_object2 *exec_list)
3712 drm_i915_private_t *dev_priv = dev->dev_private;
3713 struct drm_gem_object **object_list = NULL;
3714 struct drm_gem_object *batch_obj;
3715 struct drm_i915_gem_object *obj_priv;
3716 struct drm_clip_rect *cliprects = NULL;
3717 struct drm_i915_gem_relocation_entry *relocs = NULL;
3718 int ret = 0, ret2, i, pinned = 0;
3719 uint64_t exec_offset;
3720 uint32_t seqno, flush_domains, reloc_index;
3721 int pin_tries, flips;
3724 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3725 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3728 if (args->buffer_count < 1) {
3729 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3732 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3733 if (object_list == NULL) {
3734 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3735 args->buffer_count);
3740 if (args->num_cliprects != 0) {
3741 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3743 if (cliprects == NULL) {
3748 ret = copy_from_user(cliprects,
3749 (struct drm_clip_rect __user *)
3750 (uintptr_t) args->cliprects_ptr,
3751 sizeof(*cliprects) * args->num_cliprects);
3753 DRM_ERROR("copy %d cliprects failed: %d\n",
3754 args->num_cliprects, ret);
3759 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3764 mutex_lock(&dev->struct_mutex);
3766 i915_verify_inactive(dev, __FILE__, __LINE__);
3768 if (atomic_read(&dev_priv->mm.wedged)) {
3769 mutex_unlock(&dev->struct_mutex);
3774 if (dev_priv->mm.suspended) {
3775 mutex_unlock(&dev->struct_mutex);
3780 /* Look up object handles */
3782 for (i = 0; i < args->buffer_count; i++) {
3783 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3784 exec_list[i].handle);
3785 if (object_list[i] == NULL) {
3786 DRM_ERROR("Invalid object handle %d at index %d\n",
3787 exec_list[i].handle, i);
3788 /* prevent error path from reading uninitialized data */
3789 args->buffer_count = i + 1;
3794 obj_priv = object_list[i]->driver_private;
3795 if (obj_priv->in_execbuffer) {
3796 DRM_ERROR("Object %p appears more than once in object list\n",
3798 /* prevent error path from reading uninitialized data */
3799 args->buffer_count = i + 1;
3803 obj_priv->in_execbuffer = true;
3804 flips += atomic_read(&obj_priv->pending_flip);
3808 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3809 args->buffer_count);
3814 /* Pin and relocate */
3815 for (pin_tries = 0; ; pin_tries++) {
3819 for (i = 0; i < args->buffer_count; i++) {
3820 object_list[i]->pending_read_domains = 0;
3821 object_list[i]->pending_write_domain = 0;
3822 ret = i915_gem_object_pin_and_relocate(object_list[i],
3825 &relocs[reloc_index]);
3829 reloc_index += exec_list[i].relocation_count;
3835 /* error other than GTT full, or we've already tried again */
3836 if (ret != -ENOSPC || pin_tries >= 1) {
3837 if (ret != -ERESTARTSYS) {
3838 unsigned long long total_size = 0;
3839 for (i = 0; i < args->buffer_count; i++)
3840 total_size += object_list[i]->size;
3841 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3842 pinned+1, args->buffer_count,
3844 DRM_ERROR("%d objects [%d pinned], "
3845 "%d object bytes [%d pinned], "
3846 "%d/%d gtt bytes\n",
3847 atomic_read(&dev->object_count),
3848 atomic_read(&dev->pin_count),
3849 atomic_read(&dev->object_memory),
3850 atomic_read(&dev->pin_memory),
3851 atomic_read(&dev->gtt_memory),
3857 /* unpin all of our buffers */
3858 for (i = 0; i < pinned; i++)
3859 i915_gem_object_unpin(object_list[i]);
3862 /* evict everyone we can from the aperture */
3863 ret = i915_gem_evict_everything(dev);
3864 if (ret && ret != -ENOSPC)
3868 /* Set the pending read domains for the batch buffer to COMMAND */
3869 batch_obj = object_list[args->buffer_count-1];
3870 if (batch_obj->pending_write_domain) {
3871 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3875 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3877 /* Sanity check the batch buffer, prior to moving objects */
3878 exec_offset = exec_list[args->buffer_count - 1].offset;
3879 ret = i915_gem_check_execbuffer (args, exec_offset);
3881 DRM_ERROR("execbuf with invalid offset/length\n");
3885 i915_verify_inactive(dev, __FILE__, __LINE__);
3887 /* Zero the global flush/invalidate flags. These
3888 * will be modified as new domains are computed
3891 dev->invalidate_domains = 0;
3892 dev->flush_domains = 0;
3894 for (i = 0; i < args->buffer_count; i++) {
3895 struct drm_gem_object *obj = object_list[i];
3897 /* Compute new gpu domains and update invalidate/flush */
3898 i915_gem_object_set_to_gpu_domain(obj);
3901 i915_verify_inactive(dev, __FILE__, __LINE__);
3903 if (dev->invalidate_domains | dev->flush_domains) {
3905 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3907 dev->invalidate_domains,
3908 dev->flush_domains);
3911 dev->invalidate_domains,
3912 dev->flush_domains);
3913 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
3914 (void)i915_add_request(dev, file_priv,
3915 dev->flush_domains);
3918 for (i = 0; i < args->buffer_count; i++) {
3919 struct drm_gem_object *obj = object_list[i];
3920 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3921 uint32_t old_write_domain = obj->write_domain;
3923 obj->write_domain = obj->pending_write_domain;
3924 if (obj->write_domain)
3925 list_move_tail(&obj_priv->gpu_write_list,
3926 &dev_priv->mm.gpu_write_list);
3928 list_del_init(&obj_priv->gpu_write_list);
3930 trace_i915_gem_object_change_domain(obj,
3935 i915_verify_inactive(dev, __FILE__, __LINE__);
3938 for (i = 0; i < args->buffer_count; i++) {
3939 i915_gem_object_check_coherency(object_list[i],
3940 exec_list[i].handle);
3945 i915_gem_dump_object(batch_obj,
3951 /* Exec the batchbuffer */
3952 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3954 DRM_ERROR("dispatch failed %d\n", ret);
3959 * Ensure that the commands in the batch buffer are
3960 * finished before the interrupt fires
3962 flush_domains = i915_retire_commands(dev);
3964 i915_verify_inactive(dev, __FILE__, __LINE__);
3967 * Get a seqno representing the execution of the current buffer,
3968 * which we can wait on. We would like to mitigate these interrupts,
3969 * likely by only creating seqnos occasionally (so that we have
3970 * *some* interrupts representing completion of buffers that we can
3971 * wait on when trying to clear up gtt space).
3973 seqno = i915_add_request(dev, file_priv, flush_domains);
3975 for (i = 0; i < args->buffer_count; i++) {
3976 struct drm_gem_object *obj = object_list[i];
3978 i915_gem_object_move_to_active(obj, seqno);
3980 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3984 i915_dump_lru(dev, __func__);
3987 i915_verify_inactive(dev, __FILE__, __LINE__);
3990 for (i = 0; i < pinned; i++)
3991 i915_gem_object_unpin(object_list[i]);
3993 for (i = 0; i < args->buffer_count; i++) {
3994 if (object_list[i]) {
3995 obj_priv = object_list[i]->driver_private;
3996 obj_priv->in_execbuffer = false;
3998 drm_gem_object_unreference(object_list[i]);
4001 mutex_unlock(&dev->struct_mutex);
4004 /* Copy the updated relocations out regardless of current error
4005 * state. Failure to update the relocs would mean that the next
4006 * time userland calls execbuf, it would do so with presumed offset
4007 * state that didn't match the actual object state.
4009 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4012 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4018 drm_free_large(object_list);
4025 * Legacy execbuffer just creates an exec2 list from the original exec object
4026 * list array and passes it to the real function.
4029 i915_gem_execbuffer(struct drm_device *dev, void *data,
4030 struct drm_file *file_priv)
4032 struct drm_i915_gem_execbuffer *args = data;
4033 struct drm_i915_gem_execbuffer2 exec2;
4034 struct drm_i915_gem_exec_object *exec_list = NULL;
4035 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4039 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4040 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4043 if (args->buffer_count < 1) {
4044 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4048 /* Copy in the exec list from userland */
4049 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4050 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4051 if (exec_list == NULL || exec2_list == NULL) {
4052 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4053 args->buffer_count);
4054 drm_free_large(exec_list);
4055 drm_free_large(exec2_list);
4058 ret = copy_from_user(exec_list,
4059 (struct drm_i915_relocation_entry __user *)
4060 (uintptr_t) args->buffers_ptr,
4061 sizeof(*exec_list) * args->buffer_count);
4063 DRM_ERROR("copy %d exec entries failed %d\n",
4064 args->buffer_count, ret);
4065 drm_free_large(exec_list);
4066 drm_free_large(exec2_list);
4070 for (i = 0; i < args->buffer_count; i++) {
4071 exec2_list[i].handle = exec_list[i].handle;
4072 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4073 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4074 exec2_list[i].alignment = exec_list[i].alignment;
4075 exec2_list[i].offset = exec_list[i].offset;
4077 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4079 exec2_list[i].flags = 0;
4082 exec2.buffers_ptr = args->buffers_ptr;
4083 exec2.buffer_count = args->buffer_count;
4084 exec2.batch_start_offset = args->batch_start_offset;
4085 exec2.batch_len = args->batch_len;
4086 exec2.DR1 = args->DR1;
4087 exec2.DR4 = args->DR4;
4088 exec2.num_cliprects = args->num_cliprects;
4089 exec2.cliprects_ptr = args->cliprects_ptr;
4092 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4094 /* Copy the new buffer offsets back to the user's exec list. */
4095 for (i = 0; i < args->buffer_count; i++)
4096 exec_list[i].offset = exec2_list[i].offset;
4097 /* ... and back out to userspace */
4098 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4099 (uintptr_t) args->buffers_ptr,
4101 sizeof(*exec_list) * args->buffer_count);
4104 DRM_ERROR("failed to copy %d exec entries "
4105 "back to user (%d)\n",
4106 args->buffer_count, ret);
4110 drm_free_large(exec_list);
4111 drm_free_large(exec2_list);
4116 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4117 struct drm_file *file_priv)
4119 struct drm_i915_gem_execbuffer2 *args = data;
4120 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4124 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4125 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4128 if (args->buffer_count < 1) {
4129 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4133 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4134 if (exec2_list == NULL) {
4135 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4136 args->buffer_count);
4139 ret = copy_from_user(exec2_list,
4140 (struct drm_i915_relocation_entry __user *)
4141 (uintptr_t) args->buffers_ptr,
4142 sizeof(*exec2_list) * args->buffer_count);
4144 DRM_ERROR("copy %d exec entries failed %d\n",
4145 args->buffer_count, ret);
4146 drm_free_large(exec2_list);
4150 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4152 /* Copy the new buffer offsets back to the user's exec list. */
4153 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4154 (uintptr_t) args->buffers_ptr,
4156 sizeof(*exec2_list) * args->buffer_count);
4159 DRM_ERROR("failed to copy %d exec entries "
4160 "back to user (%d)\n",
4161 args->buffer_count, ret);
4165 drm_free_large(exec2_list);
4170 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4172 struct drm_device *dev = obj->dev;
4173 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4176 i915_verify_inactive(dev, __FILE__, __LINE__);
4177 if (obj_priv->gtt_space == NULL) {
4178 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4183 obj_priv->pin_count++;
4185 /* If the object is not active and not pending a flush,
4186 * remove it from the inactive list
4188 if (obj_priv->pin_count == 1) {
4189 atomic_inc(&dev->pin_count);
4190 atomic_add(obj->size, &dev->pin_memory);
4191 if (!obj_priv->active &&
4192 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4193 !list_empty(&obj_priv->list))
4194 list_del_init(&obj_priv->list);
4196 i915_verify_inactive(dev, __FILE__, __LINE__);
4202 i915_gem_object_unpin(struct drm_gem_object *obj)
4204 struct drm_device *dev = obj->dev;
4205 drm_i915_private_t *dev_priv = dev->dev_private;
4206 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4208 i915_verify_inactive(dev, __FILE__, __LINE__);
4209 obj_priv->pin_count--;
4210 BUG_ON(obj_priv->pin_count < 0);
4211 BUG_ON(obj_priv->gtt_space == NULL);
4213 /* If the object is no longer pinned, and is
4214 * neither active nor being flushed, then stick it on
4217 if (obj_priv->pin_count == 0) {
4218 if (!obj_priv->active &&
4219 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4220 list_move_tail(&obj_priv->list,
4221 &dev_priv->mm.inactive_list);
4222 atomic_dec(&dev->pin_count);
4223 atomic_sub(obj->size, &dev->pin_memory);
4225 i915_verify_inactive(dev, __FILE__, __LINE__);
4229 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4230 struct drm_file *file_priv)
4232 struct drm_i915_gem_pin *args = data;
4233 struct drm_gem_object *obj;
4234 struct drm_i915_gem_object *obj_priv;
4237 mutex_lock(&dev->struct_mutex);
4239 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4241 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4243 mutex_unlock(&dev->struct_mutex);
4246 obj_priv = obj->driver_private;
4248 if (obj_priv->madv != I915_MADV_WILLNEED) {
4249 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4250 drm_gem_object_unreference(obj);
4251 mutex_unlock(&dev->struct_mutex);
4255 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4256 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4258 drm_gem_object_unreference(obj);
4259 mutex_unlock(&dev->struct_mutex);
4263 obj_priv->user_pin_count++;
4264 obj_priv->pin_filp = file_priv;
4265 if (obj_priv->user_pin_count == 1) {
4266 ret = i915_gem_object_pin(obj, args->alignment);
4268 drm_gem_object_unreference(obj);
4269 mutex_unlock(&dev->struct_mutex);
4274 /* XXX - flush the CPU caches for pinned objects
4275 * as the X server doesn't manage domains yet
4277 i915_gem_object_flush_cpu_write_domain(obj);
4278 args->offset = obj_priv->gtt_offset;
4279 drm_gem_object_unreference(obj);
4280 mutex_unlock(&dev->struct_mutex);
4286 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4287 struct drm_file *file_priv)
4289 struct drm_i915_gem_pin *args = data;
4290 struct drm_gem_object *obj;
4291 struct drm_i915_gem_object *obj_priv;
4293 mutex_lock(&dev->struct_mutex);
4295 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4297 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4299 mutex_unlock(&dev->struct_mutex);
4303 obj_priv = obj->driver_private;
4304 if (obj_priv->pin_filp != file_priv) {
4305 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4307 drm_gem_object_unreference(obj);
4308 mutex_unlock(&dev->struct_mutex);
4311 obj_priv->user_pin_count--;
4312 if (obj_priv->user_pin_count == 0) {
4313 obj_priv->pin_filp = NULL;
4314 i915_gem_object_unpin(obj);
4317 drm_gem_object_unreference(obj);
4318 mutex_unlock(&dev->struct_mutex);
4323 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4324 struct drm_file *file_priv)
4326 struct drm_i915_gem_busy *args = data;
4327 struct drm_gem_object *obj;
4328 struct drm_i915_gem_object *obj_priv;
4330 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4332 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4337 mutex_lock(&dev->struct_mutex);
4338 /* Update the active list for the hardware's current position.
4339 * Otherwise this only updates on a delayed timer or when irqs are
4340 * actually unmasked, and our working set ends up being larger than
4343 i915_gem_retire_requests(dev);
4345 obj_priv = obj->driver_private;
4346 /* Don't count being on the flushing list against the object being
4347 * done. Otherwise, a buffer left on the flushing list but not getting
4348 * flushed (because nobody's flushing that domain) won't ever return
4349 * unbusy and get reused by libdrm's bo cache. The other expected
4350 * consumer of this interface, OpenGL's occlusion queries, also specs
4351 * that the objects get unbusy "eventually" without any interference.
4353 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4355 drm_gem_object_unreference(obj);
4356 mutex_unlock(&dev->struct_mutex);
4361 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4362 struct drm_file *file_priv)
4364 return i915_gem_ring_throttle(dev, file_priv);
4368 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4369 struct drm_file *file_priv)
4371 struct drm_i915_gem_madvise *args = data;
4372 struct drm_gem_object *obj;
4373 struct drm_i915_gem_object *obj_priv;
4375 switch (args->madv) {
4376 case I915_MADV_DONTNEED:
4377 case I915_MADV_WILLNEED:
4383 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4385 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4390 mutex_lock(&dev->struct_mutex);
4391 obj_priv = obj->driver_private;
4393 if (obj_priv->pin_count) {
4394 drm_gem_object_unreference(obj);
4395 mutex_unlock(&dev->struct_mutex);
4397 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4401 if (obj_priv->madv != __I915_MADV_PURGED)
4402 obj_priv->madv = args->madv;
4404 /* if the object is no longer bound, discard its backing storage */
4405 if (i915_gem_object_is_purgeable(obj_priv) &&
4406 obj_priv->gtt_space == NULL)
4407 i915_gem_object_truncate(obj);
4409 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4411 drm_gem_object_unreference(obj);
4412 mutex_unlock(&dev->struct_mutex);
4417 int i915_gem_init_object(struct drm_gem_object *obj)
4419 struct drm_i915_gem_object *obj_priv;
4421 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4422 if (obj_priv == NULL)
4426 * We've just allocated pages from the kernel,
4427 * so they've just been written by the CPU with
4428 * zeros. They'll need to be clflushed before we
4429 * use them with the GPU.
4431 obj->write_domain = I915_GEM_DOMAIN_CPU;
4432 obj->read_domains = I915_GEM_DOMAIN_CPU;
4434 obj_priv->agp_type = AGP_USER_MEMORY;
4436 obj->driver_private = obj_priv;
4437 obj_priv->obj = obj;
4438 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4439 INIT_LIST_HEAD(&obj_priv->list);
4440 INIT_LIST_HEAD(&obj_priv->gpu_write_list);
4441 INIT_LIST_HEAD(&obj_priv->fence_list);
4442 obj_priv->madv = I915_MADV_WILLNEED;
4444 trace_i915_gem_object_create(obj);
4449 void i915_gem_free_object(struct drm_gem_object *obj)
4451 struct drm_device *dev = obj->dev;
4452 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4454 trace_i915_gem_object_destroy(obj);
4456 while (obj_priv->pin_count > 0)
4457 i915_gem_object_unpin(obj);
4459 if (obj_priv->phys_obj)
4460 i915_gem_detach_phys_object(dev, obj);
4462 i915_gem_object_unbind(obj);
4464 if (obj_priv->mmap_offset)
4465 i915_gem_free_mmap_offset(obj);
4467 kfree(obj_priv->page_cpu_valid);
4468 kfree(obj_priv->bit_17);
4469 kfree(obj->driver_private);
4472 /** Unbinds all inactive objects. */
4474 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4476 drm_i915_private_t *dev_priv = dev->dev_private;
4478 while (!list_empty(&dev_priv->mm.inactive_list)) {
4479 struct drm_gem_object *obj;
4482 obj = list_first_entry(&dev_priv->mm.inactive_list,
4483 struct drm_i915_gem_object,
4486 ret = i915_gem_object_unbind(obj);
4488 DRM_ERROR("Error unbinding object: %d\n", ret);
4497 i915_gem_idle(struct drm_device *dev)
4499 drm_i915_private_t *dev_priv = dev->dev_private;
4502 mutex_lock(&dev->struct_mutex);
4504 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4505 mutex_unlock(&dev->struct_mutex);
4509 ret = i915_gpu_idle(dev);
4511 mutex_unlock(&dev->struct_mutex);
4515 /* Under UMS, be paranoid and evict. */
4516 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4517 ret = i915_gem_evict_from_inactive_list(dev);
4519 mutex_unlock(&dev->struct_mutex);
4524 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4525 * We need to replace this with a semaphore, or something.
4526 * And not confound mm.suspended!
4528 dev_priv->mm.suspended = 1;
4529 del_timer(&dev_priv->hangcheck_timer);
4531 i915_kernel_lost_context(dev);
4532 i915_gem_cleanup_ringbuffer(dev);
4534 mutex_unlock(&dev->struct_mutex);
4536 /* Cancel the retire work handler, which should be idle now. */
4537 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4543 i915_gem_init_hws(struct drm_device *dev)
4545 drm_i915_private_t *dev_priv = dev->dev_private;
4546 struct drm_gem_object *obj;
4547 struct drm_i915_gem_object *obj_priv;
4550 /* If we need a physical address for the status page, it's already
4551 * initialized at driver load time.
4553 if (!I915_NEED_GFX_HWS(dev))
4556 obj = drm_gem_object_alloc(dev, 4096);
4558 DRM_ERROR("Failed to allocate status page\n");
4561 obj_priv = obj->driver_private;
4562 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4564 ret = i915_gem_object_pin(obj, 4096);
4566 drm_gem_object_unreference(obj);
4570 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4572 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4573 if (dev_priv->hw_status_page == NULL) {
4574 DRM_ERROR("Failed to map status page.\n");
4575 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4576 i915_gem_object_unpin(obj);
4577 drm_gem_object_unreference(obj);
4580 dev_priv->hws_obj = obj;
4581 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4583 I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
4584 I915_READ(HWS_PGA_GEN6); /* posting read */
4586 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4587 I915_READ(HWS_PGA); /* posting read */
4589 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4595 i915_gem_cleanup_hws(struct drm_device *dev)
4597 drm_i915_private_t *dev_priv = dev->dev_private;
4598 struct drm_gem_object *obj;
4599 struct drm_i915_gem_object *obj_priv;
4601 if (dev_priv->hws_obj == NULL)
4604 obj = dev_priv->hws_obj;
4605 obj_priv = obj->driver_private;
4607 kunmap(obj_priv->pages[0]);
4608 i915_gem_object_unpin(obj);
4609 drm_gem_object_unreference(obj);
4610 dev_priv->hws_obj = NULL;
4612 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4613 dev_priv->hw_status_page = NULL;
4615 /* Write high address into HWS_PGA when disabling. */
4616 I915_WRITE(HWS_PGA, 0x1ffff000);
4620 i915_gem_init_ringbuffer(struct drm_device *dev)
4622 drm_i915_private_t *dev_priv = dev->dev_private;
4623 struct drm_gem_object *obj;
4624 struct drm_i915_gem_object *obj_priv;
4625 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4629 ret = i915_gem_init_hws(dev);
4633 obj = drm_gem_object_alloc(dev, 128 * 1024);
4635 DRM_ERROR("Failed to allocate ringbuffer\n");
4636 i915_gem_cleanup_hws(dev);
4639 obj_priv = obj->driver_private;
4641 ret = i915_gem_object_pin(obj, 4096);
4643 drm_gem_object_unreference(obj);
4644 i915_gem_cleanup_hws(dev);
4648 /* Set up the kernel mapping for the ring. */
4649 ring->Size = obj->size;
4651 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4652 ring->map.size = obj->size;
4654 ring->map.flags = 0;
4657 drm_core_ioremap_wc(&ring->map, dev);
4658 if (ring->map.handle == NULL) {
4659 DRM_ERROR("Failed to map ringbuffer.\n");
4660 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4661 i915_gem_object_unpin(obj);
4662 drm_gem_object_unreference(obj);
4663 i915_gem_cleanup_hws(dev);
4666 ring->ring_obj = obj;
4667 ring->virtual_start = ring->map.handle;
4669 /* Stop the ring if it's running. */
4670 I915_WRITE(PRB0_CTL, 0);
4671 I915_WRITE(PRB0_TAIL, 0);
4672 I915_WRITE(PRB0_HEAD, 0);
4674 /* Initialize the ring. */
4675 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4676 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4678 /* G45 ring initialization fails to reset head to zero */
4680 DRM_ERROR("Ring head not reset to zero "
4681 "ctl %08x head %08x tail %08x start %08x\n",
4682 I915_READ(PRB0_CTL),
4683 I915_READ(PRB0_HEAD),
4684 I915_READ(PRB0_TAIL),
4685 I915_READ(PRB0_START));
4686 I915_WRITE(PRB0_HEAD, 0);
4688 DRM_ERROR("Ring head forced to zero "
4689 "ctl %08x head %08x tail %08x start %08x\n",
4690 I915_READ(PRB0_CTL),
4691 I915_READ(PRB0_HEAD),
4692 I915_READ(PRB0_TAIL),
4693 I915_READ(PRB0_START));
4696 I915_WRITE(PRB0_CTL,
4697 ((obj->size - 4096) & RING_NR_PAGES) |
4701 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4703 /* If the head is still not zero, the ring is dead */
4705 DRM_ERROR("Ring initialization failed "
4706 "ctl %08x head %08x tail %08x start %08x\n",
4707 I915_READ(PRB0_CTL),
4708 I915_READ(PRB0_HEAD),
4709 I915_READ(PRB0_TAIL),
4710 I915_READ(PRB0_START));
4714 /* Update our cache of the ring state */
4715 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4716 i915_kernel_lost_context(dev);
4718 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4719 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4720 ring->space = ring->head - (ring->tail + 8);
4721 if (ring->space < 0)
4722 ring->space += ring->Size;
4729 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4731 drm_i915_private_t *dev_priv = dev->dev_private;
4733 if (dev_priv->ring.ring_obj == NULL)
4736 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4738 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4739 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4740 dev_priv->ring.ring_obj = NULL;
4741 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4743 i915_gem_cleanup_hws(dev);
4747 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4748 struct drm_file *file_priv)
4750 drm_i915_private_t *dev_priv = dev->dev_private;
4753 if (drm_core_check_feature(dev, DRIVER_MODESET))
4756 if (atomic_read(&dev_priv->mm.wedged)) {
4757 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4758 atomic_set(&dev_priv->mm.wedged, 0);
4761 mutex_lock(&dev->struct_mutex);
4762 dev_priv->mm.suspended = 0;
4764 ret = i915_gem_init_ringbuffer(dev);
4766 mutex_unlock(&dev->struct_mutex);
4770 spin_lock(&dev_priv->mm.active_list_lock);
4771 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4772 spin_unlock(&dev_priv->mm.active_list_lock);
4774 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4775 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4776 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4777 mutex_unlock(&dev->struct_mutex);
4779 drm_irq_install(dev);
4785 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4786 struct drm_file *file_priv)
4788 if (drm_core_check_feature(dev, DRIVER_MODESET))
4791 drm_irq_uninstall(dev);
4792 return i915_gem_idle(dev);
4796 i915_gem_lastclose(struct drm_device *dev)
4800 if (drm_core_check_feature(dev, DRIVER_MODESET))
4803 ret = i915_gem_idle(dev);
4805 DRM_ERROR("failed to idle hardware: %d\n", ret);
4809 i915_gem_load(struct drm_device *dev)
4812 drm_i915_private_t *dev_priv = dev->dev_private;
4814 spin_lock_init(&dev_priv->mm.active_list_lock);
4815 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4816 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4817 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4818 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4819 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4820 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4821 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4822 i915_gem_retire_work_handler);
4823 dev_priv->mm.next_gem_seqno = 1;
4825 spin_lock(&shrink_list_lock);
4826 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4827 spin_unlock(&shrink_list_lock);
4829 /* Old X drivers will take 0-2 for front, back, depth buffers */
4830 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4831 dev_priv->fence_reg_start = 3;
4833 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4834 dev_priv->num_fence_regs = 16;
4836 dev_priv->num_fence_regs = 8;
4838 /* Initialize fence registers to zero */
4839 if (IS_I965G(dev)) {
4840 for (i = 0; i < 16; i++)
4841 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4843 for (i = 0; i < 8; i++)
4844 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4845 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4846 for (i = 0; i < 8; i++)
4847 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4849 i915_gem_detect_bit_6_swizzle(dev);
4850 init_waitqueue_head(&dev_priv->pending_flip_queue);
4854 * Create a physically contiguous memory object for this object
4855 * e.g. for cursor + overlay regs
4857 int i915_gem_init_phys_object(struct drm_device *dev,
4860 drm_i915_private_t *dev_priv = dev->dev_private;
4861 struct drm_i915_gem_phys_object *phys_obj;
4864 if (dev_priv->mm.phys_objs[id - 1] || !size)
4867 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4873 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4874 if (!phys_obj->handle) {
4879 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4882 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4890 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4892 drm_i915_private_t *dev_priv = dev->dev_private;
4893 struct drm_i915_gem_phys_object *phys_obj;
4895 if (!dev_priv->mm.phys_objs[id - 1])
4898 phys_obj = dev_priv->mm.phys_objs[id - 1];
4899 if (phys_obj->cur_obj) {
4900 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4904 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4906 drm_pci_free(dev, phys_obj->handle);
4908 dev_priv->mm.phys_objs[id - 1] = NULL;
4911 void i915_gem_free_all_phys_object(struct drm_device *dev)
4915 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4916 i915_gem_free_phys_object(dev, i);
4919 void i915_gem_detach_phys_object(struct drm_device *dev,
4920 struct drm_gem_object *obj)
4922 struct drm_i915_gem_object *obj_priv;
4927 obj_priv = obj->driver_private;
4928 if (!obj_priv->phys_obj)
4931 ret = i915_gem_object_get_pages(obj, 0);
4935 page_count = obj->size / PAGE_SIZE;
4937 for (i = 0; i < page_count; i++) {
4938 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4939 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4941 memcpy(dst, src, PAGE_SIZE);
4942 kunmap_atomic(dst, KM_USER0);
4944 drm_clflush_pages(obj_priv->pages, page_count);
4945 drm_agp_chipset_flush(dev);
4947 i915_gem_object_put_pages(obj);
4949 obj_priv->phys_obj->cur_obj = NULL;
4950 obj_priv->phys_obj = NULL;
4954 i915_gem_attach_phys_object(struct drm_device *dev,
4955 struct drm_gem_object *obj, int id)
4957 drm_i915_private_t *dev_priv = dev->dev_private;
4958 struct drm_i915_gem_object *obj_priv;
4963 if (id > I915_MAX_PHYS_OBJECT)
4966 obj_priv = obj->driver_private;
4968 if (obj_priv->phys_obj) {
4969 if (obj_priv->phys_obj->id == id)
4971 i915_gem_detach_phys_object(dev, obj);
4975 /* create a new object */
4976 if (!dev_priv->mm.phys_objs[id - 1]) {
4977 ret = i915_gem_init_phys_object(dev, id,
4980 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4985 /* bind to the object */
4986 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4987 obj_priv->phys_obj->cur_obj = obj;
4989 ret = i915_gem_object_get_pages(obj, 0);
4991 DRM_ERROR("failed to get page list\n");
4995 page_count = obj->size / PAGE_SIZE;
4997 for (i = 0; i < page_count; i++) {
4998 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4999 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5001 memcpy(dst, src, PAGE_SIZE);
5002 kunmap_atomic(src, KM_USER0);
5005 i915_gem_object_put_pages(obj);
5013 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5014 struct drm_i915_gem_pwrite *args,
5015 struct drm_file *file_priv)
5017 struct drm_i915_gem_object *obj_priv = obj->driver_private;
5020 char __user *user_data;
5022 user_data = (char __user *) (uintptr_t) args->data_ptr;
5023 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5025 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
5026 ret = copy_from_user(obj_addr, user_data, args->size);
5030 drm_agp_chipset_flush(dev);
5034 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5036 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5038 /* Clean up our request list when the client is going away, so that
5039 * later retire_requests won't dereference our soon-to-be-gone
5042 mutex_lock(&dev->struct_mutex);
5043 while (!list_empty(&i915_file_priv->mm.request_list))
5044 list_del_init(i915_file_priv->mm.request_list.next);
5045 mutex_unlock(&dev->struct_mutex);
5049 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5051 drm_i915_private_t *dev_priv, *next_dev;
5052 struct drm_i915_gem_object *obj_priv, *next_obj;
5054 int would_deadlock = 1;
5056 /* "fast-path" to count number of available objects */
5057 if (nr_to_scan == 0) {
5058 spin_lock(&shrink_list_lock);
5059 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5060 struct drm_device *dev = dev_priv->dev;
5062 if (mutex_trylock(&dev->struct_mutex)) {
5063 list_for_each_entry(obj_priv,
5064 &dev_priv->mm.inactive_list,
5067 mutex_unlock(&dev->struct_mutex);
5070 spin_unlock(&shrink_list_lock);
5072 return (cnt / 100) * sysctl_vfs_cache_pressure;
5075 spin_lock(&shrink_list_lock);
5077 /* first scan for clean buffers */
5078 list_for_each_entry_safe(dev_priv, next_dev,
5079 &shrink_list, mm.shrink_list) {
5080 struct drm_device *dev = dev_priv->dev;
5082 if (! mutex_trylock(&dev->struct_mutex))
5085 spin_unlock(&shrink_list_lock);
5087 i915_gem_retire_requests(dev);
5089 list_for_each_entry_safe(obj_priv, next_obj,
5090 &dev_priv->mm.inactive_list,
5092 if (i915_gem_object_is_purgeable(obj_priv)) {
5093 i915_gem_object_unbind(obj_priv->obj);
5094 if (--nr_to_scan <= 0)
5099 spin_lock(&shrink_list_lock);
5100 mutex_unlock(&dev->struct_mutex);
5104 if (nr_to_scan <= 0)
5108 /* second pass, evict/count anything still on the inactive list */
5109 list_for_each_entry_safe(dev_priv, next_dev,
5110 &shrink_list, mm.shrink_list) {
5111 struct drm_device *dev = dev_priv->dev;
5113 if (! mutex_trylock(&dev->struct_mutex))
5116 spin_unlock(&shrink_list_lock);
5118 list_for_each_entry_safe(obj_priv, next_obj,
5119 &dev_priv->mm.inactive_list,
5121 if (nr_to_scan > 0) {
5122 i915_gem_object_unbind(obj_priv->obj);
5128 spin_lock(&shrink_list_lock);
5129 mutex_unlock(&dev->struct_mutex);
5134 spin_unlock(&shrink_list_lock);
5139 return (cnt / 100) * sysctl_vfs_cache_pressure;
5144 static struct shrinker shrinker = {
5145 .shrink = i915_gem_shrink,
5146 .seeks = DEFAULT_SEEKS,
5150 i915_gem_shrinker_init(void)
5152 register_shrinker(&shrinker);
5156 i915_gem_shrinker_exit(void)
5158 unregister_shrinker(&shrinker);