1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
51 #define I915_NUM_PIPE 2
56 * 1.2: Add Power Management
57 * 1.3: Add vblank support
58 * 1.4: Fix cmdbuffer path, add heap destroy
59 * 1.5: Add vblank pipe configuration
60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
63 #define DRIVER_MAJOR 1
64 #define DRIVER_MINOR 6
65 #define DRIVER_PATCHLEVEL 0
67 #define WATCH_COHERENCY 0
72 #define WATCH_INACTIVE 0
73 #define WATCH_PWRITE 0
75 #define I915_GEM_PHYS_CURSOR_0 1
76 #define I915_GEM_PHYS_CURSOR_1 2
77 #define I915_GEM_PHYS_OVERLAY_REGS 3
78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
80 struct drm_i915_gem_phys_object {
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
87 typedef struct _drm_i915_ring_buffer {
95 struct drm_gem_object *ring_obj;
96 } drm_i915_ring_buffer_t;
99 struct mem_block *next;
100 struct mem_block *prev;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header;
107 struct opregion_acpi;
108 struct opregion_swsci;
109 struct opregion_asle;
111 struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
119 struct drm_i915_master_private {
120 drm_local_map_t *sarea;
121 struct _drm_i915_sarea *sarea_priv;
123 #define I915_FENCE_REG_NONE -1
125 struct drm_i915_fence_reg {
126 struct drm_gem_object *obj;
129 struct sdvo_device_mapping {
136 typedef struct drm_i915_private {
137 struct drm_device *dev;
143 drm_i915_ring_buffer_t ring;
145 drm_dma_handle_t *status_page_dmah;
146 void *hw_status_page;
147 dma_addr_t dma_status_page;
149 unsigned int status_gfx_addr;
150 drm_local_map_t hws_map;
151 struct drm_gem_object *hws_obj;
153 struct resource mch_res;
161 wait_queue_head_t irq_queue;
162 atomic_t irq_received;
163 /** Protects user_irq_refcount and irq_mask_reg */
164 spinlock_t user_irq_lock;
165 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
166 int user_irq_refcount;
167 /** Cached value of IMR to avoid reads in updating the bitfield */
171 u32 hotplug_supported_mask;
172 struct work_struct hotplug_work;
174 int tex_lru_log_granularity;
175 int allow_batchbuffer;
176 struct mem_block *agp_heap;
177 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
180 bool cursor_needs_physical;
186 struct intel_opregion opregion;
189 int backlight_duty_cycle; /* restore backlight to this value */
190 bool panel_wants_dither;
191 struct drm_display_mode *panel_fixed_mode;
192 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
193 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
195 /* Feature bits from the VBIOS */
196 unsigned int int_tv_support:1;
197 unsigned int lvds_dither:1;
198 unsigned int lvds_vbt:1;
199 unsigned int int_crt_support:1;
200 unsigned int lvds_use_ssc:1;
203 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
204 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
205 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
212 u32 saveRENDERSTANDBY;
236 u32 savePFIT_PGM_RATIOS;
238 u32 saveBLC_PWM_CTL2;
263 u32 savePP_ON_DELAYS;
264 u32 savePP_OFF_DELAYS;
272 u32 savePFIT_CONTROL;
273 u32 save_palette_a[256];
274 u32 save_palette_b[256];
275 u32 saveFBC_CFB_BASE;
278 u32 saveFBC_CONTROL2;
282 u32 saveCACHE_MODE_0;
285 u32 saveMI_ARB_STATE;
296 uint64_t saveFENCE[16];
306 struct drm_mm gtt_space;
308 struct io_mapping *gtt_mapping;
312 * List of objects currently involved in rendering from the
315 * Includes buffers having the contents of their GPU caches
316 * flushed, not necessarily primitives. last_rendering_seqno
317 * represents when the rendering involved will be completed.
319 * A reference is held on the buffer while on this list.
321 spinlock_t active_list_lock;
322 struct list_head active_list;
325 * List of objects which are not in the ringbuffer but which
326 * still have a write_domain which needs to be flushed before
329 * last_rendering_seqno is 0 while an object is in this list.
331 * A reference is held on the buffer while on this list.
333 struct list_head flushing_list;
336 * LRU list of objects which are not in the ringbuffer and
337 * are ready to unbind, but are still in the GTT.
339 * last_rendering_seqno is 0 while an object is in this list.
341 * A reference is not held on the buffer while on this list,
342 * as merely being GTT-bound shouldn't prevent its being
343 * freed, and we'll pull it off the list in the free path.
345 struct list_head inactive_list;
348 * List of breadcrumbs associated with GPU requests currently
351 struct list_head request_list;
354 * We leave the user IRQ off as much as possible,
355 * but this means that requests will finish and never
356 * be retired once the system goes idle. Set a timer to
357 * fire periodically while the ring is running. When it
358 * fires, go retire requests.
360 struct delayed_work retire_work;
362 uint32_t next_gem_seqno;
365 * Waiting sequence number, if any
367 uint32_t waiting_gem_seqno;
370 * Last seq seen at irq time
372 uint32_t irq_gem_seqno;
375 * Flag if the X Server, and thus DRM, is not currently in
376 * control of the device.
378 * This is set between LeaveVT and EnterVT. It needs to be
379 * replaced with a semaphore. It also needs to be
380 * transitioned away from for kernel modesetting.
385 * Flag if the hardware appears to be wedged.
387 * This is set when attempts to idle the device timeout.
388 * It prevents command submission from occuring and makes
389 * every pending request fail
393 /** Bit 6 swizzling required for X tiling */
394 uint32_t bit_6_swizzle_x;
395 /** Bit 6 swizzling required for Y tiling */
396 uint32_t bit_6_swizzle_y;
398 /* storage for physical objects */
399 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
401 struct sdvo_device_mapping sdvo_mappings[2];
402 } drm_i915_private_t;
404 /** driver private structure attached to each drm_gem_object */
405 struct drm_i915_gem_object {
406 struct drm_gem_object *obj;
408 /** Current space allocated to this object in the GTT, if any. */
409 struct drm_mm_node *gtt_space;
411 /** This object's place on the active/flushing/inactive lists */
412 struct list_head list;
415 * This is set if the object is on the active or flushing lists
416 * (has pending rendering), and is not set if it's on inactive (ready
422 * This is set if the object has been written to since last bound
427 /** AGP memory structure for our GTT binding. */
428 DRM_AGP_MEM *agp_mem;
434 * Current offset of the object in GTT space.
436 * This is the same as gtt_space->start
440 * Required alignment for the object
442 uint32_t gtt_alignment;
444 * Fake offset for use by mmap(2)
446 uint64_t mmap_offset;
449 * Fence register bits (if any) for this object. Will be set
450 * as needed when mapped into the GTT.
451 * Protected by dev->struct_mutex.
455 /** Boolean whether this object has a valid gtt offset. */
458 /** How many users have pinned this object in GTT space */
461 /** Breadcrumb of last rendering to the buffer. */
462 uint32_t last_rendering_seqno;
464 /** Current tiling mode for the object. */
465 uint32_t tiling_mode;
468 /** Record of address bit 17 of each page at last unbind. */
471 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
475 * If present, while GEM_DOMAIN_CPU is in the read domain this array
476 * flags which individual pages are valid.
478 uint8_t *page_cpu_valid;
480 /** User space pin count and filp owning the pin */
481 uint32_t user_pin_count;
482 struct drm_file *pin_filp;
484 /** for phy allocated objects */
485 struct drm_i915_gem_phys_object *phys_obj;
488 * Used for checking the object doesn't appear more than once
489 * in an execbuffer object list.
495 * Request queue structure.
497 * The request queue allows us to note sequence numbers that have been emitted
498 * and may be associated with active buffers to be retired.
500 * By keeping this list, we can avoid having to do questionable
501 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
502 * an emission time with seqnos for tracking how far ahead of the GPU we are.
504 struct drm_i915_gem_request {
505 /** GEM sequence number associated with this request. */
508 /** Time at which this request was emitted, in jiffies. */
509 unsigned long emitted_jiffies;
511 /** global list entry for this request */
512 struct list_head list;
514 /** file_priv list entry for this request */
515 struct list_head client_list;
518 struct drm_i915_file_private {
520 struct list_head request_list;
524 enum intel_chip_family {
531 extern struct drm_ioctl_desc i915_ioctls[];
532 extern int i915_max_ioctl;
533 extern unsigned int i915_fbpercrtc;
535 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
536 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
539 extern void i915_kernel_lost_context(struct drm_device * dev);
540 extern int i915_driver_load(struct drm_device *, unsigned long flags);
541 extern int i915_driver_unload(struct drm_device *);
542 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
543 extern void i915_driver_lastclose(struct drm_device * dev);
544 extern void i915_driver_preclose(struct drm_device *dev,
545 struct drm_file *file_priv);
546 extern void i915_driver_postclose(struct drm_device *dev,
547 struct drm_file *file_priv);
548 extern int i915_driver_device_is_agp(struct drm_device * dev);
549 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
551 extern int i915_emit_box(struct drm_device *dev,
552 struct drm_clip_rect *boxes,
553 int i, int DR1, int DR4);
556 extern int i915_irq_emit(struct drm_device *dev, void *data,
557 struct drm_file *file_priv);
558 extern int i915_irq_wait(struct drm_device *dev, void *data,
559 struct drm_file *file_priv);
560 void i915_user_irq_get(struct drm_device *dev);
561 void i915_user_irq_put(struct drm_device *dev);
562 extern void i915_enable_interrupt (struct drm_device *dev);
564 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
565 extern void i915_driver_irq_preinstall(struct drm_device * dev);
566 extern int i915_driver_irq_postinstall(struct drm_device *dev);
567 extern void i915_driver_irq_uninstall(struct drm_device * dev);
568 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
569 struct drm_file *file_priv);
570 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
571 struct drm_file *file_priv);
572 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
573 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
574 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
575 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
576 extern int i915_vblank_swap(struct drm_device *dev, void *data,
577 struct drm_file *file_priv);
578 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
581 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
584 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
588 extern int i915_mem_alloc(struct drm_device *dev, void *data,
589 struct drm_file *file_priv);
590 extern int i915_mem_free(struct drm_device *dev, void *data,
591 struct drm_file *file_priv);
592 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
593 struct drm_file *file_priv);
594 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
595 struct drm_file *file_priv);
596 extern void i915_mem_takedown(struct mem_block **heap);
597 extern void i915_mem_release(struct drm_device * dev,
598 struct drm_file *file_priv, struct mem_block *heap);
600 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
601 struct drm_file *file_priv);
602 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
603 struct drm_file *file_priv);
604 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
605 struct drm_file *file_priv);
606 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
607 struct drm_file *file_priv);
608 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
609 struct drm_file *file_priv);
610 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
611 struct drm_file *file_priv);
612 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
613 struct drm_file *file_priv);
614 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
615 struct drm_file *file_priv);
616 int i915_gem_execbuffer(struct drm_device *dev, void *data,
617 struct drm_file *file_priv);
618 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
619 struct drm_file *file_priv);
620 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
621 struct drm_file *file_priv);
622 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
623 struct drm_file *file_priv);
624 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
625 struct drm_file *file_priv);
626 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
627 struct drm_file *file_priv);
628 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
629 struct drm_file *file_priv);
630 int i915_gem_set_tiling(struct drm_device *dev, void *data,
631 struct drm_file *file_priv);
632 int i915_gem_get_tiling(struct drm_device *dev, void *data,
633 struct drm_file *file_priv);
634 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
635 struct drm_file *file_priv);
636 void i915_gem_load(struct drm_device *dev);
637 int i915_gem_init_object(struct drm_gem_object *obj);
638 void i915_gem_free_object(struct drm_gem_object *obj);
639 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
640 void i915_gem_object_unpin(struct drm_gem_object *obj);
641 int i915_gem_object_unbind(struct drm_gem_object *obj);
642 void i915_gem_lastclose(struct drm_device *dev);
643 uint32_t i915_get_gem_seqno(struct drm_device *dev);
644 void i915_gem_retire_requests(struct drm_device *dev);
645 void i915_gem_retire_work_handler(struct work_struct *work);
646 void i915_gem_clflush_object(struct drm_gem_object *obj);
647 int i915_gem_object_set_domain(struct drm_gem_object *obj,
648 uint32_t read_domains,
649 uint32_t write_domain);
650 int i915_gem_init_ringbuffer(struct drm_device *dev);
651 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
652 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
654 int i915_gem_idle(struct drm_device *dev);
655 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
656 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
658 int i915_gem_attach_phys_object(struct drm_device *dev,
659 struct drm_gem_object *obj, int id);
660 void i915_gem_detach_phys_object(struct drm_device *dev,
661 struct drm_gem_object *obj);
662 void i915_gem_free_all_phys_object(struct drm_device *dev);
663 int i915_gem_object_get_pages(struct drm_gem_object *obj);
664 void i915_gem_object_put_pages(struct drm_gem_object *obj);
665 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
667 /* i915_gem_tiling.c */
668 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
669 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
670 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
672 /* i915_gem_debug.c */
673 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
674 const char *where, uint32_t mark);
676 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
678 #define i915_verify_inactive(dev, file, line)
680 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
681 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
682 const char *where, uint32_t mark);
683 void i915_dump_lru(struct drm_device *dev, const char *where);
686 int i915_gem_debugfs_init(struct drm_minor *minor);
687 void i915_gem_debugfs_cleanup(struct drm_minor *minor);
690 extern int i915_save_state(struct drm_device *dev);
691 extern int i915_restore_state(struct drm_device *dev);
694 extern int i915_save_state(struct drm_device *dev);
695 extern int i915_restore_state(struct drm_device *dev);
698 /* i915_opregion.c */
699 extern int intel_opregion_init(struct drm_device *dev, int resume);
700 extern void intel_opregion_free(struct drm_device *dev, int suspend);
701 extern void opregion_asle_intr(struct drm_device *dev);
702 extern void opregion_enable_asle(struct drm_device *dev);
704 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
705 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
706 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
707 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
711 extern void intel_modeset_init(struct drm_device *dev);
712 extern void intel_modeset_cleanup(struct drm_device *dev);
715 * Lock test for when it's just for synchronization of ring access.
717 * In that case, we don't need to do it when GEM is initialized as nobody else
718 * has access to the ring.
720 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
721 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
722 LOCK_TEST_WITH_RETURN(dev, file_priv); \
725 #define I915_READ(reg) readl(dev_priv->regs + (reg))
726 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
727 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
728 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
729 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
730 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
731 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
732 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
733 #define POSTING_READ(reg) (void)I915_READ(reg)
735 #define I915_VERBOSE 0
737 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
740 #define BEGIN_LP_RING(n) do { \
742 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
743 if (dev_priv->ring.space < (n)*4) \
744 i915_wait_ring(dev, (n)*4, __func__); \
746 outring = dev_priv->ring.tail; \
747 ringmask = dev_priv->ring.tail_mask; \
748 virt = dev_priv->ring.virtual_start; \
751 #define OUT_RING(n) do { \
752 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
753 *(volatile unsigned int *)(virt + outring) = (n); \
756 outring &= ringmask; \
759 #define ADVANCE_LP_RING() do { \
760 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
761 dev_priv->ring.tail = outring; \
762 dev_priv->ring.space -= outcount * 4; \
763 I915_WRITE(PRB0_TAIL, outring); \
767 * Reads a dword out of the status page, which is written to from the command
768 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
771 * The following dwords have a reserved meaning:
772 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
773 * 0x04: ring 0 head pointer
774 * 0x05: ring 1 head pointer (915-class)
775 * 0x06: ring 2 head pointer (915-class)
776 * 0x10-0x1b: Context status DWords (GM45)
777 * 0x1f: Last written status offset. (GM45)
779 * The area from dword 0x20 to 0x3ff is available for driver usage.
781 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
782 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
783 #define I915_GEM_HWS_INDEX 0x20
784 #define I915_BREADCRUMB_INDEX 0x21
786 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
788 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
789 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
790 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
791 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
792 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
794 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
795 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
796 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
797 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
798 (dev)->pci_device == 0x27AE)
799 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
800 (dev)->pci_device == 0x2982 || \
801 (dev)->pci_device == 0x2992 || \
802 (dev)->pci_device == 0x29A2 || \
803 (dev)->pci_device == 0x2A02 || \
804 (dev)->pci_device == 0x2A12 || \
805 (dev)->pci_device == 0x2A42 || \
806 (dev)->pci_device == 0x2E02 || \
807 (dev)->pci_device == 0x2E12 || \
808 (dev)->pci_device == 0x2E22 || \
809 (dev)->pci_device == 0x2E32 || \
810 (dev)->pci_device == 0x0042 || \
811 (dev)->pci_device == 0x0046)
813 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
814 (dev)->pci_device == 0x2A12)
816 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
818 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
819 (dev)->pci_device == 0x2E12 || \
820 (dev)->pci_device == 0x2E22 || \
821 (dev)->pci_device == 0x2E32 || \
824 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
825 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
826 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
828 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
829 (dev)->pci_device == 0x29B2 || \
830 (dev)->pci_device == 0x29D2 || \
833 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
834 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
835 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
837 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
838 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
841 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
842 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
843 IS_IGD(dev) || IS_IGDNG_M(dev))
845 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
847 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
848 * rows, which changed the alignment requirements and fence programming.
850 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
852 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
853 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
855 #define PRIMARY_RINGBUFFER_SIZE (128*1024)