1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
56 #define I915_NUM_PIPE 2
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
72 #define WATCH_COHERENCY 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
85 struct drm_i915_gem_phys_object {
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
92 typedef struct _drm_i915_ring_buffer {
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
103 struct mem_block *next;
104 struct mem_block *prev;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
133 struct sdvo_device_mapping {
140 struct drm_i915_error_state {
156 typedef struct drm_i915_private {
157 struct drm_device *dev;
163 struct pci_dev *bridge_dev;
164 drm_i915_ring_buffer_t ring;
166 drm_dma_handle_t *status_page_dmah;
167 void *hw_status_page;
168 dma_addr_t dma_status_page;
170 unsigned int status_gfx_addr;
171 drm_local_map_t hws_map;
172 struct drm_gem_object *hws_obj;
174 struct resource mch_res;
182 wait_queue_head_t irq_queue;
183 atomic_t irq_received;
184 /** Protects user_irq_refcount and irq_mask_reg */
185 spinlock_t user_irq_lock;
186 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
187 int user_irq_refcount;
188 /** Cached value of IMR to avoid reads in updating the bitfield */
191 /** splitted irq regs for graphics and display engine on IGDNG,
192 irq_mask_reg is still used for display irq. */
194 u32 gt_irq_enable_reg;
195 u32 de_irq_enable_reg;
197 u32 hotplug_supported_mask;
198 struct work_struct hotplug_work;
200 int tex_lru_log_granularity;
201 int allow_batchbuffer;
202 struct mem_block *agp_heap;
203 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
206 bool cursor_needs_physical;
210 unsigned long cfb_size;
211 unsigned long cfb_pitch;
217 struct intel_opregion opregion;
220 int backlight_duty_cycle; /* restore backlight to this value */
221 bool panel_wants_dither;
222 struct drm_display_mode *panel_fixed_mode;
223 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
224 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
226 /* Feature bits from the VBIOS */
227 unsigned int int_tv_support:1;
228 unsigned int lvds_dither:1;
229 unsigned int lvds_vbt:1;
230 unsigned int int_crt_support:1;
231 unsigned int lvds_use_ssc:1;
232 unsigned int edp_support:1;
235 struct notifier_block lid_notifier;
237 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
238 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
239 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
240 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
242 unsigned int fsb_freq, mem_freq;
244 spinlock_t error_lock;
245 struct drm_i915_error_state *first_error;
246 struct work_struct error_work;
247 struct workqueue_struct *wq;
254 u32 saveRENDERSTANDBY;
278 u32 savePFIT_PGM_RATIOS;
280 u32 saveBLC_PWM_CTL2;
305 u32 savePP_ON_DELAYS;
306 u32 savePP_OFF_DELAYS;
314 u32 savePFIT_CONTROL;
315 u32 save_palette_a[256];
316 u32 save_palette_b[256];
317 u32 saveFBC_CFB_BASE;
320 u32 saveFBC_CONTROL2;
324 u32 saveCACHE_MODE_0;
326 u32 saveDSPCLK_GATE_D;
327 u32 saveMI_ARB_STATE;
338 uint64_t saveFENCE[16];
349 u32 savePIPEA_GMCH_DATA_M;
350 u32 savePIPEB_GMCH_DATA_M;
351 u32 savePIPEA_GMCH_DATA_N;
352 u32 savePIPEB_GMCH_DATA_N;
353 u32 savePIPEA_DP_LINK_M;
354 u32 savePIPEB_DP_LINK_M;
355 u32 savePIPEA_DP_LINK_N;
356 u32 savePIPEB_DP_LINK_N;
359 struct drm_mm gtt_space;
361 struct io_mapping *gtt_mapping;
365 * List of objects currently involved in rendering from the
368 * Includes buffers having the contents of their GPU caches
369 * flushed, not necessarily primitives. last_rendering_seqno
370 * represents when the rendering involved will be completed.
372 * A reference is held on the buffer while on this list.
374 spinlock_t active_list_lock;
375 struct list_head active_list;
378 * List of objects which are not in the ringbuffer but which
379 * still have a write_domain which needs to be flushed before
382 * last_rendering_seqno is 0 while an object is in this list.
384 * A reference is held on the buffer while on this list.
386 struct list_head flushing_list;
389 * LRU list of objects which are not in the ringbuffer and
390 * are ready to unbind, but are still in the GTT.
392 * last_rendering_seqno is 0 while an object is in this list.
394 * A reference is not held on the buffer while on this list,
395 * as merely being GTT-bound shouldn't prevent its being
396 * freed, and we'll pull it off the list in the free path.
398 struct list_head inactive_list;
400 /** LRU list of objects with fence regs on them. */
401 struct list_head fence_list;
404 * List of breadcrumbs associated with GPU requests currently
407 struct list_head request_list;
410 * We leave the user IRQ off as much as possible,
411 * but this means that requests will finish and never
412 * be retired once the system goes idle. Set a timer to
413 * fire periodically while the ring is running. When it
414 * fires, go retire requests.
416 struct delayed_work retire_work;
418 uint32_t next_gem_seqno;
421 * Waiting sequence number, if any
423 uint32_t waiting_gem_seqno;
426 * Last seq seen at irq time
428 uint32_t irq_gem_seqno;
431 * Flag if the X Server, and thus DRM, is not currently in
432 * control of the device.
434 * This is set between LeaveVT and EnterVT. It needs to be
435 * replaced with a semaphore. It also needs to be
436 * transitioned away from for kernel modesetting.
441 * Flag if the hardware appears to be wedged.
443 * This is set when attempts to idle the device timeout.
444 * It prevents command submission from occuring and makes
445 * every pending request fail
449 /** Bit 6 swizzling required for X tiling */
450 uint32_t bit_6_swizzle_x;
451 /** Bit 6 swizzling required for Y tiling */
452 uint32_t bit_6_swizzle_y;
454 /* storage for physical objects */
455 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
457 struct sdvo_device_mapping sdvo_mappings[2];
459 /* Reclocking support */
460 bool render_reclock_avail;
461 bool lvds_downclock_avail;
462 struct work_struct idle_work;
463 struct timer_list idle_timer;
466 } drm_i915_private_t;
468 /** driver private structure attached to each drm_gem_object */
469 struct drm_i915_gem_object {
470 struct drm_gem_object *obj;
472 /** Current space allocated to this object in the GTT, if any. */
473 struct drm_mm_node *gtt_space;
475 /** This object's place on the active/flushing/inactive lists */
476 struct list_head list;
478 /** This object's place on the fenced object LRU */
479 struct list_head fence_list;
482 * This is set if the object is on the active or flushing lists
483 * (has pending rendering), and is not set if it's on inactive (ready
489 * This is set if the object has been written to since last bound
494 /** AGP memory structure for our GTT binding. */
495 DRM_AGP_MEM *agp_mem;
501 * Current offset of the object in GTT space.
503 * This is the same as gtt_space->start
507 * Required alignment for the object
509 uint32_t gtt_alignment;
511 * Fake offset for use by mmap(2)
513 uint64_t mmap_offset;
516 * Fence register bits (if any) for this object. Will be set
517 * as needed when mapped into the GTT.
518 * Protected by dev->struct_mutex.
522 /** How many users have pinned this object in GTT space */
525 /** Breadcrumb of last rendering to the buffer. */
526 uint32_t last_rendering_seqno;
528 /** Current tiling mode for the object. */
529 uint32_t tiling_mode;
532 /** Record of address bit 17 of each page at last unbind. */
535 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
539 * If present, while GEM_DOMAIN_CPU is in the read domain this array
540 * flags which individual pages are valid.
542 uint8_t *page_cpu_valid;
544 /** User space pin count and filp owning the pin */
545 uint32_t user_pin_count;
546 struct drm_file *pin_filp;
548 /** for phy allocated objects */
549 struct drm_i915_gem_phys_object *phys_obj;
552 * Used for checking the object doesn't appear more than once
553 * in an execbuffer object list.
559 * Request queue structure.
561 * The request queue allows us to note sequence numbers that have been emitted
562 * and may be associated with active buffers to be retired.
564 * By keeping this list, we can avoid having to do questionable
565 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
566 * an emission time with seqnos for tracking how far ahead of the GPU we are.
568 struct drm_i915_gem_request {
569 /** GEM sequence number associated with this request. */
572 /** Time at which this request was emitted, in jiffies. */
573 unsigned long emitted_jiffies;
575 /** global list entry for this request */
576 struct list_head list;
578 /** file_priv list entry for this request */
579 struct list_head client_list;
582 struct drm_i915_file_private {
584 struct list_head request_list;
588 enum intel_chip_family {
595 extern struct drm_ioctl_desc i915_ioctls[];
596 extern int i915_max_ioctl;
597 extern unsigned int i915_fbpercrtc;
598 extern unsigned int i915_powersave;
600 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
601 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
604 extern void i915_kernel_lost_context(struct drm_device * dev);
605 extern int i915_driver_load(struct drm_device *, unsigned long flags);
606 extern int i915_driver_unload(struct drm_device *);
607 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
608 extern void i915_driver_lastclose(struct drm_device * dev);
609 extern void i915_driver_preclose(struct drm_device *dev,
610 struct drm_file *file_priv);
611 extern void i915_driver_postclose(struct drm_device *dev,
612 struct drm_file *file_priv);
613 extern int i915_driver_device_is_agp(struct drm_device * dev);
614 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
616 extern int i915_emit_box(struct drm_device *dev,
617 struct drm_clip_rect *boxes,
618 int i, int DR1, int DR4);
621 extern int i915_irq_emit(struct drm_device *dev, void *data,
622 struct drm_file *file_priv);
623 extern int i915_irq_wait(struct drm_device *dev, void *data,
624 struct drm_file *file_priv);
625 void i915_user_irq_get(struct drm_device *dev);
626 void i915_user_irq_put(struct drm_device *dev);
627 extern void i915_enable_interrupt (struct drm_device *dev);
629 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
630 extern void i915_driver_irq_preinstall(struct drm_device * dev);
631 extern int i915_driver_irq_postinstall(struct drm_device *dev);
632 extern void i915_driver_irq_uninstall(struct drm_device * dev);
633 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
634 struct drm_file *file_priv);
635 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
636 struct drm_file *file_priv);
637 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
638 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
639 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
640 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
641 extern int i915_vblank_swap(struct drm_device *dev, void *data,
642 struct drm_file *file_priv);
643 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
646 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
649 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
653 extern int i915_mem_alloc(struct drm_device *dev, void *data,
654 struct drm_file *file_priv);
655 extern int i915_mem_free(struct drm_device *dev, void *data,
656 struct drm_file *file_priv);
657 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
658 struct drm_file *file_priv);
659 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
660 struct drm_file *file_priv);
661 extern void i915_mem_takedown(struct mem_block **heap);
662 extern void i915_mem_release(struct drm_device * dev,
663 struct drm_file *file_priv, struct mem_block *heap);
665 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
666 struct drm_file *file_priv);
667 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
668 struct drm_file *file_priv);
669 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
670 struct drm_file *file_priv);
671 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
672 struct drm_file *file_priv);
673 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
674 struct drm_file *file_priv);
675 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *file_priv);
677 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
678 struct drm_file *file_priv);
679 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
680 struct drm_file *file_priv);
681 int i915_gem_execbuffer(struct drm_device *dev, void *data,
682 struct drm_file *file_priv);
683 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
684 struct drm_file *file_priv);
685 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
686 struct drm_file *file_priv);
687 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
688 struct drm_file *file_priv);
689 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
690 struct drm_file *file_priv);
691 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
692 struct drm_file *file_priv);
693 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
694 struct drm_file *file_priv);
695 int i915_gem_set_tiling(struct drm_device *dev, void *data,
696 struct drm_file *file_priv);
697 int i915_gem_get_tiling(struct drm_device *dev, void *data,
698 struct drm_file *file_priv);
699 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
700 struct drm_file *file_priv);
701 void i915_gem_load(struct drm_device *dev);
702 int i915_gem_init_object(struct drm_gem_object *obj);
703 void i915_gem_free_object(struct drm_gem_object *obj);
704 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
705 void i915_gem_object_unpin(struct drm_gem_object *obj);
706 int i915_gem_object_unbind(struct drm_gem_object *obj);
707 void i915_gem_release_mmap(struct drm_gem_object *obj);
708 void i915_gem_lastclose(struct drm_device *dev);
709 uint32_t i915_get_gem_seqno(struct drm_device *dev);
710 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
711 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
712 void i915_gem_retire_requests(struct drm_device *dev);
713 void i915_gem_retire_work_handler(struct work_struct *work);
714 void i915_gem_clflush_object(struct drm_gem_object *obj);
715 int i915_gem_object_set_domain(struct drm_gem_object *obj,
716 uint32_t read_domains,
717 uint32_t write_domain);
718 int i915_gem_init_ringbuffer(struct drm_device *dev);
719 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
720 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
722 int i915_gem_idle(struct drm_device *dev);
723 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
724 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
726 int i915_gem_attach_phys_object(struct drm_device *dev,
727 struct drm_gem_object *obj, int id);
728 void i915_gem_detach_phys_object(struct drm_device *dev,
729 struct drm_gem_object *obj);
730 void i915_gem_free_all_phys_object(struct drm_device *dev);
731 int i915_gem_object_get_pages(struct drm_gem_object *obj);
732 void i915_gem_object_put_pages(struct drm_gem_object *obj);
733 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
735 /* i915_gem_tiling.c */
736 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
737 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
738 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
740 /* i915_gem_debug.c */
741 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
742 const char *where, uint32_t mark);
744 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
746 #define i915_verify_inactive(dev, file, line)
748 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
749 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
750 const char *where, uint32_t mark);
751 void i915_dump_lru(struct drm_device *dev, const char *where);
754 int i915_debugfs_init(struct drm_minor *minor);
755 void i915_debugfs_cleanup(struct drm_minor *minor);
758 extern int i915_save_state(struct drm_device *dev);
759 extern int i915_restore_state(struct drm_device *dev);
762 extern int i915_save_state(struct drm_device *dev);
763 extern int i915_restore_state(struct drm_device *dev);
766 /* i915_opregion.c */
767 extern int intel_opregion_init(struct drm_device *dev, int resume);
768 extern void intel_opregion_free(struct drm_device *dev, int suspend);
769 extern void opregion_asle_intr(struct drm_device *dev);
770 extern void opregion_enable_asle(struct drm_device *dev);
772 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
773 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
774 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
775 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
779 extern void intel_modeset_init(struct drm_device *dev);
780 extern void intel_modeset_cleanup(struct drm_device *dev);
781 extern void i8xx_disable_fbc(struct drm_device *dev);
784 * Lock test for when it's just for synchronization of ring access.
786 * In that case, we don't need to do it when GEM is initialized as nobody else
787 * has access to the ring.
789 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
790 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
791 LOCK_TEST_WITH_RETURN(dev, file_priv); \
794 #define I915_READ(reg) readl(dev_priv->regs + (reg))
795 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
796 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
797 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
798 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
799 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
800 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
801 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
802 #define POSTING_READ(reg) (void)I915_READ(reg)
804 #define I915_VERBOSE 0
806 #define RING_LOCALS volatile unsigned int *ring_virt__;
808 #define BEGIN_LP_RING(n) do { \
809 int bytes__ = 4*(n); \
810 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
811 /* a wrap must occur between instructions so pad beforehand */ \
812 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
813 i915_wrap_ring(dev); \
814 if (unlikely (dev_priv->ring.space < bytes__)) \
815 i915_wait_ring(dev, bytes__, __func__); \
816 ring_virt__ = (unsigned int *) \
817 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
818 dev_priv->ring.tail += bytes__; \
819 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
820 dev_priv->ring.space -= bytes__; \
823 #define OUT_RING(n) do { \
824 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
825 *ring_virt__++ = (n); \
828 #define ADVANCE_LP_RING() do { \
830 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
831 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
835 * Reads a dword out of the status page, which is written to from the command
836 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
839 * The following dwords have a reserved meaning:
840 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
841 * 0x04: ring 0 head pointer
842 * 0x05: ring 1 head pointer (915-class)
843 * 0x06: ring 2 head pointer (915-class)
844 * 0x10-0x1b: Context status DWords (GM45)
845 * 0x1f: Last written status offset. (GM45)
847 * The area from dword 0x20 to 0x3ff is available for driver usage.
849 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
850 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
851 #define I915_GEM_HWS_INDEX 0x20
852 #define I915_BREADCRUMB_INDEX 0x21
854 extern int i915_wrap_ring(struct drm_device * dev);
855 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
857 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
858 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
859 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
860 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
861 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
863 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
864 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
865 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
866 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
867 (dev)->pci_device == 0x27AE)
868 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
869 (dev)->pci_device == 0x2982 || \
870 (dev)->pci_device == 0x2992 || \
871 (dev)->pci_device == 0x29A2 || \
872 (dev)->pci_device == 0x2A02 || \
873 (dev)->pci_device == 0x2A12 || \
874 (dev)->pci_device == 0x2A42 || \
875 (dev)->pci_device == 0x2E02 || \
876 (dev)->pci_device == 0x2E12 || \
877 (dev)->pci_device == 0x2E22 || \
878 (dev)->pci_device == 0x2E32 || \
879 (dev)->pci_device == 0x2E42 || \
880 (dev)->pci_device == 0x0042 || \
881 (dev)->pci_device == 0x0046)
883 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
884 (dev)->pci_device == 0x2A12)
886 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
888 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
889 (dev)->pci_device == 0x2E12 || \
890 (dev)->pci_device == 0x2E22 || \
891 (dev)->pci_device == 0x2E32 || \
892 (dev)->pci_device == 0x2E42 || \
895 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
896 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
897 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
899 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
900 (dev)->pci_device == 0x29B2 || \
901 (dev)->pci_device == 0x29D2 || \
904 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
905 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
906 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
908 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
909 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
912 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
913 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
914 IS_IGD(dev) || IS_IGDNG_M(dev))
916 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
918 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
919 * rows, which changed the alignment requirements and fence programming.
921 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
923 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
924 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
925 #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
926 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
927 /* dsparb controlled by hw only */
928 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
930 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
931 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
932 #define I915_HAS_FBC(dev) (IS_I9XX(dev) || IS_I965G(dev))
934 #define PRIMARY_RINGBUFFER_SIZE (128*1024)