1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
56 #define I915_NUM_PIPE 2
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
72 #define WATCH_COHERENCY 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
85 struct drm_i915_gem_phys_object {
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
92 typedef struct _drm_i915_ring_buffer {
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
103 struct mem_block *next;
104 struct mem_block *prev;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
133 struct sdvo_device_mapping {
140 struct drm_i915_error_state {
156 typedef struct drm_i915_private {
157 struct drm_device *dev;
163 struct pci_dev *bridge_dev;
164 drm_i915_ring_buffer_t ring;
166 drm_dma_handle_t *status_page_dmah;
167 void *hw_status_page;
168 dma_addr_t dma_status_page;
170 unsigned int status_gfx_addr;
171 drm_local_map_t hws_map;
172 struct drm_gem_object *hws_obj;
174 struct resource mch_res;
182 wait_queue_head_t irq_queue;
183 atomic_t irq_received;
184 /** Protects user_irq_refcount and irq_mask_reg */
185 spinlock_t user_irq_lock;
186 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
187 int user_irq_refcount;
188 /** Cached value of IMR to avoid reads in updating the bitfield */
191 /** splitted irq regs for graphics and display engine on IGDNG,
192 irq_mask_reg is still used for display irq. */
194 u32 gt_irq_enable_reg;
195 u32 de_irq_enable_reg;
197 u32 hotplug_supported_mask;
198 struct work_struct hotplug_work;
200 int tex_lru_log_granularity;
201 int allow_batchbuffer;
202 struct mem_block *agp_heap;
203 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
206 /* For hangcheck timer */
207 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
208 struct timer_list hangcheck_timer;
212 bool cursor_needs_physical;
216 unsigned long cfb_size;
217 unsigned long cfb_pitch;
223 struct intel_opregion opregion;
226 int backlight_duty_cycle; /* restore backlight to this value */
227 bool panel_wants_dither;
228 struct drm_display_mode *panel_fixed_mode;
229 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
230 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
232 /* Feature bits from the VBIOS */
233 unsigned int int_tv_support:1;
234 unsigned int lvds_dither:1;
235 unsigned int lvds_vbt:1;
236 unsigned int int_crt_support:1;
237 unsigned int lvds_use_ssc:1;
238 unsigned int edp_support:1;
241 struct notifier_block lid_notifier;
243 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
244 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
245 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
246 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
248 unsigned int fsb_freq, mem_freq;
250 spinlock_t error_lock;
251 struct drm_i915_error_state *first_error;
252 struct work_struct error_work;
253 struct workqueue_struct *wq;
261 u32 saveRENDERSTANDBY;
285 u32 savePFIT_PGM_RATIOS;
287 u32 saveBLC_PWM_CTL2;
312 u32 savePP_ON_DELAYS;
313 u32 savePP_OFF_DELAYS;
321 u32 savePFIT_CONTROL;
322 u32 save_palette_a[256];
323 u32 save_palette_b[256];
324 u32 saveFBC_CFB_BASE;
327 u32 saveFBC_CONTROL2;
331 u32 saveCACHE_MODE_0;
333 u32 saveDSPCLK_GATE_D;
334 u32 saveMI_ARB_STATE;
345 uint64_t saveFENCE[16];
356 u32 savePIPEA_GMCH_DATA_M;
357 u32 savePIPEB_GMCH_DATA_M;
358 u32 savePIPEA_GMCH_DATA_N;
359 u32 savePIPEB_GMCH_DATA_N;
360 u32 savePIPEA_DP_LINK_M;
361 u32 savePIPEB_DP_LINK_M;
362 u32 savePIPEA_DP_LINK_N;
363 u32 savePIPEB_DP_LINK_N;
366 struct drm_mm gtt_space;
368 struct io_mapping *gtt_mapping;
372 * List of objects currently involved in rendering from the
375 * Includes buffers having the contents of their GPU caches
376 * flushed, not necessarily primitives. last_rendering_seqno
377 * represents when the rendering involved will be completed.
379 * A reference is held on the buffer while on this list.
381 spinlock_t active_list_lock;
382 struct list_head active_list;
385 * List of objects which are not in the ringbuffer but which
386 * still have a write_domain which needs to be flushed before
389 * last_rendering_seqno is 0 while an object is in this list.
391 * A reference is held on the buffer while on this list.
393 struct list_head flushing_list;
396 * LRU list of objects which are not in the ringbuffer and
397 * are ready to unbind, but are still in the GTT.
399 * last_rendering_seqno is 0 while an object is in this list.
401 * A reference is not held on the buffer while on this list,
402 * as merely being GTT-bound shouldn't prevent its being
403 * freed, and we'll pull it off the list in the free path.
405 struct list_head inactive_list;
407 /** LRU list of objects with fence regs on them. */
408 struct list_head fence_list;
411 * List of breadcrumbs associated with GPU requests currently
414 struct list_head request_list;
417 * We leave the user IRQ off as much as possible,
418 * but this means that requests will finish and never
419 * be retired once the system goes idle. Set a timer to
420 * fire periodically while the ring is running. When it
421 * fires, go retire requests.
423 struct delayed_work retire_work;
425 uint32_t next_gem_seqno;
428 * Waiting sequence number, if any
430 uint32_t waiting_gem_seqno;
433 * Last seq seen at irq time
435 uint32_t irq_gem_seqno;
438 * Flag if the X Server, and thus DRM, is not currently in
439 * control of the device.
441 * This is set between LeaveVT and EnterVT. It needs to be
442 * replaced with a semaphore. It also needs to be
443 * transitioned away from for kernel modesetting.
448 * Flag if the hardware appears to be wedged.
450 * This is set when attempts to idle the device timeout.
451 * It prevents command submission from occuring and makes
452 * every pending request fail
456 /** Bit 6 swizzling required for X tiling */
457 uint32_t bit_6_swizzle_x;
458 /** Bit 6 swizzling required for Y tiling */
459 uint32_t bit_6_swizzle_y;
461 /* storage for physical objects */
462 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
464 struct sdvo_device_mapping sdvo_mappings[2];
466 /* Reclocking support */
467 bool render_reclock_avail;
468 bool lvds_downclock_avail;
469 struct work_struct idle_work;
470 struct timer_list idle_timer;
473 } drm_i915_private_t;
475 /** driver private structure attached to each drm_gem_object */
476 struct drm_i915_gem_object {
477 struct drm_gem_object *obj;
479 /** Current space allocated to this object in the GTT, if any. */
480 struct drm_mm_node *gtt_space;
482 /** This object's place on the active/flushing/inactive lists */
483 struct list_head list;
485 /** This object's place on the fenced object LRU */
486 struct list_head fence_list;
489 * This is set if the object is on the active or flushing lists
490 * (has pending rendering), and is not set if it's on inactive (ready
496 * This is set if the object has been written to since last bound
501 /** AGP memory structure for our GTT binding. */
502 DRM_AGP_MEM *agp_mem;
508 * Current offset of the object in GTT space.
510 * This is the same as gtt_space->start
514 * Required alignment for the object
516 uint32_t gtt_alignment;
518 * Fake offset for use by mmap(2)
520 uint64_t mmap_offset;
523 * Fence register bits (if any) for this object. Will be set
524 * as needed when mapped into the GTT.
525 * Protected by dev->struct_mutex.
529 /** How many users have pinned this object in GTT space */
532 /** Breadcrumb of last rendering to the buffer. */
533 uint32_t last_rendering_seqno;
535 /** Current tiling mode for the object. */
536 uint32_t tiling_mode;
539 /** Record of address bit 17 of each page at last unbind. */
542 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
546 * If present, while GEM_DOMAIN_CPU is in the read domain this array
547 * flags which individual pages are valid.
549 uint8_t *page_cpu_valid;
551 /** User space pin count and filp owning the pin */
552 uint32_t user_pin_count;
553 struct drm_file *pin_filp;
555 /** for phy allocated objects */
556 struct drm_i915_gem_phys_object *phys_obj;
559 * Used for checking the object doesn't appear more than once
560 * in an execbuffer object list.
566 * Request queue structure.
568 * The request queue allows us to note sequence numbers that have been emitted
569 * and may be associated with active buffers to be retired.
571 * By keeping this list, we can avoid having to do questionable
572 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
573 * an emission time with seqnos for tracking how far ahead of the GPU we are.
575 struct drm_i915_gem_request {
576 /** GEM sequence number associated with this request. */
579 /** Time at which this request was emitted, in jiffies. */
580 unsigned long emitted_jiffies;
582 /** global list entry for this request */
583 struct list_head list;
585 /** file_priv list entry for this request */
586 struct list_head client_list;
589 struct drm_i915_file_private {
591 struct list_head request_list;
595 enum intel_chip_family {
602 extern struct drm_ioctl_desc i915_ioctls[];
603 extern int i915_max_ioctl;
604 extern unsigned int i915_fbpercrtc;
605 extern unsigned int i915_powersave;
607 extern void i915_save_display(struct drm_device *dev);
608 extern void i915_restore_display(struct drm_device *dev);
609 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
610 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
613 extern void i915_kernel_lost_context(struct drm_device * dev);
614 extern int i915_driver_load(struct drm_device *, unsigned long flags);
615 extern int i915_driver_unload(struct drm_device *);
616 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
617 extern void i915_driver_lastclose(struct drm_device * dev);
618 extern void i915_driver_preclose(struct drm_device *dev,
619 struct drm_file *file_priv);
620 extern void i915_driver_postclose(struct drm_device *dev,
621 struct drm_file *file_priv);
622 extern int i915_driver_device_is_agp(struct drm_device * dev);
623 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
625 extern int i915_emit_box(struct drm_device *dev,
626 struct drm_clip_rect *boxes,
627 int i, int DR1, int DR4);
628 extern int i965_reset(struct drm_device *dev, u8 flags);
631 void i915_hangcheck_elapsed(unsigned long data);
632 extern int i915_irq_emit(struct drm_device *dev, void *data,
633 struct drm_file *file_priv);
634 extern int i915_irq_wait(struct drm_device *dev, void *data,
635 struct drm_file *file_priv);
636 void i915_user_irq_get(struct drm_device *dev);
637 void i915_user_irq_put(struct drm_device *dev);
638 extern void i915_enable_interrupt (struct drm_device *dev);
640 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
641 extern void i915_driver_irq_preinstall(struct drm_device * dev);
642 extern int i915_driver_irq_postinstall(struct drm_device *dev);
643 extern void i915_driver_irq_uninstall(struct drm_device * dev);
644 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
645 struct drm_file *file_priv);
646 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
647 struct drm_file *file_priv);
648 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
649 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
650 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
651 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
652 extern int i915_vblank_swap(struct drm_device *dev, void *data,
653 struct drm_file *file_priv);
654 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
657 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
660 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
664 extern int i915_mem_alloc(struct drm_device *dev, void *data,
665 struct drm_file *file_priv);
666 extern int i915_mem_free(struct drm_device *dev, void *data,
667 struct drm_file *file_priv);
668 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
669 struct drm_file *file_priv);
670 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
671 struct drm_file *file_priv);
672 extern void i915_mem_takedown(struct mem_block **heap);
673 extern void i915_mem_release(struct drm_device * dev,
674 struct drm_file *file_priv, struct mem_block *heap);
676 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
677 struct drm_file *file_priv);
678 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
679 struct drm_file *file_priv);
680 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
681 struct drm_file *file_priv);
682 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
683 struct drm_file *file_priv);
684 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
685 struct drm_file *file_priv);
686 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
687 struct drm_file *file_priv);
688 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
689 struct drm_file *file_priv);
690 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
691 struct drm_file *file_priv);
692 int i915_gem_execbuffer(struct drm_device *dev, void *data,
693 struct drm_file *file_priv);
694 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
695 struct drm_file *file_priv);
696 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
697 struct drm_file *file_priv);
698 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
699 struct drm_file *file_priv);
700 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
701 struct drm_file *file_priv);
702 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
703 struct drm_file *file_priv);
704 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
705 struct drm_file *file_priv);
706 int i915_gem_set_tiling(struct drm_device *dev, void *data,
707 struct drm_file *file_priv);
708 int i915_gem_get_tiling(struct drm_device *dev, void *data,
709 struct drm_file *file_priv);
710 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *file_priv);
712 void i915_gem_load(struct drm_device *dev);
713 int i915_gem_init_object(struct drm_gem_object *obj);
714 void i915_gem_free_object(struct drm_gem_object *obj);
715 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
716 void i915_gem_object_unpin(struct drm_gem_object *obj);
717 int i915_gem_object_unbind(struct drm_gem_object *obj);
718 void i915_gem_release_mmap(struct drm_gem_object *obj);
719 void i915_gem_lastclose(struct drm_device *dev);
720 uint32_t i915_get_gem_seqno(struct drm_device *dev);
721 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
722 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
723 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
724 void i915_gem_retire_requests(struct drm_device *dev);
725 void i915_gem_retire_work_handler(struct work_struct *work);
726 void i915_gem_clflush_object(struct drm_gem_object *obj);
727 int i915_gem_object_set_domain(struct drm_gem_object *obj,
728 uint32_t read_domains,
729 uint32_t write_domain);
730 int i915_gem_init_ringbuffer(struct drm_device *dev);
731 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
732 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
734 int i915_gem_idle(struct drm_device *dev);
735 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
736 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
738 int i915_gem_attach_phys_object(struct drm_device *dev,
739 struct drm_gem_object *obj, int id);
740 void i915_gem_detach_phys_object(struct drm_device *dev,
741 struct drm_gem_object *obj);
742 void i915_gem_free_all_phys_object(struct drm_device *dev);
743 int i915_gem_object_get_pages(struct drm_gem_object *obj);
744 void i915_gem_object_put_pages(struct drm_gem_object *obj);
745 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
747 /* i915_gem_tiling.c */
748 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
749 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
750 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
752 /* i915_gem_debug.c */
753 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
754 const char *where, uint32_t mark);
756 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
758 #define i915_verify_inactive(dev, file, line)
760 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
761 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
762 const char *where, uint32_t mark);
763 void i915_dump_lru(struct drm_device *dev, const char *where);
766 int i915_debugfs_init(struct drm_minor *minor);
767 void i915_debugfs_cleanup(struct drm_minor *minor);
770 extern int i915_save_state(struct drm_device *dev);
771 extern int i915_restore_state(struct drm_device *dev);
774 extern int i915_save_state(struct drm_device *dev);
775 extern int i915_restore_state(struct drm_device *dev);
778 /* i915_opregion.c */
779 extern int intel_opregion_init(struct drm_device *dev, int resume);
780 extern void intel_opregion_free(struct drm_device *dev, int suspend);
781 extern void opregion_asle_intr(struct drm_device *dev);
782 extern void opregion_enable_asle(struct drm_device *dev);
784 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
785 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
786 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
787 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
791 extern void intel_modeset_init(struct drm_device *dev);
792 extern void intel_modeset_cleanup(struct drm_device *dev);
793 extern void i8xx_disable_fbc(struct drm_device *dev);
796 * Lock test for when it's just for synchronization of ring access.
798 * In that case, we don't need to do it when GEM is initialized as nobody else
799 * has access to the ring.
801 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
802 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
803 LOCK_TEST_WITH_RETURN(dev, file_priv); \
806 #define I915_READ(reg) readl(dev_priv->regs + (reg))
807 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
808 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
809 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
810 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
811 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
812 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
813 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
814 #define POSTING_READ(reg) (void)I915_READ(reg)
816 #define I915_VERBOSE 0
818 #define RING_LOCALS volatile unsigned int *ring_virt__;
820 #define BEGIN_LP_RING(n) do { \
821 int bytes__ = 4*(n); \
822 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
823 /* a wrap must occur between instructions so pad beforehand */ \
824 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
825 i915_wrap_ring(dev); \
826 if (unlikely (dev_priv->ring.space < bytes__)) \
827 i915_wait_ring(dev, bytes__, __func__); \
828 ring_virt__ = (unsigned int *) \
829 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
830 dev_priv->ring.tail += bytes__; \
831 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
832 dev_priv->ring.space -= bytes__; \
835 #define OUT_RING(n) do { \
836 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
837 *ring_virt__++ = (n); \
840 #define ADVANCE_LP_RING() do { \
842 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
843 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
847 * Reads a dword out of the status page, which is written to from the command
848 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
851 * The following dwords have a reserved meaning:
852 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
853 * 0x04: ring 0 head pointer
854 * 0x05: ring 1 head pointer (915-class)
855 * 0x06: ring 2 head pointer (915-class)
856 * 0x10-0x1b: Context status DWords (GM45)
857 * 0x1f: Last written status offset. (GM45)
859 * The area from dword 0x20 to 0x3ff is available for driver usage.
861 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
862 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
863 #define I915_GEM_HWS_INDEX 0x20
864 #define I915_BREADCRUMB_INDEX 0x21
866 extern int i915_wrap_ring(struct drm_device * dev);
867 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
869 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
870 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
871 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
872 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
873 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
875 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
876 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
877 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
878 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
879 (dev)->pci_device == 0x27AE)
880 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
881 (dev)->pci_device == 0x2982 || \
882 (dev)->pci_device == 0x2992 || \
883 (dev)->pci_device == 0x29A2 || \
884 (dev)->pci_device == 0x2A02 || \
885 (dev)->pci_device == 0x2A12 || \
886 (dev)->pci_device == 0x2A42 || \
887 (dev)->pci_device == 0x2E02 || \
888 (dev)->pci_device == 0x2E12 || \
889 (dev)->pci_device == 0x2E22 || \
890 (dev)->pci_device == 0x2E32 || \
891 (dev)->pci_device == 0x2E42 || \
892 (dev)->pci_device == 0x0042 || \
893 (dev)->pci_device == 0x0046)
895 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
896 (dev)->pci_device == 0x2A12)
898 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
900 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
901 (dev)->pci_device == 0x2E12 || \
902 (dev)->pci_device == 0x2E22 || \
903 (dev)->pci_device == 0x2E32 || \
904 (dev)->pci_device == 0x2E42 || \
907 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
908 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
909 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
911 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
912 (dev)->pci_device == 0x29B2 || \
913 (dev)->pci_device == 0x29D2 || \
916 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
917 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
918 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
920 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
921 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
924 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
925 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
926 IS_IGD(dev) || IS_IGDNG_M(dev))
928 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
930 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
931 * rows, which changed the alignment requirements and fence programming.
933 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
935 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
936 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
937 #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
938 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
939 /* dsparb controlled by hw only */
940 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
942 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
943 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
944 #define I915_HAS_FBC(dev) (IS_I9XX(dev) || IS_I965G(dev))
946 #define PRIMARY_RINGBUFFER_SIZE (128*1024)