1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
56 #define I915_NUM_PIPE 2
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
72 #define WATCH_COHERENCY 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
85 struct drm_i915_gem_phys_object {
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
92 typedef struct _drm_i915_ring_buffer {
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
103 struct mem_block *next;
104 struct mem_block *prev;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131 struct list_head lru_list;
134 struct sdvo_device_mapping {
142 struct drm_i915_error_state {
157 struct drm_i915_error_object {
161 } *ringbuffer, *batchbuffer[2];
162 struct drm_i915_error_buffer {
178 struct drm_i915_display_funcs {
179 void (*dpms)(struct drm_crtc *crtc, int mode);
180 bool (*fbc_enabled)(struct drm_device *dev);
181 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
182 void (*disable_fbc)(struct drm_device *dev);
183 int (*get_display_clock_speed)(struct drm_device *dev);
184 int (*get_fifo_size)(struct drm_device *dev, int plane);
185 void (*update_wm)(struct drm_device *dev, int planea_clock,
186 int planeb_clock, int sr_hdisplay, int pixel_size);
187 /* clock updates for mode set */
189 /* render clock increase/decrease */
190 /* display clock increase/decrease */
191 /* pll clock increase/decrease */
192 /* clock gating init */
195 struct intel_overlay;
197 struct intel_device_info {
214 u8 has_pipe_cxsr : 1;
216 u8 cursor_needs_physical : 1;
220 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
221 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
222 FBC_MODE_TOO_LARGE, /* mode too large for compression */
223 FBC_BAD_PLANE, /* fbc not supported on plane */
224 FBC_NOT_TILED, /* buffer not tiled */
228 PCH_IBX, /* Ibexpeak PCH */
229 PCH_CPT, /* Cougarpoint PCH */
234 typedef struct drm_i915_private {
235 struct drm_device *dev;
237 const struct intel_device_info *info;
243 struct pci_dev *bridge_dev;
244 drm_i915_ring_buffer_t ring;
246 drm_dma_handle_t *status_page_dmah;
247 void *hw_status_page;
249 dma_addr_t dma_status_page;
251 unsigned int status_gfx_addr;
252 unsigned int seqno_gfx_addr;
253 drm_local_map_t hws_map;
254 struct drm_gem_object *hws_obj;
255 struct drm_gem_object *seqno_obj;
256 struct drm_gem_object *pwrctx;
258 struct resource mch_res;
266 wait_queue_head_t irq_queue;
267 atomic_t irq_received;
268 /** Protects user_irq_refcount and irq_mask_reg */
269 spinlock_t user_irq_lock;
270 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
271 int user_irq_refcount;
273 /** Cached value of IMR to avoid reads in updating the bitfield */
276 /** splitted irq regs for graphics and display engine on Ironlake,
277 irq_mask_reg is still used for display irq. */
279 u32 gt_irq_enable_reg;
280 u32 de_irq_enable_reg;
281 u32 pch_irq_mask_reg;
282 u32 pch_irq_enable_reg;
284 u32 hotplug_supported_mask;
285 struct work_struct hotplug_work;
287 int tex_lru_log_granularity;
288 int allow_batchbuffer;
289 struct mem_block *agp_heap;
290 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
293 /* For hangcheck timer */
294 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
295 struct timer_list hangcheck_timer;
301 unsigned long cfb_size;
302 unsigned long cfb_pitch;
308 struct intel_opregion opregion;
311 struct intel_overlay *overlay;
314 int backlight_duty_cycle; /* restore backlight to this value */
315 bool panel_wants_dither;
316 struct drm_display_mode *panel_fixed_mode;
317 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
318 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
320 /* Feature bits from the VBIOS */
321 unsigned int int_tv_support:1;
322 unsigned int lvds_dither:1;
323 unsigned int lvds_vbt:1;
324 unsigned int int_crt_support:1;
325 unsigned int lvds_use_ssc:1;
326 unsigned int edp_support:1;
330 struct notifier_block lid_notifier;
332 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
333 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
334 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
335 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
337 unsigned int fsb_freq, mem_freq;
339 spinlock_t error_lock;
340 struct drm_i915_error_state *first_error;
341 struct work_struct error_work;
342 struct workqueue_struct *wq;
344 /* Display functions */
345 struct drm_i915_display_funcs display;
347 /* PCH chipset type */
348 enum intel_pch pch_type;
373 u32 saveTRANS_HTOTAL_A;
374 u32 saveTRANS_HBLANK_A;
375 u32 saveTRANS_HSYNC_A;
376 u32 saveTRANS_VTOTAL_A;
377 u32 saveTRANS_VBLANK_A;
378 u32 saveTRANS_VSYNC_A;
386 u32 savePFIT_PGM_RATIOS;
387 u32 saveBLC_HIST_CTL;
389 u32 saveBLC_PWM_CTL2;
390 u32 saveBLC_CPU_PWM_CTL;
391 u32 saveBLC_CPU_PWM_CTL2;
404 u32 saveTRANS_HTOTAL_B;
405 u32 saveTRANS_HBLANK_B;
406 u32 saveTRANS_HSYNC_B;
407 u32 saveTRANS_VTOTAL_B;
408 u32 saveTRANS_VBLANK_B;
409 u32 saveTRANS_VSYNC_B;
423 u32 savePP_ON_DELAYS;
424 u32 savePP_OFF_DELAYS;
432 u32 savePFIT_CONTROL;
433 u32 save_palette_a[256];
434 u32 save_palette_b[256];
435 u32 saveDPFC_CB_BASE;
436 u32 saveFBC_CFB_BASE;
439 u32 saveFBC_CONTROL2;
449 u32 saveCACHE_MODE_0;
450 u32 saveMI_ARB_STATE;
461 uint64_t saveFENCE[16];
472 u32 savePIPEA_GMCH_DATA_M;
473 u32 savePIPEB_GMCH_DATA_M;
474 u32 savePIPEA_GMCH_DATA_N;
475 u32 savePIPEB_GMCH_DATA_N;
476 u32 savePIPEA_DP_LINK_M;
477 u32 savePIPEB_DP_LINK_M;
478 u32 savePIPEA_DP_LINK_N;
479 u32 savePIPEB_DP_LINK_N;
490 u32 savePCH_DREF_CONTROL;
491 u32 saveDISP_ARB_CTL;
492 u32 savePIPEA_DATA_M1;
493 u32 savePIPEA_DATA_N1;
494 u32 savePIPEA_LINK_M1;
495 u32 savePIPEA_LINK_N1;
496 u32 savePIPEB_DATA_M1;
497 u32 savePIPEB_DATA_N1;
498 u32 savePIPEB_LINK_M1;
499 u32 savePIPEB_LINK_N1;
500 u32 saveMCHBAR_RENDER_STANDBY;
503 struct drm_mm gtt_space;
505 struct io_mapping *gtt_mapping;
509 * Membership on list of all loaded devices, used to evict
510 * inactive buffers under memory pressure.
512 * Modifications should only be done whilst holding the
513 * shrink_list_lock spinlock.
515 struct list_head shrink_list;
518 * List of objects currently involved in rendering from the
521 * Includes buffers having the contents of their GPU caches
522 * flushed, not necessarily primitives. last_rendering_seqno
523 * represents when the rendering involved will be completed.
525 * A reference is held on the buffer while on this list.
527 spinlock_t active_list_lock;
528 struct list_head active_list;
531 * List of objects which are not in the ringbuffer but which
532 * still have a write_domain which needs to be flushed before
535 * last_rendering_seqno is 0 while an object is in this list.
537 * A reference is held on the buffer while on this list.
539 struct list_head flushing_list;
542 * List of objects currently pending a GPU write flush.
544 * All elements on this list will belong to either the
545 * active_list or flushing_list, last_rendering_seqno can
546 * be used to differentiate between the two elements.
548 struct list_head gpu_write_list;
551 * LRU list of objects which are not in the ringbuffer and
552 * are ready to unbind, but are still in the GTT.
554 * last_rendering_seqno is 0 while an object is in this list.
556 * A reference is not held on the buffer while on this list,
557 * as merely being GTT-bound shouldn't prevent its being
558 * freed, and we'll pull it off the list in the free path.
560 struct list_head inactive_list;
562 /** LRU list of objects with fence regs on them. */
563 struct list_head fence_list;
566 * List of breadcrumbs associated with GPU requests currently
569 struct list_head request_list;
572 * We leave the user IRQ off as much as possible,
573 * but this means that requests will finish and never
574 * be retired once the system goes idle. Set a timer to
575 * fire periodically while the ring is running. When it
576 * fires, go retire requests.
578 struct delayed_work retire_work;
580 uint32_t next_gem_seqno;
583 * Waiting sequence number, if any
585 uint32_t waiting_gem_seqno;
588 * Last seq seen at irq time
590 uint32_t irq_gem_seqno;
593 * Flag if the X Server, and thus DRM, is not currently in
594 * control of the device.
596 * This is set between LeaveVT and EnterVT. It needs to be
597 * replaced with a semaphore. It also needs to be
598 * transitioned away from for kernel modesetting.
603 * Flag if the hardware appears to be wedged.
605 * This is set when attempts to idle the device timeout.
606 * It prevents command submission from occuring and makes
607 * every pending request fail
611 /** Bit 6 swizzling required for X tiling */
612 uint32_t bit_6_swizzle_x;
613 /** Bit 6 swizzling required for Y tiling */
614 uint32_t bit_6_swizzle_y;
616 /* storage for physical objects */
617 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
619 struct sdvo_device_mapping sdvo_mappings[2];
620 /* indicate whether the LVDS_BORDER should be enabled or not */
621 unsigned int lvds_border_bits;
623 struct drm_crtc *plane_to_crtc_mapping[2];
624 struct drm_crtc *pipe_to_crtc_mapping[2];
625 wait_queue_head_t pending_flip_queue;
627 /* Reclocking support */
628 bool render_reclock_avail;
629 bool lvds_downclock_avail;
630 /* indicate whether the LVDS EDID is OK */
632 /* indicates the reduced downclock for LVDS*/
634 struct work_struct idle_work;
635 struct timer_list idle_timer;
639 struct child_device_config *child_dev;
640 struct drm_connector *int_lvds_connector;
642 bool mchbar_need_disable;
648 enum no_fbc_reason no_fbc_reason;
650 struct drm_mm_node *compressed_fb;
651 struct drm_mm_node *compressed_llb;
653 /* list of fbdev register on this device */
654 struct intel_fbdev *fbdev;
655 } drm_i915_private_t;
657 /** driver private structure attached to each drm_gem_object */
658 struct drm_i915_gem_object {
659 struct drm_gem_object base;
661 /** Current space allocated to this object in the GTT, if any. */
662 struct drm_mm_node *gtt_space;
664 /** This object's place on the active/flushing/inactive lists */
665 struct list_head list;
666 /** This object's place on GPU write list */
667 struct list_head gpu_write_list;
670 * This is set if the object is on the active or flushing lists
671 * (has pending rendering), and is not set if it's on inactive (ready
677 * This is set if the object has been written to since last bound
682 /** AGP memory structure for our GTT binding. */
683 DRM_AGP_MEM *agp_mem;
689 * Current offset of the object in GTT space.
691 * This is the same as gtt_space->start
696 * Fake offset for use by mmap(2)
698 uint64_t mmap_offset;
701 * Fence register bits (if any) for this object. Will be set
702 * as needed when mapped into the GTT.
703 * Protected by dev->struct_mutex.
707 /** How many users have pinned this object in GTT space */
710 /** Breadcrumb of last rendering to the buffer. */
711 uint32_t last_rendering_seqno;
713 /** Current tiling mode for the object. */
714 uint32_t tiling_mode;
717 /** Record of address bit 17 of each page at last unbind. */
720 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
724 * If present, while GEM_DOMAIN_CPU is in the read domain this array
725 * flags which individual pages are valid.
727 uint8_t *page_cpu_valid;
729 /** User space pin count and filp owning the pin */
730 uint32_t user_pin_count;
731 struct drm_file *pin_filp;
733 /** for phy allocated objects */
734 struct drm_i915_gem_phys_object *phys_obj;
737 * Used for checking the object doesn't appear more than once
738 * in an execbuffer object list.
743 * Advice: are the backing pages purgeable?
748 * Number of crtcs where this object is currently the fb, but
749 * will be page flipped away on the next vblank. When it
750 * reaches 0, dev_priv->pending_flip_queue will be woken up.
752 atomic_t pending_flip;
755 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
758 * Request queue structure.
760 * The request queue allows us to note sequence numbers that have been emitted
761 * and may be associated with active buffers to be retired.
763 * By keeping this list, we can avoid having to do questionable
764 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
765 * an emission time with seqnos for tracking how far ahead of the GPU we are.
767 struct drm_i915_gem_request {
768 /** GEM sequence number associated with this request. */
771 /** Time at which this request was emitted, in jiffies. */
772 unsigned long emitted_jiffies;
774 /** global list entry for this request */
775 struct list_head list;
777 /** file_priv list entry for this request */
778 struct list_head client_list;
781 struct drm_i915_file_private {
783 struct list_head request_list;
787 enum intel_chip_family {
794 extern struct drm_ioctl_desc i915_ioctls[];
795 extern int i915_max_ioctl;
796 extern unsigned int i915_fbpercrtc;
797 extern unsigned int i915_powersave;
798 extern unsigned int i915_lvds_downclock;
800 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
801 extern int i915_resume(struct drm_device *dev);
802 extern void i915_save_display(struct drm_device *dev);
803 extern void i915_restore_display(struct drm_device *dev);
804 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
805 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
808 extern void i915_kernel_lost_context(struct drm_device * dev);
809 extern int i915_driver_load(struct drm_device *, unsigned long flags);
810 extern int i915_driver_unload(struct drm_device *);
811 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
812 extern void i915_driver_lastclose(struct drm_device * dev);
813 extern void i915_driver_preclose(struct drm_device *dev,
814 struct drm_file *file_priv);
815 extern void i915_driver_postclose(struct drm_device *dev,
816 struct drm_file *file_priv);
817 extern int i915_driver_device_is_agp(struct drm_device * dev);
818 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
820 extern int i915_emit_box(struct drm_device *dev,
821 struct drm_clip_rect *boxes,
822 int i, int DR1, int DR4);
823 extern int i965_reset(struct drm_device *dev, u8 flags);
826 void i915_hangcheck_elapsed(unsigned long data);
827 void i915_destroy_error_state(struct drm_device *dev);
828 extern int i915_irq_emit(struct drm_device *dev, void *data,
829 struct drm_file *file_priv);
830 extern int i915_irq_wait(struct drm_device *dev, void *data,
831 struct drm_file *file_priv);
832 void i915_user_irq_get(struct drm_device *dev);
833 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
834 void i915_user_irq_put(struct drm_device *dev);
835 extern void i915_enable_interrupt (struct drm_device *dev);
837 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
838 extern void i915_driver_irq_preinstall(struct drm_device * dev);
839 extern int i915_driver_irq_postinstall(struct drm_device *dev);
840 extern void i915_driver_irq_uninstall(struct drm_device * dev);
841 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
842 struct drm_file *file_priv);
843 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
844 struct drm_file *file_priv);
845 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
846 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
847 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
848 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
849 extern int i915_vblank_swap(struct drm_device *dev, void *data,
850 struct drm_file *file_priv);
851 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
854 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
857 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
859 void intel_enable_asle (struct drm_device *dev);
863 extern int i915_mem_alloc(struct drm_device *dev, void *data,
864 struct drm_file *file_priv);
865 extern int i915_mem_free(struct drm_device *dev, void *data,
866 struct drm_file *file_priv);
867 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
868 struct drm_file *file_priv);
869 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
870 struct drm_file *file_priv);
871 extern void i915_mem_takedown(struct mem_block **heap);
872 extern void i915_mem_release(struct drm_device * dev,
873 struct drm_file *file_priv, struct mem_block *heap);
875 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
876 struct drm_file *file_priv);
877 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
878 struct drm_file *file_priv);
879 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
880 struct drm_file *file_priv);
881 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
882 struct drm_file *file_priv);
883 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
884 struct drm_file *file_priv);
885 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
886 struct drm_file *file_priv);
887 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
890 struct drm_file *file_priv);
891 int i915_gem_execbuffer(struct drm_device *dev, void *data,
892 struct drm_file *file_priv);
893 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
894 struct drm_file *file_priv);
895 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
896 struct drm_file *file_priv);
897 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
898 struct drm_file *file_priv);
899 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
900 struct drm_file *file_priv);
901 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
902 struct drm_file *file_priv);
903 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
904 struct drm_file *file_priv);
905 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
906 struct drm_file *file_priv);
907 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
908 struct drm_file *file_priv);
909 int i915_gem_set_tiling(struct drm_device *dev, void *data,
910 struct drm_file *file_priv);
911 int i915_gem_get_tiling(struct drm_device *dev, void *data,
912 struct drm_file *file_priv);
913 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
914 struct drm_file *file_priv);
915 void i915_gem_load(struct drm_device *dev);
916 int i915_gem_init_object(struct drm_gem_object *obj);
917 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
919 void i915_gem_free_object(struct drm_gem_object *obj);
920 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
921 void i915_gem_object_unpin(struct drm_gem_object *obj);
922 int i915_gem_object_unbind(struct drm_gem_object *obj);
923 void i915_gem_release_mmap(struct drm_gem_object *obj);
924 void i915_gem_lastclose(struct drm_device *dev);
925 uint32_t i915_get_gem_seqno(struct drm_device *dev);
926 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
927 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
928 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
929 void i915_gem_retire_requests(struct drm_device *dev);
930 void i915_gem_retire_work_handler(struct work_struct *work);
931 void i915_gem_clflush_object(struct drm_gem_object *obj);
932 int i915_gem_object_set_domain(struct drm_gem_object *obj,
933 uint32_t read_domains,
934 uint32_t write_domain);
935 int i915_gem_init_ringbuffer(struct drm_device *dev);
936 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
937 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
939 int i915_gem_idle(struct drm_device *dev);
940 uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
941 uint32_t flush_domains);
942 int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
943 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
944 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
946 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
947 int i915_gem_attach_phys_object(struct drm_device *dev,
948 struct drm_gem_object *obj, int id);
949 void i915_gem_detach_phys_object(struct drm_device *dev,
950 struct drm_gem_object *obj);
951 void i915_gem_free_all_phys_object(struct drm_device *dev);
952 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
953 void i915_gem_object_put_pages(struct drm_gem_object *obj);
954 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
955 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
957 void i915_gem_shrinker_init(void);
958 void i915_gem_shrinker_exit(void);
960 /* i915_gem_tiling.c */
961 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
962 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
963 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
964 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
966 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
969 /* i915_gem_debug.c */
970 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
971 const char *where, uint32_t mark);
973 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
975 #define i915_verify_inactive(dev, file, line)
977 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
978 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
979 const char *where, uint32_t mark);
980 void i915_dump_lru(struct drm_device *dev, const char *where);
983 int i915_debugfs_init(struct drm_minor *minor);
984 void i915_debugfs_cleanup(struct drm_minor *minor);
987 extern int i915_save_state(struct drm_device *dev);
988 extern int i915_restore_state(struct drm_device *dev);
991 extern int i915_save_state(struct drm_device *dev);
992 extern int i915_restore_state(struct drm_device *dev);
995 /* i915_opregion.c */
996 extern int intel_opregion_init(struct drm_device *dev, int resume);
997 extern void intel_opregion_free(struct drm_device *dev, int suspend);
998 extern void opregion_asle_intr(struct drm_device *dev);
999 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
1000 extern void opregion_enable_asle(struct drm_device *dev);
1002 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
1003 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
1004 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
1005 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
1006 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
1010 extern void intel_modeset_init(struct drm_device *dev);
1011 extern void intel_modeset_cleanup(struct drm_device *dev);
1012 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1013 extern void i8xx_disable_fbc(struct drm_device *dev);
1014 extern void g4x_disable_fbc(struct drm_device *dev);
1015 extern void intel_disable_fbc(struct drm_device *dev);
1016 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1017 extern bool intel_fbc_enabled(struct drm_device *dev);
1019 extern void intel_detect_pch (struct drm_device *dev);
1020 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1023 * Lock test for when it's just for synchronization of ring access.
1025 * In that case, we don't need to do it when GEM is initialized as nobody else
1026 * has access to the ring.
1028 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1029 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
1030 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1033 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1034 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1035 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1036 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1037 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1038 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1039 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1040 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1041 #define POSTING_READ(reg) (void)I915_READ(reg)
1043 #define I915_VERBOSE 0
1045 #define RING_LOCALS volatile unsigned int *ring_virt__;
1047 #define BEGIN_LP_RING(n) do { \
1048 int bytes__ = 4*(n); \
1049 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
1050 /* a wrap must occur between instructions so pad beforehand */ \
1051 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
1052 i915_wrap_ring(dev); \
1053 if (unlikely (dev_priv->ring.space < bytes__)) \
1054 i915_wait_ring(dev, bytes__, __func__); \
1055 ring_virt__ = (unsigned int *) \
1056 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
1057 dev_priv->ring.tail += bytes__; \
1058 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
1059 dev_priv->ring.space -= bytes__; \
1062 #define OUT_RING(n) do { \
1063 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
1064 *ring_virt__++ = (n); \
1067 #define ADVANCE_LP_RING() do { \
1069 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
1070 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
1074 * Reads a dword out of the status page, which is written to from the command
1075 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1076 * MI_STORE_DATA_IMM.
1078 * The following dwords have a reserved meaning:
1079 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1080 * 0x04: ring 0 head pointer
1081 * 0x05: ring 1 head pointer (915-class)
1082 * 0x06: ring 2 head pointer (915-class)
1083 * 0x10-0x1b: Context status DWords (GM45)
1084 * 0x1f: Last written status offset. (GM45)
1086 * The area from dword 0x20 to 0x3ff is available for driver usage.
1088 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
1089 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1090 #define I915_GEM_HWS_INDEX 0x20
1091 #define I915_BREADCRUMB_INDEX 0x21
1093 extern int i915_wrap_ring(struct drm_device * dev);
1094 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1096 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1098 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1099 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1100 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1101 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1102 #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1103 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1104 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1105 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1106 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1107 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1108 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1109 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1110 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1111 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1112 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1113 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1114 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1115 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1116 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1117 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1118 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1119 #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1120 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1122 #define IS_GEN3(dev) (IS_I915G(dev) || \
1128 #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1129 (dev)->pci_device == 0x2982 || \
1130 (dev)->pci_device == 0x2992 || \
1131 (dev)->pci_device == 0x29A2 || \
1132 (dev)->pci_device == 0x2A02 || \
1133 (dev)->pci_device == 0x2A12 || \
1134 (dev)->pci_device == 0x2E02 || \
1135 (dev)->pci_device == 0x2E12 || \
1136 (dev)->pci_device == 0x2E22 || \
1137 (dev)->pci_device == 0x2E32 || \
1138 (dev)->pci_device == 0x2A42 || \
1139 (dev)->pci_device == 0x2E42)
1141 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1143 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1144 * rows, which changed the alignment requirements and fence programming.
1146 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1148 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1149 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1150 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1151 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1152 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1153 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1155 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1156 /* dsparb controlled by hw only */
1157 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1159 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1160 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1161 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1162 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1164 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1166 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1168 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1169 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1171 #define PRIMARY_RINGBUFFER_SIZE (128*1024)