1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
56 #define I915_NUM_PIPE 2
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
72 #define WATCH_COHERENCY 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
85 struct drm_i915_gem_phys_object {
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
92 typedef struct _drm_i915_ring_buffer {
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
103 struct mem_block *next;
104 struct mem_block *prev;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
133 struct sdvo_device_mapping {
141 struct drm_i915_error_state {
156 struct drm_i915_error_object {
160 } *ringbuffer, *batchbuffer[2];
161 struct drm_i915_error_buffer {
177 struct drm_i915_display_funcs {
178 void (*dpms)(struct drm_crtc *crtc, int mode);
179 bool (*fbc_enabled)(struct drm_device *dev);
180 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
181 void (*disable_fbc)(struct drm_device *dev);
182 int (*get_display_clock_speed)(struct drm_device *dev);
183 int (*get_fifo_size)(struct drm_device *dev, int plane);
184 void (*update_wm)(struct drm_device *dev, int planea_clock,
185 int planeb_clock, int sr_hdisplay, int pixel_size);
186 /* clock updates for mode set */
188 /* render clock increase/decrease */
189 /* display clock increase/decrease */
190 /* pll clock increase/decrease */
191 /* clock gating init */
194 struct intel_overlay;
196 struct intel_device_info {
213 u8 has_pipe_cxsr : 1;
215 u8 cursor_needs_physical : 1;
219 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
220 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
221 FBC_MODE_TOO_LARGE, /* mode too large for compression */
222 FBC_BAD_PLANE, /* fbc not supported on plane */
223 FBC_NOT_TILED, /* buffer not tiled */
227 PCH_IBX, /* Ibexpeak PCH */
228 PCH_CPT, /* Cougarpoint PCH */
233 typedef struct drm_i915_private {
234 struct drm_device *dev;
236 const struct intel_device_info *info;
242 struct pci_dev *bridge_dev;
243 drm_i915_ring_buffer_t ring;
245 drm_dma_handle_t *status_page_dmah;
246 void *hw_status_page;
248 dma_addr_t dma_status_page;
250 unsigned int status_gfx_addr;
251 unsigned int seqno_gfx_addr;
252 drm_local_map_t hws_map;
253 struct drm_gem_object *hws_obj;
254 struct drm_gem_object *seqno_obj;
255 struct drm_gem_object *pwrctx;
257 struct resource mch_res;
265 wait_queue_head_t irq_queue;
266 atomic_t irq_received;
267 /** Protects user_irq_refcount and irq_mask_reg */
268 spinlock_t user_irq_lock;
269 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
270 int user_irq_refcount;
272 /** Cached value of IMR to avoid reads in updating the bitfield */
275 /** splitted irq regs for graphics and display engine on Ironlake,
276 irq_mask_reg is still used for display irq. */
278 u32 gt_irq_enable_reg;
279 u32 de_irq_enable_reg;
280 u32 pch_irq_mask_reg;
281 u32 pch_irq_enable_reg;
283 u32 hotplug_supported_mask;
284 struct work_struct hotplug_work;
286 int tex_lru_log_granularity;
287 int allow_batchbuffer;
288 struct mem_block *agp_heap;
289 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
292 /* For hangcheck timer */
293 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
294 struct timer_list hangcheck_timer;
300 unsigned long cfb_size;
301 unsigned long cfb_pitch;
307 struct intel_opregion opregion;
310 struct intel_overlay *overlay;
313 int backlight_duty_cycle; /* restore backlight to this value */
314 bool panel_wants_dither;
315 struct drm_display_mode *panel_fixed_mode;
316 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
317 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
319 /* Feature bits from the VBIOS */
320 unsigned int int_tv_support:1;
321 unsigned int lvds_dither:1;
322 unsigned int lvds_vbt:1;
323 unsigned int int_crt_support:1;
324 unsigned int lvds_use_ssc:1;
325 unsigned int edp_support:1;
329 struct notifier_block lid_notifier;
331 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
332 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
333 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
334 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
336 unsigned int fsb_freq, mem_freq;
338 spinlock_t error_lock;
339 struct drm_i915_error_state *first_error;
340 struct work_struct error_work;
341 struct workqueue_struct *wq;
343 /* Display functions */
344 struct drm_i915_display_funcs display;
346 /* PCH chipset type */
347 enum intel_pch pch_type;
372 u32 saveTRANS_HTOTAL_A;
373 u32 saveTRANS_HBLANK_A;
374 u32 saveTRANS_HSYNC_A;
375 u32 saveTRANS_VTOTAL_A;
376 u32 saveTRANS_VBLANK_A;
377 u32 saveTRANS_VSYNC_A;
385 u32 savePFIT_PGM_RATIOS;
386 u32 saveBLC_HIST_CTL;
388 u32 saveBLC_PWM_CTL2;
389 u32 saveBLC_CPU_PWM_CTL;
390 u32 saveBLC_CPU_PWM_CTL2;
403 u32 saveTRANS_HTOTAL_B;
404 u32 saveTRANS_HBLANK_B;
405 u32 saveTRANS_HSYNC_B;
406 u32 saveTRANS_VTOTAL_B;
407 u32 saveTRANS_VBLANK_B;
408 u32 saveTRANS_VSYNC_B;
422 u32 savePP_ON_DELAYS;
423 u32 savePP_OFF_DELAYS;
431 u32 savePFIT_CONTROL;
432 u32 save_palette_a[256];
433 u32 save_palette_b[256];
434 u32 saveDPFC_CB_BASE;
435 u32 saveFBC_CFB_BASE;
438 u32 saveFBC_CONTROL2;
448 u32 saveCACHE_MODE_0;
449 u32 saveMI_ARB_STATE;
460 uint64_t saveFENCE[16];
471 u32 savePIPEA_GMCH_DATA_M;
472 u32 savePIPEB_GMCH_DATA_M;
473 u32 savePIPEA_GMCH_DATA_N;
474 u32 savePIPEB_GMCH_DATA_N;
475 u32 savePIPEA_DP_LINK_M;
476 u32 savePIPEB_DP_LINK_M;
477 u32 savePIPEA_DP_LINK_N;
478 u32 savePIPEB_DP_LINK_N;
489 u32 savePCH_DREF_CONTROL;
490 u32 saveDISP_ARB_CTL;
491 u32 savePIPEA_DATA_M1;
492 u32 savePIPEA_DATA_N1;
493 u32 savePIPEA_LINK_M1;
494 u32 savePIPEA_LINK_N1;
495 u32 savePIPEB_DATA_M1;
496 u32 savePIPEB_DATA_N1;
497 u32 savePIPEB_LINK_M1;
498 u32 savePIPEB_LINK_N1;
499 u32 saveMCHBAR_RENDER_STANDBY;
502 struct drm_mm gtt_space;
504 struct io_mapping *gtt_mapping;
508 * Membership on list of all loaded devices, used to evict
509 * inactive buffers under memory pressure.
511 * Modifications should only be done whilst holding the
512 * shrink_list_lock spinlock.
514 struct list_head shrink_list;
517 * List of objects currently involved in rendering from the
520 * Includes buffers having the contents of their GPU caches
521 * flushed, not necessarily primitives. last_rendering_seqno
522 * represents when the rendering involved will be completed.
524 * A reference is held on the buffer while on this list.
526 spinlock_t active_list_lock;
527 struct list_head active_list;
530 * List of objects which are not in the ringbuffer but which
531 * still have a write_domain which needs to be flushed before
534 * last_rendering_seqno is 0 while an object is in this list.
536 * A reference is held on the buffer while on this list.
538 struct list_head flushing_list;
541 * List of objects currently pending a GPU write flush.
543 * All elements on this list will belong to either the
544 * active_list or flushing_list, last_rendering_seqno can
545 * be used to differentiate between the two elements.
547 struct list_head gpu_write_list;
550 * LRU list of objects which are not in the ringbuffer and
551 * are ready to unbind, but are still in the GTT.
553 * last_rendering_seqno is 0 while an object is in this list.
555 * A reference is not held on the buffer while on this list,
556 * as merely being GTT-bound shouldn't prevent its being
557 * freed, and we'll pull it off the list in the free path.
559 struct list_head inactive_list;
561 /** LRU list of objects with fence regs on them. */
562 struct list_head fence_list;
565 * List of breadcrumbs associated with GPU requests currently
568 struct list_head request_list;
571 * We leave the user IRQ off as much as possible,
572 * but this means that requests will finish and never
573 * be retired once the system goes idle. Set a timer to
574 * fire periodically while the ring is running. When it
575 * fires, go retire requests.
577 struct delayed_work retire_work;
579 uint32_t next_gem_seqno;
582 * Waiting sequence number, if any
584 uint32_t waiting_gem_seqno;
587 * Last seq seen at irq time
589 uint32_t irq_gem_seqno;
592 * Flag if the X Server, and thus DRM, is not currently in
593 * control of the device.
595 * This is set between LeaveVT and EnterVT. It needs to be
596 * replaced with a semaphore. It also needs to be
597 * transitioned away from for kernel modesetting.
602 * Flag if the hardware appears to be wedged.
604 * This is set when attempts to idle the device timeout.
605 * It prevents command submission from occuring and makes
606 * every pending request fail
610 /** Bit 6 swizzling required for X tiling */
611 uint32_t bit_6_swizzle_x;
612 /** Bit 6 swizzling required for Y tiling */
613 uint32_t bit_6_swizzle_y;
615 /* storage for physical objects */
616 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
618 struct sdvo_device_mapping sdvo_mappings[2];
619 /* indicate whether the LVDS_BORDER should be enabled or not */
620 unsigned int lvds_border_bits;
622 struct drm_crtc *plane_to_crtc_mapping[2];
623 struct drm_crtc *pipe_to_crtc_mapping[2];
624 wait_queue_head_t pending_flip_queue;
626 /* Reclocking support */
627 bool render_reclock_avail;
628 bool lvds_downclock_avail;
629 /* indicate whether the LVDS EDID is OK */
631 /* indicates the reduced downclock for LVDS*/
633 struct work_struct idle_work;
634 struct timer_list idle_timer;
638 struct child_device_config *child_dev;
639 struct drm_connector *int_lvds_connector;
641 bool mchbar_need_disable;
647 enum no_fbc_reason no_fbc_reason;
649 struct drm_mm_node *compressed_fb;
650 struct drm_mm_node *compressed_llb;
652 /* list of fbdev register on this device */
653 struct intel_fbdev *fbdev;
654 } drm_i915_private_t;
656 /** driver private structure attached to each drm_gem_object */
657 struct drm_i915_gem_object {
658 struct drm_gem_object base;
660 /** Current space allocated to this object in the GTT, if any. */
661 struct drm_mm_node *gtt_space;
663 /** This object's place on the active/flushing/inactive lists */
664 struct list_head list;
665 /** This object's place on GPU write list */
666 struct list_head gpu_write_list;
668 /** This object's place on the fenced object LRU */
669 struct list_head fence_list;
672 * This is set if the object is on the active or flushing lists
673 * (has pending rendering), and is not set if it's on inactive (ready
679 * This is set if the object has been written to since last bound
684 /** AGP memory structure for our GTT binding. */
685 DRM_AGP_MEM *agp_mem;
691 * Current offset of the object in GTT space.
693 * This is the same as gtt_space->start
698 * Fake offset for use by mmap(2)
700 uint64_t mmap_offset;
703 * Fence register bits (if any) for this object. Will be set
704 * as needed when mapped into the GTT.
705 * Protected by dev->struct_mutex.
709 /** How many users have pinned this object in GTT space */
712 /** Breadcrumb of last rendering to the buffer. */
713 uint32_t last_rendering_seqno;
715 /** Current tiling mode for the object. */
716 uint32_t tiling_mode;
719 /** Record of address bit 17 of each page at last unbind. */
722 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
726 * If present, while GEM_DOMAIN_CPU is in the read domain this array
727 * flags which individual pages are valid.
729 uint8_t *page_cpu_valid;
731 /** User space pin count and filp owning the pin */
732 uint32_t user_pin_count;
733 struct drm_file *pin_filp;
735 /** for phy allocated objects */
736 struct drm_i915_gem_phys_object *phys_obj;
739 * Used for checking the object doesn't appear more than once
740 * in an execbuffer object list.
745 * Advice: are the backing pages purgeable?
750 * Number of crtcs where this object is currently the fb, but
751 * will be page flipped away on the next vblank. When it
752 * reaches 0, dev_priv->pending_flip_queue will be woken up.
754 atomic_t pending_flip;
757 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
760 * Request queue structure.
762 * The request queue allows us to note sequence numbers that have been emitted
763 * and may be associated with active buffers to be retired.
765 * By keeping this list, we can avoid having to do questionable
766 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
767 * an emission time with seqnos for tracking how far ahead of the GPU we are.
769 struct drm_i915_gem_request {
770 /** GEM sequence number associated with this request. */
773 /** Time at which this request was emitted, in jiffies. */
774 unsigned long emitted_jiffies;
776 /** global list entry for this request */
777 struct list_head list;
779 /** file_priv list entry for this request */
780 struct list_head client_list;
783 struct drm_i915_file_private {
785 struct list_head request_list;
789 enum intel_chip_family {
796 extern struct drm_ioctl_desc i915_ioctls[];
797 extern int i915_max_ioctl;
798 extern unsigned int i915_fbpercrtc;
799 extern unsigned int i915_powersave;
800 extern unsigned int i915_lvds_downclock;
802 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
803 extern int i915_resume(struct drm_device *dev);
804 extern void i915_save_display(struct drm_device *dev);
805 extern void i915_restore_display(struct drm_device *dev);
806 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
807 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
810 extern void i915_kernel_lost_context(struct drm_device * dev);
811 extern int i915_driver_load(struct drm_device *, unsigned long flags);
812 extern int i915_driver_unload(struct drm_device *);
813 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
814 extern void i915_driver_lastclose(struct drm_device * dev);
815 extern void i915_driver_preclose(struct drm_device *dev,
816 struct drm_file *file_priv);
817 extern void i915_driver_postclose(struct drm_device *dev,
818 struct drm_file *file_priv);
819 extern int i915_driver_device_is_agp(struct drm_device * dev);
820 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
822 extern int i915_emit_box(struct drm_device *dev,
823 struct drm_clip_rect *boxes,
824 int i, int DR1, int DR4);
825 extern int i965_reset(struct drm_device *dev, u8 flags);
828 void i915_hangcheck_elapsed(unsigned long data);
829 void i915_destroy_error_state(struct drm_device *dev);
830 extern int i915_irq_emit(struct drm_device *dev, void *data,
831 struct drm_file *file_priv);
832 extern int i915_irq_wait(struct drm_device *dev, void *data,
833 struct drm_file *file_priv);
834 void i915_user_irq_get(struct drm_device *dev);
835 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
836 void i915_user_irq_put(struct drm_device *dev);
837 extern void i915_enable_interrupt (struct drm_device *dev);
839 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
840 extern void i915_driver_irq_preinstall(struct drm_device * dev);
841 extern int i915_driver_irq_postinstall(struct drm_device *dev);
842 extern void i915_driver_irq_uninstall(struct drm_device * dev);
843 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
844 struct drm_file *file_priv);
845 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
846 struct drm_file *file_priv);
847 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
848 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
849 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
850 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
851 extern int i915_vblank_swap(struct drm_device *dev, void *data,
852 struct drm_file *file_priv);
853 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
856 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
859 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
861 void intel_enable_asle (struct drm_device *dev);
865 extern int i915_mem_alloc(struct drm_device *dev, void *data,
866 struct drm_file *file_priv);
867 extern int i915_mem_free(struct drm_device *dev, void *data,
868 struct drm_file *file_priv);
869 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
870 struct drm_file *file_priv);
871 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
872 struct drm_file *file_priv);
873 extern void i915_mem_takedown(struct mem_block **heap);
874 extern void i915_mem_release(struct drm_device * dev,
875 struct drm_file *file_priv, struct mem_block *heap);
877 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
878 struct drm_file *file_priv);
879 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
880 struct drm_file *file_priv);
881 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
882 struct drm_file *file_priv);
883 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
884 struct drm_file *file_priv);
885 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
886 struct drm_file *file_priv);
887 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
890 struct drm_file *file_priv);
891 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
892 struct drm_file *file_priv);
893 int i915_gem_execbuffer(struct drm_device *dev, void *data,
894 struct drm_file *file_priv);
895 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
896 struct drm_file *file_priv);
897 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
898 struct drm_file *file_priv);
899 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
900 struct drm_file *file_priv);
901 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
902 struct drm_file *file_priv);
903 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
904 struct drm_file *file_priv);
905 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
906 struct drm_file *file_priv);
907 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
908 struct drm_file *file_priv);
909 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
910 struct drm_file *file_priv);
911 int i915_gem_set_tiling(struct drm_device *dev, void *data,
912 struct drm_file *file_priv);
913 int i915_gem_get_tiling(struct drm_device *dev, void *data,
914 struct drm_file *file_priv);
915 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
916 struct drm_file *file_priv);
917 void i915_gem_load(struct drm_device *dev);
918 int i915_gem_init_object(struct drm_gem_object *obj);
919 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
921 void i915_gem_free_object(struct drm_gem_object *obj);
922 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
923 void i915_gem_object_unpin(struct drm_gem_object *obj);
924 int i915_gem_object_unbind(struct drm_gem_object *obj);
925 void i915_gem_release_mmap(struct drm_gem_object *obj);
926 void i915_gem_lastclose(struct drm_device *dev);
927 uint32_t i915_get_gem_seqno(struct drm_device *dev);
928 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
929 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
930 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
931 void i915_gem_retire_requests(struct drm_device *dev);
932 void i915_gem_retire_work_handler(struct work_struct *work);
933 void i915_gem_clflush_object(struct drm_gem_object *obj);
934 int i915_gem_object_set_domain(struct drm_gem_object *obj,
935 uint32_t read_domains,
936 uint32_t write_domain);
937 int i915_gem_init_ringbuffer(struct drm_device *dev);
938 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
939 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
941 int i915_gem_idle(struct drm_device *dev);
942 uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
943 uint32_t flush_domains);
944 int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
945 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
946 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
948 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
949 int i915_gem_attach_phys_object(struct drm_device *dev,
950 struct drm_gem_object *obj, int id);
951 void i915_gem_detach_phys_object(struct drm_device *dev,
952 struct drm_gem_object *obj);
953 void i915_gem_free_all_phys_object(struct drm_device *dev);
954 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
955 void i915_gem_object_put_pages(struct drm_gem_object *obj);
956 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
957 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
959 void i915_gem_shrinker_init(void);
960 void i915_gem_shrinker_exit(void);
962 /* i915_gem_tiling.c */
963 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
964 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
965 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
966 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
968 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
971 /* i915_gem_debug.c */
972 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
973 const char *where, uint32_t mark);
975 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
977 #define i915_verify_inactive(dev, file, line)
979 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
980 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
981 const char *where, uint32_t mark);
982 void i915_dump_lru(struct drm_device *dev, const char *where);
985 int i915_debugfs_init(struct drm_minor *minor);
986 void i915_debugfs_cleanup(struct drm_minor *minor);
989 extern int i915_save_state(struct drm_device *dev);
990 extern int i915_restore_state(struct drm_device *dev);
993 extern int i915_save_state(struct drm_device *dev);
994 extern int i915_restore_state(struct drm_device *dev);
997 /* i915_opregion.c */
998 extern int intel_opregion_init(struct drm_device *dev, int resume);
999 extern void intel_opregion_free(struct drm_device *dev, int suspend);
1000 extern void opregion_asle_intr(struct drm_device *dev);
1001 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
1002 extern void opregion_enable_asle(struct drm_device *dev);
1004 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
1005 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
1006 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
1007 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
1008 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
1012 extern void intel_modeset_init(struct drm_device *dev);
1013 extern void intel_modeset_cleanup(struct drm_device *dev);
1014 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1015 extern void i8xx_disable_fbc(struct drm_device *dev);
1016 extern void g4x_disable_fbc(struct drm_device *dev);
1017 extern void intel_disable_fbc(struct drm_device *dev);
1018 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1019 extern bool intel_fbc_enabled(struct drm_device *dev);
1021 extern void intel_detect_pch (struct drm_device *dev);
1022 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1025 * Lock test for when it's just for synchronization of ring access.
1027 * In that case, we don't need to do it when GEM is initialized as nobody else
1028 * has access to the ring.
1030 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1031 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
1032 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1035 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1036 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1037 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1038 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1039 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1040 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1041 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1042 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1043 #define POSTING_READ(reg) (void)I915_READ(reg)
1045 #define I915_VERBOSE 0
1047 #define RING_LOCALS volatile unsigned int *ring_virt__;
1049 #define BEGIN_LP_RING(n) do { \
1050 int bytes__ = 4*(n); \
1051 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
1052 /* a wrap must occur between instructions so pad beforehand */ \
1053 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
1054 i915_wrap_ring(dev); \
1055 if (unlikely (dev_priv->ring.space < bytes__)) \
1056 i915_wait_ring(dev, bytes__, __func__); \
1057 ring_virt__ = (unsigned int *) \
1058 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
1059 dev_priv->ring.tail += bytes__; \
1060 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
1061 dev_priv->ring.space -= bytes__; \
1064 #define OUT_RING(n) do { \
1065 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
1066 *ring_virt__++ = (n); \
1069 #define ADVANCE_LP_RING() do { \
1071 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
1072 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
1076 * Reads a dword out of the status page, which is written to from the command
1077 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1078 * MI_STORE_DATA_IMM.
1080 * The following dwords have a reserved meaning:
1081 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1082 * 0x04: ring 0 head pointer
1083 * 0x05: ring 1 head pointer (915-class)
1084 * 0x06: ring 2 head pointer (915-class)
1085 * 0x10-0x1b: Context status DWords (GM45)
1086 * 0x1f: Last written status offset. (GM45)
1088 * The area from dword 0x20 to 0x3ff is available for driver usage.
1090 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
1091 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1092 #define I915_GEM_HWS_INDEX 0x20
1093 #define I915_BREADCRUMB_INDEX 0x21
1095 extern int i915_wrap_ring(struct drm_device * dev);
1096 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1098 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1100 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1101 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1102 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1103 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1104 #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1105 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1106 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1107 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1108 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1109 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1110 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1111 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1112 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1113 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1114 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1115 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1116 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1117 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1118 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1119 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1120 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1121 #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1122 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1124 #define IS_GEN3(dev) (IS_I915G(dev) || \
1130 #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1131 (dev)->pci_device == 0x2982 || \
1132 (dev)->pci_device == 0x2992 || \
1133 (dev)->pci_device == 0x29A2 || \
1134 (dev)->pci_device == 0x2A02 || \
1135 (dev)->pci_device == 0x2A12 || \
1136 (dev)->pci_device == 0x2E02 || \
1137 (dev)->pci_device == 0x2E12 || \
1138 (dev)->pci_device == 0x2E22 || \
1139 (dev)->pci_device == 0x2E32 || \
1140 (dev)->pci_device == 0x2A42 || \
1141 (dev)->pci_device == 0x2E42)
1143 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1145 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1146 * rows, which changed the alignment requirements and fence programming.
1148 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1150 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1151 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1152 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1153 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1154 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1155 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1157 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1158 /* dsparb controlled by hw only */
1159 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1161 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1162 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1163 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1164 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1166 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1168 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1170 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1171 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1173 #define PRIMARY_RINGBUFFER_SIZE (128*1024)