1 /* -*- c-basic-offset: 8 -*-
3 * fw-ohci.c - Driver for OHCI 1394 boards
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/poll.h>
28 #include <linux/dma-mapping.h>
30 #include <asm/uaccess.h>
31 #include <asm/semaphore.h>
33 #include "fw-transaction.h"
36 #define descriptor_output_more 0
37 #define descriptor_output_last (1 << 12)
38 #define descriptor_input_more (2 << 12)
39 #define descriptor_input_last (3 << 12)
40 #define descriptor_status (1 << 11)
41 #define descriptor_key_immediate (2 << 8)
42 #define descriptor_ping (1 << 7)
43 #define descriptor_yy (1 << 6)
44 #define descriptor_no_irq (0 << 4)
45 #define descriptor_irq_error (1 << 4)
46 #define descriptor_irq_always (3 << 4)
47 #define descriptor_branch_always (3 << 2)
53 __le32 branch_address;
55 __le16 transfer_status;
56 } __attribute__((aligned(16)));
60 struct descriptor descriptor;
62 dma_addr_t descriptor_bus;
63 dma_addr_t buffer_bus;
69 struct tasklet_struct tasklet;
74 dma_addr_t descriptor_bus;
75 dma_addr_t buffer_bus;
77 struct list_head list;
80 struct descriptor more;
82 struct descriptor last;
89 struct tasklet_struct tasklet;
92 #define it_header_sy(v) ((v) << 0)
93 #define it_header_tcode(v) ((v) << 4)
94 #define it_header_channel(v) ((v) << 8)
95 #define it_header_tag(v) ((v) << 14)
96 #define it_header_speed(v) ((v) << 16)
97 #define it_header_data_length(v) ((v) << 16)
100 struct fw_iso_context base;
101 struct tasklet_struct tasklet;
107 struct descriptor *buffer;
108 dma_addr_t buffer_bus;
109 struct descriptor *head_descriptor;
110 struct descriptor *tail_descriptor;
111 struct descriptor *tail_descriptor_last;
112 struct descriptor *prev_descriptor;
115 #define CONFIG_ROM_SIZE 1024
120 __iomem char *registers;
121 dma_addr_t self_id_bus;
123 struct tasklet_struct bus_reset_tasklet;
125 int request_generation;
127 /* Spinlock for accessing fw_ohci data. Never call out of
128 * this driver with this lock held. */
130 u32 self_id_buffer[512];
132 /* Config rom buffers */
134 dma_addr_t config_rom_bus;
135 __be32 *next_config_rom;
136 dma_addr_t next_config_rom_bus;
139 struct ar_context ar_request_ctx;
140 struct ar_context ar_response_ctx;
141 struct at_context at_request_ctx;
142 struct at_context at_response_ctx;
145 struct iso_context *it_context_list;
147 struct iso_context *ir_context_list;
150 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
152 return container_of(card, struct fw_ohci, card);
155 #define CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
157 #define CONTEXT_RUN 0x8000
158 #define CONTEXT_WAKE 0x1000
159 #define CONTEXT_DEAD 0x0800
160 #define CONTEXT_ACTIVE 0x0400
162 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
163 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
164 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
166 #define FW_OHCI_MAJOR 240
167 #define OHCI1394_REGISTER_SIZE 0x800
168 #define OHCI_LOOP_COUNT 500
169 #define OHCI1394_PCI_HCI_Control 0x40
170 #define SELF_ID_BUF_SIZE 0x800
172 static char ohci_driver_name[] = KBUILD_MODNAME;
174 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
176 writel(data, ohci->registers + offset);
179 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
181 return readl(ohci->registers + offset);
184 static inline void flush_writes(const struct fw_ohci *ohci)
186 /* Do a dummy read to flush writes. */
187 reg_read(ohci, OHCI1394_Version);
191 ohci_update_phy_reg(struct fw_card *card, int addr,
192 int clear_bits, int set_bits)
194 struct fw_ohci *ohci = fw_ohci(card);
197 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
199 val = reg_read(ohci, OHCI1394_PhyControl);
200 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
201 fw_error("failed to set phy reg bits.\n");
205 old = OHCI1394_PhyControl_ReadData(val);
206 old = (old & ~clear_bits) | set_bits;
207 reg_write(ohci, OHCI1394_PhyControl,
208 OHCI1394_PhyControl_Write(addr, old));
213 static void ar_context_run(struct ar_context *ctx)
215 reg_write(ctx->ohci, ctx->command_ptr, ctx->descriptor_bus | 1);
216 reg_write(ctx->ohci, ctx->control_set, CONTEXT_RUN);
217 flush_writes(ctx->ohci);
220 static void ar_context_tasklet(unsigned long data)
222 struct ar_context *ctx = (struct ar_context *)data;
223 struct fw_ohci *ohci = ctx->ohci;
225 u32 status, length, tcode;
227 /* FIXME: What to do about evt_* errors? */
228 length = le16_to_cpu(ctx->descriptor.req_count) -
229 le16_to_cpu(ctx->descriptor.res_count) - 4;
230 status = le32_to_cpu(ctx->buffer[length / 4]);
232 p.ack = ((status >> 16) & 0x1f) - 16;
233 p.speed = (status >> 21) & 0x7;
234 p.timestamp = status & 0xffff;
235 p.generation = ohci->request_generation;
237 p.header[0] = le32_to_cpu(ctx->buffer[0]);
238 p.header[1] = le32_to_cpu(ctx->buffer[1]);
239 p.header[2] = le32_to_cpu(ctx->buffer[2]);
241 tcode = (p.header[0] >> 4) & 0x0f;
243 case TCODE_WRITE_QUADLET_REQUEST:
244 case TCODE_READ_QUADLET_RESPONSE:
245 p.header[3] = ctx->buffer[3];
246 p.header_length = 16;
249 case TCODE_WRITE_BLOCK_REQUEST:
250 case TCODE_READ_BLOCK_REQUEST :
251 case TCODE_READ_BLOCK_RESPONSE:
252 case TCODE_LOCK_REQUEST:
253 case TCODE_LOCK_RESPONSE:
254 p.header[3] = le32_to_cpu(ctx->buffer[3]);
255 p.header_length = 16;
258 case TCODE_WRITE_RESPONSE:
259 case TCODE_READ_QUADLET_REQUEST:
260 p.header_length = 12;
264 p.payload = (void *) ctx->buffer + p.header_length;
265 p.payload_length = length - p.header_length;
267 /* The OHCI bus reset handler synthesizes a phy packet with
268 * the new generation number when a bus reset happens (see
269 * section 8.4.2.3). This helps us determine when a request
270 * was received and make sure we send the response in the same
271 * generation. We only need this for requests; for responses
272 * we use the unique tlabel for finding the matching
275 if (p.ack + 16 == 0x09)
276 ohci->request_generation = (ctx->buffer[2] >> 16) & 0xff;
277 else if (ctx == &ohci->ar_request_ctx)
278 fw_core_handle_request(&ohci->card, &p);
280 fw_core_handle_response(&ohci->card, &p);
282 ctx->descriptor.data_address = cpu_to_le32(ctx->buffer_bus);
283 ctx->descriptor.req_count = cpu_to_le16(sizeof ctx->buffer);
284 ctx->descriptor.res_count = cpu_to_le16(sizeof ctx->buffer);
286 dma_sync_single_for_device(ohci->card.device, ctx->descriptor_bus,
287 sizeof ctx->descriptor_bus, DMA_TO_DEVICE);
289 /* FIXME: We stop and restart the ar context here, what if we
290 * stop while a receive is in progress? Maybe we could just
291 * loop the context back to itself and use it in buffer fill
292 * mode as intended... */
294 reg_write(ctx->ohci, ctx->control_clear, CONTEXT_RUN);
299 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 control_set)
301 ctx->descriptor_bus =
302 dma_map_single(ohci->card.device, &ctx->descriptor,
303 sizeof ctx->descriptor, DMA_TO_DEVICE);
304 if (ctx->descriptor_bus == 0)
307 if (ctx->descriptor_bus & 0xf)
308 fw_notify("descriptor not 16-byte aligned: 0x%08lx\n",
309 (unsigned long)ctx->descriptor_bus);
312 dma_map_single(ohci->card.device, ctx->buffer,
313 sizeof ctx->buffer, DMA_FROM_DEVICE);
315 if (ctx->buffer_bus == 0) {
316 dma_unmap_single(ohci->card.device, ctx->descriptor_bus,
317 sizeof ctx->descriptor, DMA_TO_DEVICE);
321 memset(&ctx->descriptor, 0, sizeof ctx->descriptor);
322 ctx->descriptor.control = cpu_to_le16(descriptor_input_more |
324 descriptor_branch_always);
325 ctx->descriptor.req_count = cpu_to_le16(sizeof ctx->buffer);
326 ctx->descriptor.data_address = cpu_to_le32(ctx->buffer_bus);
327 ctx->descriptor.res_count = cpu_to_le16(sizeof ctx->buffer);
329 ctx->control_set = control_set;
330 ctx->control_clear = control_set + 4;
331 ctx->command_ptr = control_set + 12;
334 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
342 do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list)
344 struct fw_packet *p, *next;
346 list_for_each_entry_safe(p, next, list, link)
347 p->callback(p, &ohci->card, p->ack);
351 complete_transmission(struct fw_packet *packet,
352 int ack, struct list_head *list)
354 list_move_tail(&packet->link, list);
358 /* This function prepares the first packet in the context queue for
359 * transmission. Must always be called with the ochi->lock held to
360 * ensure proper generation handling and locking around packet queue
363 at_context_setup_packet(struct at_context *ctx, struct list_head *list)
365 struct fw_packet *packet;
366 struct fw_ohci *ohci = ctx->ohci;
369 packet = fw_packet(ctx->list.next);
371 memset(&ctx->d, 0, sizeof ctx->d);
372 if (packet->payload_length > 0) {
373 packet->payload_bus = dma_map_single(ohci->card.device,
375 packet->payload_length,
377 if (packet->payload_bus == 0) {
378 complete_transmission(packet, -ENOMEM, list);
382 ctx->d.more.control =
383 cpu_to_le16(descriptor_output_more |
384 descriptor_key_immediate);
385 ctx->d.more.req_count = cpu_to_le16(packet->header_length);
386 ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
387 ctx->d.last.control =
388 cpu_to_le16(descriptor_output_last |
389 descriptor_irq_always |
390 descriptor_branch_always);
391 ctx->d.last.req_count = cpu_to_le16(packet->payload_length);
392 ctx->d.last.data_address = cpu_to_le32(packet->payload_bus);
395 ctx->d.more.control =
396 cpu_to_le16(descriptor_output_last |
397 descriptor_key_immediate |
398 descriptor_irq_always |
399 descriptor_branch_always);
400 ctx->d.more.req_count = cpu_to_le16(packet->header_length);
401 ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
405 /* The DMA format for asyncronous link packets is different
406 * from the IEEE1394 layout, so shift the fields around
407 * accordingly. If header_length is 8, it's a PHY packet, to
408 * which we need to prepend an extra quadlet. */
409 if (packet->header_length > 8) {
410 ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
411 (packet->speed << 16));
412 ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
413 (packet->header[0] & 0xffff0000));
414 ctx->d.header[2] = cpu_to_le32(packet->header[2]);
416 tcode = (packet->header[0] >> 4) & 0x0f;
417 if (TCODE_IS_BLOCK_PACKET(tcode))
418 ctx->d.header[3] = cpu_to_le32(packet->header[3]);
420 ctx->d.header[3] = packet->header[3];
423 cpu_to_le32((OHCI1394_phy_tcode << 4) |
424 (packet->speed << 16));
425 ctx->d.header[1] = cpu_to_le32(packet->header[0]);
426 ctx->d.header[2] = cpu_to_le32(packet->header[1]);
427 ctx->d.more.req_count = cpu_to_le16(12);
430 /* FIXME: Document how the locking works. */
431 if (ohci->generation == packet->generation) {
432 reg_write(ctx->ohci, ctx->command_ptr,
433 ctx->descriptor_bus | z);
434 reg_write(ctx->ohci, ctx->control_set,
435 CONTEXT_RUN | CONTEXT_WAKE);
437 /* We dont return error codes from this function; all
438 * transmission errors are reported through the
440 complete_transmission(packet, -ESTALE, list);
444 static void at_context_stop(struct at_context *ctx)
448 reg_write(ctx->ohci, ctx->control_clear, CONTEXT_RUN);
450 reg = reg_read(ctx->ohci, ctx->control_set);
451 if (reg & CONTEXT_ACTIVE)
452 fw_notify("Tried to stop context, but it is still active "
456 static void at_context_tasklet(unsigned long data)
458 struct at_context *ctx = (struct at_context *)data;
459 struct fw_ohci *ohci = ctx->ohci;
460 struct fw_packet *packet;
465 spin_lock_irqsave(&ohci->lock, flags);
467 packet = fw_packet(ctx->list.next);
469 at_context_stop(ctx);
471 if (packet->payload_length > 0) {
472 dma_unmap_single(ohci->card.device, packet->payload_bus,
473 packet->payload_length, DMA_TO_DEVICE);
474 evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f;
475 packet->timestamp = le16_to_cpu(ctx->d.last.res_count);
478 evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f;
479 packet->timestamp = le16_to_cpu(ctx->d.more.res_count);
484 case OHCI1394_evt_timeout:
485 /* Async response transmit timed out. */
486 complete_transmission(packet, -ETIMEDOUT, &list);
489 case OHCI1394_evt_flushed:
490 /* The packet was flushed should give same
491 * error as when we try to use a stale
492 * generation count. */
493 complete_transmission(packet, -ESTALE, &list);
496 case OHCI1394_evt_missing_ack:
497 /* This would be a higher level software
498 * error, it is using a valid (current)
499 * generation count, but the node is not on
501 complete_transmission(packet, -ENODEV, &list);
505 complete_transmission(packet, -EIO, &list);
509 complete_transmission(packet, evt - 16, &list);
511 /* If more packets are queued, set up the next one. */
512 if (!list_empty(&ctx->list))
513 at_context_setup_packet(ctx, &list);
515 spin_unlock_irqrestore(&ohci->lock, flags);
517 do_packet_callbacks(ohci, &list);
521 at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 control_set)
523 INIT_LIST_HEAD(&ctx->list);
525 ctx->descriptor_bus =
526 dma_map_single(ohci->card.device, &ctx->d,
527 sizeof ctx->d, DMA_TO_DEVICE);
528 if (ctx->descriptor_bus == 0)
531 ctx->control_set = control_set;
532 ctx->control_clear = control_set + 4;
533 ctx->command_ptr = control_set + 12;
536 tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx);
542 at_context_transmit(struct at_context *ctx, struct fw_packet *packet)
548 spin_lock_irqsave(&ctx->ohci->lock, flags);
550 was_empty = list_empty(&ctx->list);
551 list_add_tail(&packet->link, &ctx->list);
553 at_context_setup_packet(ctx, &list);
555 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
557 do_packet_callbacks(ctx->ohci, &list);
560 static void bus_reset_tasklet(unsigned long data)
562 struct fw_ohci *ohci = (struct fw_ohci *)data;
563 int self_id_count, i, j, reg, node_id;
564 int generation, new_generation;
567 reg = reg_read(ohci, OHCI1394_NodeID);
568 if (!(reg & OHCI1394_NodeID_idValid)) {
569 fw_error("node ID not valid, new bus reset in progress\n");
572 node_id = reg & 0xffff;
574 /* The count in the SelfIDCount register is the number of
575 * bytes in the self ID receive buffer. Since we also receive
576 * the inverted quadlets and a header quadlet, we shift one
577 * bit extra to get the actual number of self IDs. */
579 self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
580 generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
582 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
583 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
584 fw_error("inconsistent self IDs\n");
585 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
588 /* Check the consistency of the self IDs we just read. The
589 * problem we face is that a new bus reset can start while we
590 * read out the self IDs from the DMA buffer. If this happens,
591 * the DMA buffer will be overwritten with new self IDs and we
592 * will read out inconsistent data. The OHCI specification
593 * (section 11.2) recommends a technique similar to
594 * linux/seqlock.h, where we remember the generation of the
595 * self IDs in the buffer before reading them out and compare
596 * it to the current generation after reading them out. If
597 * the two generations match we know we have a consistent set
600 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
601 if (new_generation != generation) {
602 fw_notify("recursive bus reset detected, "
603 "discarding self ids\n");
607 /* FIXME: Document how the locking works. */
608 spin_lock_irqsave(&ohci->lock, flags);
610 ohci->generation = generation;
611 at_context_stop(&ohci->at_request_ctx);
612 at_context_stop(&ohci->at_response_ctx);
613 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
615 /* This next bit is unrelated to the AT context stuff but we
616 * have to do it under the spinlock also. If a new config rom
617 * was set up before this reset, the old one is now no longer
618 * in use and we can free it. Update the config rom pointers
619 * to point to the current config rom and clear the
620 * next_config_rom pointer so a new udpate can take place. */
622 if (ohci->next_config_rom != NULL) {
623 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
624 ohci->config_rom, ohci->config_rom_bus);
625 ohci->config_rom = ohci->next_config_rom;
626 ohci->config_rom_bus = ohci->next_config_rom_bus;
627 ohci->next_config_rom = NULL;
629 /* Restore config_rom image and manually update
630 * config_rom registers. Writing the header quadlet
631 * will indicate that the config rom is ready, so we
633 reg_write(ohci, OHCI1394_BusOptions,
634 be32_to_cpu(ohci->config_rom[2]));
635 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
636 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
639 spin_unlock_irqrestore(&ohci->lock, flags);
641 fw_core_handle_bus_reset(&ohci->card, node_id, generation,
642 self_id_count, ohci->self_id_buffer);
645 static irqreturn_t irq_handler(int irq, void *data)
647 struct fw_ohci *ohci = data;
648 u32 event, iso_event;
651 event = reg_read(ohci, OHCI1394_IntEventClear);
656 reg_write(ohci, OHCI1394_IntEventClear, event);
658 if (event & OHCI1394_selfIDComplete)
659 tasklet_schedule(&ohci->bus_reset_tasklet);
661 if (event & OHCI1394_RQPkt)
662 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
664 if (event & OHCI1394_RSPkt)
665 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
667 if (event & OHCI1394_reqTxComplete)
668 tasklet_schedule(&ohci->at_request_ctx.tasklet);
670 if (event & OHCI1394_respTxComplete)
671 tasklet_schedule(&ohci->at_response_ctx.tasklet);
673 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
674 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
677 i = ffs(iso_event) - 1;
678 tasklet_schedule(&ohci->ir_context_list[i].tasklet);
679 iso_event &= ~(1 << i);
682 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
683 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
686 i = ffs(iso_event) - 1;
687 tasklet_schedule(&ohci->it_context_list[i].tasklet);
688 iso_event &= ~(1 << i);
694 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
696 struct fw_ohci *ohci = fw_ohci(card);
697 struct pci_dev *dev = to_pci_dev(card->device);
699 /* When the link is not yet enabled, the atomic config rom
700 * update mechanism described below in ohci_set_config_rom()
701 * is not active. We have to update ConfigRomHeader and
702 * BusOptions manually, and the write to ConfigROMmap takes
703 * effect immediately. We tie this to the enabling of the
704 * link, so we have a valid config rom before enabling - the
705 * OHCI requires that ConfigROMhdr and BusOptions have valid
706 * values before enabling.
708 * However, when the ConfigROMmap is written, some controllers
709 * always read back quadlets 0 and 2 from the config rom to
710 * the ConfigRomHeader and BusOptions registers on bus reset.
711 * They shouldn't do that in this initial case where the link
712 * isn't enabled. This means we have to use the same
713 * workaround here, setting the bus header to 0 and then write
714 * the right values in the bus reset tasklet.
717 ohci->next_config_rom =
718 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
719 &ohci->next_config_rom_bus, GFP_KERNEL);
720 if (ohci->next_config_rom == NULL)
723 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
724 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
726 ohci->next_header = config_rom[0];
727 ohci->next_config_rom[0] = 0;
728 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
729 reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
730 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
732 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
734 if (request_irq(dev->irq, irq_handler,
735 SA_SHIRQ, ohci_driver_name, ohci)) {
736 fw_error("Failed to allocate shared interrupt %d.\n",
738 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
739 ohci->config_rom, ohci->config_rom_bus);
743 reg_write(ohci, OHCI1394_HCControlSet,
744 OHCI1394_HCControl_linkEnable |
745 OHCI1394_HCControl_BIBimageValid);
748 /* We are ready to go, initiate bus reset to finish the
751 fw_core_initiate_bus_reset(&ohci->card, 1);
757 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
759 struct fw_ohci *ohci;
762 __be32 *next_config_rom;
763 dma_addr_t next_config_rom_bus;
765 ohci = fw_ohci(card);
767 /* When the OHCI controller is enabled, the config rom update
768 * mechanism is a bit tricky, but easy enough to use. See
769 * section 5.5.6 in the OHCI specification.
771 * The OHCI controller caches the new config rom address in a
772 * shadow register (ConfigROMmapNext) and needs a bus reset
773 * for the changes to take place. When the bus reset is
774 * detected, the controller loads the new values for the
775 * ConfigRomHeader and BusOptions registers from the specified
776 * config rom and loads ConfigROMmap from the ConfigROMmapNext
777 * shadow register. All automatically and atomically.
779 * Now, there's a twist to this story. The automatic load of
780 * ConfigRomHeader and BusOptions doesn't honor the
781 * noByteSwapData bit, so with a be32 config rom, the
782 * controller will load be32 values in to these registers
783 * during the atomic update, even on litte endian
784 * architectures. The workaround we use is to put a 0 in the
785 * header quadlet; 0 is endian agnostic and means that the
786 * config rom isn't ready yet. In the bus reset tasklet we
787 * then set up the real values for the two registers.
789 * We use ohci->lock to avoid racing with the code that sets
790 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
794 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
795 &next_config_rom_bus, GFP_KERNEL);
796 if (next_config_rom == NULL)
799 spin_lock_irqsave(&ohci->lock, flags);
801 if (ohci->next_config_rom == NULL) {
802 ohci->next_config_rom = next_config_rom;
803 ohci->next_config_rom_bus = next_config_rom_bus;
805 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
806 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
809 ohci->next_header = config_rom[0];
810 ohci->next_config_rom[0] = 0;
812 reg_write(ohci, OHCI1394_ConfigROMmap,
813 ohci->next_config_rom_bus);
815 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
816 next_config_rom, next_config_rom_bus);
820 spin_unlock_irqrestore(&ohci->lock, flags);
822 /* Now initiate a bus reset to have the changes take
823 * effect. We clean up the old config rom memory and DMA
824 * mappings in the bus reset tasklet, since the OHCI
825 * controller could need to access it before the bus reset
828 fw_core_initiate_bus_reset(&ohci->card, 1);
833 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
835 struct fw_ohci *ohci = fw_ohci(card);
837 at_context_transmit(&ohci->at_request_ctx, packet);
840 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
842 struct fw_ohci *ohci = fw_ohci(card);
844 at_context_transmit(&ohci->at_response_ctx, packet);
848 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
850 struct fw_ohci *ohci = fw_ohci(card);
854 /* FIXME: Make sure this bitmask is cleared when we clear the busReset
855 * interrupt bit. Clear physReqResourceAllBuses on bus reset. */
857 spin_lock_irqsave(&ohci->lock, flags);
859 if (ohci->generation != generation) {
864 /* NOTE, if the node ID contains a non-local bus ID, physical DMA is
865 * enabled for _all_ nodes on remote buses. */
867 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
869 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
871 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
875 spin_unlock_irqrestore(&ohci->lock, flags);
879 static void ir_context_tasklet(unsigned long data)
881 struct iso_context *ctx = (struct iso_context *)data;
886 #define ISO_BUFFER_SIZE (64 * 1024)
888 static void flush_iso_context(struct iso_context *ctx)
890 struct fw_ohci *ohci = fw_ohci(ctx->base.card);
891 struct descriptor *d, *last;
895 dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
896 ISO_BUFFER_SIZE, DMA_TO_DEVICE);
898 d = ctx->tail_descriptor;
899 last = ctx->tail_descriptor_last;
901 while (last->branch_address != 0 && last->transfer_status != 0) {
902 address = le32_to_cpu(last->branch_address);
904 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
911 if (le16_to_cpu(last->control) & descriptor_irq_always)
912 ctx->base.callback(&ctx->base,
913 0, le16_to_cpu(last->res_count),
914 ctx->base.callback_data);
917 ctx->tail_descriptor = d;
918 ctx->tail_descriptor_last = last;
921 static void it_context_tasklet(unsigned long data)
923 struct iso_context *ctx = (struct iso_context *)data;
925 flush_iso_context(ctx);
928 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
931 struct fw_ohci *ohci = fw_ohci(card);
932 struct iso_context *ctx, *list;
933 void (*tasklet) (unsigned long data);
938 if (type == FW_ISO_CONTEXT_TRANSMIT) {
939 mask = &ohci->it_context_mask;
940 list = ohci->it_context_list;
941 tasklet = it_context_tasklet;
943 mask = &ohci->ir_context_mask;
944 list = ohci->ir_context_list;
945 tasklet = ir_context_tasklet;
948 spin_lock_irqsave(&ohci->lock, flags);
949 index = ffs(*mask) - 1;
951 *mask &= ~(1 << index);
952 spin_unlock_irqrestore(&ohci->lock, flags);
955 return ERR_PTR(-EBUSY);
958 memset(ctx, 0, sizeof *ctx);
959 tasklet_init(&ctx->tasklet, tasklet, (unsigned long)ctx);
961 ctx->buffer = kmalloc(ISO_BUFFER_SIZE, GFP_KERNEL);
962 if (ctx->buffer == NULL) {
963 spin_lock_irqsave(&ohci->lock, flags);
965 spin_unlock_irqrestore(&ohci->lock, flags);
966 return ERR_PTR(-ENOMEM);
970 dma_map_single(card->device, ctx->buffer,
971 ISO_BUFFER_SIZE, DMA_TO_DEVICE);
973 ctx->head_descriptor = ctx->buffer;
974 ctx->prev_descriptor = ctx->buffer;
975 ctx->tail_descriptor = ctx->buffer;
976 ctx->tail_descriptor_last = ctx->buffer;
978 /* We put a dummy descriptor in the buffer that has a NULL
979 * branch address and looks like it's been sent. That way we
980 * have a descriptor to append DMA programs to. Also, the
981 * ring buffer invariant is that it always has at least one
982 * element so that head == tail means buffer full. */
984 memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
985 ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
986 ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
987 ctx->head_descriptor++;
992 static int ohci_send_iso(struct fw_iso_context *base, s32 cycle)
994 struct iso_context *ctx = (struct iso_context *)base;
995 struct fw_ohci *ohci = fw_ohci(ctx->base.card);
999 index = ctx - ohci->it_context_list;
1001 cycle_match = CONTEXT_CYCLE_MATCH_ENABLE |
1002 (cycle & 0x7fff) << 16;
1004 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1005 reg_write(ohci, OHCI1394_IsoXmitCommandPtr(index),
1006 le32_to_cpu(ctx->tail_descriptor_last->branch_address));
1007 reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0);
1008 reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index),
1009 CONTEXT_RUN | cycle_match);
1015 static void ohci_free_iso_context(struct fw_iso_context *base)
1017 struct fw_ohci *ohci = fw_ohci(base->card);
1018 struct iso_context *ctx = (struct iso_context *)base;
1019 unsigned long flags;
1022 flush_iso_context(ctx);
1024 spin_lock_irqsave(&ohci->lock, flags);
1026 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1027 index = ctx - ohci->it_context_list;
1028 reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0);
1029 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1030 ohci->it_context_mask |= 1 << index;
1032 index = ctx - ohci->ir_context_list;
1033 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(index), ~0);
1034 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1035 ohci->ir_context_mask |= 1 << index;
1039 dma_unmap_single(ohci->card.device, ctx->buffer_bus,
1040 ISO_BUFFER_SIZE, DMA_TO_DEVICE);
1042 spin_unlock_irqrestore(&ohci->lock, flags);
1046 ohci_queue_iso(struct fw_iso_context *base,
1047 struct fw_iso_packet *packet, void *payload)
1049 struct iso_context *ctx = (struct iso_context *)base;
1050 struct fw_ohci *ohci = fw_ohci(ctx->base.card);
1051 struct descriptor *d, *end, *last, *tail, *pd;
1052 struct fw_iso_packet *p;
1055 u32 z, header_z, payload_z, irq;
1056 u32 payload_index, payload_end_index, next_page_index;
1057 int index, page, end_page, i, length, offset;
1059 /* FIXME: Cycle lost behavior should be configurable: lose
1060 * packet, retransmit or terminate.. */
1063 payload_index = payload - ctx->base.buffer;
1064 d = ctx->head_descriptor;
1065 tail = ctx->tail_descriptor;
1066 end = ctx->buffer + ISO_BUFFER_SIZE / sizeof(struct descriptor);
1072 if (p->header_length > 0)
1075 /* Determine the first page the payload isn't contained in. */
1076 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1077 if (p->payload_length > 0)
1078 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1084 /* Get header size in number of descriptors. */
1085 header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
1087 if (d + z + header_z <= tail) {
1089 } else if (d > tail && d + z + header_z <= end) {
1091 } else if (d > tail && ctx->buffer + z + header_z <= tail) {
1096 /* No space in buffer */
1100 memset(d, 0, (z + header_z) * sizeof *d);
1101 d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
1104 d[0].control = cpu_to_le16(descriptor_key_immediate);
1105 d[0].req_count = cpu_to_le16(8);
1107 header = (__le32 *) &d[1];
1108 header[0] = cpu_to_le32(it_header_sy(p->sy) |
1109 it_header_tag(p->tag) |
1110 it_header_tcode(TCODE_STREAM_DATA) |
1111 it_header_channel(ctx->base.channel) |
1112 it_header_speed(ctx->base.speed));
1114 cpu_to_le32(it_header_data_length(p->header_length +
1115 p->payload_length));
1118 if (p->header_length > 0) {
1119 d[2].req_count = cpu_to_le16(p->header_length);
1120 d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d);
1121 memcpy(&d[z], p->header, p->header_length);
1124 pd = d + z - payload_z;
1125 payload_end_index = payload_index + p->payload_length;
1126 for (i = 0; i < payload_z; i++) {
1127 page = payload_index >> PAGE_SHIFT;
1128 offset = payload_index & ~PAGE_MASK;
1129 next_page_index = (page + 1) << PAGE_SHIFT;
1131 min(next_page_index, payload_end_index) - payload_index;
1132 pd[i].req_count = cpu_to_le16(length);
1133 pd[i].data_address = cpu_to_le32(ctx->base.pages[page] + offset);
1135 payload_index += length;
1144 irq = descriptor_irq_always;
1146 irq = descriptor_no_irq;
1148 last->control = cpu_to_le16(descriptor_output_last |
1150 descriptor_branch_always |
1153 dma_sync_single_for_device(ohci->card.device, ctx->buffer_bus,
1154 ISO_BUFFER_SIZE, DMA_TO_DEVICE);
1156 ctx->head_descriptor = d + z + header_z;
1157 ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
1158 ctx->prev_descriptor = last;
1160 index = ctx - ohci->it_context_list;
1161 reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), CONTEXT_WAKE);
1167 static const struct fw_card_driver ohci_driver = {
1168 .name = ohci_driver_name,
1169 .enable = ohci_enable,
1170 .update_phy_reg = ohci_update_phy_reg,
1171 .set_config_rom = ohci_set_config_rom,
1172 .send_request = ohci_send_request,
1173 .send_response = ohci_send_response,
1174 .enable_phys_dma = ohci_enable_phys_dma,
1176 .allocate_iso_context = ohci_allocate_iso_context,
1177 .free_iso_context = ohci_free_iso_context,
1178 .queue_iso = ohci_queue_iso,
1179 .send_iso = ohci_send_iso,
1182 static int software_reset(struct fw_ohci *ohci)
1186 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1188 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1189 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1190 OHCI1394_HCControl_softReset) == 0)
1198 /* ---------- pci subsystem interface ---------- */
1208 static int cleanup(struct fw_ohci *ohci, int stage, int code)
1210 struct pci_dev *dev = to_pci_dev(ohci->card.device);
1213 case CLEANUP_SELF_ID:
1214 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1215 ohci->self_id_cpu, ohci->self_id_bus);
1216 case CLEANUP_REGISTERS:
1217 kfree(ohci->it_context_list);
1218 kfree(ohci->ir_context_list);
1219 pci_iounmap(dev, ohci->registers);
1221 pci_release_region(dev, 0);
1222 case CLEANUP_DISABLE:
1223 pci_disable_device(dev);
1224 case CLEANUP_PUT_CARD:
1225 fw_card_put(&ohci->card);
1231 static int __devinit
1232 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1234 struct fw_ohci *ohci;
1235 u32 bus_options, max_receive, link_speed;
1240 ohci = kzalloc(sizeof *ohci, GFP_KERNEL);
1242 fw_error("Could not malloc fw_ohci data.\n");
1246 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1248 if (pci_enable_device(dev)) {
1249 fw_error("Failed to enable OHCI hardware.\n");
1250 return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV);
1253 pci_set_master(dev);
1254 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1255 pci_set_drvdata(dev, ohci);
1257 spin_lock_init(&ohci->lock);
1259 tasklet_init(&ohci->bus_reset_tasklet,
1260 bus_reset_tasklet, (unsigned long)ohci);
1262 if (pci_request_region(dev, 0, ohci_driver_name)) {
1263 fw_error("MMIO resource unavailable\n");
1264 return cleanup(ohci, CLEANUP_DISABLE, -EBUSY);
1267 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1268 if (ohci->registers == NULL) {
1269 fw_error("Failed to remap registers\n");
1270 return cleanup(ohci, CLEANUP_IOMEM, -ENXIO);
1273 if (software_reset(ohci)) {
1274 fw_error("Failed to reset ohci card.\n");
1275 return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
1278 /* Now enable LPS, which we need in order to start accessing
1279 * most of the registers. In fact, on some cards (ALI M5251),
1280 * accessing registers in the SClk domain without LPS enabled
1281 * will lock up the machine. Wait 50msec to make sure we have
1282 * full link enabled. */
1283 reg_write(ohci, OHCI1394_HCControlSet,
1284 OHCI1394_HCControl_LPS |
1285 OHCI1394_HCControl_postedWriteEnable);
1289 reg_write(ohci, OHCI1394_HCControlClear,
1290 OHCI1394_HCControl_noByteSwapData);
1292 reg_write(ohci, OHCI1394_LinkControlSet,
1293 OHCI1394_LinkControl_rcvSelfID |
1294 OHCI1394_LinkControl_cycleTimerEnable |
1295 OHCI1394_LinkControl_cycleMaster);
1297 ar_context_init(&ohci->ar_request_ctx, ohci,
1298 OHCI1394_AsReqRcvContextControlSet);
1300 ar_context_init(&ohci->ar_response_ctx, ohci,
1301 OHCI1394_AsRspRcvContextControlSet);
1303 at_context_init(&ohci->at_request_ctx, ohci,
1304 OHCI1394_AsReqTrContextControlSet);
1306 at_context_init(&ohci->at_response_ctx, ohci,
1307 OHCI1394_AsRspTrContextControlSet);
1309 reg_write(ohci, OHCI1394_ATRetries,
1310 OHCI1394_MAX_AT_REQ_RETRIES |
1311 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1312 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1314 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1315 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1316 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1317 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1318 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1320 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1321 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1322 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1323 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1324 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1326 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1327 fw_error("Out of memory for it/ir contexts.\n");
1328 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1331 /* self-id dma buffer allocation */
1332 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1336 if (ohci->self_id_cpu == NULL) {
1337 fw_error("Out of memory for self ID buffer.\n");
1338 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1341 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1342 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1343 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1344 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1345 reg_write(ohci, OHCI1394_IntMaskSet,
1346 OHCI1394_selfIDComplete |
1347 OHCI1394_RQPkt | OHCI1394_RSPkt |
1348 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1349 OHCI1394_isochRx | OHCI1394_isochTx |
1350 OHCI1394_masterIntEnable);
1352 bus_options = reg_read(ohci, OHCI1394_BusOptions);
1353 max_receive = (bus_options >> 12) & 0xf;
1354 link_speed = bus_options & 0x7;
1355 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1356 reg_read(ohci, OHCI1394_GUIDLo);
1358 error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1360 return cleanup(ohci, CLEANUP_SELF_ID, error_code);
1362 fw_notify("Added fw-ohci device %s.\n", dev->dev.bus_id);
1367 static void pci_remove(struct pci_dev *dev)
1369 struct fw_ohci *ohci;
1371 ohci = pci_get_drvdata(dev);
1372 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable);
1373 fw_core_remove_card(&ohci->card);
1375 /* FIXME: Fail all pending packets here, now that the upper
1376 * layers can't queue any more. */
1378 software_reset(ohci);
1379 free_irq(dev->irq, ohci);
1380 cleanup(ohci, CLEANUP_SELF_ID, 0);
1382 fw_notify("Removed fw-ohci device.\n");
1385 static struct pci_device_id pci_table[] = {
1386 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1390 MODULE_DEVICE_TABLE(pci, pci_table);
1392 static struct pci_driver fw_ohci_pci_driver = {
1393 .name = ohci_driver_name,
1394 .id_table = pci_table,
1396 .remove = pci_remove,
1399 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1400 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1401 MODULE_LICENSE("GPL");
1403 static int __init fw_ohci_init(void)
1405 return pci_register_driver(&fw_ohci_pci_driver);
1408 static void __exit fw_ohci_cleanup(void)
1410 pci_unregister_driver(&fw_ohci_pci_driver);
1413 module_init(fw_ohci_init);
1414 module_exit(fw_ohci_cleanup);