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   1 /*
   2  * Intel e752x Memory Controller kernel module
   3  * (C) 2004 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * See "enum e752x_chips" below for supported chipsets
   8  *
   9  * Written by Tom Zimmerman
  10  *
  11  * Contributors:
  12  *      Thayne Harbaugh at realmsys.com (?)
  13  *      Wang Zhenyu at intel.com
  14  *      Dave Jiang at mvista.com
  15  *
  16  * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
  17  *
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/pci.h>
  23 #include <linux/pci_ids.h>
  24 #include <linux/slab.h>
  25 #include <linux/edac.h>
  26 #include "edac_core.h"
  27
  28 #define E752X_REVISION  " Ver: 2.0.2 " __DATE__
  29 #define EDAC_MOD_STR    "e752x_edac"
  30
  31 static int force_function_unhide;
  32
  33 #define e752x_printk(level, fmt, arg...) \
  34         edac_printk(level, "e752x", fmt, ##arg)
  35
  36 #define e752x_mc_printk(mci, level, fmt, arg...) \
  37         edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
  38
  39 #ifndef PCI_DEVICE_ID_INTEL_7520_0
  40 #define PCI_DEVICE_ID_INTEL_7520_0      0x3590
  41 #endif                          /* PCI_DEVICE_ID_INTEL_7520_0      */
  42
  43 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
  44 #define PCI_DEVICE_ID_INTEL_7520_1_ERR  0x3591
  45 #endif                          /* PCI_DEVICE_ID_INTEL_7520_1_ERR  */
  46
  47 #ifndef PCI_DEVICE_ID_INTEL_7525_0
  48 #define PCI_DEVICE_ID_INTEL_7525_0      0x359E
  49 #endif                          /* PCI_DEVICE_ID_INTEL_7525_0      */
  50
  51 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
  52 #define PCI_DEVICE_ID_INTEL_7525_1_ERR  0x3593
  53 #endif                          /* PCI_DEVICE_ID_INTEL_7525_1_ERR  */
  54
  55 #ifndef PCI_DEVICE_ID_INTEL_7320_0
  56 #define PCI_DEVICE_ID_INTEL_7320_0      0x3592
  57 #endif                          /* PCI_DEVICE_ID_INTEL_7320_0 */
  58
  59 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
  60 #define PCI_DEVICE_ID_INTEL_7320_1_ERR  0x3593
  61 #endif                          /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
  62
  63 #define E752X_NR_CSROWS         8       /* number of csrows */
  64
  65 /* E752X register addresses - device 0 function 0 */
  66 #define E752X_DRB               0x60    /* DRAM row boundary register (8b) */
  67 #define E752X_DRA               0x70    /* DRAM row attribute register (8b) */
  68                                         /*
  69                                          * 31:30   Device width row 7
  70                                          *      01=x8 10=x4 11=x8 DDR2
  71                                          * 27:26   Device width row 6
  72                                          * 23:22   Device width row 5
  73                                          * 19:20   Device width row 4
  74                                          * 15:14   Device width row 3
  75                                          * 11:10   Device width row 2
  76                                          *  7:6    Device width row 1
  77                                          *  3:2    Device width row 0
  78                                          */
  79 #define E752X_DRC               0x7C    /* DRAM controller mode reg (32b) */
  80                                         /* FIXME:IS THIS RIGHT? */
  81                                         /*
  82                                          * 22    Number channels 0=1,1=2
  83                                          * 19:18 DRB Granularity 32/64MB
  84                                          */
  85 #define E752X_DRM               0x80    /* Dimm mapping register */
  86 #define E752X_DDRCSR            0x9A    /* DDR control and status reg (16b) */
  87                                         /*
  88                                          * 14:12 1 single A, 2 single B, 3 dual
  89                                          */
  90 #define E752X_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
  91 #define E752X_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
  92 #define E752X_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
  93 #define E752X_REMAPOFFSET       0xCA    /* DRAM remap limit offset reg (16b) */
  94
  95 /* E752X register addresses - device 0 function 1 */
  96 #define E752X_FERR_GLOBAL       0x40    /* Global first error register (32b) */
  97 #define E752X_NERR_GLOBAL       0x44    /* Global next error register (32b) */
  98 #define E752X_HI_FERR           0x50    /* Hub interface first error reg (8b) */
  99 #define E752X_HI_NERR           0x52    /* Hub interface next error reg (8b) */
 100 #define E752X_HI_ERRMASK        0x54    /* Hub interface error mask reg (8b) */
 101 #define E752X_HI_SMICMD         0x5A    /* Hub interface SMI command reg (8b) */
 102 #define E752X_SYSBUS_FERR       0x60    /* System buss first error reg (16b) */
 103 #define E752X_SYSBUS_NERR       0x62    /* System buss next error reg (16b) */
 104 #define E752X_SYSBUS_ERRMASK    0x64    /* System buss error mask reg (16b) */
 105 #define E752X_SYSBUS_SMICMD     0x6A    /* System buss SMI command reg (16b) */
 106 #define E752X_BUF_FERR          0x70    /* Memory buffer first error reg (8b) */
 107 #define E752X_BUF_NERR          0x72    /* Memory buffer next error reg (8b) */
 108 #define E752X_BUF_ERRMASK       0x74    /* Memory buffer error mask reg (8b) */
 109 #define E752X_BUF_SMICMD        0x7A    /* Memory buffer SMI command reg (8b) */
 110 #define E752X_DRAM_FERR         0x80    /* DRAM first error register (16b) */
 111 #define E752X_DRAM_NERR         0x82    /* DRAM next error register (16b) */
 112 #define E752X_DRAM_ERRMASK      0x84    /* DRAM error mask register (8b) */
 113 #define E752X_DRAM_SMICMD       0x8A    /* DRAM SMI command register (8b) */
 114 #define E752X_DRAM_RETR_ADD     0xAC    /* DRAM Retry address register (32b) */
 115 #define E752X_DRAM_SEC1_ADD     0xA0    /* DRAM first correctable memory */
 116                                         /*     error address register (32b) */
 117                                         /*
 118                                          * 31    Reserved
 119                                          * 30:2  CE address (64 byte block 34:6)
 120                                          * 1     Reserved
 121                                          * 0     HiLoCS
 122                                          */
 123 #define E752X_DRAM_SEC2_ADD     0xC8    /* DRAM first correctable memory */
 124                                         /*     error address register (32b) */
 125                                         /*
 126                                          * 31    Reserved
 127                                          * 30:2  CE address (64 byte block 34:6)
 128                                          * 1     Reserved
 129                                          * 0     HiLoCS
 130                                          */
 131 #define E752X_DRAM_DED_ADD      0xA4    /* DRAM first uncorrectable memory */
 132                                         /*     error address register (32b) */
 133                                         /*
 134                                          * 31    Reserved
 135                                          * 30:2  CE address (64 byte block 34:6)
 136                                          * 1     Reserved
 137                                          * 0     HiLoCS
 138                                          */
 139 #define E752X_DRAM_SCRB_ADD     0xA8    /* DRAM first uncorrectable scrub memory */
 140                                         /*     error address register (32b) */
 141                                         /*
 142                                          * 31    Reserved
 143                                          * 30:2  CE address (64 byte block 34:6)
 144                                          * 1     Reserved
 145                                          * 0     HiLoCS
 146                                          */
 147 #define E752X_DRAM_SEC1_SYNDROME 0xC4   /* DRAM first correctable memory */
 148                                         /*     error syndrome register (16b) */
 149 #define E752X_DRAM_SEC2_SYNDROME 0xC6   /* DRAM second correctable memory */
 150                                         /*     error syndrome register (16b) */
 151 #define E752X_DEVPRES1          0xF4    /* Device Present 1 register (8b) */
 152
 153 /* ICH5R register addresses - device 30 function 0 */
 154 #define ICH5R_PCI_STAT          0x06    /* PCI status register (16b) */
 155 #define ICH5R_PCI_2ND_STAT      0x1E    /* PCI status secondary reg (16b) */
 156 #define ICH5R_PCI_BRIDGE_CTL    0x3E    /* PCI bridge control register (16b) */
 157
 158 enum e752x_chips {
 159         E7520 = 0,
 160         E7525 = 1,
 161         E7320 = 2
 162 };
 163
 164 struct e752x_pvt {
 165         struct pci_dev *bridge_ck;
 166         struct pci_dev *dev_d0f0;
 167         struct pci_dev *dev_d0f1;
 168         u32 tolm;
 169         u32 remapbase;
 170         u32 remaplimit;
 171         int mc_symmetric;
 172         u8 map[8];
 173         int map_type;
 174         const struct e752x_dev_info *dev_info;
 175 };
 176
 177 struct e752x_dev_info {
 178         u16 err_dev;
 179         u16 ctl_dev;
 180         const char *ctl_name;
 181 };
 182
 183 struct e752x_error_info {
 184         u32 ferr_global;
 185         u32 nerr_global;
 186         u8 hi_ferr;
 187         u8 hi_nerr;
 188         u16 sysbus_ferr;
 189         u16 sysbus_nerr;
 190         u8 buf_ferr;
 191         u8 buf_nerr;
 192         u16 dram_ferr;
 193         u16 dram_nerr;
 194         u32 dram_sec1_add;
 195         u32 dram_sec2_add;
 196         u16 dram_sec1_syndrome;
 197         u16 dram_sec2_syndrome;
 198         u32 dram_ded_add;
 199         u32 dram_scrb_add;
 200         u32 dram_retr_add;
 201 };
 202
 203 static const struct e752x_dev_info e752x_devs[] = {
 204         [E7520] = {
 205                 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
 206                 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
 207                 .ctl_name = "E7520"
 208         },
 209         [E7525] = {
 210                 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
 211                 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
 212                 .ctl_name = "E7525"
 213         },
 214         [E7320] = {
 215                 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
 216                 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
 217                 .ctl_name = "E7320"
 218         },
 219 };
 220
 221 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
 222                 unsigned long page)
 223 {
 224         u32 remap;
 225         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 226
 227         debugf3("%s()\n", __func__);
 228
 229         if (page < pvt->tolm)
 230                 return page;
 231
 232         if ((page >= 0x100000) && (page < pvt->remapbase))
 233                 return page;
 234
 235         remap = (page - pvt->tolm) + pvt->remapbase;
 236
 237         if (remap < pvt->remaplimit)
 238                 return remap;
 239
 240         e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
 241         return pvt->tolm - 1;
 242 }
 243
 244 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
 245                 u32 sec1_add, u16 sec1_syndrome)
 246 {
 247         u32 page;
 248         int row;
 249         int channel;
 250         int i;
 251         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 252
 253         debugf3("%s()\n", __func__);
 254
 255         /* convert the addr to 4k page */
 256         page = sec1_add >> (PAGE_SHIFT - 4);
 257
 258         /* FIXME - check for -1 */
 259         if (pvt->mc_symmetric) {
 260                 /* chip select are bits 14 & 13 */
 261                 row = ((page >> 1) & 3);
 262                 e752x_printk(KERN_WARNING,
 263                         "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
 264                         pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
 265                         pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
 266
 267                 /* test for channel remapping */
 268                 for (i = 0; i < 8; i++) {
 269                         if (pvt->map[i] == row)
 270                                 break;
 271                 }
 272
 273                 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
 274
 275                 if (i < 8)
 276                         row = i;
 277                 else
 278                         e752x_mc_printk(mci, KERN_WARNING,
 279                                 "row %d not found in remap table\n", row);
 280         } else
 281                 row = edac_mc_find_csrow_by_page(mci, page);
 282
 283         /* 0 = channel A, 1 = channel B */
 284         channel = !(error_one & 1);
 285
 286         if (!pvt->map_type)
 287                 row = 7 - row;
 288
 289         /* e752x mc reads 34:6 of the DRAM linear address */
 290         edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4),
 291                         sec1_syndrome, row, channel, "e752x CE");
 292 }
 293
 294 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
 295                 u32 sec1_add, u16 sec1_syndrome, int *error_found,
 296                 int handle_error)
 297 {
 298         *error_found = 1;
 299
 300         if (handle_error)
 301                 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
 302 }
 303
 304 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
 305                 u32 ded_add, u32 scrb_add)
 306 {
 307         u32 error_2b, block_page;
 308         int row;
 309         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 310
 311         debugf3("%s()\n", __func__);
 312
 313         if (error_one & 0x0202) {
 314                 error_2b = ded_add;
 315
 316                 /* convert to 4k address */
 317                 block_page = error_2b >> (PAGE_SHIFT - 4);
 318
 319                 row = pvt->mc_symmetric ?
 320                         /* chip select are bits 14 & 13 */
 321                         ((block_page >> 1) & 3) :
 322                         edac_mc_find_csrow_by_page(mci, block_page);
 323
 324                 /* e752x mc reads 34:6 of the DRAM linear address */
 325                 edac_mc_handle_ue(mci, block_page,
 326                                         offset_in_page(error_2b << 4),
 327                                         row, "e752x UE from Read");
 328         }
 329         if (error_one & 0x0404) {
 330                 error_2b = scrb_add;
 331
 332                 /* convert to 4k address */
 333                 block_page = error_2b >> (PAGE_SHIFT - 4);
 334
 335                 row = pvt->mc_symmetric ?
 336                         /* chip select are bits 14 & 13 */
 337                         ((block_page >> 1) & 3) :
 338                         edac_mc_find_csrow_by_page(mci, block_page);
 339
 340                 /* e752x mc reads 34:6 of the DRAM linear address */
 341                 edac_mc_handle_ue(mci, block_page,
 342                                         offset_in_page(error_2b << 4),
 343                                         row, "e752x UE from Scruber");
 344         }
 345 }
 346
 347 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
 348                 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
 349 {
 350         *error_found = 1;
 351
 352         if (handle_error)
 353                 do_process_ue(mci, error_one, ded_add, scrb_add);
 354 }
 355
 356 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
 357                 int *error_found, int handle_error)
 358 {
 359         *error_found = 1;
 360
 361         if (!handle_error)
 362                 return;
 363
 364         debugf3("%s()\n", __func__);
 365         edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
 366 }
 367
 368 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
 369                 u32 retry_add)
 370 {
 371         u32 error_1b, page;
 372         int row;
 373         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 374
 375         error_1b = retry_add;
 376         page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
 377         row = pvt->mc_symmetric ?
 378                 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
 379                 edac_mc_find_csrow_by_page(mci, page);
 380         e752x_mc_printk(mci, KERN_WARNING,
 381                 "CE page 0x%lx, row %d : Memory read retry\n",
 382                 (long unsigned int) page, row);
 383 }
 384
 385 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
 386                 u32 retry_add, int *error_found, int handle_error)
 387 {
 388         *error_found = 1;
 389
 390         if (handle_error)
 391                 do_process_ded_retry(mci, error, retry_add);
 392 }
 393
 394 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
 395                 int *error_found, int handle_error)
 396 {
 397         *error_found = 1;
 398
 399         if (handle_error)
 400                 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
 401 }
 402
 403 static char *global_message[11] = {
 404         "PCI Express C1", "PCI Express C", "PCI Express B1",
 405         "PCI Express B", "PCI Express A1", "PCI Express A",
 406         "DMA Controler", "HUB Interface", "System Bus",
 407         "DRAM Controler", "Internal Buffer"
 408 };
 409
 410 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
 411
 412 static void do_global_error(int fatal, u32 errors)
 413 {
 414         int i;
 415
 416         for (i = 0; i < 11; i++) {
 417                 if (errors & (1 << i))
 418                         e752x_printk(KERN_WARNING, "%sError %s\n",
 419                                 fatal_message[fatal], global_message[i]);
 420         }
 421 }
 422
 423 static inline void global_error(int fatal, u32 errors, int *error_found,
 424                 int handle_error)
 425 {
 426         *error_found = 1;
 427
 428         if (handle_error)
 429                 do_global_error(fatal, errors);
 430 }
 431
 432 static char *hub_message[7] = {
 433         "HI Address or Command Parity", "HI Illegal Access",
 434         "HI Internal Parity", "Out of Range Access",
 435         "HI Data Parity", "Enhanced Config Access",
 436         "Hub Interface Target Abort"
 437 };
 438
 439 static void do_hub_error(int fatal, u8 errors)
 440 {
 441         int i;
 442
 443         for (i = 0; i < 7; i++) {
 444                 if (errors & (1 << i))
 445                         e752x_printk(KERN_WARNING, "%sError %s\n",
 446                                 fatal_message[fatal], hub_message[i]);
 447         }
 448 }
 449
 450 static inline void hub_error(int fatal, u8 errors, int *error_found,
 451                 int handle_error)
 452 {
 453         *error_found = 1;
 454
 455         if (handle_error)
 456                 do_hub_error(fatal, errors);
 457 }
 458
 459 static char *membuf_message[4] = {
 460         "Internal PMWB to DRAM parity",
 461         "Internal PMWB to System Bus Parity",
 462         "Internal System Bus or IO to PMWB Parity",
 463         "Internal DRAM to PMWB Parity"
 464 };
 465
 466 static void do_membuf_error(u8 errors)
 467 {
 468         int i;
 469
 470         for (i = 0; i < 4; i++) {
 471                 if (errors & (1 << i))
 472                         e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
 473                                 membuf_message[i]);
 474         }
 475 }
 476
 477 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
 478 {
 479         *error_found = 1;
 480
 481         if (handle_error)
 482                 do_membuf_error(errors);
 483 }
 484
 485 static char *sysbus_message[10] = {
 486         "Addr or Request Parity",
 487         "Data Strobe Glitch",
 488         "Addr Strobe Glitch",
 489         "Data Parity",
 490         "Addr Above TOM",
 491         "Non DRAM Lock Error",
 492         "MCERR", "BINIT",
 493         "Memory Parity",
 494         "IO Subsystem Parity"
 495 };
 496
 497 static void do_sysbus_error(int fatal, u32 errors)
 498 {
 499         int i;
 500
 501         for (i = 0; i < 10; i++) {
 502                 if (errors & (1 << i))
 503                         e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
 504                                 fatal_message[fatal], sysbus_message[i]);
 505         }
 506 }
 507
 508 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
 509                 int handle_error)
 510 {
 511         *error_found = 1;
 512
 513         if (handle_error)
 514                 do_sysbus_error(fatal, errors);
 515 }
 516
 517 static void e752x_check_hub_interface(struct e752x_error_info *info,
 518                 int *error_found, int handle_error)
 519 {
 520         u8 stat8;
 521
 522         //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
 523
 524         stat8 = info->hi_ferr;
 525
 526         if(stat8 & 0x7f) { /* Error, so process */
 527                 stat8 &= 0x7f;
 528
 529                 if(stat8 & 0x2b)
 530                         hub_error(1, stat8 & 0x2b, error_found, handle_error);
 531
 532                 if(stat8 & 0x54)
 533                         hub_error(0, stat8 & 0x54, error_found, handle_error);
 534         }
 535
 536         //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
 537
 538         stat8 = info->hi_nerr;
 539
 540         if(stat8 & 0x7f) { /* Error, so process */
 541                 stat8 &= 0x7f;
 542
 543                 if (stat8 & 0x2b)
 544                         hub_error(1, stat8 & 0x2b, error_found, handle_error);
 545
 546                 if(stat8 & 0x54)
 547                         hub_error(0, stat8 & 0x54, error_found, handle_error);
 548         }
 549 }
 550
 551 static void e752x_check_sysbus(struct e752x_error_info *info,
 552                 int *error_found, int handle_error)
 553 {
 554         u32 stat32, error32;
 555
 556         //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
 557         stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
 558
 559         if (stat32 == 0)
 560                 return;  /* no errors */
 561
 562         error32 = (stat32 >> 16) & 0x3ff;
 563         stat32 = stat32 & 0x3ff;
 564
 565         if(stat32 & 0x087)
 566                 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
 567
 568         if(stat32 & 0x378)
 569                 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
 570
 571         if(error32 & 0x087)
 572                 sysbus_error(1, error32 & 0x087, error_found, handle_error);
 573
 574         if(error32 & 0x378)
 575                 sysbus_error(0, error32 & 0x378, error_found, handle_error);
 576 }
 577
 578 static void e752x_check_membuf (struct e752x_error_info *info,
 579                 int *error_found, int handle_error)
 580 {
 581         u8 stat8;
 582
 583         stat8 = info->buf_ferr;
 584
 585         if (stat8 & 0x0f) { /* Error, so process */
 586                 stat8 &= 0x0f;
 587                 membuf_error(stat8, error_found, handle_error);
 588         }
 589
 590         stat8 = info->buf_nerr;
 591
 592         if (stat8 & 0x0f) { /* Error, so process */
 593                 stat8 &= 0x0f;
 594                 membuf_error(stat8, error_found, handle_error);
 595         }
 596 }
 597
 598 static void e752x_check_dram (struct mem_ctl_info *mci,
 599                 struct e752x_error_info *info, int *error_found,
 600                 int handle_error)
 601 {
 602         u16 error_one, error_next;
 603
 604         error_one = info->dram_ferr;
 605         error_next = info->dram_nerr;
 606
 607         /* decode and report errors */
 608         if(error_one & 0x0101)  /* check first error correctable */
 609                 process_ce(mci, error_one, info->dram_sec1_add,
 610                            info->dram_sec1_syndrome, error_found,
 611                            handle_error);
 612
 613         if(error_next & 0x0101)  /* check next error correctable */
 614                 process_ce(mci, error_next, info->dram_sec2_add,
 615                            info->dram_sec2_syndrome, error_found,
 616                            handle_error);
 617
 618         if(error_one & 0x4040)
 619                 process_ue_no_info_wr(mci, error_found, handle_error);
 620
 621         if(error_next & 0x4040)
 622                 process_ue_no_info_wr(mci, error_found, handle_error);
 623
 624         if(error_one & 0x2020)
 625                 process_ded_retry(mci, error_one, info->dram_retr_add,
 626                                   error_found, handle_error);
 627
 628         if(error_next & 0x2020)
 629                 process_ded_retry(mci, error_next, info->dram_retr_add,
 630                                   error_found, handle_error);
 631
 632         if(error_one & 0x0808)
 633                 process_threshold_ce(mci, error_one, error_found,
 634                                      handle_error);
 635
 636         if(error_next & 0x0808)
 637                 process_threshold_ce(mci, error_next, error_found,
 638                                      handle_error);
 639
 640         if(error_one & 0x0606)
 641                 process_ue(mci, error_one, info->dram_ded_add,
 642                            info->dram_scrb_add, error_found, handle_error);
 643
 644         if(error_next & 0x0606)
 645                 process_ue(mci, error_next, info->dram_ded_add,
 646                            info->dram_scrb_add, error_found, handle_error);
 647 }
 648
 649 static void e752x_get_error_info (struct mem_ctl_info *mci,
 650                 struct e752x_error_info *info)
 651 {
 652         struct pci_dev *dev;
 653         struct e752x_pvt *pvt;
 654
 655         memset(info, 0, sizeof(*info));
 656         pvt = (struct e752x_pvt *) mci->pvt_info;
 657         dev = pvt->dev_d0f1;
 658         pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
 659
 660         if (info->ferr_global) {
 661                 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
 662                 pci_read_config_word(dev, E752X_SYSBUS_FERR,
 663                                 &info->sysbus_ferr);
 664                 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
 665                 pci_read_config_word(dev, E752X_DRAM_FERR,
 666                                 &info->dram_ferr);
 667                 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
 668                                 &info->dram_sec1_add);
 669                 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
 670                                 &info->dram_sec1_syndrome);
 671                 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
 672                                 &info->dram_ded_add);
 673                 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
 674                                 &info->dram_scrb_add);
 675                 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
 676                                 &info->dram_retr_add);
 677
 678                 if (info->hi_ferr & 0x7f)
 679                         pci_write_config_byte(dev, E752X_HI_FERR,
 680                                         info->hi_ferr);
 681
 682                 if (info->sysbus_ferr)
 683                         pci_write_config_word(dev, E752X_SYSBUS_FERR,
 684                                         info->sysbus_ferr);
 685
 686                 if (info->buf_ferr & 0x0f)
 687                         pci_write_config_byte(dev, E752X_BUF_FERR,
 688                                         info->buf_ferr);
 689
 690                 if (info->dram_ferr)
 691                         pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
 692                                         info->dram_ferr, info->dram_ferr);
 693
 694                 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
 695                                 info->ferr_global);
 696         }
 697
 698         pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
 699
 700         if (info->nerr_global) {
 701                 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
 702                 pci_read_config_word(dev, E752X_SYSBUS_NERR,
 703                                 &info->sysbus_nerr);
 704                 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
 705                 pci_read_config_word(dev, E752X_DRAM_NERR,
 706                                 &info->dram_nerr);
 707                 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
 708                                 &info->dram_sec2_add);
 709                 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
 710                                 &info->dram_sec2_syndrome);
 711
 712                 if (info->hi_nerr & 0x7f)
 713                         pci_write_config_byte(dev, E752X_HI_NERR,
 714                                         info->hi_nerr);
 715
 716                 if (info->sysbus_nerr)
 717                         pci_write_config_word(dev, E752X_SYSBUS_NERR,
 718                                         info->sysbus_nerr);
 719
 720                 if (info->buf_nerr & 0x0f)
 721                         pci_write_config_byte(dev, E752X_BUF_NERR,
 722                                         info->buf_nerr);
 723
 724                 if (info->dram_nerr)
 725                         pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
 726                                         info->dram_nerr, info->dram_nerr);
 727
 728                 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
 729                                 info->nerr_global);
 730         }
 731 }
 732
 733 static int e752x_process_error_info (struct mem_ctl_info *mci,
 734                 struct e752x_error_info *info, int handle_errors)
 735 {
 736         u32 error32, stat32;
 737         int error_found;
 738
 739         error_found = 0;
 740         error32 = (info->ferr_global >> 18) & 0x3ff;
 741         stat32 = (info->ferr_global >> 4) & 0x7ff;
 742
 743         if (error32)
 744                 global_error(1, error32, &error_found, handle_errors);
 745
 746         if (stat32)
 747                 global_error(0, stat32, &error_found, handle_errors);
 748
 749         error32 = (info->nerr_global >> 18) & 0x3ff;
 750         stat32 = (info->nerr_global >> 4) & 0x7ff;
 751
 752         if (error32)
 753                 global_error(1, error32, &error_found, handle_errors);
 754
 755         if (stat32)
 756                 global_error(0, stat32, &error_found, handle_errors);
 757
 758         e752x_check_hub_interface(info, &error_found, handle_errors);
 759         e752x_check_sysbus(info, &error_found, handle_errors);
 760         e752x_check_membuf(info, &error_found, handle_errors);
 761         e752x_check_dram(mci, info, &error_found, handle_errors);
 762         return error_found;
 763 }
 764
 765 static void e752x_check(struct mem_ctl_info *mci)
 766 {
 767         struct e752x_error_info info;
 768
 769         debugf3("%s()\n", __func__);
 770         e752x_get_error_info(mci, &info);
 771         e752x_process_error_info(mci, &info, 1);
 772 }
 773
 774 /* Return 1 if dual channel mode is active.  Else return 0. */
 775 static inline int dual_channel_active(u16 ddrcsr)
 776 {
 777         return (((ddrcsr >> 12) & 3) == 3);
 778 }
 779
 780 static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 781                 u16 ddrcsr)
 782 {
 783         struct csrow_info *csrow;
 784         unsigned long last_cumul_size;
 785         int index, mem_dev, drc_chan;
 786         int drc_drbg;  /* DRB granularity 0=64mb, 1=128mb */
 787         int drc_ddim;  /* DRAM Data Integrity Mode 0=none, 2=edac */
 788         u8 value;
 789         u32 dra, drc, cumul_size;
 790
 791         dra = 0;
 792         for (index=0; index < 4; index++) {
 793                 u8 dra_reg;
 794                 pci_read_config_byte(pdev, E752X_DRA+index, &dra_reg);
 795                 dra |= dra_reg << (index * 8);
 796         }
 797         pci_read_config_dword(pdev, E752X_DRC, &drc);
 798         drc_chan = dual_channel_active(ddrcsr);
 799         drc_drbg = drc_chan + 1;  /* 128 in dual mode, 64 in single */
 800         drc_ddim = (drc >> 20) & 0x3;
 801
 802         /* The dram row boundary (DRB) reg values are boundary address for
 803          * each DRAM row with a granularity of 64 or 128MB (single/dual
 804          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 805          * contain the total memory contained in all eight rows.
 806          */
 807         for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
 808                 /* mem_dev 0=x8, 1=x4 */
 809                 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
 810                 csrow = &mci->csrows[index];
 811
 812                 mem_dev = (mem_dev == 2);
 813                 pci_read_config_byte(pdev, E752X_DRB + index, &value);
 814                 /* convert a 128 or 64 MiB DRB to a page size. */
 815                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
 816                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 817                         cumul_size);
 818                 if (cumul_size == last_cumul_size)
 819                         continue;       /* not populated */
 820
 821                 csrow->first_page = last_cumul_size;
 822                 csrow->last_page = cumul_size - 1;
 823                 csrow->nr_pages = cumul_size - last_cumul_size;
 824                 last_cumul_size = cumul_size;
 825                 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
 826                 csrow->mtype = MEM_RDDR;        /* only one type supported */
 827                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
 828
 829                 /*
 830                  * if single channel or x8 devices then SECDED
 831                  * if dual channel and x4 then S4ECD4ED
 832                  */
 833                 if (drc_ddim) {
 834                         if (drc_chan && mem_dev) {
 835                                 csrow->edac_mode = EDAC_S4ECD4ED;
 836                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
 837                         } else {
 838                                 csrow->edac_mode = EDAC_SECDED;
 839                                 mci->edac_cap |= EDAC_FLAG_SECDED;
 840                         }
 841                 } else
 842                         csrow->edac_mode = EDAC_NONE;
 843         }
 844 }
 845
 846 static void e752x_init_mem_map_table(struct pci_dev *pdev,
 847                 struct e752x_pvt *pvt)
 848 {
 849         int index;
 850         u8 value, last, row, stat8;
 851
 852         last = 0;
 853         row = 0;
 854
 855         for (index = 0; index < 8; index += 2) {
 856                 pci_read_config_byte(pdev, E752X_DRB + index, &value);
 857                 /* test if there is a dimm in this slot */
 858                 if (value == last) {
 859                         /* no dimm in the slot, so flag it as empty */
 860                         pvt->map[index] = 0xff;
 861                         pvt->map[index + 1] = 0xff;
 862                 } else {        /* there is a dimm in the slot */
 863                         pvt->map[index] = row;
 864                         row++;
 865                         last = value;
 866                         /* test the next value to see if the dimm is double
 867                          * sided
 868                          */
 869                         pci_read_config_byte(pdev, E752X_DRB + index + 1,
 870                                              &value);
 871                         pvt->map[index + 1] = (value == last) ?
 872                             0xff :      /* the dimm is single sided,
 873                                            so flag as empty */
 874                             row;        /* this is a double sided dimm
 875                                            to save the next row # */
 876                         row++;
 877                         last = value;
 878                 }
 879         }
 880
 881         /* set the map type.  1 = normal, 0 = reversed */
 882         pci_read_config_byte(pdev, E752X_DRM, &stat8);
 883         pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
 884 }
 885
 886 /* Return 0 on success or 1 on failure. */
 887 static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
 888                 struct e752x_pvt *pvt)
 889 {
 890         struct pci_dev *dev;
 891
 892         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
 893                                         pvt->dev_info->err_dev,
 894                                         pvt->bridge_ck);
 895
 896         if (pvt->bridge_ck == NULL)
 897                 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
 898                                                         PCI_DEVFN(0, 1));
 899
 900         if (pvt->bridge_ck == NULL) {
 901                 e752x_printk(KERN_ERR, "error reporting device not found:"
 902                        "vendor %x device 0x%x (broken BIOS?)\n",
 903                        PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
 904                 return 1;
 905         }
 906
 907         dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
 908                              NULL);
 909
 910         if (dev == NULL)
 911                 goto fail;
 912
 913         pvt->dev_d0f0 = dev;
 914         pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
 915
 916         return 0;
 917
 918 fail:
 919         pci_dev_put(pvt->bridge_ck);
 920         return 1;
 921 }
 922
 923 static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
 924 {
 925         struct pci_dev *dev;
 926
 927         dev = pvt->dev_d0f1;
 928         /* Turn off error disable & SMI in case the BIOS turned it on */
 929         pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
 930         pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
 931         pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
 932         pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
 933         pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
 934         pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
 935         pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
 936         pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
 937 }
 938
 939 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
 940 {
 941         u16 pci_data;
 942         u8 stat8;
 943         struct mem_ctl_info *mci;
 944         struct e752x_pvt *pvt;
 945         u16 ddrcsr;
 946         int drc_chan;   /* Number of channels 0=1chan,1=2chan */
 947         struct e752x_error_info discard;
 948
 949         debugf0("%s(): mci\n", __func__);
 950         debugf0("Starting Probe1\n");
 951
 952         /* make sure error reporting method is sane */
 953         switch(edac_op_state) {
 954                 case EDAC_OPSTATE_POLL:
 955                 case EDAC_OPSTATE_NMI:
 956                         break;
 957                 default:
 958                         edac_op_state = EDAC_OPSTATE_POLL;
 959                         break;
 960         }
 961
 962         /* check to see if device 0 function 1 is enabled; if it isn't, we
 963          * assume the BIOS has reserved it for a reason and is expecting
 964          * exclusive access, we take care not to violate that assumption and
 965          * fail the probe. */
 966         pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
 967         if (!force_function_unhide && !(stat8 & (1 << 5))) {
 968                 printk(KERN_INFO "Contact your BIOS vendor to see if the "
 969                         "E752x error registers can be safely un-hidden\n");
 970                 return -ENOMEM;
 971         }
 972         stat8 |= (1 << 5);
 973         pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
 974
 975         pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
 976         /* FIXME: should check >>12 or 0xf, true for all? */
 977         /* Dual channel = 1, Single channel = 0 */
 978         drc_chan = dual_channel_active(ddrcsr);
 979
 980         mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
 981
 982         if (mci == NULL) {
 983                 return -ENOMEM;
 984         }
 985
 986         debugf3("%s(): init mci\n", __func__);
 987         mci->mtype_cap = MEM_FLAG_RDDR;
 988         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
 989             EDAC_FLAG_S4ECD4ED;
 990         /* FIXME - what if different memory types are in different csrows? */
 991         mci->mod_name = EDAC_MOD_STR;
 992         mci->mod_ver = E752X_REVISION;
 993         mci->dev = &pdev->dev;
 994
 995         debugf3("%s(): init pvt\n", __func__);
 996         pvt = (struct e752x_pvt *) mci->pvt_info;
 997         pvt->dev_info = &e752x_devs[dev_idx];
 998         pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
 999
1000         if (e752x_get_devs(pdev, dev_idx, pvt)) {
1001                 edac_mc_free(mci);
1002                 return -ENODEV;
1003         }
1004
1005         debugf3("%s(): more mci init\n", __func__);
1006         mci->ctl_name = pvt->dev_info->ctl_name;
1007         mci->dev_name = pci_name(pdev);
1008         mci->edac_check = e752x_check;
1009         mci->ctl_page_to_phys = ctl_page_to_phys;
1010
1011         e752x_init_csrows(mci, pdev, ddrcsr);
1012         e752x_init_mem_map_table(pdev, pvt);
1013
1014         /* set the map type.  1 = normal, 0 = reversed */
1015         pci_read_config_byte(pdev, E752X_DRM, &stat8);
1016         pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1017
1018         mci->edac_cap |= EDAC_FLAG_NONE;
1019         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
1020
1021         /* load the top of low memory, remap base, and remap limit vars */
1022         pci_read_config_word(pdev, E752X_TOLM, &pci_data);
1023         pvt->tolm = ((u32) pci_data) << 4;
1024         pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
1025         pvt->remapbase = ((u32) pci_data) << 14;
1026         pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
1027         pvt->remaplimit = ((u32) pci_data) << 14;
1028         e752x_printk(KERN_INFO,
1029                 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
1030                 pvt->remapbase, pvt->remaplimit);
1031
1032         /* Here we assume that we will never see multiple instances of this
1033          * type of memory controller.  The ID is therefore hardcoded to 0.
1034          */
1035         if (edac_mc_add_mc(mci,0)) {
1036                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1037                 goto fail;
1038         }
1039
1040         e752x_init_error_reporting_regs(pvt);
1041         e752x_get_error_info(mci, &discard); /* clear other MCH errors */
1042
1043         /* get this far and it's successful */
1044         debugf3("%s(): success\n", __func__);
1045         return 0;
1046
1047 fail:
1048         pci_dev_put(pvt->dev_d0f0);
1049         pci_dev_put(pvt->dev_d0f1);
1050         pci_dev_put(pvt->bridge_ck);
1051         edac_mc_free(mci);
1052
1053         return -ENODEV;
1054 }
1055
1056 /* returns count (>= 0), or negative on error */
1057 static int __devinit e752x_init_one(struct pci_dev *pdev,
1058                 const struct pci_device_id *ent)
1059 {
1060         debugf0("%s()\n", __func__);
1061
1062         /* wake up and enable device */
1063         if(pci_enable_device(pdev) < 0)
1064                 return -EIO;
1065
1066         return e752x_probe1(pdev, ent->driver_data);
1067 }
1068
1069 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1070 {
1071         struct mem_ctl_info *mci;
1072         struct e752x_pvt *pvt;
1073
1074         debugf0("%s()\n", __func__);
1075
1076         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1077                 return;
1078
1079         pvt = (struct e752x_pvt *) mci->pvt_info;
1080         pci_dev_put(pvt->dev_d0f0);
1081         pci_dev_put(pvt->dev_d0f1);
1082         pci_dev_put(pvt->bridge_ck);
1083         edac_mc_free(mci);
1084 }
1085
1086 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
1087         {
1088                 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1089                 E7520
1090         },
1091         {
1092                 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1093                 E7525
1094         },
1095         {
1096                 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1097                 E7320
1098         },
1099         {
1100                 0,
1101         }       /* 0 terminated list. */
1102 };
1103
1104 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1105
1106 static struct pci_driver e752x_driver = {
1107         .name = EDAC_MOD_STR,
1108         .probe = e752x_init_one,
1109         .remove = __devexit_p(e752x_remove_one),
1110         .id_table = e752x_pci_tbl,
1111 };
1112
1113 static int __init e752x_init(void)
1114 {
1115         int pci_rc;
1116
1117         debugf3("%s()\n", __func__);
1118         pci_rc = pci_register_driver(&e752x_driver);
1119         return (pci_rc < 0) ? pci_rc : 0;
1120 }
1121
1122 static void __exit e752x_exit(void)
1123 {
1124         debugf3("%s()\n", __func__);
1125         pci_unregister_driver(&e752x_driver);
1126 }
1127
1128 module_init(e752x_init);
1129 module_exit(e752x_exit);
1130
1131 MODULE_LICENSE("GPL");
1132 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1133 MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
1134
1135 module_param(force_function_unhide, int, 0444);
1136 MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1137 " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
1138 module_param(edac_op_state, int, 0444);
1139 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");