2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * See "enum e752x_chips" below for supported chipsets
9 * Written by Tom Zimmerman
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
20 #include <linux/config.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/pci_ids.h>
25 #include <linux/slab.h>
28 #define E752X_REVISION " Ver: 2.0.0 " __DATE__
30 static int force_function_unhide;
32 #define e752x_printk(level, fmt, arg...) \
33 edac_printk(level, "e752x", fmt, ##arg)
35 #define e752x_mc_printk(mci, level, fmt, arg...) \
36 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
38 #ifndef PCI_DEVICE_ID_INTEL_7520_0
39 #define PCI_DEVICE_ID_INTEL_7520_0 0x3590
40 #endif /* PCI_DEVICE_ID_INTEL_7520_0 */
42 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
43 #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
44 #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
46 #ifndef PCI_DEVICE_ID_INTEL_7525_0
47 #define PCI_DEVICE_ID_INTEL_7525_0 0x359E
48 #endif /* PCI_DEVICE_ID_INTEL_7525_0 */
50 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
51 #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
52 #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
54 #ifndef PCI_DEVICE_ID_INTEL_7320_0
55 #define PCI_DEVICE_ID_INTEL_7320_0 0x3592
56 #endif /* PCI_DEVICE_ID_INTEL_7320_0 */
58 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
59 #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
60 #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
62 #define E752X_NR_CSROWS 8 /* number of csrows */
64 /* E752X register addresses - device 0 function 0 */
65 #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
66 #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
68 * 31:30 Device width row 7
69 * 01=x8 10=x4 11=x8 DDR2
70 * 27:26 Device width row 6
71 * 23:22 Device width row 5
72 * 19:20 Device width row 4
73 * 15:14 Device width row 3
74 * 11:10 Device width row 2
75 * 7:6 Device width row 1
76 * 3:2 Device width row 0
78 #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
79 /* FIXME:IS THIS RIGHT? */
81 * 22 Number channels 0=1,1=2
82 * 19:18 DRB Granularity 32/64MB
84 #define E752X_DRM 0x80 /* Dimm mapping register */
85 #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
87 * 14:12 1 single A, 2 single B, 3 dual
89 #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
90 #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
91 #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
92 #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
94 /* E752X register addresses - device 0 function 1 */
95 #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
96 #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
97 #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
98 #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
99 #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
100 #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
101 #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
102 #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
103 #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
104 #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
105 #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
106 #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
107 #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
108 #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
109 #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
110 #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
111 #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
112 #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
113 #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
114 #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
115 /* error address register (32b) */
118 * 30:2 CE address (64 byte block 34:6)
122 #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
123 /* error address register (32b) */
126 * 30:2 CE address (64 byte block 34:6)
130 #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
131 /* error address register (32b) */
134 * 30:2 CE address (64 byte block 34:6)
138 #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
139 /* error address register (32b) */
142 * 30:2 CE address (64 byte block 34:6)
146 #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
147 /* error syndrome register (16b) */
148 #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
149 /* error syndrome register (16b) */
150 #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
152 /* ICH5R register addresses - device 30 function 0 */
153 #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
154 #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
155 #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
164 struct pci_dev *bridge_ck;
165 struct pci_dev *dev_d0f0;
166 struct pci_dev *dev_d0f1;
173 const struct e752x_dev_info *dev_info;
176 struct e752x_dev_info {
179 const char *ctl_name;
182 struct e752x_error_info {
195 u16 dram_sec1_syndrome;
196 u16 dram_sec2_syndrome;
202 static const struct e752x_dev_info e752x_devs[] = {
204 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
205 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
209 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
210 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
214 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
215 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
220 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
224 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
226 debugf3("%s()\n", __func__);
228 if (page < pvt->tolm)
231 if ((page >= 0x100000) && (page < pvt->remapbase))
234 remap = (page - pvt->tolm) + pvt->remapbase;
236 if (remap < pvt->remaplimit)
239 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
240 return pvt->tolm - 1;
243 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
244 u32 sec1_add, u16 sec1_syndrome)
250 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
252 debugf3("%s()\n", __func__);
254 /* convert the addr to 4k page */
255 page = sec1_add >> (PAGE_SHIFT - 4);
257 /* FIXME - check for -1 */
258 if (pvt->mc_symmetric) {
259 /* chip select are bits 14 & 13 */
260 row = ((page >> 1) & 3);
261 e752x_printk(KERN_WARNING,
262 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
263 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
264 pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
266 /* test for channel remapping */
267 for (i = 0; i < 8; i++) {
268 if (pvt->map[i] == row)
272 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
277 e752x_mc_printk(mci, KERN_WARNING,
278 "row %d not found in remap table\n", row);
280 row = edac_mc_find_csrow_by_page(mci, page);
282 /* 0 = channel A, 1 = channel B */
283 channel = !(error_one & 1);
288 edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel,
292 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
293 u32 sec1_add, u16 sec1_syndrome, int *error_found,
299 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
302 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
303 u32 ded_add, u32 scrb_add)
305 u32 error_2b, block_page;
307 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
309 debugf3("%s()\n", __func__);
311 if (error_one & 0x0202) {
314 /* convert to 4k address */
315 block_page = error_2b >> (PAGE_SHIFT - 4);
317 row = pvt->mc_symmetric ?
318 /* chip select are bits 14 & 13 */
319 ((block_page >> 1) & 3) :
320 edac_mc_find_csrow_by_page(mci, block_page);
322 edac_mc_handle_ue(mci, block_page, 0, row,
323 "e752x UE from Read");
325 if (error_one & 0x0404) {
328 /* convert to 4k address */
329 block_page = error_2b >> (PAGE_SHIFT - 4);
331 row = pvt->mc_symmetric ?
332 /* chip select are bits 14 & 13 */
333 ((block_page >> 1) & 3) :
334 edac_mc_find_csrow_by_page(mci, block_page);
336 edac_mc_handle_ue(mci, block_page, 0, row,
337 "e752x UE from Scruber");
341 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
342 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
347 do_process_ue(mci, error_one, ded_add, scrb_add);
350 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
351 int *error_found, int handle_error)
358 debugf3("%s()\n", __func__);
359 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
362 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
367 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
369 error_1b = retry_add;
370 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
371 row = pvt->mc_symmetric ?
372 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
373 edac_mc_find_csrow_by_page(mci, page);
374 e752x_mc_printk(mci, KERN_WARNING,
375 "CE page 0x%lx, row %d : Memory read retry\n",
376 (long unsigned int) page, row);
379 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
380 u32 retry_add, int *error_found, int handle_error)
385 do_process_ded_retry(mci, error, retry_add);
388 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
389 int *error_found, int handle_error)
394 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
397 static char *global_message[11] = {
398 "PCI Express C1", "PCI Express C", "PCI Express B1",
399 "PCI Express B", "PCI Express A1", "PCI Express A",
400 "DMA Controler", "HUB Interface", "System Bus",
401 "DRAM Controler", "Internal Buffer"
404 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
406 static void do_global_error(int fatal, u32 errors)
410 for (i = 0; i < 11; i++) {
411 if (errors & (1 << i))
412 e752x_printk(KERN_WARNING, "%sError %s\n",
413 fatal_message[fatal], global_message[i]);
417 static inline void global_error(int fatal, u32 errors, int *error_found,
423 do_global_error(fatal, errors);
426 static char *hub_message[7] = {
427 "HI Address or Command Parity", "HI Illegal Access",
428 "HI Internal Parity", "Out of Range Access",
429 "HI Data Parity", "Enhanced Config Access",
430 "Hub Interface Target Abort"
433 static void do_hub_error(int fatal, u8 errors)
437 for (i = 0; i < 7; i++) {
438 if (errors & (1 << i))
439 e752x_printk(KERN_WARNING, "%sError %s\n",
440 fatal_message[fatal], hub_message[i]);
444 static inline void hub_error(int fatal, u8 errors, int *error_found,
450 do_hub_error(fatal, errors);
453 static char *membuf_message[4] = {
454 "Internal PMWB to DRAM parity",
455 "Internal PMWB to System Bus Parity",
456 "Internal System Bus or IO to PMWB Parity",
457 "Internal DRAM to PMWB Parity"
460 static void do_membuf_error(u8 errors)
464 for (i = 0; i < 4; i++) {
465 if (errors & (1 << i))
466 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
471 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
476 do_membuf_error(errors);
479 static char *sysbus_message[10] = {
480 "Addr or Request Parity",
481 "Data Strobe Glitch",
482 "Addr Strobe Glitch",
485 "Non DRAM Lock Error",
488 "IO Subsystem Parity"
491 static void do_sysbus_error(int fatal, u32 errors)
495 for (i = 0; i < 10; i++) {
496 if (errors & (1 << i))
497 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
498 fatal_message[fatal], sysbus_message[i]);
502 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
508 do_sysbus_error(fatal, errors);
511 static void e752x_check_hub_interface(struct e752x_error_info *info,
512 int *error_found, int handle_error)
516 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
518 stat8 = info->hi_ferr;
520 if(stat8 & 0x7f) { /* Error, so process */
524 hub_error(1, stat8 & 0x2b, error_found, handle_error);
527 hub_error(0, stat8 & 0x54, error_found, handle_error);
530 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
532 stat8 = info->hi_nerr;
534 if(stat8 & 0x7f) { /* Error, so process */
538 hub_error(1, stat8 & 0x2b, error_found, handle_error);
541 hub_error(0, stat8 & 0x54, error_found, handle_error);
545 static void e752x_check_sysbus(struct e752x_error_info *info,
546 int *error_found, int handle_error)
550 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
551 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
554 return; /* no errors */
556 error32 = (stat32 >> 16) & 0x3ff;
557 stat32 = stat32 & 0x3ff;
560 sysbus_error(1, stat32 & 0x083, error_found, handle_error);
563 sysbus_error(0, stat32 & 0x37c, error_found, handle_error);
566 sysbus_error(1, error32 & 0x083, error_found, handle_error);
569 sysbus_error(0, error32 & 0x37c, error_found, handle_error);
572 static void e752x_check_membuf (struct e752x_error_info *info,
573 int *error_found, int handle_error)
577 stat8 = info->buf_ferr;
579 if (stat8 & 0x0f) { /* Error, so process */
581 membuf_error(stat8, error_found, handle_error);
584 stat8 = info->buf_nerr;
586 if (stat8 & 0x0f) { /* Error, so process */
588 membuf_error(stat8, error_found, handle_error);
592 static void e752x_check_dram (struct mem_ctl_info *mci,
593 struct e752x_error_info *info, int *error_found,
596 u16 error_one, error_next;
598 error_one = info->dram_ferr;
599 error_next = info->dram_nerr;
601 /* decode and report errors */
602 if(error_one & 0x0101) /* check first error correctable */
603 process_ce(mci, error_one, info->dram_sec1_add,
604 info->dram_sec1_syndrome, error_found,
607 if(error_next & 0x0101) /* check next error correctable */
608 process_ce(mci, error_next, info->dram_sec2_add,
609 info->dram_sec2_syndrome, error_found,
612 if(error_one & 0x4040)
613 process_ue_no_info_wr(mci, error_found, handle_error);
615 if(error_next & 0x4040)
616 process_ue_no_info_wr(mci, error_found, handle_error);
618 if(error_one & 0x2020)
619 process_ded_retry(mci, error_one, info->dram_retr_add,
620 error_found, handle_error);
622 if(error_next & 0x2020)
623 process_ded_retry(mci, error_next, info->dram_retr_add,
624 error_found, handle_error);
626 if(error_one & 0x0808)
627 process_threshold_ce(mci, error_one, error_found,
630 if(error_next & 0x0808)
631 process_threshold_ce(mci, error_next, error_found,
634 if(error_one & 0x0606)
635 process_ue(mci, error_one, info->dram_ded_add,
636 info->dram_scrb_add, error_found, handle_error);
638 if(error_next & 0x0606)
639 process_ue(mci, error_next, info->dram_ded_add,
640 info->dram_scrb_add, error_found, handle_error);
643 static void e752x_get_error_info (struct mem_ctl_info *mci,
644 struct e752x_error_info *info)
647 struct e752x_pvt *pvt;
649 memset(info, 0, sizeof(*info));
650 pvt = (struct e752x_pvt *) mci->pvt_info;
652 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
654 if (info->ferr_global) {
655 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
656 pci_read_config_word(dev, E752X_SYSBUS_FERR,
658 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
659 pci_read_config_word(dev, E752X_DRAM_FERR,
661 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
662 &info->dram_sec1_add);
663 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
664 &info->dram_sec1_syndrome);
665 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
666 &info->dram_ded_add);
667 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
668 &info->dram_scrb_add);
669 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
670 &info->dram_retr_add);
672 if (info->hi_ferr & 0x7f)
673 pci_write_config_byte(dev, E752X_HI_FERR,
676 if (info->sysbus_ferr)
677 pci_write_config_word(dev, E752X_SYSBUS_FERR,
680 if (info->buf_ferr & 0x0f)
681 pci_write_config_byte(dev, E752X_BUF_FERR,
685 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
686 info->dram_ferr, info->dram_ferr);
688 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
692 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
694 if (info->nerr_global) {
695 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
696 pci_read_config_word(dev, E752X_SYSBUS_NERR,
698 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
699 pci_read_config_word(dev, E752X_DRAM_NERR,
701 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
702 &info->dram_sec2_add);
703 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
704 &info->dram_sec2_syndrome);
706 if (info->hi_nerr & 0x7f)
707 pci_write_config_byte(dev, E752X_HI_NERR,
710 if (info->sysbus_nerr)
711 pci_write_config_word(dev, E752X_SYSBUS_NERR,
714 if (info->buf_nerr & 0x0f)
715 pci_write_config_byte(dev, E752X_BUF_NERR,
719 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
720 info->dram_nerr, info->dram_nerr);
722 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
727 static int e752x_process_error_info (struct mem_ctl_info *mci,
728 struct e752x_error_info *info, int handle_errors)
734 error32 = (info->ferr_global >> 18) & 0x3ff;
735 stat32 = (info->ferr_global >> 4) & 0x7ff;
738 global_error(1, error32, &error_found, handle_errors);
741 global_error(0, stat32, &error_found, handle_errors);
743 error32 = (info->nerr_global >> 18) & 0x3ff;
744 stat32 = (info->nerr_global >> 4) & 0x7ff;
747 global_error(1, error32, &error_found, handle_errors);
750 global_error(0, stat32, &error_found, handle_errors);
752 e752x_check_hub_interface(info, &error_found, handle_errors);
753 e752x_check_sysbus(info, &error_found, handle_errors);
754 e752x_check_membuf(info, &error_found, handle_errors);
755 e752x_check_dram(mci, info, &error_found, handle_errors);
759 static void e752x_check(struct mem_ctl_info *mci)
761 struct e752x_error_info info;
763 debugf3("%s()\n", __func__);
764 e752x_get_error_info(mci, &info);
765 e752x_process_error_info(mci, &info, 1);
768 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
774 struct mem_ctl_info *mci = NULL;
775 struct e752x_pvt *pvt = NULL;
778 int drc_chan; /* Number of channels 0=1chan,1=2chan */
779 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
780 int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
782 unsigned long last_cumul_size;
783 struct pci_dev *dev = NULL;
784 struct e752x_error_info discard;
786 debugf0("%s(): mci\n", __func__);
787 debugf0("Starting Probe1\n");
789 /* check to see if device 0 function 1 is enabled; if it isn't, we
790 * assume the BIOS has reserved it for a reason and is expecting
791 * exclusive access, we take care not to violate that assumption and
793 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
794 if (!force_function_unhide && !(stat8 & (1 << 5))) {
795 printk(KERN_INFO "Contact your BIOS vendor to see if the "
796 "E752x error registers can be safely un-hidden\n");
800 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
802 /* need to find out the number of channels */
803 pci_read_config_dword(pdev, E752X_DRC, &drc);
804 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
805 /* FIXME: should check >>12 or 0xf, true for all? */
806 /* Dual channel = 1, Single channel = 0 */
807 drc_chan = (((ddrcsr >> 12) & 3) == 3);
808 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
809 drc_ddim = (drc >> 20) & 0x3;
811 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
818 debugf3("%s(): init mci\n", __func__);
819 mci->mtype_cap = MEM_FLAG_RDDR;
820 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
822 /* FIXME - what if different memory types are in different csrows? */
823 mci->mod_name = EDAC_MOD_STR;
824 mci->mod_ver = E752X_REVISION;
825 mci->dev = &pdev->dev;
827 debugf3("%s(): init pvt\n", __func__);
828 pvt = (struct e752x_pvt *) mci->pvt_info;
829 pvt->dev_info = &e752x_devs[dev_idx];
830 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
831 pvt->dev_info->err_dev,
834 if (pvt->bridge_ck == NULL)
835 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
838 if (pvt->bridge_ck == NULL) {
839 e752x_printk(KERN_ERR, "error reporting device not found:"
840 "vendor %x device 0x%x (broken BIOS?)\n",
841 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
845 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
846 debugf3("%s(): more mci init\n", __func__);
847 mci->ctl_name = pvt->dev_info->ctl_name;
848 mci->edac_check = e752x_check;
849 mci->ctl_page_to_phys = ctl_page_to_phys;
851 /* find out the device types */
852 pci_read_config_dword(pdev, E752X_DRA, &dra);
855 * The dram row boundary (DRB) reg values are boundary address for
856 * each DRAM row with a granularity of 64 or 128MB (single/dual
857 * channel operation). DRB regs are cumulative; therefore DRB7 will
858 * contain the total memory contained in all eight rows.
860 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
864 /* mem_dev 0=x8, 1=x4 */
865 int mem_dev = (dra >> (index * 4 + 2)) & 0x3;
866 struct csrow_info *csrow = &mci->csrows[index];
868 mem_dev = (mem_dev == 2);
869 pci_read_config_byte(pdev, E752X_DRB + index, &value);
870 /* convert a 128 or 64 MiB DRB to a page size. */
871 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
872 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
875 if (cumul_size == last_cumul_size)
876 continue; /* not populated */
878 csrow->first_page = last_cumul_size;
879 csrow->last_page = cumul_size - 1;
880 csrow->nr_pages = cumul_size - last_cumul_size;
881 last_cumul_size = cumul_size;
882 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
883 csrow->mtype = MEM_RDDR; /* only one type supported */
884 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
887 * if single channel or x8 devices then SECDED
888 * if dual channel and x4 then S4ECD4ED
891 if (drc_chan && mem_dev) {
892 csrow->edac_mode = EDAC_S4ECD4ED;
893 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
895 csrow->edac_mode = EDAC_SECDED;
896 mci->edac_cap |= EDAC_FLAG_SECDED;
899 csrow->edac_mode = EDAC_NONE;
902 /* Fill in the memory map table */
908 for (index = 0; index < 8; index += 2) {
909 pci_read_config_byte(pdev, E752X_DRB + index, &value);
911 /* test if there is a dimm in this slot */
913 /* no dimm in the slot, so flag it as empty */
914 pvt->map[index] = 0xff;
915 pvt->map[index + 1] = 0xff;
916 } else { /* there is a dimm in the slot */
917 pvt->map[index] = row;
920 /* test the next value to see if the dimm is
922 pci_read_config_byte(pdev,
923 E752X_DRB + index + 1,
925 pvt->map[index + 1] = (value == last) ?
926 0xff : /* the dimm is single sided,
929 row; /* this is a double sided dimm
930 * to save the next row #
938 /* set the map type. 1 = normal, 0 = reversed */
939 pci_read_config_byte(pdev, E752X_DRM, &stat8);
940 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
942 mci->edac_cap |= EDAC_FLAG_NONE;
943 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
945 /* load the top of low memory, remap base, and remap limit vars */
946 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
947 pvt->tolm = ((u32) pci_data) << 4;
948 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
949 pvt->remapbase = ((u32) pci_data) << 14;
950 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
951 pvt->remaplimit = ((u32) pci_data) << 14;
952 e752x_printk(KERN_INFO,
953 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
954 pvt->remapbase, pvt->remaplimit);
956 if (edac_mc_add_mc(mci)) {
957 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
961 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
964 /* find the error reporting device and clear errors */
965 dev = pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
966 /* Turn off error disable & SMI in case the BIOS turned it on */
967 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
968 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
969 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
970 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
971 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
972 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
973 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
974 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
976 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
978 /* get this far and it's successful */
979 debugf3("%s(): success\n", __func__);
985 pci_dev_put(pvt->dev_d0f0);
988 pci_dev_put(pvt->dev_d0f1);
991 pci_dev_put(pvt->bridge_ck);
999 /* returns count (>= 0), or negative on error */
1000 static int __devinit e752x_init_one(struct pci_dev *pdev,
1001 const struct pci_device_id *ent)
1003 debugf0("%s()\n", __func__);
1005 /* wake up and enable device */
1006 if(pci_enable_device(pdev) < 0)
1009 return e752x_probe1(pdev, ent->driver_data);
1012 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1014 struct mem_ctl_info *mci;
1015 struct e752x_pvt *pvt;
1017 debugf0("%s()\n", __func__);
1019 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1022 pvt = (struct e752x_pvt *) mci->pvt_info;
1023 pci_dev_put(pvt->dev_d0f0);
1024 pci_dev_put(pvt->dev_d0f1);
1025 pci_dev_put(pvt->bridge_ck);
1029 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
1031 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1035 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1039 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1044 } /* 0 terminated list. */
1047 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1049 static struct pci_driver e752x_driver = {
1050 .name = EDAC_MOD_STR,
1051 .probe = e752x_init_one,
1052 .remove = __devexit_p(e752x_remove_one),
1053 .id_table = e752x_pci_tbl,
1056 static int __init e752x_init(void)
1060 debugf3("%s()\n", __func__);
1061 pci_rc = pci_register_driver(&e752x_driver);
1062 return (pci_rc < 0) ? pci_rc : 0;
1065 static void __exit e752x_exit(void)
1067 debugf3("%s()\n", __func__);
1068 pci_unregister_driver(&e752x_driver);
1071 module_init(e752x_init);
1072 module_exit(e752x_exit);
1074 MODULE_LICENSE("GPL");
1075 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1076 MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
1078 module_param(force_function_unhide, int, 0444);
1079 MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1080 " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");