1 #include "amd64_edac.h"
4 static struct edac_pci_ctl_info *amd64_ctl_pci;
6 static int report_gart_errors;
7 module_param(report_gart_errors, int, 0644);
10 * Set by command line parameter. If BIOS has enabled the ECC, this override is
11 * cleared to prevent re-enabling the hardware by this driver.
13 static int ecc_enable_override;
14 module_param(ecc_enable_override, int, 0644);
16 /* Lookup table for all possible MC control instances */
18 static struct mem_ctl_info *mci_lookup[EDAC_MAX_NUMNODES];
19 static struct amd64_pvt *pvt_lookup[EDAC_MAX_NUMNODES];
22 * Address to DRAM bank mapping: see F2x80 for K8 and F2x[1,0]80 for Fam10 and
25 static int ddr2_dbam_revCG[] = {
35 static int ddr2_dbam_revD[] = {
47 static int ddr2_dbam[] = { [0] = 128,
56 static int ddr3_dbam[] = { [0] = -1,
67 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
68 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
71 *FIXME: Produce a better mapping/linearisation.
74 struct scrubrate scrubrates[] = {
75 { 0x01, 1600000000UL},
97 { 0x00, 0UL}, /* scrubbing off */
101 * Memory scrubber control interface. For K8, memory scrubbing is handled by
102 * hardware and can involve L2 cache, dcache as well as the main memory. With
103 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
106 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
107 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
108 * bytes/sec for the setting.
110 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
111 * other archs, we might not have access to the caches directly.
115 * scan the scrub rate mapping table for a close or matching bandwidth value to
116 * issue. If requested is too big, then use last maximum value found.
118 static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw,
125 * map the configured rate (new_bw) to a value specific to the AMD64
126 * memory controller and apply to register. Search for the first
127 * bandwidth entry that is greater or equal than the setting requested
128 * and program that. If at last entry, turn off DRAM scrubbing.
130 for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
132 * skip scrub rates which aren't recommended
133 * (see F10 BKDG, F3x58)
135 if (scrubrates[i].scrubval < min_scrubrate)
138 if (scrubrates[i].bandwidth <= new_bw)
142 * if no suitable bandwidth found, turn off DRAM scrubbing
143 * entirely by falling back to the last element in the
148 scrubval = scrubrates[i].scrubval;
150 edac_printk(KERN_DEBUG, EDAC_MC,
151 "Setting scrub rate bandwidth: %u\n",
152 scrubrates[i].bandwidth);
154 edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n");
156 pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F);
161 static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 *bandwidth)
163 struct amd64_pvt *pvt = mci->pvt_info;
164 u32 min_scrubrate = 0x0;
166 switch (boot_cpu_data.x86) {
168 min_scrubrate = K8_MIN_SCRUB_RATE_BITS;
171 min_scrubrate = F10_MIN_SCRUB_RATE_BITS;
174 min_scrubrate = F11_MIN_SCRUB_RATE_BITS;
178 amd64_printk(KERN_ERR, "Unsupported family!\n");
181 return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, *bandwidth,
185 static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
187 struct amd64_pvt *pvt = mci->pvt_info;
191 amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval);
193 scrubval = scrubval & 0x001F;
195 edac_printk(KERN_DEBUG, EDAC_MC,
196 "pci-read, sdram scrub control value: %d \n", scrubval);
198 for (i = 0; ARRAY_SIZE(scrubrates); i++) {
199 if (scrubrates[i].scrubval == scrubval) {
200 *bw = scrubrates[i].bandwidth;
209 /* Map from a CSROW entry to the mask entry that operates on it */
210 static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow)
212 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F)
218 /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */
219 static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow)
222 return pvt->dcsb0[csrow];
224 return pvt->dcsb1[csrow];
228 * Return the 'mask' address the i'th CS entry. This function is needed because
229 * there number of DCSM registers on Rev E and prior vs Rev F and later is
232 static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow)
235 return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)];
237 return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)];
242 * In *base and *limit, pass back the full 40-bit base and limit physical
243 * addresses for the node given by node_id. This information is obtained from
244 * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The
245 * base and limit addresses are of type SysAddr, as defined at the start of
246 * section 3.4.4 (p. 70). They are the lowest and highest physical addresses
247 * in the address range they represent.
249 static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id,
250 u64 *base, u64 *limit)
252 *base = pvt->dram_base[node_id];
253 *limit = pvt->dram_limit[node_id];
257 * Return 1 if the SysAddr given by sys_addr matches the base/limit associated
260 static int amd64_base_limit_match(struct amd64_pvt *pvt,
261 u64 sys_addr, int node_id)
263 u64 base, limit, addr;
265 amd64_get_base_and_limit(pvt, node_id, &base, &limit);
267 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
268 * all ones if the most significant implemented address bit is 1.
269 * Here we discard bits 63-40. See section 3.4.2 of AMD publication
270 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
271 * Application Programming.
273 addr = sys_addr & 0x000000ffffffffffull;
275 return (addr >= base) && (addr <= limit);
279 * Attempt to map a SysAddr to a node. On success, return a pointer to the
280 * mem_ctl_info structure for the node that the SysAddr maps to.
282 * On failure, return NULL.
284 static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
287 struct amd64_pvt *pvt;
292 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
293 * 3.4.4.2) registers to map the SysAddr to a node ID.
298 * The value of this field should be the same for all DRAM Base
299 * registers. Therefore we arbitrarily choose to read it from the
300 * register for node 0.
302 intlv_en = pvt->dram_IntlvEn[0];
305 for (node_id = 0; node_id < DRAM_REG_COUNT; node_id++) {
306 if (amd64_base_limit_match(pvt, sys_addr, node_id))
312 if (unlikely((intlv_en != 0x01) &&
313 (intlv_en != 0x03) &&
314 (intlv_en != 0x07))) {
315 amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from "
316 "IntlvEn field of DRAM Base Register for node 0: "
317 "this probably indicates a BIOS bug.\n", intlv_en);
321 bits = (((u32) sys_addr) >> 12) & intlv_en;
323 for (node_id = 0; ; ) {
324 if ((pvt->dram_IntlvSel[node_id] & intlv_en) == bits)
325 break; /* intlv_sel field matches */
327 if (++node_id >= DRAM_REG_COUNT)
331 /* sanity test for sys_addr */
332 if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) {
333 amd64_printk(KERN_WARNING,
334 "%s(): sys_addr 0x%llx falls outside base/limit "
335 "address range for node %d with node interleaving "
337 __func__, sys_addr, node_id);
342 return edac_mc_find(node_id);
345 debugf2("sys_addr 0x%lx doesn't match any node\n",
346 (unsigned long)sys_addr);
352 * Extract the DRAM CS base address from selected csrow register.
354 static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow)
356 return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) <<
361 * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way.
363 static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow)
365 u64 dcsm_bits, other_bits;
368 /* Extract bits from DRAM CS Mask. */
369 dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask;
371 other_bits = pvt->dcsm_mask;
372 other_bits = ~(other_bits << pvt->dcs_shift);
375 * The extracted bits from DCSM belong in the spaces represented by
376 * the cleared bits in other_bits.
378 mask = (dcsm_bits << pvt->dcs_shift) | other_bits;
384 * @input_addr is an InputAddr associated with the node given by mci. Return the
385 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
387 static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
389 struct amd64_pvt *pvt;
396 * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS
397 * base/mask register pair, test the condition shown near the start of
398 * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).
400 for (csrow = 0; csrow < pvt->cs_count; csrow++) {
402 /* This DRAM chip select is disabled on this node */
403 if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0)
406 base = base_from_dct_base(pvt, csrow);
407 mask = ~mask_from_dct_mask(pvt, csrow);
409 if ((input_addr & mask) == (base & mask)) {
410 debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n",
411 (unsigned long)input_addr, csrow,
418 debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n",
419 (unsigned long)input_addr, pvt->mc_node_id);
425 * Return the base value defined by the DRAM Base register for the node
426 * represented by mci. This function returns the full 40-bit value despite the
427 * fact that the register only stores bits 39-24 of the value. See section
428 * 3.4.4.1 (BKDG #26094, K8, revA-E)
430 static inline u64 get_dram_base(struct mem_ctl_info *mci)
432 struct amd64_pvt *pvt = mci->pvt_info;
434 return pvt->dram_base[pvt->mc_node_id];
438 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
439 * for the node represented by mci. Info is passed back in *hole_base,
440 * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
441 * info is invalid. Info may be invalid for either of the following reasons:
443 * - The revision of the node is not E or greater. In this case, the DRAM Hole
444 * Address Register does not exist.
446 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
447 * indicating that its contents are not valid.
449 * The values passed back in *hole_base, *hole_offset, and *hole_size are
450 * complete 32-bit values despite the fact that the bitfields in the DHAR
451 * only represent bits 31-24 of the base and offset values.
453 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
454 u64 *hole_offset, u64 *hole_size)
456 struct amd64_pvt *pvt = mci->pvt_info;
459 /* only revE and later have the DRAM Hole Address Register */
460 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) {
461 debugf1(" revision %d for node %d does not support DHAR\n",
462 pvt->ext_model, pvt->mc_node_id);
466 /* only valid for Fam10h */
467 if (boot_cpu_data.x86 == 0x10 &&
468 (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) {
469 debugf1(" Dram Memory Hoisting is DISABLED on this system\n");
473 if ((pvt->dhar & DHAR_VALID) == 0) {
474 debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n",
479 /* This node has Memory Hoisting */
481 /* +------------------+--------------------+--------------------+-----
482 * | memory | DRAM hole | relocated |
483 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
485 * | | | [0x100000000, |
486 * | | | (0x100000000+ |
487 * | | | (0xffffffff-x))] |
488 * +------------------+--------------------+--------------------+-----
490 * Above is a diagram of physical memory showing the DRAM hole and the
491 * relocated addresses from the DRAM hole. As shown, the DRAM hole
492 * starts at address x (the base address) and extends through address
493 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
494 * addresses in the hole so that they start at 0x100000000.
497 base = dhar_base(pvt->dhar);
500 *hole_size = (0x1ull << 32) - base;
502 if (boot_cpu_data.x86 > 0xf)
503 *hole_offset = f10_dhar_offset(pvt->dhar);
505 *hole_offset = k8_dhar_offset(pvt->dhar);
507 debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
508 pvt->mc_node_id, (unsigned long)*hole_base,
509 (unsigned long)*hole_offset, (unsigned long)*hole_size);
513 EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);
516 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
517 * assumed that sys_addr maps to the node given by mci.
519 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
520 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
521 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
522 * then it is also involved in translating a SysAddr to a DramAddr. Sections
523 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
524 * These parts of the documentation are unclear. I interpret them as follows:
526 * When node n receives a SysAddr, it processes the SysAddr as follows:
528 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
529 * Limit registers for node n. If the SysAddr is not within the range
530 * specified by the base and limit values, then node n ignores the Sysaddr
531 * (since it does not map to node n). Otherwise continue to step 2 below.
533 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
534 * disabled so skip to step 3 below. Otherwise see if the SysAddr is within
535 * the range of relocated addresses (starting at 0x100000000) from the DRAM
536 * hole. If not, skip to step 3 below. Else get the value of the
537 * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
538 * offset defined by this value from the SysAddr.
540 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
541 * Base register for node n. To obtain the DramAddr, subtract the base
542 * address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
544 static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
546 u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
549 dram_base = get_dram_base(mci);
551 ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
554 if ((sys_addr >= (1ull << 32)) &&
555 (sys_addr < ((1ull << 32) + hole_size))) {
556 /* use DHAR to translate SysAddr to DramAddr */
557 dram_addr = sys_addr - hole_offset;
559 debugf2("using DHAR to translate SysAddr 0x%lx to "
561 (unsigned long)sys_addr,
562 (unsigned long)dram_addr);
569 * Translate the SysAddr to a DramAddr as shown near the start of
570 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
571 * only deals with 40-bit values. Therefore we discard bits 63-40 of
572 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
573 * discard are all 1s. Otherwise the bits we discard are all 0s. See
574 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
575 * Programmer's Manual Volume 1 Application Programming.
577 dram_addr = (sys_addr & 0xffffffffffull) - dram_base;
579 debugf2("using DRAM Base register to translate SysAddr 0x%lx to "
580 "DramAddr 0x%lx\n", (unsigned long)sys_addr,
581 (unsigned long)dram_addr);
586 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
587 * (section 3.4.4.1). Return the number of bits from a SysAddr that are used
588 * for node interleaving.
590 static int num_node_interleave_bits(unsigned intlv_en)
592 static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
595 BUG_ON(intlv_en > 7);
596 n = intlv_shift_table[intlv_en];
600 /* Translate the DramAddr given by @dram_addr to an InputAddr. */
601 static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
603 struct amd64_pvt *pvt;
610 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
611 * concerning translating a DramAddr to an InputAddr.
613 intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]);
614 input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) +
617 debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
618 intlv_shift, (unsigned long)dram_addr,
619 (unsigned long)input_addr);
625 * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
626 * assumed that @sys_addr maps to the node given by mci.
628 static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
633 dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));
635 debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
636 (unsigned long)sys_addr, (unsigned long)input_addr);
643 * @input_addr is an InputAddr associated with the node represented by mci.
644 * Translate @input_addr to a DramAddr and return the result.
646 static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
648 struct amd64_pvt *pvt;
649 int node_id, intlv_shift;
654 * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
655 * shows how to translate a DramAddr to an InputAddr. Here we reverse
656 * this procedure. When translating from a DramAddr to an InputAddr, the
657 * bits used for node interleaving are discarded. Here we recover these
658 * bits from the IntlvSel field of the DRAM Limit register (section
659 * 3.4.4.2) for the node that input_addr is associated with.
662 node_id = pvt->mc_node_id;
663 BUG_ON((node_id < 0) || (node_id > 7));
665 intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]);
667 if (intlv_shift == 0) {
668 debugf1(" InputAddr 0x%lx translates to DramAddr of "
669 "same value\n", (unsigned long)input_addr);
674 bits = ((input_addr & 0xffffff000ull) << intlv_shift) +
675 (input_addr & 0xfff);
677 intlv_sel = pvt->dram_IntlvSel[node_id] & ((1 << intlv_shift) - 1);
678 dram_addr = bits + (intlv_sel << 12);
680 debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx "
681 "(%d node interleave bits)\n", (unsigned long)input_addr,
682 (unsigned long)dram_addr, intlv_shift);
688 * @dram_addr is a DramAddr that maps to the node represented by mci. Convert
689 * @dram_addr to a SysAddr.
691 static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
693 struct amd64_pvt *pvt = mci->pvt_info;
694 u64 hole_base, hole_offset, hole_size, base, limit, sys_addr;
697 ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
700 if ((dram_addr >= hole_base) &&
701 (dram_addr < (hole_base + hole_size))) {
702 sys_addr = dram_addr + hole_offset;
704 debugf1("using DHAR to translate DramAddr 0x%lx to "
705 "SysAddr 0x%lx\n", (unsigned long)dram_addr,
706 (unsigned long)sys_addr);
712 amd64_get_base_and_limit(pvt, pvt->mc_node_id, &base, &limit);
713 sys_addr = dram_addr + base;
716 * The sys_addr we have computed up to this point is a 40-bit value
717 * because the k8 deals with 40-bit values. However, the value we are
718 * supposed to return is a full 64-bit physical address. The AMD
719 * x86-64 architecture specifies that the most significant implemented
720 * address bit through bit 63 of a physical address must be either all
721 * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a
722 * 64-bit value below. See section 3.4.2 of AMD publication 24592:
723 * AMD x86-64 Architecture Programmer's Manual Volume 1 Application
726 sys_addr |= ~((sys_addr & (1ull << 39)) - 1);
728 debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n",
729 pvt->mc_node_id, (unsigned long)dram_addr,
730 (unsigned long)sys_addr);
736 * @input_addr is an InputAddr associated with the node given by mci. Translate
737 * @input_addr to a SysAddr.
739 static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci,
742 return dram_addr_to_sys_addr(mci,
743 input_addr_to_dram_addr(mci, input_addr));
747 * Find the minimum and maximum InputAddr values that map to the given @csrow.
748 * Pass back these values in *input_addr_min and *input_addr_max.
750 static void find_csrow_limits(struct mem_ctl_info *mci, int csrow,
751 u64 *input_addr_min, u64 *input_addr_max)
753 struct amd64_pvt *pvt;
757 BUG_ON((csrow < 0) || (csrow >= pvt->cs_count));
759 base = base_from_dct_base(pvt, csrow);
760 mask = mask_from_dct_mask(pvt, csrow);
762 *input_addr_min = base & ~mask;
763 *input_addr_max = base | mask | pvt->dcs_mask_notused;
767 * Extract error address from MCA NB Address Low (section 3.6.4.5) and MCA NB
768 * Address High (section 3.6.4.6) register values and return the result. Address
769 * is located in the info structure (nbeah and nbeal), the encoding is device
772 static u64 extract_error_address(struct mem_ctl_info *mci,
773 struct err_regs *info)
775 struct amd64_pvt *pvt = mci->pvt_info;
777 return pvt->ops->get_error_address(mci, info);
781 /* Map the Error address to a PAGE and PAGE OFFSET. */
782 static inline void error_address_to_page_and_offset(u64 error_address,
783 u32 *page, u32 *offset)
785 *page = (u32) (error_address >> PAGE_SHIFT);
786 *offset = ((u32) error_address) & ~PAGE_MASK;
790 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
791 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
792 * of a node that detected an ECC memory error. mci represents the node that
793 * the error address maps to (possibly different from the node that detected
794 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
797 static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
801 csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));
804 amd64_mc_printk(mci, KERN_ERR,
805 "Failed to translate InputAddr to csrow for "
806 "address 0x%lx\n", (unsigned long)sys_addr);
810 static int get_channel_from_ecc_syndrome(unsigned short syndrome);
812 static void amd64_cpu_display_info(struct amd64_pvt *pvt)
814 if (boot_cpu_data.x86 == 0x11)
815 edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n");
816 else if (boot_cpu_data.x86 == 0x10)
817 edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n");
818 else if (boot_cpu_data.x86 == 0xf)
819 edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n",
820 (pvt->ext_model >= K8_REV_F) ?
821 "Rev F or later" : "Rev E or earlier");
823 /* we'll hardly ever ever get here */
824 edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n");
828 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
831 static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
834 enum dev_type edac_cap = EDAC_FLAG_NONE;
836 bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F)
840 if (pvt->dclr0 & BIT(bit))
841 edac_cap = EDAC_FLAG_SECDED;
847 static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt);
849 static void amd64_dump_dramcfg_low(u32 dclr, int chan)
851 debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
853 debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n",
854 (dclr & BIT(16)) ? "un" : "",
855 (dclr & BIT(19)) ? "yes" : "no");
857 debugf1(" PAR/ERR parity: %s\n",
858 (dclr & BIT(8)) ? "enabled" : "disabled");
860 debugf1(" DCT 128bit mode width: %s\n",
861 (dclr & BIT(11)) ? "128b" : "64b");
863 debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
864 (dclr & BIT(12)) ? "yes" : "no",
865 (dclr & BIT(13)) ? "yes" : "no",
866 (dclr & BIT(14)) ? "yes" : "no",
867 (dclr & BIT(15)) ? "yes" : "no");
870 /* Display and decode various NB registers for debug purposes. */
871 static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
875 debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
877 debugf1(" NB two channel DRAM capable: %s\n",
878 (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "yes" : "no");
880 debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n",
881 (pvt->nbcap & K8_NBCAP_SECDED) ? "yes" : "no",
882 (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "yes" : "no");
884 amd64_dump_dramcfg_low(pvt->dclr0, 0);
886 debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
888 debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, "
891 dhar_base(pvt->dhar),
892 (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt->dhar)
893 : f10_dhar_offset(pvt->dhar));
895 debugf1(" DramHoleValid: %s\n",
896 (pvt->dhar & DHAR_VALID) ? "yes" : "no");
898 /* everything below this point is Fam10h and above */
899 if (boot_cpu_data.x86 == 0xf) {
900 amd64_debug_display_dimm_sizes(0, pvt);
904 /* Only if NOT ganged does dclr1 have valid info */
905 if (!dct_ganging_enabled(pvt))
906 amd64_dump_dramcfg_low(pvt->dclr1, 1);
909 * Determine if ganged and then dump memory sizes for first controller,
910 * and if NOT ganged dump info for 2nd controller.
912 ganged = dct_ganging_enabled(pvt);
914 amd64_debug_display_dimm_sizes(0, pvt);
917 amd64_debug_display_dimm_sizes(1, pvt);
920 /* Read in both of DBAM registers */
921 static void amd64_read_dbam_reg(struct amd64_pvt *pvt)
923 amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM0, &pvt->dbam0);
925 if (boot_cpu_data.x86 >= 0x10)
926 amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM1, &pvt->dbam1);
930 * NOTE: CPU Revision Dependent code: Rev E and Rev F
932 * Set the DCSB and DCSM mask values depending on the CPU revision value. Also
933 * set the shift factor for the DCSB and DCSM values.
935 * ->dcs_mask_notused, RevE:
937 * To find the max InputAddr for the csrow, start with the base address and set
938 * all bits that are "don't care" bits in the test at the start of section
941 * The "don't care" bits are all set bits in the mask and all bits in the gaps
942 * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS
943 * represents bits [24:20] and [12:0], which are all bits in the above-mentioned
946 * ->dcs_mask_notused, RevF and later:
948 * To find the max InputAddr for the csrow, start with the base address and set
949 * all bits that are "don't care" bits in the test at the start of NPT section
952 * The "don't care" bits are all set bits in the mask and all bits in the gaps
953 * between bit ranges [36:27] and [21:13].
955 * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0],
956 * which are all bits in the above-mentioned gaps.
958 static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt)
961 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) {
962 pvt->dcsb_base = REV_E_DCSB_BASE_BITS;
963 pvt->dcsm_mask = REV_E_DCSM_MASK_BITS;
964 pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS;
965 pvt->dcs_shift = REV_E_DCS_SHIFT;
969 pvt->dcsb_base = REV_F_F1Xh_DCSB_BASE_BITS;
970 pvt->dcsm_mask = REV_F_F1Xh_DCSM_MASK_BITS;
971 pvt->dcs_mask_notused = REV_F_F1Xh_DCS_NOTUSED_BITS;
972 pvt->dcs_shift = REV_F_F1Xh_DCS_SHIFT;
974 if (boot_cpu_data.x86 == 0x11) {
985 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers
987 static void amd64_read_dct_base_mask(struct amd64_pvt *pvt)
991 amd64_set_dct_base_and_mask(pvt);
993 for (cs = 0; cs < pvt->cs_count; cs++) {
994 reg = K8_DCSB0 + (cs * 4);
995 if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsb0[cs]))
996 debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n",
997 cs, pvt->dcsb0[cs], reg);
999 /* If DCT are NOT ganged, then read in DCT1's base */
1000 if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) {
1001 reg = F10_DCSB1 + (cs * 4);
1002 if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg,
1004 debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n",
1005 cs, pvt->dcsb1[cs], reg);
1011 for (cs = 0; cs < pvt->num_dcsm; cs++) {
1012 reg = K8_DCSM0 + (cs * 4);
1013 if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsm0[cs]))
1014 debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n",
1015 cs, pvt->dcsm0[cs], reg);
1017 /* If DCT are NOT ganged, then read in DCT1's mask */
1018 if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) {
1019 reg = F10_DCSM1 + (cs * 4);
1020 if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg,
1022 debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n",
1023 cs, pvt->dcsm1[cs], reg);
1030 static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt)
1034 if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= K8_REV_F) {
1035 /* Rev F and later */
1036 type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
1038 /* Rev E and earlier */
1039 type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
1042 debugf1(" Memory type is: %s\n",
1043 (type == MEM_DDR2) ? "MEM_DDR2" :
1044 (type == MEM_RDDR2) ? "MEM_RDDR2" :
1045 (type == MEM_DDR) ? "MEM_DDR" : "MEM_RDDR");
1051 * Read the DRAM Configuration Low register. It differs between CG, D & E revs
1052 * and the later RevF memory controllers (DDR vs DDR2)
1055 * number of memory channels in operation
1057 * contents of the DCL0_LOW register
1059 static int k8_early_channel_count(struct amd64_pvt *pvt)
1063 err = amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
1067 if ((boot_cpu_data.x86_model >> 4) >= K8_REV_F) {
1068 /* RevF (NPT) and later */
1069 flag = pvt->dclr0 & F10_WIDTH_128;
1071 /* RevE and earlier */
1072 flag = pvt->dclr0 & REVE_WIDTH_128;
1078 return (flag) ? 2 : 1;
1081 /* extract the ERROR ADDRESS for the K8 CPUs */
1082 static u64 k8_get_error_address(struct mem_ctl_info *mci,
1083 struct err_regs *info)
1085 return (((u64) (info->nbeah & 0xff)) << 32) +
1086 (info->nbeal & ~0x03);
1090 * Read the Base and Limit registers for K8 based Memory controllers; extract
1091 * fields from the 'raw' reg into separate data fields
1093 * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN
1095 static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
1098 u32 off = dram << 3; /* 8 bytes between DRAM entries */
1100 amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_BASE_LOW + off, &low);
1102 /* Extract parts into separate data entries */
1103 pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8;
1104 pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7;
1105 pvt->dram_rw_en[dram] = (low & 0x3);
1107 amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_LIMIT_LOW + off, &low);
1110 * Extract parts into separate data entries. Limit is the HIGHEST memory
1111 * location of the region, so lower 24 bits need to be all ones
1113 pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF;
1114 pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7;
1115 pvt->dram_DstNode[dram] = (low & 0x7);
1118 static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
1119 struct err_regs *info,
1122 struct mem_ctl_info *src_mci;
1123 unsigned short syndrome;
1127 /* Extract the syndrome parts and form a 16-bit syndrome */
1128 syndrome = HIGH_SYNDROME(info->nbsl) << 8;
1129 syndrome |= LOW_SYNDROME(info->nbsh);
1131 /* CHIPKILL enabled */
1132 if (info->nbcfg & K8_NBCFG_CHIPKILL) {
1133 channel = get_channel_from_ecc_syndrome(syndrome);
1136 * Syndrome didn't map, so we don't know which of the
1137 * 2 DIMMs is in error. So we need to ID 'both' of them
1140 amd64_mc_printk(mci, KERN_WARNING,
1141 "unknown syndrome 0x%x - possible error "
1142 "reporting race\n", syndrome);
1143 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
1148 * non-chipkill ecc mode
1150 * The k8 documentation is unclear about how to determine the
1151 * channel number when using non-chipkill memory. This method
1152 * was obtained from email communication with someone at AMD.
1153 * (Wish the email was placed in this comment - norsk)
1155 channel = ((SystemAddress & BIT(3)) != 0);
1159 * Find out which node the error address belongs to. This may be
1160 * different from the node that detected the error.
1162 src_mci = find_mc_by_sys_addr(mci, SystemAddress);
1164 amd64_mc_printk(mci, KERN_ERR,
1165 "failed to map error address 0x%lx to a node\n",
1166 (unsigned long)SystemAddress);
1167 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
1171 /* Now map the SystemAddress to a CSROW */
1172 csrow = sys_addr_to_csrow(src_mci, SystemAddress);
1174 edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR);
1176 error_address_to_page_and_offset(SystemAddress, &page, &offset);
1178 edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow,
1179 channel, EDAC_MOD_STR);
1183 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode)
1187 if (pvt->ext_model >= K8_REV_F)
1188 dbam_map = ddr2_dbam;
1189 else if (pvt->ext_model >= K8_REV_D)
1190 dbam_map = ddr2_dbam_revD;
1192 dbam_map = ddr2_dbam_revCG;
1194 return dbam_map[cs_mode];
1198 * Get the number of DCT channels in use.
1201 * number of Memory Channels in operation
1203 * contents of the DCL0_LOW register
1205 static int f10_early_channel_count(struct amd64_pvt *pvt)
1207 int dbams[] = { DBAM0, DBAM1 };
1208 int i, j, channels = 0;
1211 /* If we are in 128 bit mode, then we are using 2 channels */
1212 if (pvt->dclr0 & F10_WIDTH_128) {
1218 * Need to check if in unganged mode: In such, there are 2 channels,
1219 * but they are not in 128 bit mode and thus the above 'dclr0' status
1222 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
1223 * their CSEnable bit on. If so, then SINGLE DIMM case.
1225 debugf0("Data width is not 128 bits - need more decoding\n");
1228 * Check DRAM Bank Address Mapping values for each DIMM to see if there
1229 * is more than just one DIMM present in unganged mode. Need to check
1230 * both controllers since DIMMs can be placed in either one.
1232 for (i = 0; i < ARRAY_SIZE(dbams); i++) {
1233 if (amd64_read_pci_cfg(pvt->dram_f2_ctl, dbams[i], &dbam))
1236 for (j = 0; j < 4; j++) {
1237 if (DBAM_DIMM(j, dbam) > 0) {
1247 debugf0("MCT channel count: %d\n", channels);
1256 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode)
1260 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
1261 dbam_map = ddr3_dbam;
1263 dbam_map = ddr2_dbam;
1265 return dbam_map[cs_mode];
1268 /* Enable extended configuration access via 0xCF8 feature */
1269 static void amd64_setup(struct amd64_pvt *pvt)
1273 amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®);
1275 pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG);
1276 reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG;
1277 pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg);
1280 /* Restore the extended configuration access via 0xCF8 feature */
1281 static void amd64_teardown(struct amd64_pvt *pvt)
1285 amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®);
1287 reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG;
1288 if (pvt->flags.cf8_extcfg)
1289 reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG;
1290 pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg);
1293 static u64 f10_get_error_address(struct mem_ctl_info *mci,
1294 struct err_regs *info)
1296 return (((u64) (info->nbeah & 0xffff)) << 32) +
1297 (info->nbeal & ~0x01);
1301 * Read the Base and Limit registers for F10 based Memory controllers. Extract
1302 * fields from the 'raw' reg into separate data fields.
1304 * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN.
1306 static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
1308 u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit;
1310 low_offset = K8_DRAM_BASE_LOW + (dram << 3);
1311 high_offset = F10_DRAM_BASE_HIGH + (dram << 3);
1313 /* read the 'raw' DRAM BASE Address register */
1314 amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_base);
1316 /* Read from the ECS data register */
1317 amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_base);
1319 /* Extract parts into separate data entries */
1320 pvt->dram_rw_en[dram] = (low_base & 0x3);
1322 if (pvt->dram_rw_en[dram] == 0)
1325 pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7;
1327 pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) |
1328 (((u64)low_base & 0xFFFF0000) << 8);
1330 low_offset = K8_DRAM_LIMIT_LOW + (dram << 3);
1331 high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3);
1333 /* read the 'raw' LIMIT registers */
1334 amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_limit);
1336 /* Read from the ECS data register for the HIGH portion */
1337 amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_limit);
1339 debugf0(" HW Regs: BASE=0x%08x-%08x LIMIT= 0x%08x-%08x\n",
1340 high_base, low_base, high_limit, low_limit);
1342 pvt->dram_DstNode[dram] = (low_limit & 0x7);
1343 pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7;
1346 * Extract address values and form a LIMIT address. Limit is the HIGHEST
1347 * memory location of the region, so low 24 bits need to be all ones.
1349 pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) |
1350 (((u64) low_limit & 0xFFFF0000) << 8) |
1354 static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
1357 if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW,
1358 &pvt->dram_ctl_select_low)) {
1359 debugf0("F2x110 (DCTL Sel. Low): 0x%08x, "
1360 "High range addresses at: 0x%x\n",
1361 pvt->dram_ctl_select_low,
1362 dct_sel_baseaddr(pvt));
1364 debugf0(" DCT mode: %s, All DCTs on: %s\n",
1365 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"),
1366 (dct_dram_enabled(pvt) ? "yes" : "no"));
1368 if (!dct_ganging_enabled(pvt))
1369 debugf0(" Address range split per DCT: %s\n",
1370 (dct_high_range_enabled(pvt) ? "yes" : "no"));
1372 debugf0(" DCT data interleave for ECC: %s, "
1373 "DRAM cleared since last warm reset: %s\n",
1374 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
1375 (dct_memory_cleared(pvt) ? "yes" : "no"));
1377 debugf0(" DCT channel interleave: %s, "
1378 "DCT interleave bits selector: 0x%x\n",
1379 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
1380 dct_sel_interleave_addr(pvt));
1383 amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH,
1384 &pvt->dram_ctl_select_high);
1388 * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory
1389 * Interleaving Modes.
1391 static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
1392 int hi_range_sel, u32 intlv_en)
1394 u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1;
1396 if (dct_ganging_enabled(pvt))
1398 else if (hi_range_sel)
1400 else if (dct_interleave_enabled(pvt)) {
1402 * see F2x110[DctSelIntLvAddr] - channel interleave mode
1404 if (dct_sel_interleave_addr(pvt) == 0)
1405 cs = sys_addr >> 6 & 1;
1406 else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) {
1407 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2;
1409 if (dct_sel_interleave_addr(pvt) & 1)
1410 cs = (sys_addr >> 9 & 1) ^ temp;
1412 cs = (sys_addr >> 6 & 1) ^ temp;
1413 } else if (intlv_en & 4)
1414 cs = sys_addr >> 15 & 1;
1415 else if (intlv_en & 2)
1416 cs = sys_addr >> 14 & 1;
1417 else if (intlv_en & 1)
1418 cs = sys_addr >> 13 & 1;
1420 cs = sys_addr >> 12 & 1;
1421 } else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt))
1422 cs = ~dct_sel_high & 1;
1429 static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en)
1433 else if (intlv_en == 3)
1435 else if (intlv_en == 7)
1441 /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */
1442 static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel,
1443 u32 dct_sel_base_addr,
1444 u64 dct_sel_base_off,
1445 u32 hole_valid, u32 hole_off,
1451 if (!(dct_sel_base_addr & 0xFFFFF800) &&
1452 hole_valid && (sys_addr >= 0x100000000ULL))
1453 chan_off = hole_off << 16;
1455 chan_off = dct_sel_base_off;
1457 if (hole_valid && (sys_addr >= 0x100000000ULL))
1458 chan_off = hole_off << 16;
1460 chan_off = dram_base & 0xFFFFF8000000ULL;
1463 return (sys_addr & 0x0000FFFFFFFFFFC0ULL) -
1464 (chan_off & 0x0000FFFFFF800000ULL);
1467 /* Hack for the time being - Can we get this from BIOS?? */
1468 #define CH0SPARE_RANK 0
1469 #define CH1SPARE_RANK 1
1472 * checks if the csrow passed in is marked as SPARED, if so returns the new
1475 static inline int f10_process_possible_spare(int csrow,
1476 u32 cs, struct amd64_pvt *pvt)
1481 /* Depending on channel, isolate respective SPARING info */
1483 swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare);
1484 bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare);
1485 if (swap_done && (csrow == bad_dram_cs))
1486 csrow = CH1SPARE_RANK;
1488 swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare);
1489 bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare);
1490 if (swap_done && (csrow == bad_dram_cs))
1491 csrow = CH0SPARE_RANK;
1497 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
1498 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
1501 * -EINVAL: NOT FOUND
1502 * 0..csrow = Chip-Select Row
1504 static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs)
1506 struct mem_ctl_info *mci;
1507 struct amd64_pvt *pvt;
1508 u32 cs_base, cs_mask;
1509 int cs_found = -EINVAL;
1512 mci = mci_lookup[nid];
1516 pvt = mci->pvt_info;
1518 debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs);
1520 for (csrow = 0; csrow < pvt->cs_count; csrow++) {
1522 cs_base = amd64_get_dct_base(pvt, cs, csrow);
1523 if (!(cs_base & K8_DCSB_CS_ENABLE))
1527 * We have an ENABLED CSROW, Isolate just the MASK bits of the
1528 * target: [28:19] and [13:5], which map to [36:27] and [21:13]
1529 * of the actual address.
1531 cs_base &= REV_F_F1Xh_DCSB_BASE_BITS;
1534 * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and
1535 * [4:0] to become ON. Then mask off bits [28:0] ([36:8])
1537 cs_mask = amd64_get_dct_mask(pvt, cs, csrow);
1539 debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n",
1540 csrow, cs_base, cs_mask);
1542 cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF;
1544 debugf1(" Final CSMask=0x%x\n", cs_mask);
1545 debugf1(" (InputAddr & ~CSMask)=0x%x "
1546 "(CSBase & ~CSMask)=0x%x\n",
1547 (in_addr & ~cs_mask), (cs_base & ~cs_mask));
1549 if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) {
1550 cs_found = f10_process_possible_spare(csrow, cs, pvt);
1552 debugf1(" MATCH csrow=%d\n", cs_found);
1559 /* For a given @dram_range, check if @sys_addr falls within it. */
1560 static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range,
1561 u64 sys_addr, int *nid, int *chan_sel)
1563 int node_id, cs_found = -EINVAL, high_range = 0;
1564 u32 intlv_en, intlv_sel, intlv_shift, hole_off;
1565 u32 hole_valid, tmp, dct_sel_base, channel;
1566 u64 dram_base, chan_addr, dct_sel_base_off;
1568 dram_base = pvt->dram_base[dram_range];
1569 intlv_en = pvt->dram_IntlvEn[dram_range];
1571 node_id = pvt->dram_DstNode[dram_range];
1572 intlv_sel = pvt->dram_IntlvSel[dram_range];
1574 debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n",
1575 dram_range, dram_base, sys_addr, pvt->dram_limit[dram_range]);
1578 * This assumes that one node's DHAR is the same as all the other
1581 hole_off = (pvt->dhar & 0x0000FF80);
1582 hole_valid = (pvt->dhar & 0x1);
1583 dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16;
1585 debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n",
1586 hole_off, hole_valid, intlv_sel);
1589 (intlv_sel != ((sys_addr >> 12) & intlv_en)))
1592 dct_sel_base = dct_sel_baseaddr(pvt);
1595 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
1596 * select between DCT0 and DCT1.
1598 if (dct_high_range_enabled(pvt) &&
1599 !dct_ganging_enabled(pvt) &&
1600 ((sys_addr >> 27) >= (dct_sel_base >> 11)))
1603 channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en);
1605 chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base,
1606 dct_sel_base_off, hole_valid,
1607 hole_off, dram_base);
1609 intlv_shift = f10_map_intlv_en_to_shift(intlv_en);
1611 /* remove Node ID (in case of memory interleaving) */
1612 tmp = chan_addr & 0xFC0;
1614 chan_addr = ((chan_addr >> intlv_shift) & 0xFFFFFFFFF000ULL) | tmp;
1616 /* remove channel interleave and hash */
1617 if (dct_interleave_enabled(pvt) &&
1618 !dct_high_range_enabled(pvt) &&
1619 !dct_ganging_enabled(pvt)) {
1620 if (dct_sel_interleave_addr(pvt) != 1)
1621 chan_addr = (chan_addr >> 1) & 0xFFFFFFFFFFFFFFC0ULL;
1623 tmp = chan_addr & 0xFC0;
1624 chan_addr = ((chan_addr & 0xFFFFFFFFFFFFC000ULL) >> 1)
1629 debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n",
1630 chan_addr, (u32)(chan_addr >> 8));
1632 cs_found = f10_lookup_addr_in_dct(chan_addr >> 8, node_id, channel);
1634 if (cs_found >= 0) {
1636 *chan_sel = channel;
1641 static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
1642 int *node, int *chan_sel)
1644 int dram_range, cs_found = -EINVAL;
1645 u64 dram_base, dram_limit;
1647 for (dram_range = 0; dram_range < DRAM_REG_COUNT; dram_range++) {
1649 if (!pvt->dram_rw_en[dram_range])
1652 dram_base = pvt->dram_base[dram_range];
1653 dram_limit = pvt->dram_limit[dram_range];
1655 if ((dram_base <= sys_addr) && (sys_addr <= dram_limit)) {
1657 cs_found = f10_match_to_this_node(pvt, dram_range,
1668 * This the F10h reference code from AMD to map a @sys_addr to NodeID,
1671 * The @sys_addr is usually an error address received from the hardware.
1673 static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
1674 struct err_regs *info,
1677 struct amd64_pvt *pvt = mci->pvt_info;
1679 unsigned short syndrome;
1680 int nid, csrow, chan = 0;
1682 csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan);
1685 error_address_to_page_and_offset(sys_addr, &page, &offset);
1687 syndrome = HIGH_SYNDROME(info->nbsl) << 8;
1688 syndrome |= LOW_SYNDROME(info->nbsh);
1691 * Is CHIPKILL on? If so, then we can attempt to use the
1692 * syndrome to isolate which channel the error was on.
1694 if (pvt->nbcfg & K8_NBCFG_CHIPKILL)
1695 chan = get_channel_from_ecc_syndrome(syndrome);
1698 edac_mc_handle_ce(mci, page, offset, syndrome,
1699 csrow, chan, EDAC_MOD_STR);
1702 * Channel unknown, report all channels on this
1705 for (chan = 0; chan < mci->csrows[csrow].nr_channels;
1707 edac_mc_handle_ce(mci, page, offset,
1715 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
1720 * debug routine to display the memory sizes of all logical DIMMs and its
1723 static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
1725 int dimm, size0, size1;
1729 if (boot_cpu_data.x86 == 0xf) {
1730 /* K8 families < revF not supported yet */
1731 if (pvt->ext_model < K8_REV_F)
1737 debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
1738 ctrl, ctrl ? pvt->dbam1 : pvt->dbam0);
1740 dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
1741 dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0;
1743 edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
1745 /* Dump memory sizes for DIMM and its CSROWs */
1746 for (dimm = 0; dimm < 4; dimm++) {
1749 if (dcsb[dimm*2] & K8_DCSB_CS_ENABLE)
1750 size0 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam));
1753 if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE)
1754 size1 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam));
1756 edac_printk(KERN_DEBUG, EDAC_MC, " %d: %5dMB %d: %5dMB\n",
1757 dimm * 2, size0, dimm * 2 + 1, size1);
1762 * Very early hardware probe on pci_probe thread to determine if this module
1763 * supports the hardware.
1769 static int f10_probe_valid_hardware(struct amd64_pvt *pvt)
1774 * If we are on a DDR3 machine, we don't know yet if
1775 * we support that properly at this time
1777 if ((pvt->dchr0 & DDR3_MODE) ||
1778 (pvt->dchr1 & DDR3_MODE)) {
1780 amd64_printk(KERN_WARNING,
1781 "%s() This machine is running with DDR3 memory. "
1782 "This is not currently supported. "
1783 "DCHR0=0x%x DCHR1=0x%x\n",
1784 __func__, pvt->dchr0, pvt->dchr1);
1786 amd64_printk(KERN_WARNING,
1787 " Contact '%s' module MAINTAINER to help add"
1798 * There currently are 3 types type of MC devices for AMD Athlon/Opterons
1799 * (as per PCI DEVICE_IDs):
1801 * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI
1802 * DEVICE ID, even though there is differences between the different Revisions
1805 * Family F10h and F11h.
1808 static struct amd64_family_type amd64_family_types[] = {
1811 .addr_f1_ctl = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
1812 .misc_f3_ctl = PCI_DEVICE_ID_AMD_K8_NB_MISC,
1814 .early_channel_count = k8_early_channel_count,
1815 .get_error_address = k8_get_error_address,
1816 .read_dram_base_limit = k8_read_dram_base_limit,
1817 .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow,
1818 .dbam_to_cs = k8_dbam_to_chip_select,
1822 .ctl_name = "Family 10h",
1823 .addr_f1_ctl = PCI_DEVICE_ID_AMD_10H_NB_MAP,
1824 .misc_f3_ctl = PCI_DEVICE_ID_AMD_10H_NB_MISC,
1826 .probe_valid_hardware = f10_probe_valid_hardware,
1827 .early_channel_count = f10_early_channel_count,
1828 .get_error_address = f10_get_error_address,
1829 .read_dram_base_limit = f10_read_dram_base_limit,
1830 .read_dram_ctl_register = f10_read_dram_ctl_register,
1831 .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow,
1832 .dbam_to_cs = f10_dbam_to_chip_select,
1836 .ctl_name = "Family 11h",
1837 .addr_f1_ctl = PCI_DEVICE_ID_AMD_11H_NB_MAP,
1838 .misc_f3_ctl = PCI_DEVICE_ID_AMD_11H_NB_MISC,
1840 .probe_valid_hardware = f10_probe_valid_hardware,
1841 .early_channel_count = f10_early_channel_count,
1842 .get_error_address = f10_get_error_address,
1843 .read_dram_base_limit = f10_read_dram_base_limit,
1844 .read_dram_ctl_register = f10_read_dram_ctl_register,
1845 .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow,
1846 .dbam_to_cs = f10_dbam_to_chip_select,
1851 static struct pci_dev *pci_get_related_function(unsigned int vendor,
1852 unsigned int device,
1853 struct pci_dev *related)
1855 struct pci_dev *dev = NULL;
1857 dev = pci_get_device(vendor, device, dev);
1859 if ((dev->bus->number == related->bus->number) &&
1860 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
1862 dev = pci_get_device(vendor, device, dev);
1869 * syndrome mapping table for ECC ChipKill devices
1871 * The comment in each row is the token (nibble) number that is in error.
1872 * The least significant nibble of the syndrome is the mask for the bits
1873 * that are in error (need to be toggled) for the particular nibble.
1875 * Each row contains 16 entries.
1876 * The first entry (0th) is the channel number for that row of syndromes.
1877 * The remaining 15 entries are the syndromes for the respective Error
1880 * 1st index entry is 0x0001 mask, indicating that the rightmost bit is the
1882 * The 2nd index entry is 0x0010 that the second bit is damaged.
1883 * The 3rd index entry is 0x0011 indicating that the rightmost 2 bits
1885 * Thus so on until index 15, 0x1111, whose entry has the syndrome
1886 * indicating that all 4 bits are damaged.
1888 * A search is performed on this table looking for a given syndrome.
1890 * See the AMD documentation for ECC syndromes. This ECC table is valid
1891 * across all the versions of the AMD64 processors.
1893 * A fast lookup is to use the LAST four bits of the 16-bit syndrome as a
1894 * COLUMN index, then search all ROWS of that column, looking for a match
1895 * with the input syndrome. The ROW value will be the token number.
1897 * The 0'th entry on that row, can be returned as the CHANNEL (0 or 1) of this
1900 #define NUMBER_ECC_ROWS 36
1901 static const unsigned short ecc_chipkill_syndromes[NUMBER_ECC_ROWS][16] = {
1902 /* Channel 0 syndromes */
1903 {/*0*/ 0, 0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57,
1904 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df },
1905 {/*1*/ 0, 0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7,
1906 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f },
1907 {/*2*/ 0, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
1908 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f },
1909 {/*3*/ 0, 0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057,
1910 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df },
1911 {/*4*/ 0, 0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097,
1912 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f },
1913 {/*5*/ 0, 0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857,
1914 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf },
1915 {/*6*/ 0, 0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467,
1916 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f },
1917 {/*7*/ 0, 0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27,
1918 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff },
1919 {/*8*/ 0, 0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177,
1920 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f },
1921 {/*9*/ 0, 0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07,
1922 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f },
1923 {/*a*/ 0, 0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07,
1924 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f },
1925 {/*b*/ 0, 0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7,
1926 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f },
1927 {/*c*/ 0, 0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87,
1928 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x542c, 0x85fd, 0x164e, 0xf79f },
1929 {/*d*/ 0, 0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067,
1930 0x20e8, 0x40b9, 0x904a, 0x601b, 0x307c, 0x502d, 0x80de, 0xe08f },
1931 {/*e*/ 0, 0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77,
1932 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f },
1933 {/*f*/ 0, 0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77,
1934 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x956d, 0xa6ee, 0xb72f },
1936 /* Channel 1 syndromes */
1937 {/*10*/ 1, 0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187,
1938 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f },
1939 {/*11*/ 1, 0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627,
1940 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff },
1941 {/*12*/ 1, 0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97,
1942 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f },
1943 {/*13*/ 1, 0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0xce97,
1944 0x1aa8, 0xc7e9, 0x7c2a, 0xa1fb, 0x2ffc, 0xf2bd, 0x497e, 0x943f },
1945 {/*14*/ 1, 0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987,
1946 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f },
1947 {/*15*/ 1, 0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677,
1948 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f },
1949 {/*16*/ 1, 0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387,
1950 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f },
1951 {/*17*/ 1, 0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17,
1952 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf },
1953 {/*18*/ 1, 0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7,
1954 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f },
1955 {/*19*/ 1, 0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397,
1956 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f },
1957 {/*1a*/ 1, 0x9891, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617,
1958 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf },
1959 {/*1b*/ 1, 0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3f55, 0xb9c6, 0x7527,
1960 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff },
1961 {/*1c*/ 1, 0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7,
1962 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef },
1963 {/*1d*/ 1, 0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7,
1964 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def },
1965 {/*1e*/ 1, 0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67,
1966 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f },
1967 {/*1f*/ 1, 0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377,
1968 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f },
1970 /* ECC bits are also in the set of tokens and they too can go bad
1971 * first 2 cover channel 0, while the second 2 cover channel 1
1973 {/*20*/ 0, 0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807,
1974 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f },
1975 {/*21*/ 0, 0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07,
1976 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0x640c, 0xb50d, 0x760e, 0x370f },
1977 {/*22*/ 1, 0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97,
1978 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f },
1979 {/*23*/ 1, 0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757,
1980 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df }
1984 * Given the syndrome argument, scan each of the channel tables for a syndrome
1985 * match. Depending on which table it is found, return the channel number.
1987 static int get_channel_from_ecc_syndrome(unsigned short syndrome)
1992 /* Determine column to scan */
1993 column = syndrome & 0xF;
1995 /* Scan all rows, looking for syndrome, or end of table */
1996 for (row = 0; row < NUMBER_ECC_ROWS; row++) {
1997 if (ecc_chipkill_syndromes[row][column] == syndrome)
1998 return ecc_chipkill_syndromes[row][0];
2001 debugf0("syndrome(%x) not found\n", syndrome);
2006 * Check for valid error in the NB Status High register. If so, proceed to read
2007 * NB Status Low, NB Address Low and NB Address High registers and store data
2008 * into error structure.
2011 * - 1: if hardware regs contains valid error info
2012 * - 0: if no valid error is indicated
2014 static int amd64_get_error_info_regs(struct mem_ctl_info *mci,
2015 struct err_regs *regs)
2017 struct amd64_pvt *pvt;
2018 struct pci_dev *misc_f3_ctl;
2020 pvt = mci->pvt_info;
2021 misc_f3_ctl = pvt->misc_f3_ctl;
2023 if (amd64_read_pci_cfg(misc_f3_ctl, K8_NBSH, ®s->nbsh))
2026 if (!(regs->nbsh & K8_NBSH_VALID_BIT))
2029 /* valid error, read remaining error information registers */
2030 if (amd64_read_pci_cfg(misc_f3_ctl, K8_NBSL, ®s->nbsl) ||
2031 amd64_read_pci_cfg(misc_f3_ctl, K8_NBEAL, ®s->nbeal) ||
2032 amd64_read_pci_cfg(misc_f3_ctl, K8_NBEAH, ®s->nbeah) ||
2033 amd64_read_pci_cfg(misc_f3_ctl, K8_NBCFG, ®s->nbcfg))
2040 * This function is called to retrieve the error data from hardware and store it
2041 * in the info structure.
2044 * - 1: if a valid error is found
2045 * - 0: if no error is found
2047 static int amd64_get_error_info(struct mem_ctl_info *mci,
2048 struct err_regs *info)
2050 struct amd64_pvt *pvt;
2051 struct err_regs regs;
2053 pvt = mci->pvt_info;
2055 if (!amd64_get_error_info_regs(mci, info))
2059 * Here's the problem with the K8's EDAC reporting: There are four
2060 * registers which report pieces of error information. They are shared
2061 * between CEs and UEs. Furthermore, contrary to what is stated in the
2062 * BKDG, the overflow bit is never used! Every error always updates the
2063 * reporting registers.
2065 * Can you see the race condition? All four error reporting registers
2066 * must be read before a new error updates them! There is no way to read
2067 * all four registers atomically. The best than can be done is to detect
2068 * that a race has occured and then report the error without any kind of
2071 * What is still positive is that errors are still reported and thus
2072 * problems can still be detected - just not localized because the
2073 * syndrome and address are spread out across registers.
2075 * Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev.
2076 * UEs and CEs should have separate register sets with proper overflow
2077 * bits that are used! At very least the problem can be fixed by
2078 * honoring the ErrValid bit in 'nbsh' and not updating registers - just
2079 * set the overflow bit - unless the current error is CE and the new
2080 * error is UE which would be the only situation for overwriting the
2086 /* Use info from the second read - most current */
2087 if (unlikely(!amd64_get_error_info_regs(mci, info)))
2090 /* clear the error bits in hardware */
2091 pci_write_bits32(pvt->misc_f3_ctl, K8_NBSH, 0, K8_NBSH_VALID_BIT);
2093 /* Check for the possible race condition */
2094 if ((regs.nbsh != info->nbsh) ||
2095 (regs.nbsl != info->nbsl) ||
2096 (regs.nbeah != info->nbeah) ||
2097 (regs.nbeal != info->nbeal)) {
2098 amd64_mc_printk(mci, KERN_WARNING,
2099 "hardware STATUS read access race condition "
2107 * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
2108 * ADDRESS and process.
2110 static void amd64_handle_ce(struct mem_ctl_info *mci,
2111 struct err_regs *info)
2113 struct amd64_pvt *pvt = mci->pvt_info;
2116 /* Ensure that the Error Address is VALID */
2117 if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) {
2118 amd64_mc_printk(mci, KERN_ERR,
2119 "HW has no ERROR_ADDRESS available\n");
2120 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
2124 SystemAddress = extract_error_address(mci, info);
2126 amd64_mc_printk(mci, KERN_ERR,
2127 "CE ERROR_ADDRESS= 0x%llx\n", SystemAddress);
2129 pvt->ops->map_sysaddr_to_csrow(mci, info, SystemAddress);
2132 /* Handle any Un-correctable Errors (UEs) */
2133 static void amd64_handle_ue(struct mem_ctl_info *mci,
2134 struct err_regs *info)
2139 struct mem_ctl_info *log_mci, *src_mci = NULL;
2143 if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) {
2144 amd64_mc_printk(mci, KERN_CRIT,
2145 "HW has no ERROR_ADDRESS available\n");
2146 edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
2150 SystemAddress = extract_error_address(mci, info);
2153 * Find out which node the error address belongs to. This may be
2154 * different from the node that detected the error.
2156 src_mci = find_mc_by_sys_addr(mci, SystemAddress);
2158 amd64_mc_printk(mci, KERN_CRIT,
2159 "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n",
2160 (unsigned long)SystemAddress);
2161 edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
2167 csrow = sys_addr_to_csrow(log_mci, SystemAddress);
2169 amd64_mc_printk(mci, KERN_CRIT,
2170 "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n",
2171 (unsigned long)SystemAddress);
2172 edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
2174 error_address_to_page_and_offset(SystemAddress, &page, &offset);
2175 edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR);
2179 static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
2180 struct err_regs *info)
2182 u32 ec = ERROR_CODE(info->nbsl);
2183 u32 xec = EXT_ERROR_CODE(info->nbsl);
2184 int ecc_type = (info->nbsh >> 13) & 0x3;
2186 /* Bail early out if this was an 'observed' error */
2187 if (PP(ec) == K8_NBSL_PP_OBS)
2190 /* Do only ECC errors */
2191 if (xec && xec != F10_NBSL_EXT_ERR_ECC)
2195 amd64_handle_ce(mci, info);
2196 else if (ecc_type == 1)
2197 amd64_handle_ue(mci, info);
2200 * If main error is CE then overflow must be CE. If main error is UE
2201 * then overflow is unknown. We'll call the overflow a CE - if
2202 * panic_on_ue is set then we're already panic'ed and won't arrive
2203 * here. Else, then apparently someone doesn't think that UE's are
2206 if (info->nbsh & K8_NBSH_OVERFLOW)
2207 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR "Error Overflow");
2210 void amd64_decode_bus_error(int node_id, struct err_regs *regs)
2212 struct mem_ctl_info *mci = mci_lookup[node_id];
2214 __amd64_decode_bus_error(mci, regs);
2217 * Check the UE bit of the NB status high register, if set generate some
2218 * logs. If NOT a GART error, then process the event as a NO-INFO event.
2219 * If it was a GART error, skip that process.
2221 * FIXME: this should go somewhere else, if at all.
2223 if (regs->nbsh & K8_NBSH_UC_ERR && !report_gart_errors)
2224 edac_mc_handle_ue_no_info(mci, "UE bit is set");
2229 * The main polling 'check' function, called FROM the edac core to perform the
2230 * error checking and if an error is encountered, error processing.
2232 static void amd64_check(struct mem_ctl_info *mci)
2234 struct err_regs regs;
2236 if (amd64_get_error_info(mci, ®s)) {
2237 struct amd64_pvt *pvt = mci->pvt_info;
2238 amd_decode_nb_mce(pvt->mc_node_id, ®s, 1);
2244 * 1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer
2245 * 2) AMD Family index value
2248 * Upon return of 0, the following filled in:
2250 * struct pvt->addr_f1_ctl
2251 * struct pvt->misc_f3_ctl
2253 * Filled in with related device funcitions of 'dram_f2_ctl'
2254 * These devices are "reserved" via the pci_get_device()
2256 * Upon return of 1 (error status):
2260 static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, int mc_idx)
2262 const struct amd64_family_type *amd64_dev = &amd64_family_types[mc_idx];
2264 /* Reserve the ADDRESS MAP Device */
2265 pvt->addr_f1_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor,
2266 amd64_dev->addr_f1_ctl,
2269 if (!pvt->addr_f1_ctl) {
2270 amd64_printk(KERN_ERR, "error address map device not found: "
2271 "vendor %x device 0x%x (broken BIOS?)\n",
2272 PCI_VENDOR_ID_AMD, amd64_dev->addr_f1_ctl);
2276 /* Reserve the MISC Device */
2277 pvt->misc_f3_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor,
2278 amd64_dev->misc_f3_ctl,
2281 if (!pvt->misc_f3_ctl) {
2282 pci_dev_put(pvt->addr_f1_ctl);
2283 pvt->addr_f1_ctl = NULL;
2285 amd64_printk(KERN_ERR, "error miscellaneous device not found: "
2286 "vendor %x device 0x%x (broken BIOS?)\n",
2287 PCI_VENDOR_ID_AMD, amd64_dev->misc_f3_ctl);
2291 debugf1(" Addr Map device PCI Bus ID:\t%s\n",
2292 pci_name(pvt->addr_f1_ctl));
2293 debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n",
2294 pci_name(pvt->dram_f2_ctl));
2295 debugf1(" Misc device PCI Bus ID:\t%s\n",
2296 pci_name(pvt->misc_f3_ctl));
2301 static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt)
2303 pci_dev_put(pvt->addr_f1_ctl);
2304 pci_dev_put(pvt->misc_f3_ctl);
2308 * Retrieve the hardware registers of the memory controller (this includes the
2309 * 'Address Map' and 'Misc' device regs)
2311 static void amd64_read_mc_registers(struct amd64_pvt *pvt)
2317 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
2318 * those are Read-As-Zero
2320 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
2321 debugf0(" TOP_MEM: 0x%016llx\n", pvt->top_mem);
2323 /* check first whether TOP_MEM2 is enabled */
2324 rdmsrl(MSR_K8_SYSCFG, msr_val);
2325 if (msr_val & (1U << 21)) {
2326 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
2327 debugf0(" TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
2329 debugf0(" TOP_MEM2 disabled.\n");
2331 amd64_cpu_display_info(pvt);
2333 amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCAP, &pvt->nbcap);
2335 if (pvt->ops->read_dram_ctl_register)
2336 pvt->ops->read_dram_ctl_register(pvt);
2338 for (dram = 0; dram < DRAM_REG_COUNT; dram++) {
2340 * Call CPU specific READ function to get the DRAM Base and
2341 * Limit values from the DCT.
2343 pvt->ops->read_dram_base_limit(pvt, dram);
2346 * Only print out debug info on rows with both R and W Enabled.
2347 * Normal processing, compiler should optimize this whole 'if'
2348 * debug output block away.
2350 if (pvt->dram_rw_en[dram] != 0) {
2351 debugf1(" DRAM-BASE[%d]: 0x%016llx "
2352 "DRAM-LIMIT: 0x%016llx\n",
2354 pvt->dram_base[dram],
2355 pvt->dram_limit[dram]);
2357 debugf1(" IntlvEn=%s %s %s "
2358 "IntlvSel=%d DstNode=%d\n",
2359 pvt->dram_IntlvEn[dram] ?
2360 "Enabled" : "Disabled",
2361 (pvt->dram_rw_en[dram] & 0x2) ? "W" : "!W",
2362 (pvt->dram_rw_en[dram] & 0x1) ? "R" : "!R",
2363 pvt->dram_IntlvSel[dram],
2364 pvt->dram_DstNode[dram]);
2368 amd64_read_dct_base_mask(pvt);
2370 amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DHAR, &pvt->dhar);
2371 amd64_read_dbam_reg(pvt);
2373 amd64_read_pci_cfg(pvt->misc_f3_ctl,
2374 F10_ONLINE_SPARE, &pvt->online_spare);
2376 amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
2377 amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0);
2379 if (!dct_ganging_enabled(pvt)) {
2380 amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1);
2381 amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_1, &pvt->dchr1);
2383 amd64_dump_misc_regs(pvt);
2387 * NOTE: CPU Revision Dependent code
2390 * @csrow_nr ChipSelect Row Number (0..pvt->cs_count-1)
2391 * k8 private pointer to -->
2392 * DRAM Bank Address mapping register
2394 * DCL register where dual_channel_active is
2396 * The DBAM register consists of 4 sets of 4 bits each definitions:
2399 * 0-3 CSROWs 0 and 1
2400 * 4-7 CSROWs 2 and 3
2401 * 8-11 CSROWs 4 and 5
2402 * 12-15 CSROWs 6 and 7
2404 * Values range from: 0 to 15
2405 * The meaning of the values depends on CPU revision and dual-channel state,
2406 * see relevant BKDG more info.
2408 * The memory controller provides for total of only 8 CSROWs in its current
2409 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
2410 * single channel or two (2) DIMMs in dual channel mode.
2412 * The following code logic collapses the various tables for CSROW based on CPU
2416 * The number of PAGE_SIZE pages on the specified CSROW number it
2420 static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt)
2422 u32 cs_mode, nr_pages;
2425 * The math on this doesn't look right on the surface because x/2*4 can
2426 * be simplified to x*2 but this expression makes use of the fact that
2427 * it is integral math where 1/2=0. This intermediate value becomes the
2428 * number of bits to shift the DBAM register to extract the proper CSROW
2431 cs_mode = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF;
2433 nr_pages = pvt->ops->dbam_to_cs(pvt, cs_mode) << (20 - PAGE_SHIFT);
2436 * If dual channel then double the memory size of single channel.
2437 * Channel count is 1 or 2
2439 nr_pages <<= (pvt->channel_count - 1);
2441 debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
2442 debugf0(" nr_pages= %u channel-count = %d\n",
2443 nr_pages, pvt->channel_count);
2449 * Initialize the array of csrow attribute instances, based on the values
2450 * from pci config hardware registers.
2452 static int amd64_init_csrows(struct mem_ctl_info *mci)
2454 struct csrow_info *csrow;
2455 struct amd64_pvt *pvt;
2456 u64 input_addr_min, input_addr_max, sys_addr;
2459 pvt = mci->pvt_info;
2461 amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &pvt->nbcfg);
2463 debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg,
2464 (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
2465 (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"
2468 for (i = 0; i < pvt->cs_count; i++) {
2469 csrow = &mci->csrows[i];
2471 if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) {
2472 debugf1("----CSROW %d EMPTY for node %d\n", i,
2477 debugf1("----CSROW %d VALID for MC node %d\n",
2478 i, pvt->mc_node_id);
2481 csrow->nr_pages = amd64_csrow_nr_pages(i, pvt);
2482 find_csrow_limits(mci, i, &input_addr_min, &input_addr_max);
2483 sys_addr = input_addr_to_sys_addr(mci, input_addr_min);
2484 csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT);
2485 sys_addr = input_addr_to_sys_addr(mci, input_addr_max);
2486 csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT);
2487 csrow->page_mask = ~mask_from_dct_mask(pvt, i);
2488 /* 8 bytes of resolution */
2490 csrow->mtype = amd64_determine_memory_type(pvt);
2492 debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i);
2493 debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n",
2494 (unsigned long)input_addr_min,
2495 (unsigned long)input_addr_max);
2496 debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n",
2497 (unsigned long)sys_addr, csrow->page_mask);
2498 debugf1(" nr_pages: %u first_page: 0x%lx "
2499 "last_page: 0x%lx\n",
2500 (unsigned)csrow->nr_pages,
2501 csrow->first_page, csrow->last_page);
2504 * determine whether CHIPKILL or JUST ECC or NO ECC is operating
2506 if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE)
2508 (pvt->nbcfg & K8_NBCFG_CHIPKILL) ?
2509 EDAC_S4ECD4ED : EDAC_SECDED;
2511 csrow->edac_mode = EDAC_NONE;
2517 /* get all cores on this DCT */
2518 static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid)
2522 for_each_online_cpu(cpu)
2523 if (amd_get_nb_id(cpu) == nid)
2524 cpumask_set_cpu(cpu, mask);
2527 /* check MCG_CTL on all the cpus on this node */
2528 static bool amd64_nb_mce_bank_enabled_on_node(int nid)
2532 int cpu, nbe, idx = 0;
2535 if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
2536 amd64_printk(KERN_WARNING, "%s: error allocating mask\n",
2541 get_cpus_on_this_dct_cpumask(mask, nid);
2543 msrs = kzalloc(sizeof(struct msr) * cpumask_weight(mask), GFP_KERNEL);
2545 amd64_printk(KERN_WARNING, "%s: error allocating msrs\n",
2547 free_cpumask_var(mask);
2551 rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);
2553 for_each_cpu(cpu, mask) {
2554 nbe = msrs[idx].l & K8_MSR_MCGCTL_NBE;
2556 debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
2558 (nbe ? "enabled" : "disabled"));
2569 free_cpumask_var(mask);
2573 static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
2575 cpumask_var_t cmask;
2576 struct msr *msrs = NULL;
2579 if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
2580 amd64_printk(KERN_WARNING, "%s: error allocating mask\n",
2585 get_cpus_on_this_dct_cpumask(cmask, pvt->mc_node_id);
2587 msrs = kzalloc(sizeof(struct msr) * cpumask_weight(cmask), GFP_KERNEL);
2589 amd64_printk(KERN_WARNING, "%s: error allocating msrs\n",
2594 rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
2596 for_each_cpu(cpu, cmask) {
2599 if (msrs[idx].l & K8_MSR_MCGCTL_NBE)
2600 pvt->flags.ecc_report = 1;
2602 msrs[idx].l |= K8_MSR_MCGCTL_NBE;
2605 * Turn off ECC reporting only when it was off before
2607 if (!pvt->flags.ecc_report)
2608 msrs[idx].l &= ~K8_MSR_MCGCTL_NBE;
2612 wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
2615 free_cpumask_var(cmask);
2621 * Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we"
2624 static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
2626 struct amd64_pvt *pvt = mci->pvt_info;
2627 u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
2629 if (!ecc_enable_override)
2632 amd64_printk(KERN_WARNING,
2633 "'ecc_enable_override' parameter is active, "
2634 "Enabling AMD ECC hardware now: CAUTION\n");
2636 amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value);
2638 /* turn on UECCn and CECCEn bits */
2639 pvt->old_nbctl = value & mask;
2640 pvt->nbctl_mcgctl_saved = 1;
2643 pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
2645 if (amd64_toggle_ecc_err_reporting(pvt, ON))
2646 amd64_printk(KERN_WARNING, "Error enabling ECC reporting over "
2649 amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value);
2651 debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
2652 (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
2653 (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
2655 if (!(value & K8_NBCFG_ECC_ENABLE)) {
2656 amd64_printk(KERN_WARNING,
2657 "This node reports that DRAM ECC is "
2658 "currently Disabled; ENABLING now\n");
2660 /* Attempt to turn on DRAM ECC Enable */
2661 value |= K8_NBCFG_ECC_ENABLE;
2662 pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value);
2664 amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value);
2666 if (!(value & K8_NBCFG_ECC_ENABLE)) {
2667 amd64_printk(KERN_WARNING,
2668 "Hardware rejects Enabling DRAM ECC checking\n"
2669 "Check memory DIMM configuration\n");
2671 amd64_printk(KERN_DEBUG,
2672 "Hardware accepted DRAM ECC Enable\n");
2675 debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
2676 (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
2677 (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
2679 pvt->ctl_error_info.nbcfg = value;
2682 static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
2684 u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
2686 if (!pvt->nbctl_mcgctl_saved)
2689 amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value);
2691 value |= pvt->old_nbctl;
2693 /* restore the NB Enable MCGCTL bit */
2694 pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
2696 if (amd64_toggle_ecc_err_reporting(pvt, OFF))
2697 amd64_printk(KERN_WARNING, "Error restoring ECC reporting over "
2702 * EDAC requires that the BIOS have ECC enabled before taking over the
2703 * processing of ECC errors. This is because the BIOS can properly initialize
2704 * the memory system completely. A command line option allows to force-enable
2705 * hardware ECC later in amd64_enable_ecc_error_reporting().
2707 static const char *ecc_warning =
2708 "WARNING: ECC is disabled by BIOS. Module will NOT be loaded.\n"
2709 " Either Enable ECC in the BIOS, or set 'ecc_enable_override'.\n"
2710 " Also, use of the override can cause unknown side effects.\n";
2712 static int amd64_check_ecc_enabled(struct amd64_pvt *pvt)
2716 bool nb_mce_en = false;
2718 amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value);
2720 ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE);
2722 amd64_printk(KERN_WARNING, "This node reports that Memory ECC "
2723 "is currently disabled, set F3x%x[22] (%s).\n",
2724 K8_NBCFG, pci_name(pvt->misc_f3_ctl));
2726 amd64_printk(KERN_INFO, "ECC is enabled by BIOS.\n");
2728 nb_mce_en = amd64_nb_mce_bank_enabled_on_node(pvt->mc_node_id);
2730 amd64_printk(KERN_WARNING, "NB MCE bank disabled, set MSR "
2731 "0x%08x[4] on node %d to enable.\n",
2732 MSR_IA32_MCG_CTL, pvt->mc_node_id);
2734 if (!ecc_enabled || !nb_mce_en) {
2735 if (!ecc_enable_override) {
2736 amd64_printk(KERN_WARNING, "%s", ecc_warning);
2740 /* CLEAR the override, since BIOS controlled it */
2741 ecc_enable_override = 0;
2746 struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) +
2747 ARRAY_SIZE(amd64_inj_attrs) +
2750 struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } };
2752 static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
2754 unsigned int i = 0, j = 0;
2756 for (; i < ARRAY_SIZE(amd64_dbg_attrs); i++)
2757 sysfs_attrs[i] = amd64_dbg_attrs[i];
2759 for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++)
2760 sysfs_attrs[i] = amd64_inj_attrs[j];
2762 sysfs_attrs[i] = terminator;
2764 mci->mc_driver_sysfs_attributes = sysfs_attrs;
2767 static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci)
2769 struct amd64_pvt *pvt = mci->pvt_info;
2771 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
2772 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2774 if (pvt->nbcap & K8_NBCAP_SECDED)
2775 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
2777 if (pvt->nbcap & K8_NBCAP_CHIPKILL)
2778 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
2780 mci->edac_cap = amd64_determine_edac_cap(pvt);
2781 mci->mod_name = EDAC_MOD_STR;
2782 mci->mod_ver = EDAC_AMD64_VERSION;
2783 mci->ctl_name = get_amd_family_name(pvt->mc_type_index);
2784 mci->dev_name = pci_name(pvt->dram_f2_ctl);
2785 mci->ctl_page_to_phys = NULL;
2787 /* IMPORTANT: Set the polling 'check' function in this module */
2788 mci->edac_check = amd64_check;
2790 /* memory scrubber interface */
2791 mci->set_sdram_scrub_rate = amd64_set_scrub_rate;
2792 mci->get_sdram_scrub_rate = amd64_get_scrub_rate;
2796 * Init stuff for this DRAM Controller device.
2798 * Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration
2799 * Space feature MUST be enabled on ALL Processors prior to actually reading
2800 * from the ECS registers. Since the loading of the module can occur on any
2801 * 'core', and cores don't 'see' all the other processors ECS data when the
2802 * others are NOT enabled. Our solution is to first enable ECS access in this
2803 * routine on all processors, gather some data in a amd64_pvt structure and
2804 * later come back in a finish-setup function to perform that final
2805 * initialization. See also amd64_init_2nd_stage() for that.
2807 static int amd64_probe_one_instance(struct pci_dev *dram_f2_ctl,
2810 struct amd64_pvt *pvt = NULL;
2814 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
2818 pvt->mc_node_id = get_node_id(dram_f2_ctl);
2820 pvt->dram_f2_ctl = dram_f2_ctl;
2821 pvt->ext_model = boot_cpu_data.x86_model >> 4;
2822 pvt->mc_type_index = mc_type_index;
2823 pvt->ops = family_ops(mc_type_index);
2826 * We have the dram_f2_ctl device as an argument, now go reserve its
2827 * sibling devices from the PCI system.
2830 err = amd64_reserve_mc_sibling_devices(pvt, mc_type_index);
2835 err = amd64_check_ecc_enabled(pvt);
2840 * Key operation here: setup of HW prior to performing ops on it. Some
2841 * setup is required to access ECS data. After this is performed, the
2842 * 'teardown' function must be called upon error and normal exit paths.
2844 if (boot_cpu_data.x86 >= 0x10)
2848 * Save the pointer to the private data for use in 2nd initialization
2851 pvt_lookup[pvt->mc_node_id] = pvt;
2856 amd64_free_mc_sibling_devices(pvt);
2866 * This is the finishing stage of the init code. Needs to be performed after all
2867 * MCs' hardware have been prepped for accessing extended config space.
2869 static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
2871 int node_id = pvt->mc_node_id;
2872 struct mem_ctl_info *mci;
2875 amd64_read_mc_registers(pvt);
2878 if (pvt->ops->probe_valid_hardware) {
2879 err = pvt->ops->probe_valid_hardware(pvt);
2885 * We need to determine how many memory channels there are. Then use
2886 * that information for calculating the size of the dynamic instance
2887 * tables in the 'mci' structure
2889 pvt->channel_count = pvt->ops->early_channel_count(pvt);
2890 if (pvt->channel_count < 0)
2894 mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, node_id);
2898 mci->pvt_info = pvt;
2900 mci->dev = &pvt->dram_f2_ctl->dev;
2901 amd64_setup_mci_misc_attributes(mci);
2903 if (amd64_init_csrows(mci))
2904 mci->edac_cap = EDAC_FLAG_NONE;
2906 amd64_enable_ecc_error_reporting(mci);
2907 amd64_set_mc_sysfs_attributes(mci);
2910 if (edac_mc_add_mc(mci)) {
2911 debugf1("failed edac_mc_add_mc()\n");
2915 mci_lookup[node_id] = mci;
2916 pvt_lookup[node_id] = NULL;
2918 /* register stuff with EDAC MCE */
2919 if (report_gart_errors)
2920 amd_report_gart_errors(true);
2922 amd_register_ecc_decoder(amd64_decode_bus_error);
2930 debugf0("failure to init 2nd stage: ret=%d\n", ret);
2932 amd64_restore_ecc_error_reporting(pvt);
2934 if (boot_cpu_data.x86 > 0xf)
2935 amd64_teardown(pvt);
2937 amd64_free_mc_sibling_devices(pvt);
2939 kfree(pvt_lookup[pvt->mc_node_id]);
2940 pvt_lookup[node_id] = NULL;
2946 static int __devinit amd64_init_one_instance(struct pci_dev *pdev,
2947 const struct pci_device_id *mc_type)
2951 debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev),
2952 get_amd_family_name(mc_type->driver_data));
2954 ret = pci_enable_device(pdev);
2958 ret = amd64_probe_one_instance(pdev, mc_type->driver_data);
2961 debugf0("ret=%d\n", ret);
2966 static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
2968 struct mem_ctl_info *mci;
2969 struct amd64_pvt *pvt;
2971 /* Remove from EDAC CORE tracking list */
2972 mci = edac_mc_del_mc(&pdev->dev);
2976 pvt = mci->pvt_info;
2978 amd64_restore_ecc_error_reporting(pvt);
2980 if (boot_cpu_data.x86 > 0xf)
2981 amd64_teardown(pvt);
2983 amd64_free_mc_sibling_devices(pvt);
2986 mci->pvt_info = NULL;
2988 mci_lookup[pvt->mc_node_id] = NULL;
2990 /* unregister from EDAC MCE */
2991 amd_report_gart_errors(false);
2992 amd_unregister_ecc_decoder(amd64_decode_bus_error);
2994 /* Free the EDAC CORE resources */
2999 * This table is part of the interface for loading drivers for PCI devices. The
3000 * PCI core identifies what devices are on a system during boot, and then
3001 * inquiry this table to see if this driver is for a given device found.
3003 static const struct pci_device_id amd64_pci_table[] __devinitdata = {
3005 .vendor = PCI_VENDOR_ID_AMD,
3006 .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
3007 .subvendor = PCI_ANY_ID,
3008 .subdevice = PCI_ANY_ID,
3011 .driver_data = K8_CPUS
3014 .vendor = PCI_VENDOR_ID_AMD,
3015 .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM,
3016 .subvendor = PCI_ANY_ID,
3017 .subdevice = PCI_ANY_ID,
3020 .driver_data = F10_CPUS
3023 .vendor = PCI_VENDOR_ID_AMD,
3024 .device = PCI_DEVICE_ID_AMD_11H_NB_DRAM,
3025 .subvendor = PCI_ANY_ID,
3026 .subdevice = PCI_ANY_ID,
3029 .driver_data = F11_CPUS
3033 MODULE_DEVICE_TABLE(pci, amd64_pci_table);
3035 static struct pci_driver amd64_pci_driver = {
3036 .name = EDAC_MOD_STR,
3037 .probe = amd64_init_one_instance,
3038 .remove = __devexit_p(amd64_remove_one_instance),
3039 .id_table = amd64_pci_table,
3042 static void amd64_setup_pci_device(void)
3044 struct mem_ctl_info *mci;
3045 struct amd64_pvt *pvt;
3050 mci = mci_lookup[0];
3053 pvt = mci->pvt_info;
3055 edac_pci_create_generic_ctl(&pvt->dram_f2_ctl->dev,
3058 if (!amd64_ctl_pci) {
3059 pr_warning("%s(): Unable to create PCI control\n",
3062 pr_warning("%s(): PCI error report via EDAC not set\n",
3068 static int __init amd64_edac_init(void)
3070 int nb, err = -ENODEV;
3072 edac_printk(KERN_INFO, EDAC_MOD_STR, EDAC_AMD64_VERSION "\n");
3076 if (cache_k8_northbridges() < 0)
3079 err = pci_register_driver(&amd64_pci_driver);
3084 * At this point, the array 'pvt_lookup[]' contains pointers to alloc'd
3085 * amd64_pvt structs. These will be used in the 2nd stage init function
3086 * to finish initialization of the MC instances.
3088 for (nb = 0; nb < num_k8_northbridges; nb++) {
3089 if (!pvt_lookup[nb])
3092 err = amd64_init_2nd_stage(pvt_lookup[nb]);
3097 amd64_setup_pci_device();
3102 debugf0("2nd stage failed\n");
3103 pci_unregister_driver(&amd64_pci_driver);
3108 static void __exit amd64_edac_exit(void)
3111 edac_pci_release_generic_ctl(amd64_ctl_pci);
3113 pci_unregister_driver(&amd64_pci_driver);
3116 module_init(amd64_edac_init);
3117 module_exit(amd64_edac_exit);
3119 MODULE_LICENSE("GPL");
3120 MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
3121 "Dave Peterson, Thayne Harbaugh");
3122 MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
3123 EDAC_AMD64_VERSION);
3125 module_param(edac_op_state, int, 0444);
3126 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");