SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/dma/iop-adma.c

   1 /*
   2  * offload engine driver for the Intel Xscale series of i/o processors
   3  * Copyright © 2006, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  */
  19
  20 /*
  21  * This driver supports the asynchrounous DMA copy and RAID engines available
  22  * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/async_tx.h>
  28 #include <linux/delay.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/memory.h>
  34 #include <linux/ioport.h>
  35
  36 #include <asm/arch/adma.h>
  37
  38 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
  39 #define to_iop_adma_device(dev) \
  40         container_of(dev, struct iop_adma_device, common)
  41 #define tx_to_iop_adma_slot(tx) \
  42         container_of(tx, struct iop_adma_desc_slot, async_tx)
  43
  44 /**
  45  * iop_adma_free_slots - flags descriptor slots for reuse
  46  * @slot: Slot to free
  47  * Caller must hold &iop_chan->lock while calling this function
  48  */
  49 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
  50 {
  51         int stride = slot->slots_per_op;
  52
  53         while (stride--) {
  54                 slot->slots_per_op = 0;
  55                 slot = list_entry(slot->slot_node.next,
  56                                 struct iop_adma_desc_slot,
  57                                 slot_node);
  58         }
  59 }
  60
  61 static dma_cookie_t
  62 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
  63         struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
  64 {
  65         BUG_ON(desc->async_tx.cookie < 0);
  66         if (desc->async_tx.cookie > 0) {
  67                 cookie = desc->async_tx.cookie;
  68                 desc->async_tx.cookie = 0;
  69
  70                 /* call the callback (must not sleep or submit new
  71                  * operations to this channel)
  72                  */
  73                 if (desc->async_tx.callback)
  74                         desc->async_tx.callback(
  75                                 desc->async_tx.callback_param);
  76
  77                 /* unmap dma addresses
  78                  * (unmap_single vs unmap_page?)
  79                  */
  80                 if (desc->group_head && desc->unmap_len) {
  81                         struct iop_adma_desc_slot *unmap = desc->group_head;
  82                         struct device *dev =
  83                                 &iop_chan->device->pdev->dev;
  84                         u32 len = unmap->unmap_len;
  85                         u32 src_cnt = unmap->unmap_src_cnt;
  86                         dma_addr_t addr = iop_desc_get_dest_addr(unmap,
  87                                 iop_chan);
  88
  89                         dma_unmap_page(dev, addr, len, DMA_FROM_DEVICE);
  90                         while (src_cnt--) {
  91                                 addr = iop_desc_get_src_addr(unmap,
  92                                                         iop_chan,
  93                                                         src_cnt);
  94                                 dma_unmap_page(dev, addr, len,
  95                                         DMA_TO_DEVICE);
  96                         }
  97                         desc->group_head = NULL;
  98                 }
  99         }
 100
 101         /* run dependent operations */
 102         async_tx_run_dependencies(&desc->async_tx);
 103
 104         return cookie;
 105 }
 106
 107 static int
 108 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
 109         struct iop_adma_chan *iop_chan)
 110 {
 111         /* the client is allowed to attach dependent operations
 112          * until 'ack' is set
 113          */
 114         if (!desc->async_tx.ack)
 115                 return 0;
 116
 117         /* leave the last descriptor in the chain
 118          * so we can append to it
 119          */
 120         if (desc->chain_node.next == &iop_chan->chain)
 121                 return 1;
 122
 123         dev_dbg(iop_chan->device->common.dev,
 124                 "\tfree slot: %d slots_per_op: %d\n",
 125                 desc->idx, desc->slots_per_op);
 126
 127         list_del(&desc->chain_node);
 128         iop_adma_free_slots(desc);
 129
 130         return 0;
 131 }
 132
 133 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
 134 {
 135         struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
 136         dma_cookie_t cookie = 0;
 137         u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
 138         int busy = iop_chan_is_busy(iop_chan);
 139         int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
 140
 141         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
 142         /* free completed slots from the chain starting with
 143          * the oldest descriptor
 144          */
 145         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
 146                                         chain_node) {
 147                 pr_debug("\tcookie: %d slot: %d busy: %d "
 148                         "this_desc: %#x next_desc: %#x ack: %d\n",
 149                         iter->async_tx.cookie, iter->idx, busy,
 150                         iter->async_tx.phys, iop_desc_get_next_desc(iter),
 151                         iter->async_tx.ack);
 152                 prefetch(_iter);
 153                 prefetch(&_iter->async_tx);
 154
 155                 /* do not advance past the current descriptor loaded into the
 156                  * hardware channel, subsequent descriptors are either in
 157                  * process or have not been submitted
 158                  */
 159                 if (seen_current)
 160                         break;
 161
 162                 /* stop the search if we reach the current descriptor and the
 163                  * channel is busy, or if it appears that the current descriptor
 164                  * needs to be re-read (i.e. has been appended to)
 165                  */
 166                 if (iter->async_tx.phys == current_desc) {
 167                         BUG_ON(seen_current++);
 168                         if (busy || iop_desc_get_next_desc(iter))
 169                                 break;
 170                 }
 171
 172                 /* detect the start of a group transaction */
 173                 if (!slot_cnt && !slots_per_op) {
 174                         slot_cnt = iter->slot_cnt;
 175                         slots_per_op = iter->slots_per_op;
 176                         if (slot_cnt <= slots_per_op) {
 177                                 slot_cnt = 0;
 178                                 slots_per_op = 0;
 179                         }
 180                 }
 181
 182                 if (slot_cnt) {
 183                         pr_debug("\tgroup++\n");
 184                         if (!grp_start)
 185                                 grp_start = iter;
 186                         slot_cnt -= slots_per_op;
 187                 }
 188
 189                 /* all the members of a group are complete */
 190                 if (slots_per_op != 0 && slot_cnt == 0) {
 191                         struct iop_adma_desc_slot *grp_iter, *_grp_iter;
 192                         int end_of_chain = 0;
 193                         pr_debug("\tgroup end\n");
 194
 195                         /* collect the total results */
 196                         if (grp_start->xor_check_result) {
 197                                 u32 zero_sum_result = 0;
 198                                 slot_cnt = grp_start->slot_cnt;
 199                                 grp_iter = grp_start;
 200
 201                                 list_for_each_entry_from(grp_iter,
 202                                         &iop_chan->chain, chain_node) {
 203                                         zero_sum_result |=
 204                                             iop_desc_get_zero_result(grp_iter);
 205                                             pr_debug("\titer%d result: %d\n",
 206                                             grp_iter->idx, zero_sum_result);
 207                                         slot_cnt -= slots_per_op;
 208                                         if (slot_cnt == 0)
 209                                                 break;
 210                                 }
 211                                 pr_debug("\tgrp_start->xor_check_result: %p\n",
 212                                         grp_start->xor_check_result);
 213                                 *grp_start->xor_check_result = zero_sum_result;
 214                         }
 215
 216                         /* clean up the group */
 217                         slot_cnt = grp_start->slot_cnt;
 218                         grp_iter = grp_start;
 219                         list_for_each_entry_safe_from(grp_iter, _grp_iter,
 220                                 &iop_chan->chain, chain_node) {
 221                                 cookie = iop_adma_run_tx_complete_actions(
 222                                         grp_iter, iop_chan, cookie);
 223
 224                                 slot_cnt -= slots_per_op;
 225                                 end_of_chain = iop_adma_clean_slot(grp_iter,
 226                                         iop_chan);
 227
 228                                 if (slot_cnt == 0 || end_of_chain)
 229                                         break;
 230                         }
 231
 232                         /* the group should be complete at this point */
 233                         BUG_ON(slot_cnt);
 234
 235                         slots_per_op = 0;
 236                         grp_start = NULL;
 237                         if (end_of_chain)
 238                                 break;
 239                         else
 240                                 continue;
 241                 } else if (slots_per_op) /* wait for group completion */
 242                         continue;
 243
 244                 /* write back zero sum results (single descriptor case) */
 245                 if (iter->xor_check_result && iter->async_tx.cookie)
 246                         *iter->xor_check_result =
 247                                 iop_desc_get_zero_result(iter);
 248
 249                 cookie = iop_adma_run_tx_complete_actions(
 250                                         iter, iop_chan, cookie);
 251
 252                 if (iop_adma_clean_slot(iter, iop_chan))
 253                         break;
 254         }
 255
 256         BUG_ON(!seen_current);
 257
 258         if (cookie > 0) {
 259                 iop_chan->completed_cookie = cookie;
 260                 pr_debug("\tcompleted cookie %d\n", cookie);
 261         }
 262 }
 263
 264 static void
 265 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
 266 {
 267         spin_lock_bh(&iop_chan->lock);
 268         __iop_adma_slot_cleanup(iop_chan);
 269         spin_unlock_bh(&iop_chan->lock);
 270 }
 271
 272 static void iop_adma_tasklet(unsigned long data)
 273 {
 274         struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
 275
 276         spin_lock(&iop_chan->lock);
 277         __iop_adma_slot_cleanup(iop_chan);
 278         spin_unlock(&iop_chan->lock);
 279 }
 280
 281 static struct iop_adma_desc_slot *
 282 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
 283                         int slots_per_op)
 284 {
 285         struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
 286         LIST_HEAD(chain);
 287         int slots_found, retry = 0;
 288
 289         /* start search from the last allocated descrtiptor
 290          * if a contiguous allocation can not be found start searching
 291          * from the beginning of the list
 292          */
 293 retry:
 294         slots_found = 0;
 295         if (retry == 0)
 296                 iter = iop_chan->last_used;
 297         else
 298                 iter = list_entry(&iop_chan->all_slots,
 299                         struct iop_adma_desc_slot,
 300                         slot_node);
 301
 302         list_for_each_entry_safe_continue(
 303                 iter, _iter, &iop_chan->all_slots, slot_node) {
 304                 prefetch(_iter);
 305                 prefetch(&_iter->async_tx);
 306                 if (iter->slots_per_op) {
 307                         /* give up after finding the first busy slot
 308                          * on the second pass through the list
 309                          */
 310                         if (retry)
 311                                 break;
 312
 313                         slots_found = 0;
 314                         continue;
 315                 }
 316
 317                 /* start the allocation if the slot is correctly aligned */
 318                 if (!slots_found++) {
 319                         if (iop_desc_is_aligned(iter, slots_per_op))
 320                                 alloc_start = iter;
 321                         else {
 322                                 slots_found = 0;
 323                                 continue;
 324                         }
 325                 }
 326
 327                 if (slots_found == num_slots) {
 328                         struct iop_adma_desc_slot *alloc_tail = NULL;
 329                         struct iop_adma_desc_slot *last_used = NULL;
 330                         iter = alloc_start;
 331                         while (num_slots) {
 332                                 int i;
 333                                 dev_dbg(iop_chan->device->common.dev,
 334                                         "allocated slot: %d "
 335                                         "(desc %p phys: %#x) slots_per_op %d\n",
 336                                         iter->idx, iter->hw_desc,
 337                                         iter->async_tx.phys, slots_per_op);
 338
 339                                 /* pre-ack all but the last descriptor */
 340                                 if (num_slots != slots_per_op)
 341                                         iter->async_tx.ack = 1;
 342                                 else
 343                                         iter->async_tx.ack = 0;
 344
 345                                 list_add_tail(&iter->chain_node, &chain);
 346                                 alloc_tail = iter;
 347                                 iter->async_tx.cookie = 0;
 348                                 iter->slot_cnt = num_slots;
 349                                 iter->xor_check_result = NULL;
 350                                 for (i = 0; i < slots_per_op; i++) {
 351                                         iter->slots_per_op = slots_per_op - i;
 352                                         last_used = iter;
 353                                         iter = list_entry(iter->slot_node.next,
 354                                                 struct iop_adma_desc_slot,
 355                                                 slot_node);
 356                                 }
 357                                 num_slots -= slots_per_op;
 358                         }
 359                         alloc_tail->group_head = alloc_start;
 360                         alloc_tail->async_tx.cookie = -EBUSY;
 361                         list_splice(&chain, &alloc_tail->async_tx.tx_list);
 362                         iop_chan->last_used = last_used;
 363                         iop_desc_clear_next_desc(alloc_start);
 364                         iop_desc_clear_next_desc(alloc_tail);
 365                         return alloc_tail;
 366                 }
 367         }
 368         if (!retry++)
 369                 goto retry;
 370
 371         /* try to free some slots if the allocation fails */
 372         tasklet_schedule(&iop_chan->irq_tasklet);
 373
 374         return NULL;
 375 }
 376
 377 static dma_cookie_t
 378 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
 379         struct iop_adma_desc_slot *desc)
 380 {
 381         dma_cookie_t cookie = iop_chan->common.cookie;
 382         cookie++;
 383         if (cookie < 0)
 384                 cookie = 1;
 385         iop_chan->common.cookie = desc->async_tx.cookie = cookie;
 386         return cookie;
 387 }
 388
 389 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
 390 {
 391         dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
 392                 iop_chan->pending);
 393
 394         if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
 395                 iop_chan->pending = 0;
 396                 iop_chan_append(iop_chan);
 397         }
 398 }
 399
 400 static dma_cookie_t
 401 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
 402 {
 403         struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
 404         struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
 405         struct iop_adma_desc_slot *grp_start, *old_chain_tail;
 406         int slot_cnt;
 407         int slots_per_op;
 408         dma_cookie_t cookie;
 409
 410         grp_start = sw_desc->group_head;
 411         slot_cnt = grp_start->slot_cnt;
 412         slots_per_op = grp_start->slots_per_op;
 413
 414         spin_lock_bh(&iop_chan->lock);
 415         cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
 416
 417         old_chain_tail = list_entry(iop_chan->chain.prev,
 418                 struct iop_adma_desc_slot, chain_node);
 419         list_splice_init(&sw_desc->async_tx.tx_list,
 420                          &old_chain_tail->chain_node);
 421
 422         /* fix up the hardware chain */
 423         iop_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
 424
 425         /* 1/ don't add pre-chained descriptors
 426          * 2/ dummy read to flush next_desc write
 427          */
 428         BUG_ON(iop_desc_get_next_desc(sw_desc));
 429
 430         /* increment the pending count by the number of slots
 431          * memcpy operations have a 1:1 (slot:operation) relation
 432          * other operations are heavier and will pop the threshold
 433          * more often.
 434          */
 435         iop_chan->pending += slot_cnt;
 436         iop_adma_check_threshold(iop_chan);
 437         spin_unlock_bh(&iop_chan->lock);
 438
 439         dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
 440                 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
 441
 442         return cookie;
 443 }
 444
 445 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
 446 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
 447
 448 /* returns the number of allocated descriptors */
 449 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
 450 {
 451         char *hw_desc;
 452         int idx;
 453         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 454         struct iop_adma_desc_slot *slot = NULL;
 455         int init = iop_chan->slots_allocated ? 0 : 1;
 456         struct iop_adma_platform_data *plat_data =
 457                 iop_chan->device->pdev->dev.platform_data;
 458         int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
 459
 460         /* Allocate descriptor slots */
 461         do {
 462                 idx = iop_chan->slots_allocated;
 463                 if (idx == num_descs_in_pool)
 464                         break;
 465
 466                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 467                 if (!slot) {
 468                         printk(KERN_INFO "IOP ADMA Channel only initialized"
 469                                 " %d descriptor slots", idx);
 470                         break;
 471                 }
 472                 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
 473                 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
 474
 475                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
 476                 slot->async_tx.tx_submit = iop_adma_tx_submit;
 477                 INIT_LIST_HEAD(&slot->chain_node);
 478                 INIT_LIST_HEAD(&slot->slot_node);
 479                 INIT_LIST_HEAD(&slot->async_tx.tx_list);
 480                 hw_desc = (char *) iop_chan->device->dma_desc_pool;
 481                 slot->async_tx.phys =
 482                         (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
 483                 slot->idx = idx;
 484
 485                 spin_lock_bh(&iop_chan->lock);
 486                 iop_chan->slots_allocated++;
 487                 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
 488                 spin_unlock_bh(&iop_chan->lock);
 489         } while (iop_chan->slots_allocated < num_descs_in_pool);
 490
 491         if (idx && !iop_chan->last_used)
 492                 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
 493                                         struct iop_adma_desc_slot,
 494                                         slot_node);
 495
 496         dev_dbg(iop_chan->device->common.dev,
 497                 "allocated %d descriptor slots last_used: %p\n",
 498                 iop_chan->slots_allocated, iop_chan->last_used);
 499
 500         /* initialize the channel and the chain with a null operation */
 501         if (init) {
 502                 if (dma_has_cap(DMA_MEMCPY,
 503                         iop_chan->device->common.cap_mask))
 504                         iop_chan_start_null_memcpy(iop_chan);
 505                 else if (dma_has_cap(DMA_XOR,
 506                         iop_chan->device->common.cap_mask))
 507                         iop_chan_start_null_xor(iop_chan);
 508                 else
 509                         BUG();
 510         }
 511
 512         return (idx > 0) ? idx : -ENOMEM;
 513 }
 514
 515 static struct dma_async_tx_descriptor *
 516 iop_adma_prep_dma_interrupt(struct dma_chan *chan)
 517 {
 518         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 519         struct iop_adma_desc_slot *sw_desc, *grp_start;
 520         int slot_cnt, slots_per_op;
 521
 522         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
 523
 524         spin_lock_bh(&iop_chan->lock);
 525         slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
 526         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 527         if (sw_desc) {
 528                 grp_start = sw_desc->group_head;
 529                 iop_desc_init_interrupt(grp_start, iop_chan);
 530                 grp_start->unmap_len = 0;
 531         }
 532         spin_unlock_bh(&iop_chan->lock);
 533
 534         return sw_desc ? &sw_desc->async_tx : NULL;
 535 }
 536
 537 static struct dma_async_tx_descriptor *
 538 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
 539                          dma_addr_t dma_src, size_t len, unsigned long flags)
 540 {
 541         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 542         struct iop_adma_desc_slot *sw_desc, *grp_start;
 543         int slot_cnt, slots_per_op;
 544
 545         if (unlikely(!len))
 546                 return NULL;
 547         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
 548
 549         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
 550                 __func__, len);
 551
 552         spin_lock_bh(&iop_chan->lock);
 553         slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
 554         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 555         if (sw_desc) {
 556                 grp_start = sw_desc->group_head;
 557                 iop_desc_init_memcpy(grp_start, flags);
 558                 iop_desc_set_byte_count(grp_start, iop_chan, len);
 559                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
 560                 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
 561                 sw_desc->unmap_src_cnt = 1;
 562                 sw_desc->unmap_len = len;
 563         }
 564         spin_unlock_bh(&iop_chan->lock);
 565
 566         return sw_desc ? &sw_desc->async_tx : NULL;
 567 }
 568
 569 static struct dma_async_tx_descriptor *
 570 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
 571                          int value, size_t len, unsigned long flags)
 572 {
 573         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 574         struct iop_adma_desc_slot *sw_desc, *grp_start;
 575         int slot_cnt, slots_per_op;
 576
 577         if (unlikely(!len))
 578                 return NULL;
 579         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
 580
 581         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
 582                 __func__, len);
 583
 584         spin_lock_bh(&iop_chan->lock);
 585         slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
 586         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 587         if (sw_desc) {
 588                 grp_start = sw_desc->group_head;
 589                 iop_desc_init_memset(grp_start, flags);
 590                 iop_desc_set_byte_count(grp_start, iop_chan, len);
 591                 iop_desc_set_block_fill_val(grp_start, value);
 592                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
 593                 sw_desc->unmap_src_cnt = 1;
 594                 sw_desc->unmap_len = len;
 595         }
 596         spin_unlock_bh(&iop_chan->lock);
 597
 598         return sw_desc ? &sw_desc->async_tx : NULL;
 599 }
 600
 601 static struct dma_async_tx_descriptor *
 602 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
 603                       dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
 604                       unsigned long flags)
 605 {
 606         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 607         struct iop_adma_desc_slot *sw_desc, *grp_start;
 608         int slot_cnt, slots_per_op;
 609
 610         if (unlikely(!len))
 611                 return NULL;
 612         BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
 613
 614         dev_dbg(iop_chan->device->common.dev,
 615                 "%s src_cnt: %d len: %u flags: %lx\n",
 616                 __func__, src_cnt, len, flags);
 617
 618         spin_lock_bh(&iop_chan->lock);
 619         slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
 620         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 621         if (sw_desc) {
 622                 grp_start = sw_desc->group_head;
 623                 iop_desc_init_xor(grp_start, src_cnt, flags);
 624                 iop_desc_set_byte_count(grp_start, iop_chan, len);
 625                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
 626                 sw_desc->unmap_src_cnt = src_cnt;
 627                 sw_desc->unmap_len = len;
 628                 while (src_cnt--)
 629                         iop_desc_set_xor_src_addr(grp_start, src_cnt,
 630                                                   dma_src[src_cnt]);
 631         }
 632         spin_unlock_bh(&iop_chan->lock);
 633
 634         return sw_desc ? &sw_desc->async_tx : NULL;
 635 }
 636
 637 static struct dma_async_tx_descriptor *
 638 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
 639                            unsigned int src_cnt, size_t len, u32 *result,
 640                            unsigned long flags)
 641 {
 642         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 643         struct iop_adma_desc_slot *sw_desc, *grp_start;
 644         int slot_cnt, slots_per_op;
 645
 646         if (unlikely(!len))
 647                 return NULL;
 648
 649         dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
 650                 __func__, src_cnt, len);
 651
 652         spin_lock_bh(&iop_chan->lock);
 653         slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
 654         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 655         if (sw_desc) {
 656                 grp_start = sw_desc->group_head;
 657                 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
 658                 iop_desc_set_zero_sum_byte_count(grp_start, len);
 659                 grp_start->xor_check_result = result;
 660                 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
 661                         __func__, grp_start->xor_check_result);
 662                 sw_desc->unmap_src_cnt = src_cnt;
 663                 sw_desc->unmap_len = len;
 664                 while (src_cnt--)
 665                         iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
 666                                                        dma_src[src_cnt]);
 667         }
 668         spin_unlock_bh(&iop_chan->lock);
 669
 670         return sw_desc ? &sw_desc->async_tx : NULL;
 671 }
 672
 673 static void iop_adma_free_chan_resources(struct dma_chan *chan)
 674 {
 675         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 676         struct iop_adma_desc_slot *iter, *_iter;
 677         int in_use_descs = 0;
 678
 679         iop_adma_slot_cleanup(iop_chan);
 680
 681         spin_lock_bh(&iop_chan->lock);
 682         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
 683                                         chain_node) {
 684                 in_use_descs++;
 685                 list_del(&iter->chain_node);
 686         }
 687         list_for_each_entry_safe_reverse(
 688                 iter, _iter, &iop_chan->all_slots, slot_node) {
 689                 list_del(&iter->slot_node);
 690                 kfree(iter);
 691                 iop_chan->slots_allocated--;
 692         }
 693         iop_chan->last_used = NULL;
 694
 695         dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
 696                 __func__, iop_chan->slots_allocated);
 697         spin_unlock_bh(&iop_chan->lock);
 698
 699         /* one is ok since we left it on there on purpose */
 700         if (in_use_descs > 1)
 701                 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
 702                         in_use_descs - 1);
 703 }
 704
 705 /**
 706  * iop_adma_is_complete - poll the status of an ADMA transaction
 707  * @chan: ADMA channel handle
 708  * @cookie: ADMA transaction identifier
 709  */
 710 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
 711                                         dma_cookie_t cookie,
 712                                         dma_cookie_t *done,
 713                                         dma_cookie_t *used)
 714 {
 715         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 716         dma_cookie_t last_used;
 717         dma_cookie_t last_complete;
 718         enum dma_status ret;
 719
 720         last_used = chan->cookie;
 721         last_complete = iop_chan->completed_cookie;
 722
 723         if (done)
 724                 *done = last_complete;
 725         if (used)
 726                 *used = last_used;
 727
 728         ret = dma_async_is_complete(cookie, last_complete, last_used);
 729         if (ret == DMA_SUCCESS)
 730                 return ret;
 731
 732         iop_adma_slot_cleanup(iop_chan);
 733
 734         last_used = chan->cookie;
 735         last_complete = iop_chan->completed_cookie;
 736
 737         if (done)
 738                 *done = last_complete;
 739         if (used)
 740                 *used = last_used;
 741
 742         return dma_async_is_complete(cookie, last_complete, last_used);
 743 }
 744
 745 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
 746 {
 747         struct iop_adma_chan *chan = data;
 748
 749         dev_dbg(chan->device->common.dev, "%s\n", __func__);
 750
 751         tasklet_schedule(&chan->irq_tasklet);
 752
 753         iop_adma_device_clear_eot_status(chan);
 754
 755         return IRQ_HANDLED;
 756 }
 757
 758 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
 759 {
 760         struct iop_adma_chan *chan = data;
 761
 762         dev_dbg(chan->device->common.dev, "%s\n", __func__);
 763
 764         tasklet_schedule(&chan->irq_tasklet);
 765
 766         iop_adma_device_clear_eoc_status(chan);
 767
 768         return IRQ_HANDLED;
 769 }
 770
 771 static irqreturn_t iop_adma_err_handler(int irq, void *data)
 772 {
 773         struct iop_adma_chan *chan = data;
 774         unsigned long status = iop_chan_get_status(chan);
 775
 776         dev_printk(KERN_ERR, chan->device->common.dev,
 777                 "error ( %s%s%s%s%s%s%s)\n",
 778                 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
 779                 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
 780                 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
 781                 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
 782                 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
 783                 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
 784                 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
 785
 786         iop_adma_device_clear_err_status(chan);
 787
 788         BUG();
 789
 790         return IRQ_HANDLED;
 791 }
 792
 793 static void iop_adma_issue_pending(struct dma_chan *chan)
 794 {
 795         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 796
 797         if (iop_chan->pending) {
 798                 iop_chan->pending = 0;
 799                 iop_chan_append(iop_chan);
 800         }
 801 }
 802
 803 /*
 804  * Perform a transaction to verify the HW works.
 805  */
 806 #define IOP_ADMA_TEST_SIZE 2000
 807
 808 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
 809 {
 810         int i;
 811         void *src, *dest;
 812         dma_addr_t src_dma, dest_dma;
 813         struct dma_chan *dma_chan;
 814         dma_cookie_t cookie;
 815         struct dma_async_tx_descriptor *tx;
 816         int err = 0;
 817         struct iop_adma_chan *iop_chan;
 818
 819         dev_dbg(device->common.dev, "%s\n", __func__);
 820
 821         src = kzalloc(sizeof(u8) * IOP_ADMA_TEST_SIZE, GFP_KERNEL);
 822         if (!src)
 823                 return -ENOMEM;
 824         dest = kzalloc(sizeof(u8) * IOP_ADMA_TEST_SIZE, GFP_KERNEL);
 825         if (!dest) {
 826                 kfree(src);
 827                 return -ENOMEM;
 828         }
 829
 830         /* Fill in src buffer */
 831         for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
 832                 ((u8 *) src)[i] = (u8)i;
 833
 834         memset(dest, 0, IOP_ADMA_TEST_SIZE);
 835
 836         /* Start copy, using first DMA channel */
 837         dma_chan = container_of(device->common.channels.next,
 838                                 struct dma_chan,
 839                                 device_node);
 840         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
 841                 err = -ENODEV;
 842                 goto out;
 843         }
 844
 845         dest_dma = dma_map_single(dma_chan->device->dev, dest,
 846                                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
 847         src_dma = dma_map_single(dma_chan->device->dev, src,
 848                                 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
 849         tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
 850                                       IOP_ADMA_TEST_SIZE, 1);
 851
 852         cookie = iop_adma_tx_submit(tx);
 853         iop_adma_issue_pending(dma_chan);
 854         async_tx_ack(tx);
 855         msleep(1);
 856
 857         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
 858                         DMA_SUCCESS) {
 859                 dev_printk(KERN_ERR, dma_chan->device->dev,
 860                         "Self-test copy timed out, disabling\n");
 861                 err = -ENODEV;
 862                 goto free_resources;
 863         }
 864
 865         iop_chan = to_iop_adma_chan(dma_chan);
 866         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
 867                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
 868         if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
 869                 dev_printk(KERN_ERR, dma_chan->device->dev,
 870                         "Self-test copy failed compare, disabling\n");
 871                 err = -ENODEV;
 872                 goto free_resources;
 873         }
 874
 875 free_resources:
 876         iop_adma_free_chan_resources(dma_chan);
 877 out:
 878         kfree(src);
 879         kfree(dest);
 880         return err;
 881 }
 882
 883 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
 884 static int __devinit
 885 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
 886 {
 887         int i, src_idx;
 888         struct page *dest;
 889         struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
 890         struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
 891         dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
 892         dma_addr_t dma_addr, dest_dma;
 893         struct dma_async_tx_descriptor *tx;
 894         struct dma_chan *dma_chan;
 895         dma_cookie_t cookie;
 896         u8 cmp_byte = 0;
 897         u32 cmp_word;
 898         u32 zero_sum_result;
 899         int err = 0;
 900         struct iop_adma_chan *iop_chan;
 901
 902         dev_dbg(device->common.dev, "%s\n", __func__);
 903
 904         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
 905                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
 906                 if (!xor_srcs[src_idx])
 907                         while (src_idx--) {
 908                                 __free_page(xor_srcs[src_idx]);
 909                                 return -ENOMEM;
 910                         }
 911         }
 912
 913         dest = alloc_page(GFP_KERNEL);
 914         if (!dest)
 915                 while (src_idx--) {
 916                         __free_page(xor_srcs[src_idx]);
 917                         return -ENOMEM;
 918                 }
 919
 920         /* Fill in src buffers */
 921         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
 922                 u8 *ptr = page_address(xor_srcs[src_idx]);
 923                 for (i = 0; i < PAGE_SIZE; i++)
 924                         ptr[i] = (1 << src_idx);
 925         }
 926
 927         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
 928                 cmp_byte ^= (u8) (1 << src_idx);
 929
 930         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
 931                         (cmp_byte << 8) | cmp_byte;
 932
 933         memset(page_address(dest), 0, PAGE_SIZE);
 934
 935         dma_chan = container_of(device->common.channels.next,
 936                                 struct dma_chan,
 937                                 device_node);
 938         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
 939                 err = -ENODEV;
 940                 goto out;
 941         }
 942
 943         /* test xor */
 944         dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
 945                                 PAGE_SIZE, DMA_FROM_DEVICE);
 946         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
 947                 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
 948                                            0, PAGE_SIZE, DMA_TO_DEVICE);
 949         tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
 950                                    IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, 1);
 951
 952         cookie = iop_adma_tx_submit(tx);
 953         iop_adma_issue_pending(dma_chan);
 954         async_tx_ack(tx);
 955         msleep(8);
 956
 957         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
 958                 DMA_SUCCESS) {
 959                 dev_printk(KERN_ERR, dma_chan->device->dev,
 960                         "Self-test xor timed out, disabling\n");
 961                 err = -ENODEV;
 962                 goto free_resources;
 963         }
 964
 965         iop_chan = to_iop_adma_chan(dma_chan);
 966         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
 967                 PAGE_SIZE, DMA_FROM_DEVICE);
 968         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
 969                 u32 *ptr = page_address(dest);
 970                 if (ptr[i] != cmp_word) {
 971                         dev_printk(KERN_ERR, dma_chan->device->dev,
 972                                 "Self-test xor failed compare, disabling\n");
 973                         err = -ENODEV;
 974                         goto free_resources;
 975                 }
 976         }
 977         dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
 978                 PAGE_SIZE, DMA_TO_DEVICE);
 979
 980         /* skip zero sum if the capability is not present */
 981         if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
 982                 goto free_resources;
 983
 984         /* zero sum the sources with the destintation page */
 985         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
 986                 zero_sum_srcs[i] = xor_srcs[i];
 987         zero_sum_srcs[i] = dest;
 988
 989         zero_sum_result = 1;
 990
 991         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
 992                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
 993                                            zero_sum_srcs[i], 0, PAGE_SIZE,
 994                                            DMA_TO_DEVICE);
 995         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
 996                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
 997                                         &zero_sum_result, 1);
 998
 999         cookie = iop_adma_tx_submit(tx);
1000         iop_adma_issue_pending(dma_chan);
1001         async_tx_ack(tx);
1002         msleep(8);
1003
1004         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1005                 dev_printk(KERN_ERR, dma_chan->device->dev,
1006                         "Self-test zero sum timed out, disabling\n");
1007                 err = -ENODEV;
1008                 goto free_resources;
1009         }
1010
1011         if (zero_sum_result != 0) {
1012                 dev_printk(KERN_ERR, dma_chan->device->dev,
1013                         "Self-test zero sum failed compare, disabling\n");
1014                 err = -ENODEV;
1015                 goto free_resources;
1016         }
1017
1018         /* test memset */
1019         dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1020                         PAGE_SIZE, DMA_FROM_DEVICE);
1021         tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, 1);
1022
1023         cookie = iop_adma_tx_submit(tx);
1024         iop_adma_issue_pending(dma_chan);
1025         async_tx_ack(tx);
1026         msleep(8);
1027
1028         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1029                 dev_printk(KERN_ERR, dma_chan->device->dev,
1030                         "Self-test memset timed out, disabling\n");
1031                 err = -ENODEV;
1032                 goto free_resources;
1033         }
1034
1035         for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1036                 u32 *ptr = page_address(dest);
1037                 if (ptr[i]) {
1038                         dev_printk(KERN_ERR, dma_chan->device->dev,
1039                                 "Self-test memset failed compare, disabling\n");
1040                         err = -ENODEV;
1041                         goto free_resources;
1042                 }
1043         }
1044
1045         /* test for non-zero parity sum */
1046         zero_sum_result = 0;
1047         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1048                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1049                                            zero_sum_srcs[i], 0, PAGE_SIZE,
1050                                            DMA_TO_DEVICE);
1051         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1052                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1053                                         &zero_sum_result, 1);
1054
1055         cookie = iop_adma_tx_submit(tx);
1056         iop_adma_issue_pending(dma_chan);
1057         async_tx_ack(tx);
1058         msleep(8);
1059
1060         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1061                 dev_printk(KERN_ERR, dma_chan->device->dev,
1062                         "Self-test non-zero sum timed out, disabling\n");
1063                 err = -ENODEV;
1064                 goto free_resources;
1065         }
1066
1067         if (zero_sum_result != 1) {
1068                 dev_printk(KERN_ERR, dma_chan->device->dev,
1069                         "Self-test non-zero sum failed compare, disabling\n");
1070                 err = -ENODEV;
1071                 goto free_resources;
1072         }
1073
1074 free_resources:
1075         iop_adma_free_chan_resources(dma_chan);
1076 out:
1077         src_idx = IOP_ADMA_NUM_SRC_TEST;
1078         while (src_idx--)
1079                 __free_page(xor_srcs[src_idx]);
1080         __free_page(dest);
1081         return err;
1082 }
1083
1084 static int __devexit iop_adma_remove(struct platform_device *dev)
1085 {
1086         struct iop_adma_device *device = platform_get_drvdata(dev);
1087         struct dma_chan *chan, *_chan;
1088         struct iop_adma_chan *iop_chan;
1089         int i;
1090         struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1091
1092         dma_async_device_unregister(&device->common);
1093
1094         for (i = 0; i < 3; i++) {
1095                 unsigned int irq;
1096                 irq = platform_get_irq(dev, i);
1097                 free_irq(irq, device);
1098         }
1099
1100         dma_free_coherent(&dev->dev, plat_data->pool_size,
1101                         device->dma_desc_pool_virt, device->dma_desc_pool);
1102
1103         do {
1104                 struct resource *res;
1105                 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1106                 release_mem_region(res->start, res->end - res->start);
1107         } while (0);
1108
1109         list_for_each_entry_safe(chan, _chan, &device->common.channels,
1110                                 device_node) {
1111                 iop_chan = to_iop_adma_chan(chan);
1112                 list_del(&chan->device_node);
1113                 kfree(iop_chan);
1114         }
1115         kfree(device);
1116
1117         return 0;
1118 }
1119
1120 static int __devinit iop_adma_probe(struct platform_device *pdev)
1121 {
1122         struct resource *res;
1123         int ret = 0, i;
1124         struct iop_adma_device *adev;
1125         struct iop_adma_chan *iop_chan;
1126         struct dma_device *dma_dev;
1127         struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1128
1129         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1130         if (!res)
1131                 return -ENODEV;
1132
1133         if (!devm_request_mem_region(&pdev->dev, res->start,
1134                                 res->end - res->start, pdev->name))
1135                 return -EBUSY;
1136
1137         adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1138         if (!adev)
1139                 return -ENOMEM;
1140         dma_dev = &adev->common;
1141
1142         /* allocate coherent memory for hardware descriptors
1143          * note: writecombine gives slightly better performance, but
1144          * requires that we explicitly flush the writes
1145          */
1146         if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1147                                         plat_data->pool_size,
1148                                         &adev->dma_desc_pool,
1149                                         GFP_KERNEL)) == NULL) {
1150                 ret = -ENOMEM;
1151                 goto err_free_adev;
1152         }
1153
1154         dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1155                 __func__, adev->dma_desc_pool_virt,
1156                 (void *) adev->dma_desc_pool);
1157
1158         adev->id = plat_data->hw_id;
1159
1160         /* discover transaction capabilites from the platform data */
1161         dma_dev->cap_mask = plat_data->cap_mask;
1162
1163         adev->pdev = pdev;
1164         platform_set_drvdata(pdev, adev);
1165
1166         INIT_LIST_HEAD(&dma_dev->channels);
1167
1168         /* set base routines */
1169         dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1170         dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1171         dma_dev->device_is_tx_complete = iop_adma_is_complete;
1172         dma_dev->device_issue_pending = iop_adma_issue_pending;
1173         dma_dev->dev = &pdev->dev;
1174
1175         /* set prep routines based on capability */
1176         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1177                 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1178         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1179                 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1180         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1181                 dma_dev->max_xor = iop_adma_get_max_xor();
1182                 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1183         }
1184         if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1185                 dma_dev->device_prep_dma_zero_sum =
1186                         iop_adma_prep_dma_zero_sum;
1187         if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1188                 dma_dev->device_prep_dma_interrupt =
1189                         iop_adma_prep_dma_interrupt;
1190
1191         iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1192         if (!iop_chan) {
1193                 ret = -ENOMEM;
1194                 goto err_free_dma;
1195         }
1196         iop_chan->device = adev;
1197
1198         iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1199                                         res->end - res->start);
1200         if (!iop_chan->mmr_base) {
1201                 ret = -ENOMEM;
1202                 goto err_free_iop_chan;
1203         }
1204         tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1205                 iop_chan);
1206
1207         /* clear errors before enabling interrupts */
1208         iop_adma_device_clear_err_status(iop_chan);
1209
1210         for (i = 0; i < 3; i++) {
1211                 irq_handler_t handler[] = { iop_adma_eot_handler,
1212                                         iop_adma_eoc_handler,
1213                                         iop_adma_err_handler };
1214                 int irq = platform_get_irq(pdev, i);
1215                 if (irq < 0) {
1216                         ret = -ENXIO;
1217                         goto err_free_iop_chan;
1218                 } else {
1219                         ret = devm_request_irq(&pdev->dev, irq,
1220                                         handler[i], 0, pdev->name, iop_chan);
1221                         if (ret)
1222                                 goto err_free_iop_chan;
1223                 }
1224         }
1225
1226         spin_lock_init(&iop_chan->lock);
1227         INIT_LIST_HEAD(&iop_chan->chain);
1228         INIT_LIST_HEAD(&iop_chan->all_slots);
1229         INIT_RCU_HEAD(&iop_chan->common.rcu);
1230         iop_chan->common.device = dma_dev;
1231         list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1232
1233         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1234                 ret = iop_adma_memcpy_self_test(adev);
1235                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1236                 if (ret)
1237                         goto err_free_iop_chan;
1238         }
1239
1240         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1241                 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1242                 ret = iop_adma_xor_zero_sum_self_test(adev);
1243                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1244                 if (ret)
1245                         goto err_free_iop_chan;
1246         }
1247
1248         dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1249           "( %s%s%s%s%s%s%s%s%s%s)\n",
1250           dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1251           dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1252           dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1253           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1254           dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1255           dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1256           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
1257           dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1258           dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1259           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1260
1261         dma_async_device_register(dma_dev);
1262         goto out;
1263
1264  err_free_iop_chan:
1265         kfree(iop_chan);
1266  err_free_dma:
1267         dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1268                         adev->dma_desc_pool_virt, adev->dma_desc_pool);
1269  err_free_adev:
1270         kfree(adev);
1271  out:
1272         return ret;
1273 }
1274
1275 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1276 {
1277         struct iop_adma_desc_slot *sw_desc, *grp_start;
1278         dma_cookie_t cookie;
1279         int slot_cnt, slots_per_op;
1280
1281         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1282
1283         spin_lock_bh(&iop_chan->lock);
1284         slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1285         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1286         if (sw_desc) {
1287                 grp_start = sw_desc->group_head;
1288
1289                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1290                 sw_desc->async_tx.ack = 1;
1291                 iop_desc_init_memcpy(grp_start, 0);
1292                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1293                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1294                 iop_desc_set_memcpy_src_addr(grp_start, 0);
1295
1296                 cookie = iop_chan->common.cookie;
1297                 cookie++;
1298                 if (cookie <= 1)
1299                         cookie = 2;
1300
1301                 /* initialize the completed cookie to be less than
1302                  * the most recently used cookie
1303                  */
1304                 iop_chan->completed_cookie = cookie - 1;
1305                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1306
1307                 /* channel should not be busy */
1308                 BUG_ON(iop_chan_is_busy(iop_chan));
1309
1310                 /* clear any prior error-status bits */
1311                 iop_adma_device_clear_err_status(iop_chan);
1312
1313                 /* disable operation */
1314                 iop_chan_disable(iop_chan);
1315
1316                 /* set the descriptor address */
1317                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1318
1319                 /* 1/ don't add pre-chained descriptors
1320                  * 2/ dummy read to flush next_desc write
1321                  */
1322                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1323
1324                 /* run the descriptor */
1325                 iop_chan_enable(iop_chan);
1326         } else
1327                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1328                          "failed to allocate null descriptor\n");
1329         spin_unlock_bh(&iop_chan->lock);
1330 }
1331
1332 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1333 {
1334         struct iop_adma_desc_slot *sw_desc, *grp_start;
1335         dma_cookie_t cookie;
1336         int slot_cnt, slots_per_op;
1337
1338         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1339
1340         spin_lock_bh(&iop_chan->lock);
1341         slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1342         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1343         if (sw_desc) {
1344                 grp_start = sw_desc->group_head;
1345                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1346                 sw_desc->async_tx.ack = 1;
1347                 iop_desc_init_null_xor(grp_start, 2, 0);
1348                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1349                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1350                 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1351                 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1352
1353                 cookie = iop_chan->common.cookie;
1354                 cookie++;
1355                 if (cookie <= 1)
1356                         cookie = 2;
1357
1358                 /* initialize the completed cookie to be less than
1359                  * the most recently used cookie
1360                  */
1361                 iop_chan->completed_cookie = cookie - 1;
1362                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1363
1364                 /* channel should not be busy */
1365                 BUG_ON(iop_chan_is_busy(iop_chan));
1366
1367                 /* clear any prior error-status bits */
1368                 iop_adma_device_clear_err_status(iop_chan);
1369
1370                 /* disable operation */
1371                 iop_chan_disable(iop_chan);
1372
1373                 /* set the descriptor address */
1374                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1375
1376                 /* 1/ don't add pre-chained descriptors
1377                  * 2/ dummy read to flush next_desc write
1378                  */
1379                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1380
1381                 /* run the descriptor */
1382                 iop_chan_enable(iop_chan);
1383         } else
1384                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1385                         "failed to allocate null descriptor\n");
1386         spin_unlock_bh(&iop_chan->lock);
1387 }
1388
1389 static struct platform_driver iop_adma_driver = {
1390         .probe          = iop_adma_probe,
1391         .remove         = iop_adma_remove,
1392         .driver         = {
1393                 .owner  = THIS_MODULE,
1394                 .name   = "iop-adma",
1395         },
1396 };
1397
1398 static int __init iop_adma_init (void)
1399 {
1400         return platform_driver_register(&iop_adma_driver);
1401 }
1402
1403 /* it's currently unsafe to unload this module */
1404 #if 0
1405 static void __exit iop_adma_exit (void)
1406 {
1407         platform_driver_unregister(&iop_adma_driver);
1408         return;
1409 }
1410 module_exit(iop_adma_exit);
1411 #endif
1412
1413 module_init(iop_adma_init);
1414
1415 MODULE_AUTHOR("Intel Corporation");
1416 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1417 MODULE_LICENSE("GPL");