SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/dma/fsldma.c

   1 /*
   2  * Freescale MPC85xx, MPC83xx DMA Engine support
   3  *
   4  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author:
   7  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
   8  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
   9  *
  10  * Description:
  11  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
  12  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
  13  *   The support for MPC8349 DMA contorller is also added.
  14  *
  15  * This is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dmaengine.h>
  27 #include <linux/delay.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/of_platform.h>
  31
  32 #include "fsldma.h"
  33
  34 static void dma_init(struct fsl_dma_chan *fsl_chan)
  35 {
  36         /* Reset the channel */
  37         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
  38
  39         switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
  40         case FSL_DMA_IP_85XX:
  41                 /* Set the channel to below modes:
  42                  * EIE - Error interrupt enable
  43                  * EOSIE - End of segments interrupt enable (basic mode)
  44                  * EOLNIE - End of links interrupt enable
  45                  */
  46                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
  47                                 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
  48                 break;
  49         case FSL_DMA_IP_83XX:
  50                 /* Set the channel to below modes:
  51                  * EOTIE - End-of-transfer interrupt enable
  52                  */
  53                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE,
  54                                 32);
  55                 break;
  56         }
  57
  58 }
  59
  60 static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
  61 {
  62         DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
  63 }
  64
  65 static u32 get_sr(struct fsl_dma_chan *fsl_chan)
  66 {
  67         return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
  68 }
  69
  70 static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
  71                                 struct fsl_dma_ld_hw *hw, u32 count)
  72 {
  73         hw->count = CPU_TO_DMA(fsl_chan, count, 32);
  74 }
  75
  76 static void set_desc_src(struct fsl_dma_chan *fsl_chan,
  77                                 struct fsl_dma_ld_hw *hw, dma_addr_t src)
  78 {
  79         u64 snoop_bits;
  80
  81         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  82                 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
  83         hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
  84 }
  85
  86 static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
  87                                 struct fsl_dma_ld_hw *hw, dma_addr_t dest)
  88 {
  89         u64 snoop_bits;
  90
  91         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  92                 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
  93         hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
  94 }
  95
  96 static void set_desc_next(struct fsl_dma_chan *fsl_chan,
  97                                 struct fsl_dma_ld_hw *hw, dma_addr_t next)
  98 {
  99         u64 snoop_bits;
 100
 101         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
 102                 ? FSL_DMA_SNEN : 0;
 103         hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
 104 }
 105
 106 static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
 107 {
 108         DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
 109 }
 110
 111 static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
 112 {
 113         return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
 114 }
 115
 116 static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
 117 {
 118         DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
 119 }
 120
 121 static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
 122 {
 123         return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
 124 }
 125
 126 static u32 get_bcr(struct fsl_dma_chan *fsl_chan)
 127 {
 128         return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32);
 129 }
 130
 131 static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
 132 {
 133         u32 sr = get_sr(fsl_chan);
 134         return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
 135 }
 136
 137 static void dma_start(struct fsl_dma_chan *fsl_chan)
 138 {
 139         u32 mr_set = 0;;
 140
 141         if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
 142                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
 143                 mr_set |= FSL_DMA_MR_EMP_EN;
 144         } else
 145                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 146                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 147                                 & ~FSL_DMA_MR_EMP_EN, 32);
 148
 149         if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
 150                 mr_set |= FSL_DMA_MR_EMS_EN;
 151         else
 152                 mr_set |= FSL_DMA_MR_CS;
 153
 154         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 155                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 156                         | mr_set, 32);
 157 }
 158
 159 static void dma_halt(struct fsl_dma_chan *fsl_chan)
 160 {
 161         int i = 0;
 162         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 163                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
 164                 32);
 165         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 166                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
 167                 | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
 168
 169         while (!dma_is_idle(fsl_chan) && (i++ < 100))
 170                 udelay(10);
 171         if (i >= 100 && !dma_is_idle(fsl_chan))
 172                 dev_err(fsl_chan->dev, "DMA halt timeout!\n");
 173 }
 174
 175 static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
 176                         struct fsl_desc_sw *desc)
 177 {
 178         desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
 179                 DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL,
 180                 64);
 181 }
 182
 183 static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
 184                 struct fsl_desc_sw *new_desc)
 185 {
 186         struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
 187
 188         if (list_empty(&fsl_chan->ld_queue))
 189                 return;
 190
 191         /* Link to the new descriptor physical address and
 192          * Enable End-of-segment interrupt for
 193          * the last link descriptor.
 194          * (the previous node's next link descriptor)
 195          *
 196          * For FSL_DMA_IP_83xx, the snoop enable bit need be set.
 197          */
 198         queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
 199                         new_desc->async_tx.phys | FSL_DMA_EOSIE |
 200                         (((fsl_chan->feature & FSL_DMA_IP_MASK)
 201                                 == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
 202 }
 203
 204 /**
 205  * fsl_chan_set_src_loop_size - Set source address hold transfer size
 206  * @fsl_chan : Freescale DMA channel
 207  * @size     : Address loop size, 0 for disable loop
 208  *
 209  * The set source address hold transfer size. The source
 210  * address hold or loop transfer size is when the DMA transfer
 211  * data from source address (SA), if the loop size is 4, the DMA will
 212  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
 213  * SA + 1 ... and so on.
 214  */
 215 static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
 216 {
 217         switch (size) {
 218         case 0:
 219                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 220                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
 221                         (~FSL_DMA_MR_SAHE), 32);
 222                 break;
 223         case 1:
 224         case 2:
 225         case 4:
 226         case 8:
 227                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 228                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
 229                         FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
 230                         32);
 231                 break;
 232         }
 233 }
 234
 235 /**
 236  * fsl_chan_set_dest_loop_size - Set destination address hold transfer size
 237  * @fsl_chan : Freescale DMA channel
 238  * @size     : Address loop size, 0 for disable loop
 239  *
 240  * The set destination address hold transfer size. The destination
 241  * address hold or loop transfer size is when the DMA transfer
 242  * data to destination address (TA), if the loop size is 4, the DMA will
 243  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
 244  * TA + 1 ... and so on.
 245  */
 246 static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
 247 {
 248         switch (size) {
 249         case 0:
 250                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 251                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
 252                         (~FSL_DMA_MR_DAHE), 32);
 253                 break;
 254         case 1:
 255         case 2:
 256         case 4:
 257         case 8:
 258                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 259                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
 260                         FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
 261                         32);
 262                 break;
 263         }
 264 }
 265
 266 /**
 267  * fsl_chan_toggle_ext_pause - Toggle channel external pause status
 268  * @fsl_chan : Freescale DMA channel
 269  * @size     : Pause control size, 0 for disable external pause control.
 270  *             The maximum is 1024.
 271  *
 272  * The Freescale DMA channel can be controlled by the external
 273  * signal DREQ#. The pause control size is how many bytes are allowed
 274  * to transfer before pausing the channel, after which a new assertion
 275  * of DREQ# resumes channel operation.
 276  */
 277 static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
 278 {
 279         if (size > 1024)
 280                 return;
 281
 282         if (size) {
 283                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 284                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 285                                 | ((__ilog2(size) << 24) & 0x0f000000),
 286                         32);
 287                 fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
 288         } else
 289                 fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
 290 }
 291
 292 /**
 293  * fsl_chan_toggle_ext_start - Toggle channel external start status
 294  * @fsl_chan : Freescale DMA channel
 295  * @enable   : 0 is disabled, 1 is enabled.
 296  *
 297  * If enable the external start, the channel can be started by an
 298  * external DMA start pin. So the dma_start() does not start the
 299  * transfer immediately. The DMA channel will wait for the
 300  * control pin asserted.
 301  */
 302 static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
 303 {
 304         if (enable)
 305                 fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
 306         else
 307                 fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
 308 }
 309
 310 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 311 {
 312         struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
 313         struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
 314         unsigned long flags;
 315         dma_cookie_t cookie;
 316
 317         /* cookie increment and adding to ld_queue must be atomic */
 318         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 319
 320         cookie = fsl_chan->common.cookie;
 321         cookie++;
 322         if (cookie < 0)
 323                 cookie = 1;
 324         desc->async_tx.cookie = cookie;
 325         fsl_chan->common.cookie = desc->async_tx.cookie;
 326
 327         append_ld_queue(fsl_chan, desc);
 328         list_splice_init(&desc->async_tx.tx_list, fsl_chan->ld_queue.prev);
 329
 330         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 331
 332         return cookie;
 333 }
 334
 335 /**
 336  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
 337  * @fsl_chan : Freescale DMA channel
 338  *
 339  * Return - The descriptor allocated. NULL for failed.
 340  */
 341 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
 342                                         struct fsl_dma_chan *fsl_chan)
 343 {
 344         dma_addr_t pdesc;
 345         struct fsl_desc_sw *desc_sw;
 346
 347         desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
 348         if (desc_sw) {
 349                 memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
 350                 dma_async_tx_descriptor_init(&desc_sw->async_tx,
 351                                                 &fsl_chan->common);
 352                 desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
 353                 INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
 354                 desc_sw->async_tx.phys = pdesc;
 355         }
 356
 357         return desc_sw;
 358 }
 359
 360
 361 /**
 362  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
 363  * @fsl_chan : Freescale DMA channel
 364  *
 365  * This function will create a dma pool for descriptor allocation.
 366  *
 367  * Return - The number of descriptors allocated.
 368  */
 369 static int fsl_dma_alloc_chan_resources(struct dma_chan *chan,
 370                                         struct dma_client *client)
 371 {
 372         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 373         LIST_HEAD(tmp_list);
 374
 375         /* We need the descriptor to be aligned to 32bytes
 376          * for meeting FSL DMA specification requirement.
 377          */
 378         fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
 379                         fsl_chan->dev, sizeof(struct fsl_desc_sw),
 380                         32, 0);
 381         if (!fsl_chan->desc_pool) {
 382                 dev_err(fsl_chan->dev, "No memory for channel %d "
 383                         "descriptor dma pool.\n", fsl_chan->id);
 384                 return 0;
 385         }
 386
 387         return 1;
 388 }
 389
 390 /**
 391  * fsl_dma_free_chan_resources - Free all resources of the channel.
 392  * @fsl_chan : Freescale DMA channel
 393  */
 394 static void fsl_dma_free_chan_resources(struct dma_chan *chan)
 395 {
 396         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 397         struct fsl_desc_sw *desc, *_desc;
 398         unsigned long flags;
 399
 400         dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
 401         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 402         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
 403 #ifdef FSL_DMA_LD_DEBUG
 404                 dev_dbg(fsl_chan->dev,
 405                                 "LD %p will be released.\n", desc);
 406 #endif
 407                 list_del(&desc->node);
 408                 /* free link descriptor */
 409                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
 410         }
 411         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 412         dma_pool_destroy(fsl_chan->desc_pool);
 413 }
 414
 415 static struct dma_async_tx_descriptor *
 416 fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
 417 {
 418         struct fsl_dma_chan *fsl_chan;
 419         struct fsl_desc_sw *new;
 420
 421         if (!chan)
 422                 return NULL;
 423
 424         fsl_chan = to_fsl_chan(chan);
 425
 426         new = fsl_dma_alloc_descriptor(fsl_chan);
 427         if (!new) {
 428                 dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
 429                 return NULL;
 430         }
 431
 432         new->async_tx.cookie = -EBUSY;
 433         new->async_tx.flags = flags;
 434
 435         /* Insert the link descriptor to the LD ring */
 436         list_add_tail(&new->node, &new->async_tx.tx_list);
 437
 438         /* Set End-of-link to the last link descriptor of new list*/
 439         set_ld_eol(fsl_chan, new);
 440
 441         return &new->async_tx;
 442 }
 443
 444 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
 445         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 446         size_t len, unsigned long flags)
 447 {
 448         struct fsl_dma_chan *fsl_chan;
 449         struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
 450         size_t copy;
 451         LIST_HEAD(link_chain);
 452
 453         if (!chan)
 454                 return NULL;
 455
 456         if (!len)
 457                 return NULL;
 458
 459         fsl_chan = to_fsl_chan(chan);
 460
 461         do {
 462
 463                 /* Allocate the link descriptor from DMA pool */
 464                 new = fsl_dma_alloc_descriptor(fsl_chan);
 465                 if (!new) {
 466                         dev_err(fsl_chan->dev,
 467                                         "No free memory for link descriptor\n");
 468                         return NULL;
 469                 }
 470 #ifdef FSL_DMA_LD_DEBUG
 471                 dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
 472 #endif
 473
 474                 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
 475
 476                 set_desc_cnt(fsl_chan, &new->hw, copy);
 477                 set_desc_src(fsl_chan, &new->hw, dma_src);
 478                 set_desc_dest(fsl_chan, &new->hw, dma_dest);
 479
 480                 if (!first)
 481                         first = new;
 482                 else
 483                         set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
 484
 485                 new->async_tx.cookie = 0;
 486                 async_tx_ack(&new->async_tx);
 487
 488                 prev = new;
 489                 len -= copy;
 490                 dma_src += copy;
 491                 dma_dest += copy;
 492
 493                 /* Insert the link descriptor to the LD ring */
 494                 list_add_tail(&new->node, &first->async_tx.tx_list);
 495         } while (len);
 496
 497         new->async_tx.flags = flags; /* client is in control of this ack */
 498         new->async_tx.cookie = -EBUSY;
 499
 500         /* Set End-of-link to the last link descriptor of new list*/
 501         set_ld_eol(fsl_chan, new);
 502
 503         return first ? &first->async_tx : NULL;
 504 }
 505
 506 /**
 507  * fsl_dma_update_completed_cookie - Update the completed cookie.
 508  * @fsl_chan : Freescale DMA channel
 509  */
 510 static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
 511 {
 512         struct fsl_desc_sw *cur_desc, *desc;
 513         dma_addr_t ld_phy;
 514
 515         ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
 516
 517         if (ld_phy) {
 518                 cur_desc = NULL;
 519                 list_for_each_entry(desc, &fsl_chan->ld_queue, node)
 520                         if (desc->async_tx.phys == ld_phy) {
 521                                 cur_desc = desc;
 522                                 break;
 523                         }
 524
 525                 if (cur_desc && cur_desc->async_tx.cookie) {
 526                         if (dma_is_idle(fsl_chan))
 527                                 fsl_chan->completed_cookie =
 528                                         cur_desc->async_tx.cookie;
 529                         else
 530                                 fsl_chan->completed_cookie =
 531                                         cur_desc->async_tx.cookie - 1;
 532                 }
 533         }
 534 }
 535
 536 /**
 537  * fsl_chan_ld_cleanup - Clean up link descriptors
 538  * @fsl_chan : Freescale DMA channel
 539  *
 540  * This function clean up the ld_queue of DMA channel.
 541  * If 'in_intr' is set, the function will move the link descriptor to
 542  * the recycle list. Otherwise, free it directly.
 543  */
 544 static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
 545 {
 546         struct fsl_desc_sw *desc, *_desc;
 547         unsigned long flags;
 548
 549         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 550
 551         dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
 552                         fsl_chan->completed_cookie);
 553         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
 554                 dma_async_tx_callback callback;
 555                 void *callback_param;
 556
 557                 if (dma_async_is_complete(desc->async_tx.cookie,
 558                             fsl_chan->completed_cookie, fsl_chan->common.cookie)
 559                                 == DMA_IN_PROGRESS)
 560                         break;
 561
 562                 callback = desc->async_tx.callback;
 563                 callback_param = desc->async_tx.callback_param;
 564
 565                 /* Remove from ld_queue list */
 566                 list_del(&desc->node);
 567
 568                 dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
 569                                 desc);
 570                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
 571
 572                 /* Run the link descriptor callback function */
 573                 if (callback) {
 574                         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 575                         dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
 576                                         desc);
 577                         callback(callback_param);
 578                         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 579                 }
 580         }
 581         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 582 }
 583
 584 /**
 585  * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
 586  * @fsl_chan : Freescale DMA channel
 587  */
 588 static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
 589 {
 590         struct list_head *ld_node;
 591         dma_addr_t next_dest_addr;
 592         unsigned long flags;
 593
 594         if (!dma_is_idle(fsl_chan))
 595                 return;
 596
 597         dma_halt(fsl_chan);
 598
 599         /* If there are some link descriptors
 600          * not transfered in queue. We need to start it.
 601          */
 602         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 603
 604         /* Find the first un-transfer desciptor */
 605         for (ld_node = fsl_chan->ld_queue.next;
 606                 (ld_node != &fsl_chan->ld_queue)
 607                         && (dma_async_is_complete(
 608                                 to_fsl_desc(ld_node)->async_tx.cookie,
 609                                 fsl_chan->completed_cookie,
 610                                 fsl_chan->common.cookie) == DMA_SUCCESS);
 611                 ld_node = ld_node->next);
 612
 613         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 614
 615         if (ld_node != &fsl_chan->ld_queue) {
 616                 /* Get the ld start address from ld_queue */
 617                 next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
 618                 dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n",
 619                                 (void *)next_dest_addr);
 620                 set_cdar(fsl_chan, next_dest_addr);
 621                 dma_start(fsl_chan);
 622         } else {
 623                 set_cdar(fsl_chan, 0);
 624                 set_ndar(fsl_chan, 0);
 625         }
 626 }
 627
 628 /**
 629  * fsl_dma_memcpy_issue_pending - Issue the DMA start command
 630  * @fsl_chan : Freescale DMA channel
 631  */
 632 static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
 633 {
 634         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 635
 636 #ifdef FSL_DMA_LD_DEBUG
 637         struct fsl_desc_sw *ld;
 638         unsigned long flags;
 639
 640         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 641         if (list_empty(&fsl_chan->ld_queue)) {
 642                 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 643                 return;
 644         }
 645
 646         dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
 647         list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
 648                 int i;
 649                 dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
 650                                 fsl_chan->id, ld->async_tx.phys);
 651                 for (i = 0; i < 8; i++)
 652                         dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
 653                                         i, *(((u32 *)&ld->hw) + i));
 654         }
 655         dev_dbg(fsl_chan->dev, "----------------\n");
 656         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 657 #endif
 658
 659         fsl_chan_xfer_ld_queue(fsl_chan);
 660 }
 661
 662 /**
 663  * fsl_dma_is_complete - Determine the DMA status
 664  * @fsl_chan : Freescale DMA channel
 665  */
 666 static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
 667                                         dma_cookie_t cookie,
 668                                         dma_cookie_t *done,
 669                                         dma_cookie_t *used)
 670 {
 671         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 672         dma_cookie_t last_used;
 673         dma_cookie_t last_complete;
 674
 675         fsl_chan_ld_cleanup(fsl_chan);
 676
 677         last_used = chan->cookie;
 678         last_complete = fsl_chan->completed_cookie;
 679
 680         if (done)
 681                 *done = last_complete;
 682
 683         if (used)
 684                 *used = last_used;
 685
 686         return dma_async_is_complete(cookie, last_complete, last_used);
 687 }
 688
 689 static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
 690 {
 691         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
 692         u32 stat;
 693         int update_cookie = 0;
 694         int xfer_ld_q = 0;
 695
 696         stat = get_sr(fsl_chan);
 697         dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
 698                                                 fsl_chan->id, stat);
 699         set_sr(fsl_chan, stat);         /* Clear the event register */
 700
 701         stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
 702         if (!stat)
 703                 return IRQ_NONE;
 704
 705         if (stat & FSL_DMA_SR_TE)
 706                 dev_err(fsl_chan->dev, "Transfer Error!\n");
 707
 708         /* Programming Error
 709          * The DMA_INTERRUPT async_tx is a NULL transfer, which will
 710          * triger a PE interrupt.
 711          */
 712         if (stat & FSL_DMA_SR_PE) {
 713                 dev_dbg(fsl_chan->dev, "event: Programming Error INT\n");
 714                 if (get_bcr(fsl_chan) == 0) {
 715                         /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
 716                          * Now, update the completed cookie, and continue the
 717                          * next uncompleted transfer.
 718                          */
 719                         update_cookie = 1;
 720                         xfer_ld_q = 1;
 721                 }
 722                 stat &= ~FSL_DMA_SR_PE;
 723         }
 724
 725         /* If the link descriptor segment transfer finishes,
 726          * we will recycle the used descriptor.
 727          */
 728         if (stat & FSL_DMA_SR_EOSI) {
 729                 dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
 730                 dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n",
 731                         (void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan));
 732                 stat &= ~FSL_DMA_SR_EOSI;
 733                 update_cookie = 1;
 734         }
 735
 736         /* For MPC8349, EOCDI event need to update cookie
 737          * and start the next transfer if it exist.
 738          */
 739         if (stat & FSL_DMA_SR_EOCDI) {
 740                 dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n");
 741                 stat &= ~FSL_DMA_SR_EOCDI;
 742                 update_cookie = 1;
 743                 xfer_ld_q = 1;
 744         }
 745
 746         /* If it current transfer is the end-of-transfer,
 747          * we should clear the Channel Start bit for
 748          * prepare next transfer.
 749          */
 750         if (stat & FSL_DMA_SR_EOLNI) {
 751                 dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
 752                 stat &= ~FSL_DMA_SR_EOLNI;
 753                 xfer_ld_q = 1;
 754         }
 755
 756         if (update_cookie)
 757                 fsl_dma_update_completed_cookie(fsl_chan);
 758         if (xfer_ld_q)
 759                 fsl_chan_xfer_ld_queue(fsl_chan);
 760         if (stat)
 761                 dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
 762                                         stat);
 763
 764         dev_dbg(fsl_chan->dev, "event: Exit\n");
 765         tasklet_schedule(&fsl_chan->tasklet);
 766         return IRQ_HANDLED;
 767 }
 768
 769 static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
 770 {
 771         struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
 772         u32 gsr;
 773         int ch_nr;
 774
 775         gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
 776                         : in_le32(fdev->reg_base);
 777         ch_nr = (32 - ffs(gsr)) / 8;
 778
 779         return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
 780                         fdev->chan[ch_nr]) : IRQ_NONE;
 781 }
 782
 783 static void dma_do_tasklet(unsigned long data)
 784 {
 785         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
 786         fsl_chan_ld_cleanup(fsl_chan);
 787 }
 788
 789 static int __devinit of_fsl_dma_chan_probe(struct of_device *dev,
 790                         const struct of_device_id *match)
 791 {
 792         struct fsl_dma_device *fdev;
 793         struct fsl_dma_chan *new_fsl_chan;
 794         int err;
 795
 796         fdev = dev_get_drvdata(dev->dev.parent);
 797         BUG_ON(!fdev);
 798
 799         /* alloc channel */
 800         new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
 801         if (!new_fsl_chan) {
 802                 dev_err(&dev->dev, "No free memory for allocating "
 803                                 "dma channels!\n");
 804                 return -ENOMEM;
 805         }
 806
 807         /* get dma channel register base */
 808         err = of_address_to_resource(dev->node, 0, &new_fsl_chan->reg);
 809         if (err) {
 810                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
 811                                 dev->node->full_name);
 812                 goto err_no_reg;
 813         }
 814
 815         new_fsl_chan->feature = *(u32 *)match->data;
 816
 817         if (!fdev->feature)
 818                 fdev->feature = new_fsl_chan->feature;
 819
 820         /* If the DMA device's feature is different than its channels',
 821          * report the bug.
 822          */
 823         WARN_ON(fdev->feature != new_fsl_chan->feature);
 824
 825         new_fsl_chan->dev = &dev->dev;
 826         new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
 827                         new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
 828
 829         new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
 830         if (new_fsl_chan->id > FSL_DMA_MAX_CHANS_PER_DEVICE) {
 831                 dev_err(&dev->dev, "There is no %d channel!\n",
 832                                 new_fsl_chan->id);
 833                 err = -EINVAL;
 834                 goto err_no_chan;
 835         }
 836         fdev->chan[new_fsl_chan->id] = new_fsl_chan;
 837         tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
 838                         (unsigned long)new_fsl_chan);
 839
 840         /* Init the channel */
 841         dma_init(new_fsl_chan);
 842
 843         /* Clear cdar registers */
 844         set_cdar(new_fsl_chan, 0);
 845
 846         switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
 847         case FSL_DMA_IP_85XX:
 848                 new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
 849                 new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
 850         case FSL_DMA_IP_83XX:
 851                 new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
 852                 new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
 853         }
 854
 855         spin_lock_init(&new_fsl_chan->desc_lock);
 856         INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
 857
 858         new_fsl_chan->common.device = &fdev->common;
 859
 860         /* Add the channel to DMA device channel list */
 861         list_add_tail(&new_fsl_chan->common.device_node,
 862                         &fdev->common.channels);
 863         fdev->common.chancnt++;
 864
 865         new_fsl_chan->irq = irq_of_parse_and_map(dev->node, 0);
 866         if (new_fsl_chan->irq != NO_IRQ) {
 867                 err = request_irq(new_fsl_chan->irq,
 868                                         &fsl_dma_chan_do_interrupt, IRQF_SHARED,
 869                                         "fsldma-channel", new_fsl_chan);
 870                 if (err) {
 871                         dev_err(&dev->dev, "DMA channel %s request_irq error "
 872                                 "with return %d\n", dev->node->full_name, err);
 873                         goto err_no_irq;
 874                 }
 875         }
 876
 877         dev_info(&dev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
 878                                 match->compatible, new_fsl_chan->irq);
 879
 880         return 0;
 881
 882 err_no_irq:
 883         list_del(&new_fsl_chan->common.device_node);
 884 err_no_chan:
 885         iounmap(new_fsl_chan->reg_base);
 886 err_no_reg:
 887         kfree(new_fsl_chan);
 888         return err;
 889 }
 890
 891 const u32 mpc8540_dma_ip_feature = FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN;
 892 const u32 mpc8349_dma_ip_feature = FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN;
 893
 894 static struct of_device_id of_fsl_dma_chan_ids[] = {
 895         {
 896                 .compatible = "fsl,eloplus-dma-channel",
 897                 .data = (void *)&mpc8540_dma_ip_feature,
 898         },
 899         {
 900                 .compatible = "fsl,elo-dma-channel",
 901                 .data = (void *)&mpc8349_dma_ip_feature,
 902         },
 903         {}
 904 };
 905
 906 static struct of_platform_driver of_fsl_dma_chan_driver = {
 907         .name = "of-fsl-dma-channel",
 908         .match_table = of_fsl_dma_chan_ids,
 909         .probe = of_fsl_dma_chan_probe,
 910 };
 911
 912 static __init int of_fsl_dma_chan_init(void)
 913 {
 914         return of_register_platform_driver(&of_fsl_dma_chan_driver);
 915 }
 916
 917 static int __devinit of_fsl_dma_probe(struct of_device *dev,
 918                         const struct of_device_id *match)
 919 {
 920         int err;
 921         unsigned int irq;
 922         struct fsl_dma_device *fdev;
 923
 924         fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
 925         if (!fdev) {
 926                 dev_err(&dev->dev, "No enough memory for 'priv'\n");
 927                 return -ENOMEM;
 928         }
 929         fdev->dev = &dev->dev;
 930         INIT_LIST_HEAD(&fdev->common.channels);
 931
 932         /* get DMA controller register base */
 933         err = of_address_to_resource(dev->node, 0, &fdev->reg);
 934         if (err) {
 935                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
 936                                 dev->node->full_name);
 937                 goto err_no_reg;
 938         }
 939
 940         dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
 941                         "controller at %p...\n",
 942                         match->compatible, (void *)fdev->reg.start);
 943         fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
 944                                                 - fdev->reg.start + 1);
 945
 946         dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
 947         dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
 948         fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
 949         fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
 950         fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
 951         fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
 952         fdev->common.device_is_tx_complete = fsl_dma_is_complete;
 953         fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
 954         fdev->common.dev = &dev->dev;
 955
 956         irq = irq_of_parse_and_map(dev->node, 0);
 957         if (irq != NO_IRQ) {
 958                 err = request_irq(irq, &fsl_dma_do_interrupt, IRQF_SHARED,
 959                                         "fsldma-device", fdev);
 960                 if (err) {
 961                         dev_err(&dev->dev, "DMA device request_irq error "
 962                                 "with return %d\n", err);
 963                         goto err;
 964                 }
 965         }
 966
 967         dev_set_drvdata(&(dev->dev), fdev);
 968         of_platform_bus_probe(dev->node, of_fsl_dma_chan_ids, &dev->dev);
 969
 970         dma_async_device_register(&fdev->common);
 971         return 0;
 972
 973 err:
 974         iounmap(fdev->reg_base);
 975 err_no_reg:
 976         kfree(fdev);
 977         return err;
 978 }
 979
 980 static struct of_device_id of_fsl_dma_ids[] = {
 981         { .compatible = "fsl,eloplus-dma", },
 982         { .compatible = "fsl,elo-dma", },
 983         {}
 984 };
 985
 986 static struct of_platform_driver of_fsl_dma_driver = {
 987         .name = "of-fsl-dma",
 988         .match_table = of_fsl_dma_ids,
 989         .probe = of_fsl_dma_probe,
 990 };
 991
 992 static __init int of_fsl_dma_init(void)
 993 {
 994         return of_register_platform_driver(&of_fsl_dma_driver);
 995 }
 996
 997 subsys_initcall(of_fsl_dma_chan_init);
 998 subsys_initcall(of_fsl_dma_init);