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   1 /*
   2  * driver/dma/coh901318.c
   3  *
   4  * Copyright (C) 2007-2009 ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  * DMA driver for COH 901 318
   7  * Author: Per Friden <per.friden@stericsson.com>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/kernel.h> /* printk() */
  13 #include <linux/fs.h> /* everything... */
  14 #include <linux/slab.h> /* kmalloc() */
  15 #include <linux/dmaengine.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/device.h>
  18 #include <linux/irqreturn.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/uaccess.h>
  22 #include <linux/debugfs.h>
  23 #include <mach/coh901318.h>
  24
  25 #include "coh901318_lli.h"
  26
  27 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
  28
  29 #ifdef VERBOSE_DEBUG
  30 #define COH_DBG(x) ({ if (1) x; 0; })
  31 #else
  32 #define COH_DBG(x) ({ if (0) x; 0; })
  33 #endif
  34
  35 struct coh901318_desc {
  36         struct dma_async_tx_descriptor desc;
  37         struct list_head node;
  38         struct scatterlist *sg;
  39         unsigned int sg_len;
  40         struct coh901318_lli *data;
  41         enum dma_data_direction dir;
  42         int pending_irqs;
  43         unsigned long flags;
  44 };
  45
  46 struct coh901318_base {
  47         struct device *dev;
  48         void __iomem *virtbase;
  49         struct coh901318_pool pool;
  50         struct powersave pm;
  51         struct dma_device dma_slave;
  52         struct dma_device dma_memcpy;
  53         struct coh901318_chan *chans;
  54         struct coh901318_platform *platform;
  55 };
  56
  57 struct coh901318_chan {
  58         spinlock_t lock;
  59         int allocated;
  60         int completed;
  61         int id;
  62         int stopped;
  63
  64         struct work_struct free_work;
  65         struct dma_chan chan;
  66
  67         struct tasklet_struct tasklet;
  68
  69         struct list_head active;
  70         struct list_head queue;
  71         struct list_head free;
  72
  73         unsigned long nbr_active_done;
  74         unsigned long busy;
  75         int pending_irqs;
  76
  77         struct coh901318_base *base;
  78 };
  79
  80 static void coh901318_list_print(struct coh901318_chan *cohc,
  81                                  struct coh901318_lli *lli)
  82 {
  83         struct coh901318_lli *l = lli;
  84         int i = 0;
  85
  86         while (l) {
  87                 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
  88                          ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
  89                          i, l, l->control, l->src_addr, l->dst_addr,
  90                          l->link_addr, l->virt_link_addr);
  91                 i++;
  92                 l = l->virt_link_addr;
  93         }
  94 }
  95
  96 #ifdef CONFIG_DEBUG_FS
  97
  98 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
  99
 100 static struct coh901318_base *debugfs_dma_base;
 101 static struct dentry *dma_dentry;
 102
 103 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
 104 {
 105
 106         file->private_data = inode->i_private;
 107         return 0;
 108 }
 109
 110 static int coh901318_debugfs_read(struct file *file, char __user *buf,
 111                                   size_t count, loff_t *f_pos)
 112 {
 113         u64 started_channels = debugfs_dma_base->pm.started_channels;
 114         int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
 115         int i;
 116         int ret = 0;
 117         char *dev_buf;
 118         char *tmp;
 119         int dev_size;
 120
 121         dev_buf = kmalloc(4*1024, GFP_KERNEL);
 122         if (dev_buf == NULL)
 123                 goto err_kmalloc;
 124         tmp = dev_buf;
 125
 126         tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
 127
 128         for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
 129                 if (started_channels & (1 << i))
 130                         tmp += sprintf(tmp, "channel %d\n", i);
 131
 132         tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
 133         dev_size = tmp  - dev_buf;
 134
 135         /* No more to read if offset != 0 */
 136         if (*f_pos > dev_size)
 137                 goto out;
 138
 139         if (count > dev_size - *f_pos)
 140                 count = dev_size - *f_pos;
 141
 142         if (copy_to_user(buf, dev_buf + *f_pos, count))
 143                 ret = -EINVAL;
 144         ret = count;
 145         *f_pos += count;
 146
 147  out:
 148         kfree(dev_buf);
 149         return ret;
 150
 151  err_kmalloc:
 152         return 0;
 153 }
 154
 155 static const struct file_operations coh901318_debugfs_status_operations = {
 156         .owner          = THIS_MODULE,
 157         .open           = coh901318_debugfs_open,
 158         .read           = coh901318_debugfs_read,
 159 };
 160
 161
 162 static int __init init_coh901318_debugfs(void)
 163 {
 164
 165         dma_dentry = debugfs_create_dir("dma", NULL);
 166
 167         (void) debugfs_create_file("status",
 168                                    S_IFREG | S_IRUGO,
 169                                    dma_dentry, NULL,
 170                                    &coh901318_debugfs_status_operations);
 171         return 0;
 172 }
 173
 174 static void __exit exit_coh901318_debugfs(void)
 175 {
 176         debugfs_remove_recursive(dma_dentry);
 177 }
 178
 179 module_init(init_coh901318_debugfs);
 180 module_exit(exit_coh901318_debugfs);
 181 #else
 182
 183 #define COH901318_DEBUGFS_ASSIGN(x, y)
 184
 185 #endif /* CONFIG_DEBUG_FS */
 186
 187 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
 188 {
 189         return container_of(chan, struct coh901318_chan, chan);
 190 }
 191
 192 static inline dma_addr_t
 193 cohc_dev_addr(struct coh901318_chan *cohc)
 194 {
 195         return cohc->base->platform->chan_conf[cohc->id].dev_addr;
 196 }
 197
 198 static inline const struct coh901318_params *
 199 cohc_chan_param(struct coh901318_chan *cohc)
 200 {
 201         return &cohc->base->platform->chan_conf[cohc->id].param;
 202 }
 203
 204 static inline const struct coh_dma_channel *
 205 cohc_chan_conf(struct coh901318_chan *cohc)
 206 {
 207         return &cohc->base->platform->chan_conf[cohc->id];
 208 }
 209
 210 static void enable_powersave(struct coh901318_chan *cohc)
 211 {
 212         unsigned long flags;
 213         struct powersave *pm = &cohc->base->pm;
 214
 215         spin_lock_irqsave(&pm->lock, flags);
 216
 217         pm->started_channels &= ~(1ULL << cohc->id);
 218
 219         if (!pm->started_channels) {
 220                 /* DMA no longer intends to access memory */
 221                 cohc->base->platform->access_memory_state(cohc->base->dev,
 222                                                           false);
 223         }
 224
 225         spin_unlock_irqrestore(&pm->lock, flags);
 226 }
 227 static void disable_powersave(struct coh901318_chan *cohc)
 228 {
 229         unsigned long flags;
 230         struct powersave *pm = &cohc->base->pm;
 231
 232         spin_lock_irqsave(&pm->lock, flags);
 233
 234         if (!pm->started_channels) {
 235                 /* DMA intends to access memory */
 236                 cohc->base->platform->access_memory_state(cohc->base->dev,
 237                                                           true);
 238         }
 239
 240         pm->started_channels |= (1ULL << cohc->id);
 241
 242         spin_unlock_irqrestore(&pm->lock, flags);
 243 }
 244
 245 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
 246 {
 247         int channel = cohc->id;
 248         void __iomem *virtbase = cohc->base->virtbase;
 249
 250         writel(control,
 251                virtbase + COH901318_CX_CTRL +
 252                COH901318_CX_CTRL_SPACING * channel);
 253         return 0;
 254 }
 255
 256 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
 257 {
 258         int channel = cohc->id;
 259         void __iomem *virtbase = cohc->base->virtbase;
 260
 261         writel(conf,
 262                virtbase + COH901318_CX_CFG +
 263                COH901318_CX_CFG_SPACING*channel);
 264         return 0;
 265 }
 266
 267
 268 static int coh901318_start(struct coh901318_chan *cohc)
 269 {
 270         u32 val;
 271         int channel = cohc->id;
 272         void __iomem *virtbase = cohc->base->virtbase;
 273
 274         disable_powersave(cohc);
 275
 276         val = readl(virtbase + COH901318_CX_CFG +
 277                     COH901318_CX_CFG_SPACING * channel);
 278
 279         /* Enable channel */
 280         val |= COH901318_CX_CFG_CH_ENABLE;
 281         writel(val, virtbase + COH901318_CX_CFG +
 282                COH901318_CX_CFG_SPACING * channel);
 283
 284         return 0;
 285 }
 286
 287 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
 288                                       struct coh901318_lli *data)
 289 {
 290         int channel = cohc->id;
 291         void __iomem *virtbase = cohc->base->virtbase;
 292
 293         BUG_ON(readl(virtbase + COH901318_CX_STAT +
 294                      COH901318_CX_STAT_SPACING*channel) &
 295                COH901318_CX_STAT_ACTIVE);
 296
 297         writel(data->src_addr,
 298                virtbase + COH901318_CX_SRC_ADDR +
 299                COH901318_CX_SRC_ADDR_SPACING * channel);
 300
 301         writel(data->dst_addr, virtbase +
 302                COH901318_CX_DST_ADDR +
 303                COH901318_CX_DST_ADDR_SPACING * channel);
 304
 305         writel(data->link_addr, virtbase + COH901318_CX_LNK_ADDR +
 306                COH901318_CX_LNK_ADDR_SPACING * channel);
 307
 308         writel(data->control, virtbase + COH901318_CX_CTRL +
 309                COH901318_CX_CTRL_SPACING * channel);
 310
 311         return 0;
 312 }
 313 static dma_cookie_t
 314 coh901318_assign_cookie(struct coh901318_chan *cohc,
 315                         struct coh901318_desc *cohd)
 316 {
 317         dma_cookie_t cookie = cohc->chan.cookie;
 318
 319         if (++cookie < 0)
 320                 cookie = 1;
 321
 322         cohc->chan.cookie = cookie;
 323         cohd->desc.cookie = cookie;
 324
 325         return cookie;
 326 }
 327
 328 static struct coh901318_desc *
 329 coh901318_desc_get(struct coh901318_chan *cohc)
 330 {
 331         struct coh901318_desc *desc;
 332
 333         if (list_empty(&cohc->free)) {
 334                 /* alloc new desc because we're out of used ones
 335                  * TODO: alloc a pile of descs instead of just one,
 336                  * avoid many small allocations.
 337                  */
 338                 desc = kmalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
 339                 if (desc == NULL)
 340                         goto out;
 341                 INIT_LIST_HEAD(&desc->node);
 342         } else {
 343                 /* Reuse an old desc. */
 344                 desc = list_first_entry(&cohc->free,
 345                                         struct coh901318_desc,
 346                                         node);
 347                 list_del(&desc->node);
 348         }
 349
 350  out:
 351         return desc;
 352 }
 353
 354 static void
 355 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
 356 {
 357         list_add_tail(&cohd->node, &cohc->free);
 358 }
 359
 360 /* call with irq lock held */
 361 static void
 362 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 363 {
 364         list_add_tail(&desc->node, &cohc->active);
 365
 366         BUG_ON(cohc->pending_irqs != 0);
 367
 368         cohc->pending_irqs = desc->pending_irqs;
 369 }
 370
 371 static struct coh901318_desc *
 372 coh901318_first_active_get(struct coh901318_chan *cohc)
 373 {
 374         struct coh901318_desc *d;
 375
 376         if (list_empty(&cohc->active))
 377                 return NULL;
 378
 379         d = list_first_entry(&cohc->active,
 380                              struct coh901318_desc,
 381                              node);
 382         return d;
 383 }
 384
 385 static void
 386 coh901318_desc_remove(struct coh901318_desc *cohd)
 387 {
 388         list_del(&cohd->node);
 389 }
 390
 391 static void
 392 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 393 {
 394         list_add_tail(&desc->node, &cohc->queue);
 395 }
 396
 397 static struct coh901318_desc *
 398 coh901318_first_queued(struct coh901318_chan *cohc)
 399 {
 400         struct coh901318_desc *d;
 401
 402         if (list_empty(&cohc->queue))
 403                 return NULL;
 404
 405         d = list_first_entry(&cohc->queue,
 406                              struct coh901318_desc,
 407                              node);
 408         return d;
 409 }
 410
 411 /*
 412  * DMA start/stop controls
 413  */
 414 u32 coh901318_get_bytes_left(struct dma_chan *chan)
 415 {
 416         unsigned long flags;
 417         u32 ret;
 418         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 419
 420         spin_lock_irqsave(&cohc->lock, flags);
 421
 422         /* Read transfer count value */
 423         ret = readl(cohc->base->virtbase +
 424                     COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
 425                     cohc->id) & COH901318_CX_CTRL_TC_VALUE_MASK;
 426
 427         spin_unlock_irqrestore(&cohc->lock, flags);
 428
 429         return ret;
 430 }
 431 EXPORT_SYMBOL(coh901318_get_bytes_left);
 432
 433
 434 /* Stops a transfer without losing data. Enables power save.
 435    Use this function in conjunction with coh901318_continue(..)
 436 */
 437 void coh901318_stop(struct dma_chan *chan)
 438 {
 439         u32 val;
 440         unsigned long flags;
 441         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 442         int channel = cohc->id;
 443         void __iomem *virtbase = cohc->base->virtbase;
 444
 445         spin_lock_irqsave(&cohc->lock, flags);
 446
 447         /* Disable channel in HW */
 448         val = readl(virtbase + COH901318_CX_CFG +
 449                     COH901318_CX_CFG_SPACING * channel);
 450
 451         /* Stopping infinit transfer */
 452         if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
 453             (val & COH901318_CX_CFG_CH_ENABLE))
 454                 cohc->stopped = 1;
 455
 456
 457         val &= ~COH901318_CX_CFG_CH_ENABLE;
 458         /* Enable twice, HW bug work around */
 459         writel(val, virtbase + COH901318_CX_CFG +
 460                COH901318_CX_CFG_SPACING * channel);
 461         writel(val, virtbase + COH901318_CX_CFG +
 462                COH901318_CX_CFG_SPACING * channel);
 463
 464         /* Spin-wait for it to actually go inactive */
 465         while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
 466                      channel) & COH901318_CX_STAT_ACTIVE)
 467                 cpu_relax();
 468
 469         /* Check if we stopped an active job */
 470         if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
 471                    channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
 472                 cohc->stopped = 1;
 473
 474         enable_powersave(cohc);
 475
 476         spin_unlock_irqrestore(&cohc->lock, flags);
 477 }
 478 EXPORT_SYMBOL(coh901318_stop);
 479
 480 /* Continues a transfer that has been stopped via 300_dma_stop(..).
 481    Power save is handled.
 482 */
 483 void coh901318_continue(struct dma_chan *chan)
 484 {
 485         u32 val;
 486         unsigned long flags;
 487         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 488         int channel = cohc->id;
 489
 490         spin_lock_irqsave(&cohc->lock, flags);
 491
 492         disable_powersave(cohc);
 493
 494         if (cohc->stopped) {
 495                 /* Enable channel in HW */
 496                 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
 497                             COH901318_CX_CFG_SPACING * channel);
 498
 499                 val |= COH901318_CX_CFG_CH_ENABLE;
 500
 501                 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
 502                        COH901318_CX_CFG_SPACING*channel);
 503
 504                 cohc->stopped = 0;
 505         }
 506
 507         spin_unlock_irqrestore(&cohc->lock, flags);
 508 }
 509 EXPORT_SYMBOL(coh901318_continue);
 510
 511 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
 512 {
 513         unsigned int ch_nr = (unsigned int) chan_id;
 514
 515         if (ch_nr == to_coh901318_chan(chan)->id)
 516                 return true;
 517
 518         return false;
 519 }
 520 EXPORT_SYMBOL(coh901318_filter_id);
 521
 522 /*
 523  * DMA channel allocation
 524  */
 525 static int coh901318_config(struct coh901318_chan *cohc,
 526                             struct coh901318_params *param)
 527 {
 528         unsigned long flags;
 529         const struct coh901318_params *p;
 530         int channel = cohc->id;
 531         void __iomem *virtbase = cohc->base->virtbase;
 532
 533         spin_lock_irqsave(&cohc->lock, flags);
 534
 535         if (param)
 536                 p = param;
 537         else
 538                 p = &cohc->base->platform->chan_conf[channel].param;
 539
 540         /* Clear any pending BE or TC interrupt */
 541         if (channel < 32) {
 542                 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
 543                 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
 544         } else {
 545                 writel(1 << (channel - 32), virtbase +
 546                        COH901318_BE_INT_CLEAR2);
 547                 writel(1 << (channel - 32), virtbase +
 548                        COH901318_TC_INT_CLEAR2);
 549         }
 550
 551         coh901318_set_conf(cohc, p->config);
 552         coh901318_set_ctrl(cohc, p->ctrl_lli_last);
 553
 554         spin_unlock_irqrestore(&cohc->lock, flags);
 555
 556         return 0;
 557 }
 558
 559 /* must lock when calling this function
 560  * start queued jobs, if any
 561  * TODO: start all queued jobs in one go
 562  *
 563  * Returns descriptor if queued job is started otherwise NULL.
 564  * If the queue is empty NULL is returned.
 565  */
 566 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
 567 {
 568         struct coh901318_desc *cohd_que;
 569
 570         /* start queued jobs, if any
 571          * TODO: transmit all queued jobs in one go
 572          */
 573         cohd_que = coh901318_first_queued(cohc);
 574
 575         if (cohd_que != NULL) {
 576                 /* Remove from queue */
 577                 coh901318_desc_remove(cohd_que);
 578                 /* initiate DMA job */
 579                 cohc->busy = 1;
 580
 581                 coh901318_desc_submit(cohc, cohd_que);
 582
 583                 coh901318_prep_linked_list(cohc, cohd_que->data);
 584
 585                 /* start dma job */
 586                 coh901318_start(cohc);
 587
 588         }
 589
 590         return cohd_que;
 591 }
 592
 593 /*
 594  * This tasklet is called from the interrupt handler to
 595  * handle each descriptor (DMA job) that is sent to a channel.
 596  */
 597 static void dma_tasklet(unsigned long data)
 598 {
 599         struct coh901318_chan *cohc = (struct coh901318_chan *) data;
 600         struct coh901318_desc *cohd_fin;
 601         unsigned long flags;
 602         dma_async_tx_callback callback;
 603         void *callback_param;
 604
 605         dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
 606                  " nbr_active_done %ld\n", __func__,
 607                  cohc->id, cohc->nbr_active_done);
 608
 609         spin_lock_irqsave(&cohc->lock, flags);
 610
 611         /* get first active descriptor entry from list */
 612         cohd_fin = coh901318_first_active_get(cohc);
 613
 614         BUG_ON(cohd_fin->pending_irqs == 0);
 615
 616         if (cohd_fin == NULL)
 617                 goto err;
 618
 619         cohd_fin->pending_irqs--;
 620         cohc->completed = cohd_fin->desc.cookie;
 621
 622         if (cohc->nbr_active_done == 0)
 623                 return;
 624
 625         if (!cohd_fin->pending_irqs) {
 626                 /* release the lli allocation*/
 627                 coh901318_lli_free(&cohc->base->pool, &cohd_fin->data);
 628         }
 629
 630         dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d pending_irqs %d"
 631                  " nbr_active_done %ld\n", __func__,
 632                  cohc->id, cohc->pending_irqs, cohc->nbr_active_done);
 633
 634         /* callback to client */
 635         callback = cohd_fin->desc.callback;
 636         callback_param = cohd_fin->desc.callback_param;
 637
 638         if (!cohd_fin->pending_irqs) {
 639                 coh901318_desc_remove(cohd_fin);
 640
 641                 /* return desc to free-list */
 642                 coh901318_desc_free(cohc, cohd_fin);
 643         }
 644
 645         /*
 646          * If another interrupt fired while the tasklet was scheduling,
 647          * we don't get called twice, so we have this number of active
 648          * counter that keep track of the number of IRQs expected to
 649          * be handled for this channel. If there happen to be more than
 650          * one IRQ to be ack:ed, we simply schedule this tasklet again.
 651          */
 652         if (cohc->nbr_active_done)
 653                 cohc->nbr_active_done--;
 654
 655         if (cohc->nbr_active_done) {
 656                 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
 657                         "came in while we were scheduling this tasklet\n");
 658                 if (cohc_chan_conf(cohc)->priority_high)
 659                         tasklet_hi_schedule(&cohc->tasklet);
 660                 else
 661                         tasklet_schedule(&cohc->tasklet);
 662         }
 663         spin_unlock_irqrestore(&cohc->lock, flags);
 664
 665         if (callback)
 666                 callback(callback_param);
 667
 668         return;
 669
 670  err:
 671         spin_unlock_irqrestore(&cohc->lock, flags);
 672         dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
 673 }
 674
 675
 676 /* called from interrupt context */
 677 static void dma_tc_handle(struct coh901318_chan *cohc)
 678 {
 679         BUG_ON(!cohc->allocated && (list_empty(&cohc->active) ||
 680                                     list_empty(&cohc->queue)));
 681
 682         if (!cohc->allocated)
 683                 return;
 684
 685         BUG_ON(cohc->pending_irqs == 0);
 686
 687         cohc->pending_irqs--;
 688         cohc->nbr_active_done++;
 689
 690         if (cohc->pending_irqs == 0 && coh901318_queue_start(cohc) == NULL)
 691                 cohc->busy = 0;
 692
 693         BUG_ON(list_empty(&cohc->active));
 694
 695         if (cohc_chan_conf(cohc)->priority_high)
 696                 tasklet_hi_schedule(&cohc->tasklet);
 697         else
 698                 tasklet_schedule(&cohc->tasklet);
 699 }
 700
 701
 702 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 703 {
 704         u32 status1;
 705         u32 status2;
 706         int i;
 707         int ch;
 708         struct coh901318_base *base  = dev_id;
 709         struct coh901318_chan *cohc;
 710         void __iomem *virtbase = base->virtbase;
 711
 712         status1 = readl(virtbase + COH901318_INT_STATUS1);
 713         status2 = readl(virtbase + COH901318_INT_STATUS2);
 714
 715         if (unlikely(status1 == 0 && status2 == 0)) {
 716                 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
 717                 return IRQ_HANDLED;
 718         }
 719
 720         /* TODO: consider handle IRQ in tasklet here to
 721          *       minimize interrupt latency */
 722
 723         /* Check the first 32 DMA channels for IRQ */
 724         while (status1) {
 725                 /* Find first bit set, return as a number. */
 726                 i = ffs(status1) - 1;
 727                 ch = i;
 728
 729                 cohc = &base->chans[ch];
 730                 spin_lock(&cohc->lock);
 731
 732                 /* Mask off this bit */
 733                 status1 &= ~(1 << i);
 734                 /* Check the individual channel bits */
 735                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
 736                         dev_crit(COHC_2_DEV(cohc),
 737                                  "DMA bus error on channel %d!\n", ch);
 738                         BUG_ON(1);
 739                         /* Clear BE interrupt */
 740                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
 741                 } else {
 742                         /* Caused by TC, really? */
 743                         if (unlikely(!test_bit(i, virtbase +
 744                                                COH901318_TC_INT_STATUS1))) {
 745                                 dev_warn(COHC_2_DEV(cohc),
 746                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 747                                 /* Clear TC interrupt */
 748                                 BUG_ON(1);
 749                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 750                         } else {
 751                                 /* Enable powersave if transfer has finished */
 752                                 if (!(readl(virtbase + COH901318_CX_STAT +
 753                                             COH901318_CX_STAT_SPACING*ch) &
 754                                       COH901318_CX_STAT_ENABLED)) {
 755                                         enable_powersave(cohc);
 756                                 }
 757
 758                                 /* Must clear TC interrupt before calling
 759                                  * dma_tc_handle
 760                                  * in case tc_handle initate a new dma job
 761                                  */
 762                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 763
 764                                 dma_tc_handle(cohc);
 765                         }
 766                 }
 767                 spin_unlock(&cohc->lock);
 768         }
 769
 770         /* Check the remaining 32 DMA channels for IRQ */
 771         while (status2) {
 772                 /* Find first bit set, return as a number. */
 773                 i = ffs(status2) - 1;
 774                 ch = i + 32;
 775                 cohc = &base->chans[ch];
 776                 spin_lock(&cohc->lock);
 777
 778                 /* Mask off this bit */
 779                 status2 &= ~(1 << i);
 780                 /* Check the individual channel bits */
 781                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
 782                         dev_crit(COHC_2_DEV(cohc),
 783                                  "DMA bus error on channel %d!\n", ch);
 784                         /* Clear BE interrupt */
 785                         BUG_ON(1);
 786                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
 787                 } else {
 788                         /* Caused by TC, really? */
 789                         if (unlikely(!test_bit(i, virtbase +
 790                                                COH901318_TC_INT_STATUS2))) {
 791                                 dev_warn(COHC_2_DEV(cohc),
 792                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 793                                 /* Clear TC interrupt */
 794                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 795                                 BUG_ON(1);
 796                         } else {
 797                                 /* Enable powersave if transfer has finished */
 798                                 if (!(readl(virtbase + COH901318_CX_STAT +
 799                                             COH901318_CX_STAT_SPACING*ch) &
 800                                       COH901318_CX_STAT_ENABLED)) {
 801                                         enable_powersave(cohc);
 802                                 }
 803                                 /* Must clear TC interrupt before calling
 804                                  * dma_tc_handle
 805                                  * in case tc_handle initate a new dma job
 806                                  */
 807                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 808
 809                                 dma_tc_handle(cohc);
 810                         }
 811                 }
 812                 spin_unlock(&cohc->lock);
 813         }
 814
 815         return IRQ_HANDLED;
 816 }
 817
 818 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
 819 {
 820         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 821
 822         dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
 823                  __func__, cohc->id);
 824
 825         if (chan->client_count > 1)
 826                 return -EBUSY;
 827
 828         coh901318_config(cohc, NULL);
 829
 830         cohc->allocated = 1;
 831         cohc->completed = chan->cookie = 1;
 832
 833         return 1;
 834 }
 835
 836 static void
 837 coh901318_free_chan_resources(struct dma_chan *chan)
 838 {
 839         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 840         int channel = cohc->id;
 841         unsigned long flags;
 842
 843         spin_lock_irqsave(&cohc->lock, flags);
 844
 845         /* Disable HW */
 846         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
 847                COH901318_CX_CFG_SPACING*channel);
 848         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
 849                COH901318_CX_CTRL_SPACING*channel);
 850
 851         cohc->allocated = 0;
 852
 853         spin_unlock_irqrestore(&cohc->lock, flags);
 854
 855         chan->device->device_terminate_all(chan);
 856 }
 857
 858
 859 static dma_cookie_t
 860 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
 861 {
 862         struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
 863                                                    desc);
 864         struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
 865         unsigned long flags;
 866
 867         spin_lock_irqsave(&cohc->lock, flags);
 868
 869         tx->cookie = coh901318_assign_cookie(cohc, cohd);
 870
 871         coh901318_desc_queue(cohc, cohd);
 872
 873         spin_unlock_irqrestore(&cohc->lock, flags);
 874
 875         return tx->cookie;
 876 }
 877
 878 static struct dma_async_tx_descriptor *
 879 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 880                       size_t size, unsigned long flags)
 881 {
 882         struct coh901318_lli *data;
 883         struct coh901318_desc *cohd;
 884         unsigned long flg;
 885         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 886         int lli_len;
 887         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
 888
 889         spin_lock_irqsave(&cohc->lock, flg);
 890
 891         dev_vdbg(COHC_2_DEV(cohc),
 892                  "[%s] channel %d src 0x%x dest 0x%x size %d\n",
 893                  __func__, cohc->id, src, dest, size);
 894
 895         if (flags & DMA_PREP_INTERRUPT)
 896                 /* Trigger interrupt after last lli */
 897                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
 898
 899         lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
 900         if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
 901                 lli_len++;
 902
 903         data = coh901318_lli_alloc(&cohc->base->pool, lli_len);
 904
 905         if (data == NULL)
 906                 goto err;
 907
 908         cohd = coh901318_desc_get(cohc);
 909         cohd->sg = NULL;
 910         cohd->sg_len = 0;
 911         cohd->data = data;
 912
 913         cohd->pending_irqs =
 914                 coh901318_lli_fill_memcpy(
 915                                 &cohc->base->pool, data, src, size, dest,
 916                                 cohc_chan_param(cohc)->ctrl_lli_chained,
 917                                 ctrl_last);
 918         cohd->flags = flags;
 919
 920         COH_DBG(coh901318_list_print(cohc, data));
 921
 922         dma_async_tx_descriptor_init(&cohd->desc, chan);
 923
 924         cohd->desc.tx_submit = coh901318_tx_submit;
 925
 926         spin_unlock_irqrestore(&cohc->lock, flg);
 927
 928         return &cohd->desc;
 929  err:
 930         spin_unlock_irqrestore(&cohc->lock, flg);
 931         return NULL;
 932 }
 933
 934 static struct dma_async_tx_descriptor *
 935 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 936                         unsigned int sg_len, enum dma_data_direction direction,
 937                         unsigned long flags)
 938 {
 939         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 940         struct coh901318_lli *data;
 941         struct coh901318_desc *cohd;
 942         struct scatterlist *sg;
 943         int len = 0;
 944         int size;
 945         int i;
 946         u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
 947         u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
 948         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
 949         unsigned long flg;
 950
 951         if (!sgl)
 952                 goto out;
 953         if (sgl->length == 0)
 954                 goto out;
 955
 956         spin_lock_irqsave(&cohc->lock, flg);
 957
 958         dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
 959                  __func__, sg_len, direction);
 960
 961         if (flags & DMA_PREP_INTERRUPT)
 962                 /* Trigger interrupt after last lli */
 963                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
 964
 965         cohd = coh901318_desc_get(cohc);
 966         cohd->sg = NULL;
 967         cohd->sg_len = 0;
 968         cohd->dir = direction;
 969
 970         if (direction == DMA_TO_DEVICE) {
 971                 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
 972                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
 973
 974                 ctrl_chained |= tx_flags;
 975                 ctrl_last |= tx_flags;
 976                 ctrl |= tx_flags;
 977         } else if (direction == DMA_FROM_DEVICE) {
 978                 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
 979                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
 980
 981                 ctrl_chained |= rx_flags;
 982                 ctrl_last |= rx_flags;
 983                 ctrl |= rx_flags;
 984         } else
 985                 goto err_direction;
 986
 987         dma_async_tx_descriptor_init(&cohd->desc, chan);
 988
 989         cohd->desc.tx_submit = coh901318_tx_submit;
 990
 991
 992         /* The dma only supports transmitting packages up to
 993          * MAX_DMA_PACKET_SIZE. Calculate to total number of
 994          * dma elemts required to send the entire sg list
 995          */
 996         for_each_sg(sgl, sg, sg_len, i) {
 997                 unsigned int factor;
 998                 size = sg_dma_len(sg);
 999
1000                 if (size <= MAX_DMA_PACKET_SIZE) {
1001                         len++;
1002                         continue;
1003                 }
1004
1005                 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1006                 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1007                         factor++;
1008
1009                 len += factor;
1010         }
1011
1012         pr_debug("Allocate %d lli:s for this transfer\n", len);
1013         data = coh901318_lli_alloc(&cohc->base->pool, len);
1014
1015         if (data == NULL)
1016                 goto err_dma_alloc;
1017
1018         /* initiate allocated data list */
1019         cohd->pending_irqs =
1020                 coh901318_lli_fill_sg(&cohc->base->pool, data, sgl, sg_len,
1021                                       cohc_dev_addr(cohc),
1022                                       ctrl_chained,
1023                                       ctrl,
1024                                       ctrl_last,
1025                                       direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1026         cohd->data = data;
1027
1028         cohd->flags = flags;
1029
1030         COH_DBG(coh901318_list_print(cohc, data));
1031
1032         spin_unlock_irqrestore(&cohc->lock, flg);
1033
1034         return &cohd->desc;
1035  err_dma_alloc:
1036  err_direction:
1037         coh901318_desc_remove(cohd);
1038         coh901318_desc_free(cohc, cohd);
1039         spin_unlock_irqrestore(&cohc->lock, flg);
1040  out:
1041         return NULL;
1042 }
1043
1044 static enum dma_status
1045 coh901318_is_tx_complete(struct dma_chan *chan,
1046                          dma_cookie_t cookie, dma_cookie_t *done,
1047                          dma_cookie_t *used)
1048 {
1049         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1050         dma_cookie_t last_used;
1051         dma_cookie_t last_complete;
1052         int ret;
1053
1054         last_complete = cohc->completed;
1055         last_used = chan->cookie;
1056
1057         ret = dma_async_is_complete(cookie, last_complete, last_used);
1058
1059         if (done)
1060                 *done = last_complete;
1061         if (used)
1062                 *used = last_used;
1063
1064         return ret;
1065 }
1066
1067 static void
1068 coh901318_issue_pending(struct dma_chan *chan)
1069 {
1070         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1071         unsigned long flags;
1072
1073         spin_lock_irqsave(&cohc->lock, flags);
1074
1075         /* Busy means that pending jobs are already being processed */
1076         if (!cohc->busy)
1077                 coh901318_queue_start(cohc);
1078
1079         spin_unlock_irqrestore(&cohc->lock, flags);
1080 }
1081
1082 static void
1083 coh901318_terminate_all(struct dma_chan *chan)
1084 {
1085         unsigned long flags;
1086         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1087         struct coh901318_desc *cohd;
1088         void __iomem *virtbase = cohc->base->virtbase;
1089
1090         coh901318_stop(chan);
1091
1092         spin_lock_irqsave(&cohc->lock, flags);
1093
1094         /* Clear any pending BE or TC interrupt */
1095         if (cohc->id < 32) {
1096                 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1097                 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1098         } else {
1099                 writel(1 << (cohc->id - 32), virtbase +
1100                        COH901318_BE_INT_CLEAR2);
1101                 writel(1 << (cohc->id - 32), virtbase +
1102                        COH901318_TC_INT_CLEAR2);
1103         }
1104
1105         enable_powersave(cohc);
1106
1107         while ((cohd = coh901318_first_active_get(cohc))) {
1108                 /* release the lli allocation*/
1109                 coh901318_lli_free(&cohc->base->pool, &cohd->data);
1110
1111                 /* return desc to free-list */
1112                 coh901318_desc_remove(cohd);
1113                 coh901318_desc_free(cohc, cohd);
1114         }
1115
1116         while ((cohd = coh901318_first_queued(cohc))) {
1117                 /* release the lli allocation*/
1118                 coh901318_lli_free(&cohc->base->pool, &cohd->data);
1119
1120                 /* return desc to free-list */
1121                 coh901318_desc_remove(cohd);
1122                 coh901318_desc_free(cohc, cohd);
1123         }
1124
1125
1126         cohc->nbr_active_done = 0;
1127         cohc->busy = 0;
1128         cohc->pending_irqs = 0;
1129
1130         spin_unlock_irqrestore(&cohc->lock, flags);
1131 }
1132 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1133                          struct coh901318_base *base)
1134 {
1135         int chans_i;
1136         int i = 0;
1137         struct coh901318_chan *cohc;
1138
1139         INIT_LIST_HEAD(&dma->channels);
1140
1141         for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1142                 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1143                         cohc = &base->chans[i];
1144
1145                         cohc->base = base;
1146                         cohc->chan.device = dma;
1147                         cohc->id = i;
1148
1149                         /* TODO: do we really need this lock if only one
1150                          * client is connected to each channel?
1151                          */
1152
1153                         spin_lock_init(&cohc->lock);
1154
1155                         cohc->pending_irqs = 0;
1156                         cohc->nbr_active_done = 0;
1157                         cohc->busy = 0;
1158                         INIT_LIST_HEAD(&cohc->free);
1159                         INIT_LIST_HEAD(&cohc->active);
1160                         INIT_LIST_HEAD(&cohc->queue);
1161
1162                         tasklet_init(&cohc->tasklet, dma_tasklet,
1163                                      (unsigned long) cohc);
1164
1165                         list_add_tail(&cohc->chan.device_node,
1166                                       &dma->channels);
1167                 }
1168         }
1169 }
1170
1171 static int __init coh901318_probe(struct platform_device *pdev)
1172 {
1173         int err = 0;
1174         struct coh901318_platform *pdata;
1175         struct coh901318_base *base;
1176         int irq;
1177         struct resource *io;
1178
1179         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1180         if (!io)
1181                 goto err_get_resource;
1182
1183         /* Map DMA controller registers to virtual memory */
1184         if (request_mem_region(io->start,
1185                                resource_size(io),
1186                                pdev->dev.driver->name) == NULL) {
1187                 err = -EBUSY;
1188                 goto err_request_mem;
1189         }
1190
1191         pdata = pdev->dev.platform_data;
1192         if (!pdata)
1193                 goto err_no_platformdata;
1194
1195         base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1196                        pdata->max_channels *
1197                        sizeof(struct coh901318_chan),
1198                        GFP_KERNEL);
1199         if (!base)
1200                 goto err_alloc_coh_dma_channels;
1201
1202         base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1203
1204         base->virtbase = ioremap(io->start, resource_size(io));
1205         if (!base->virtbase) {
1206                 err = -ENOMEM;
1207                 goto err_no_ioremap;
1208         }
1209
1210         base->dev = &pdev->dev;
1211         base->platform = pdata;
1212         spin_lock_init(&base->pm.lock);
1213         base->pm.started_channels = 0;
1214
1215         COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1216
1217         platform_set_drvdata(pdev, base);
1218
1219         irq = platform_get_irq(pdev, 0);
1220         if (irq < 0)
1221                 goto err_no_irq;
1222
1223         err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1224                           "coh901318", base);
1225         if (err) {
1226                 dev_crit(&pdev->dev,
1227                          "Cannot allocate IRQ for DMA controller!\n");
1228                 goto err_request_irq;
1229         }
1230
1231         err = coh901318_pool_create(&base->pool, &pdev->dev,
1232                                     sizeof(struct coh901318_lli),
1233                                     32);
1234         if (err)
1235                 goto err_pool_create;
1236
1237         /* init channels for device transfers */
1238         coh901318_base_init(&base->dma_slave,  base->platform->chans_slave,
1239                             base);
1240
1241         dma_cap_zero(base->dma_slave.cap_mask);
1242         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1243
1244         base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1245         base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1246         base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1247         base->dma_slave.device_is_tx_complete = coh901318_is_tx_complete;
1248         base->dma_slave.device_issue_pending = coh901318_issue_pending;
1249         base->dma_slave.device_terminate_all = coh901318_terminate_all;
1250         base->dma_slave.dev = &pdev->dev;
1251
1252         err = dma_async_device_register(&base->dma_slave);
1253
1254         if (err)
1255                 goto err_register_slave;
1256
1257         /* init channels for memcpy */
1258         coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1259                             base);
1260
1261         dma_cap_zero(base->dma_memcpy.cap_mask);
1262         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1263
1264         base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1265         base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1266         base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1267         base->dma_memcpy.device_is_tx_complete = coh901318_is_tx_complete;
1268         base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1269         base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
1270         base->dma_memcpy.dev = &pdev->dev;
1271         err = dma_async_device_register(&base->dma_memcpy);
1272
1273         if (err)
1274                 goto err_register_memcpy;
1275
1276         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1277                 (u32) base->virtbase);
1278
1279         return err;
1280
1281  err_register_memcpy:
1282         dma_async_device_unregister(&base->dma_slave);
1283  err_register_slave:
1284         coh901318_pool_destroy(&base->pool);
1285  err_pool_create:
1286         free_irq(platform_get_irq(pdev, 0), base);
1287  err_request_irq:
1288  err_no_irq:
1289         iounmap(base->virtbase);
1290  err_no_ioremap:
1291         kfree(base);
1292  err_alloc_coh_dma_channels:
1293  err_no_platformdata:
1294         release_mem_region(pdev->resource->start,
1295                            resource_size(pdev->resource));
1296  err_request_mem:
1297  err_get_resource:
1298         return err;
1299 }
1300
1301 static int __exit coh901318_remove(struct platform_device *pdev)
1302 {
1303         struct coh901318_base *base = platform_get_drvdata(pdev);
1304
1305         dma_async_device_unregister(&base->dma_memcpy);
1306         dma_async_device_unregister(&base->dma_slave);
1307         coh901318_pool_destroy(&base->pool);
1308         free_irq(platform_get_irq(pdev, 0), base);
1309         iounmap(base->virtbase);
1310         kfree(base);
1311         release_mem_region(pdev->resource->start,
1312                            resource_size(pdev->resource));
1313         return 0;
1314 }
1315
1316
1317 static struct platform_driver coh901318_driver = {
1318         .remove = __exit_p(coh901318_remove),
1319         .driver = {
1320                 .name   = "coh901318",
1321         },
1322 };
1323
1324 int __init coh901318_init(void)
1325 {
1326         return platform_driver_probe(&coh901318_driver, coh901318_probe);
1327 }
1328 subsys_initcall(coh901318_init);
1329
1330 void __exit coh901318_exit(void)
1331 {
1332         platform_driver_unregister(&coh901318_driver);
1333 }
1334 module_exit(coh901318_exit);
1335
1336 MODULE_LICENSE("GPL");
1337 MODULE_AUTHOR("Per Friden");