SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/crypto/talitos.c

   1 /*
   2  * talitos - Freescale Integrated Security Engine (SEC) device driver
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor, Inc.
   5  *
   6  * Scatterlist Crypto API glue code copied from files with the following:
   7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
   8  *
   9  * Crypto algorithm registration code copied from hifn driver:
  10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11  * All rights reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/io.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/rtnetlink.h>
  40
  41 #include <crypto/algapi.h>
  42 #include <crypto/aes.h>
  43 #include <crypto/des.h>
  44 #include <crypto/sha.h>
  45 #include <crypto/aead.h>
  46 #include <crypto/authenc.h>
  47
  48 #include "talitos.h"
  49
  50 #define TALITOS_TIMEOUT 100000
  51 #define TALITOS_MAX_DATA_LEN 65535
  52
  53 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
  54 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
  55 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
  56
  57 /* descriptor pointer entry */
  58 struct talitos_ptr {
  59         __be16 len;     /* length */
  60         u8 j_extent;    /* jump to sg link table and/or extent */
  61         u8 eptr;        /* extended address */
  62         __be32 ptr;     /* address */
  63 };
  64
  65 /* descriptor */
  66 struct talitos_desc {
  67         __be32 hdr;                     /* header high bits */
  68         __be32 hdr_lo;                  /* header low bits */
  69         struct talitos_ptr ptr[7];      /* ptr/len pair array */
  70 };
  71
  72 /**
  73  * talitos_request - descriptor submission request
  74  * @desc: descriptor pointer (kernel virtual)
  75  * @dma_desc: descriptor's physical bus address
  76  * @callback: whom to call when descriptor processing is done
  77  * @context: caller context (optional)
  78  */
  79 struct talitos_request {
  80         struct talitos_desc *desc;
  81         dma_addr_t dma_desc;
  82         void (*callback) (struct device *dev, struct talitos_desc *desc,
  83                           void *context, int error);
  84         void *context;
  85 };
  86
  87 struct talitos_private {
  88         struct device *dev;
  89         struct of_device *ofdev;
  90         void __iomem *reg;
  91         int irq;
  92
  93         /* SEC version geometry (from device tree node) */
  94         unsigned int num_channels;
  95         unsigned int chfifo_len;
  96         unsigned int exec_units;
  97         unsigned int desc_types;
  98
  99         /* SEC Compatibility info */
 100         unsigned long features;
 101
 102         /* next channel to be assigned next incoming descriptor */
 103         atomic_t last_chan;
 104
 105         /* per-channel number of requests pending in channel h/w fifo */
 106         atomic_t *submit_count;
 107
 108         /* per-channel request fifo */
 109         struct talitos_request **fifo;
 110
 111         /*
 112          * length of the request fifo
 113          * fifo_len is chfifo_len rounded up to next power of 2
 114          * so we can use bitwise ops to wrap
 115          */
 116         unsigned int fifo_len;
 117
 118         /* per-channel index to next free descriptor request */
 119         int *head;
 120
 121         /* per-channel index to next in-progress/done descriptor request */
 122         int *tail;
 123
 124         /* per-channel request submission (head) and release (tail) locks */
 125         spinlock_t *head_lock;
 126         spinlock_t *tail_lock;
 127
 128         /* request callback tasklet */
 129         struct tasklet_struct done_task;
 130
 131         /* list of registered algorithms */
 132         struct list_head alg_list;
 133
 134         /* hwrng device */
 135         struct hwrng rng;
 136 };
 137
 138 /* .features flag */
 139 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
 140
 141 /*
 142  * map virtual single (contiguous) pointer to h/w descriptor pointer
 143  */
 144 static void map_single_talitos_ptr(struct device *dev,
 145                                    struct talitos_ptr *talitos_ptr,
 146                                    unsigned short len, void *data,
 147                                    unsigned char extent,
 148                                    enum dma_data_direction dir)
 149 {
 150         talitos_ptr->len = cpu_to_be16(len);
 151         talitos_ptr->ptr = cpu_to_be32(dma_map_single(dev, data, len, dir));
 152         talitos_ptr->j_extent = extent;
 153 }
 154
 155 /*
 156  * unmap bus single (contiguous) h/w descriptor pointer
 157  */
 158 static void unmap_single_talitos_ptr(struct device *dev,
 159                                      struct talitos_ptr *talitos_ptr,
 160                                      enum dma_data_direction dir)
 161 {
 162         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
 163                          be16_to_cpu(talitos_ptr->len), dir);
 164 }
 165
 166 static int reset_channel(struct device *dev, int ch)
 167 {
 168         struct talitos_private *priv = dev_get_drvdata(dev);
 169         unsigned int timeout = TALITOS_TIMEOUT;
 170
 171         setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
 172
 173         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
 174                && --timeout)
 175                 cpu_relax();
 176
 177         if (timeout == 0) {
 178                 dev_err(dev, "failed to reset channel %d\n", ch);
 179                 return -EIO;
 180         }
 181
 182         /* set done writeback and IRQ */
 183         setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_CDWE |
 184                   TALITOS_CCCR_LO_CDIE);
 185
 186         return 0;
 187 }
 188
 189 static int reset_device(struct device *dev)
 190 {
 191         struct talitos_private *priv = dev_get_drvdata(dev);
 192         unsigned int timeout = TALITOS_TIMEOUT;
 193
 194         setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
 195
 196         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
 197                && --timeout)
 198                 cpu_relax();
 199
 200         if (timeout == 0) {
 201                 dev_err(dev, "failed to reset device\n");
 202                 return -EIO;
 203         }
 204
 205         return 0;
 206 }
 207
 208 /*
 209  * Reset and initialize the device
 210  */
 211 static int init_device(struct device *dev)
 212 {
 213         struct talitos_private *priv = dev_get_drvdata(dev);
 214         int ch, err;
 215
 216         /*
 217          * Master reset
 218          * errata documentation: warning: certain SEC interrupts
 219          * are not fully cleared by writing the MCR:SWR bit,
 220          * set bit twice to completely reset
 221          */
 222         err = reset_device(dev);
 223         if (err)
 224                 return err;
 225
 226         err = reset_device(dev);
 227         if (err)
 228                 return err;
 229
 230         /* reset channels */
 231         for (ch = 0; ch < priv->num_channels; ch++) {
 232                 err = reset_channel(dev, ch);
 233                 if (err)
 234                         return err;
 235         }
 236
 237         /* enable channel done and error interrupts */
 238         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 239         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 240
 241         return 0;
 242 }
 243
 244 /**
 245  * talitos_submit - submits a descriptor to the device for processing
 246  * @dev:        the SEC device to be used
 247  * @desc:       the descriptor to be processed by the device
 248  * @callback:   whom to call when processing is complete
 249  * @context:    a handle for use by caller (optional)
 250  *
 251  * desc must contain valid dma-mapped (bus physical) address pointers.
 252  * callback must check err and feedback in descriptor header
 253  * for device processing status.
 254  */
 255 static int talitos_submit(struct device *dev, struct talitos_desc *desc,
 256                           void (*callback)(struct device *dev,
 257                                            struct talitos_desc *desc,
 258                                            void *context, int error),
 259                           void *context)
 260 {
 261         struct talitos_private *priv = dev_get_drvdata(dev);
 262         struct talitos_request *request;
 263         unsigned long flags, ch;
 264         int head;
 265
 266         /* select done notification */
 267         desc->hdr |= DESC_HDR_DONE_NOTIFY;
 268
 269         /* emulate SEC's round-robin channel fifo polling scheme */
 270         ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
 271
 272         spin_lock_irqsave(&priv->head_lock[ch], flags);
 273
 274         if (!atomic_inc_not_zero(&priv->submit_count[ch])) {
 275                 /* h/w fifo is full */
 276                 spin_unlock_irqrestore(&priv->head_lock[ch], flags);
 277                 return -EAGAIN;
 278         }
 279
 280         head = priv->head[ch];
 281         request = &priv->fifo[ch][head];
 282
 283         /* map descriptor and save caller data */
 284         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
 285                                            DMA_BIDIRECTIONAL);
 286         request->callback = callback;
 287         request->context = context;
 288
 289         /* increment fifo head */
 290         priv->head[ch] = (priv->head[ch] + 1) & (priv->fifo_len - 1);
 291
 292         smp_wmb();
 293         request->desc = desc;
 294
 295         /* GO! */
 296         wmb();
 297         out_be32(priv->reg + TALITOS_FF_LO(ch), request->dma_desc);
 298
 299         spin_unlock_irqrestore(&priv->head_lock[ch], flags);
 300
 301         return -EINPROGRESS;
 302 }
 303
 304 /*
 305  * process what was done, notify callback of error if not
 306  */
 307 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
 308 {
 309         struct talitos_private *priv = dev_get_drvdata(dev);
 310         struct talitos_request *request, saved_req;
 311         unsigned long flags;
 312         int tail, status;
 313
 314         spin_lock_irqsave(&priv->tail_lock[ch], flags);
 315
 316         tail = priv->tail[ch];
 317         while (priv->fifo[ch][tail].desc) {
 318                 request = &priv->fifo[ch][tail];
 319
 320                 /* descriptors with their done bits set don't get the error */
 321                 rmb();
 322                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
 323                         status = 0;
 324                 else
 325                         if (!error)
 326                                 break;
 327                         else
 328                                 status = error;
 329
 330                 dma_unmap_single(dev, request->dma_desc,
 331                         sizeof(struct talitos_desc), DMA_BIDIRECTIONAL);
 332
 333                 /* copy entries so we can call callback outside lock */
 334                 saved_req.desc = request->desc;
 335                 saved_req.callback = request->callback;
 336                 saved_req.context = request->context;
 337
 338                 /* release request entry in fifo */
 339                 smp_wmb();
 340                 request->desc = NULL;
 341
 342                 /* increment fifo tail */
 343                 priv->tail[ch] = (tail + 1) & (priv->fifo_len - 1);
 344
 345                 spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
 346
 347                 atomic_dec(&priv->submit_count[ch]);
 348
 349                 saved_req.callback(dev, saved_req.desc, saved_req.context,
 350                                    status);
 351                 /* channel may resume processing in single desc error case */
 352                 if (error && !reset_ch && status == error)
 353                         return;
 354                 spin_lock_irqsave(&priv->tail_lock[ch], flags);
 355                 tail = priv->tail[ch];
 356         }
 357
 358         spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
 359 }
 360
 361 /*
 362  * process completed requests for channels that have done status
 363  */
 364 static void talitos_done(unsigned long data)
 365 {
 366         struct device *dev = (struct device *)data;
 367         struct talitos_private *priv = dev_get_drvdata(dev);
 368         int ch;
 369
 370         for (ch = 0; ch < priv->num_channels; ch++)
 371                 flush_channel(dev, ch, 0, 0);
 372 }
 373
 374 /*
 375  * locate current (offending) descriptor
 376  */
 377 static struct talitos_desc *current_desc(struct device *dev, int ch)
 378 {
 379         struct talitos_private *priv = dev_get_drvdata(dev);
 380         int tail = priv->tail[ch];
 381         dma_addr_t cur_desc;
 382
 383         cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
 384
 385         while (priv->fifo[ch][tail].dma_desc != cur_desc) {
 386                 tail = (tail + 1) & (priv->fifo_len - 1);
 387                 if (tail == priv->tail[ch]) {
 388                         dev_err(dev, "couldn't locate current descriptor\n");
 389                         return NULL;
 390                 }
 391         }
 392
 393         return priv->fifo[ch][tail].desc;
 394 }
 395
 396 /*
 397  * user diagnostics; report root cause of error based on execution unit status
 398  */
 399 static void report_eu_error(struct device *dev, int ch, struct talitos_desc *desc)
 400 {
 401         struct talitos_private *priv = dev_get_drvdata(dev);
 402         int i;
 403
 404         switch (desc->hdr & DESC_HDR_SEL0_MASK) {
 405         case DESC_HDR_SEL0_AFEU:
 406                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
 407                         in_be32(priv->reg + TALITOS_AFEUISR),
 408                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
 409                 break;
 410         case DESC_HDR_SEL0_DEU:
 411                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
 412                         in_be32(priv->reg + TALITOS_DEUISR),
 413                         in_be32(priv->reg + TALITOS_DEUISR_LO));
 414                 break;
 415         case DESC_HDR_SEL0_MDEUA:
 416         case DESC_HDR_SEL0_MDEUB:
 417                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 418                         in_be32(priv->reg + TALITOS_MDEUISR),
 419                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 420                 break;
 421         case DESC_HDR_SEL0_RNG:
 422                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
 423                         in_be32(priv->reg + TALITOS_RNGUISR),
 424                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
 425                 break;
 426         case DESC_HDR_SEL0_PKEU:
 427                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
 428                         in_be32(priv->reg + TALITOS_PKEUISR),
 429                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
 430                 break;
 431         case DESC_HDR_SEL0_AESU:
 432                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
 433                         in_be32(priv->reg + TALITOS_AESUISR),
 434                         in_be32(priv->reg + TALITOS_AESUISR_LO));
 435                 break;
 436         case DESC_HDR_SEL0_CRCU:
 437                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 438                         in_be32(priv->reg + TALITOS_CRCUISR),
 439                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 440                 break;
 441         case DESC_HDR_SEL0_KEU:
 442                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
 443                         in_be32(priv->reg + TALITOS_KEUISR),
 444                         in_be32(priv->reg + TALITOS_KEUISR_LO));
 445                 break;
 446         }
 447
 448         switch (desc->hdr & DESC_HDR_SEL1_MASK) {
 449         case DESC_HDR_SEL1_MDEUA:
 450         case DESC_HDR_SEL1_MDEUB:
 451                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 452                         in_be32(priv->reg + TALITOS_MDEUISR),
 453                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 454                 break;
 455         case DESC_HDR_SEL1_CRCU:
 456                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 457                         in_be32(priv->reg + TALITOS_CRCUISR),
 458                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 459                 break;
 460         }
 461
 462         for (i = 0; i < 8; i++)
 463                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
 464                         in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
 465                         in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
 466 }
 467
 468 /*
 469  * recover from error interrupts
 470  */
 471 static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
 472 {
 473         struct device *dev = (struct device *)data;
 474         struct talitos_private *priv = dev_get_drvdata(dev);
 475         unsigned int timeout = TALITOS_TIMEOUT;
 476         int ch, error, reset_dev = 0, reset_ch = 0;
 477         u32 v, v_lo;
 478
 479         for (ch = 0; ch < priv->num_channels; ch++) {
 480                 /* skip channels without errors */
 481                 if (!(isr & (1 << (ch * 2 + 1))))
 482                         continue;
 483
 484                 error = -EINVAL;
 485
 486                 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
 487                 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
 488
 489                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
 490                         dev_err(dev, "double fetch fifo overflow error\n");
 491                         error = -EAGAIN;
 492                         reset_ch = 1;
 493                 }
 494                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
 495                         /* h/w dropped descriptor */
 496                         dev_err(dev, "single fetch fifo overflow error\n");
 497                         error = -EAGAIN;
 498                 }
 499                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
 500                         dev_err(dev, "master data transfer error\n");
 501                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
 502                         dev_err(dev, "s/g data length zero error\n");
 503                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
 504                         dev_err(dev, "fetch pointer zero error\n");
 505                 if (v_lo & TALITOS_CCPSR_LO_IDH)
 506                         dev_err(dev, "illegal descriptor header error\n");
 507                 if (v_lo & TALITOS_CCPSR_LO_IEU)
 508                         dev_err(dev, "invalid execution unit error\n");
 509                 if (v_lo & TALITOS_CCPSR_LO_EU)
 510                         report_eu_error(dev, ch, current_desc(dev, ch));
 511                 if (v_lo & TALITOS_CCPSR_LO_GB)
 512                         dev_err(dev, "gather boundary error\n");
 513                 if (v_lo & TALITOS_CCPSR_LO_GRL)
 514                         dev_err(dev, "gather return/length error\n");
 515                 if (v_lo & TALITOS_CCPSR_LO_SB)
 516                         dev_err(dev, "scatter boundary error\n");
 517                 if (v_lo & TALITOS_CCPSR_LO_SRL)
 518                         dev_err(dev, "scatter return/length error\n");
 519
 520                 flush_channel(dev, ch, error, reset_ch);
 521
 522                 if (reset_ch) {
 523                         reset_channel(dev, ch);
 524                 } else {
 525                         setbits32(priv->reg + TALITOS_CCCR(ch),
 526                                   TALITOS_CCCR_CONT);
 527                         setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
 528                         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
 529                                TALITOS_CCCR_CONT) && --timeout)
 530                                 cpu_relax();
 531                         if (timeout == 0) {
 532                                 dev_err(dev, "failed to restart channel %d\n",
 533                                         ch);
 534                                 reset_dev = 1;
 535                         }
 536                 }
 537         }
 538         if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
 539                 dev_err(dev, "done overflow, internal time out, or rngu error: "
 540                         "ISR 0x%08x_%08x\n", isr, isr_lo);
 541
 542                 /* purge request queues */
 543                 for (ch = 0; ch < priv->num_channels; ch++)
 544                         flush_channel(dev, ch, -EIO, 1);
 545
 546                 /* reset and reinitialize the device */
 547                 init_device(dev);
 548         }
 549 }
 550
 551 static irqreturn_t talitos_interrupt(int irq, void *data)
 552 {
 553         struct device *dev = data;
 554         struct talitos_private *priv = dev_get_drvdata(dev);
 555         u32 isr, isr_lo;
 556
 557         isr = in_be32(priv->reg + TALITOS_ISR);
 558         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
 559
 560         /* ack */
 561         out_be32(priv->reg + TALITOS_ICR, isr);
 562         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
 563
 564         if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
 565                 talitos_error((unsigned long)data, isr, isr_lo);
 566         else
 567                 if (likely(isr & TALITOS_ISR_CHDONE))
 568                         tasklet_schedule(&priv->done_task);
 569
 570         return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
 571 }
 572
 573 /*
 574  * hwrng
 575  */
 576 static int talitos_rng_data_present(struct hwrng *rng, int wait)
 577 {
 578         struct device *dev = (struct device *)rng->priv;
 579         struct talitos_private *priv = dev_get_drvdata(dev);
 580         u32 ofl;
 581         int i;
 582
 583         for (i = 0; i < 20; i++) {
 584                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
 585                       TALITOS_RNGUSR_LO_OFL;
 586                 if (ofl || !wait)
 587                         break;
 588                 udelay(10);
 589         }
 590
 591         return !!ofl;
 592 }
 593
 594 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
 595 {
 596         struct device *dev = (struct device *)rng->priv;
 597         struct talitos_private *priv = dev_get_drvdata(dev);
 598
 599         /* rng fifo requires 64-bit accesses */
 600         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
 601         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
 602
 603         return sizeof(u32);
 604 }
 605
 606 static int talitos_rng_init(struct hwrng *rng)
 607 {
 608         struct device *dev = (struct device *)rng->priv;
 609         struct talitos_private *priv = dev_get_drvdata(dev);
 610         unsigned int timeout = TALITOS_TIMEOUT;
 611
 612         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
 613         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
 614                && --timeout)
 615                 cpu_relax();
 616         if (timeout == 0) {
 617                 dev_err(dev, "failed to reset rng hw\n");
 618                 return -ENODEV;
 619         }
 620
 621         /* start generating */
 622         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
 623
 624         return 0;
 625 }
 626
 627 static int talitos_register_rng(struct device *dev)
 628 {
 629         struct talitos_private *priv = dev_get_drvdata(dev);
 630
 631         priv->rng.name          = dev_driver_string(dev),
 632         priv->rng.init          = talitos_rng_init,
 633         priv->rng.data_present  = talitos_rng_data_present,
 634         priv->rng.data_read     = talitos_rng_data_read,
 635         priv->rng.priv          = (unsigned long)dev;
 636
 637         return hwrng_register(&priv->rng);
 638 }
 639
 640 static void talitos_unregister_rng(struct device *dev)
 641 {
 642         struct talitos_private *priv = dev_get_drvdata(dev);
 643
 644         hwrng_unregister(&priv->rng);
 645 }
 646
 647 /*
 648  * crypto alg
 649  */
 650 #define TALITOS_CRA_PRIORITY            3000
 651 #define TALITOS_MAX_KEY_SIZE            64
 652 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
 653
 654 #define MD5_DIGEST_SIZE   16
 655
 656 struct talitos_ctx {
 657         struct device *dev;
 658         __be32 desc_hdr_template;
 659         u8 key[TALITOS_MAX_KEY_SIZE];
 660         u8 iv[TALITOS_MAX_IV_LENGTH];
 661         unsigned int keylen;
 662         unsigned int enckeylen;
 663         unsigned int authkeylen;
 664         unsigned int authsize;
 665 };
 666
 667 static int aead_authenc_setauthsize(struct crypto_aead *authenc,
 668                                                  unsigned int authsize)
 669 {
 670         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 671
 672         ctx->authsize = authsize;
 673
 674         return 0;
 675 }
 676
 677 static int aead_authenc_setkey(struct crypto_aead *authenc,
 678                                             const u8 *key, unsigned int keylen)
 679 {
 680         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 681         struct rtattr *rta = (void *)key;
 682         struct crypto_authenc_key_param *param;
 683         unsigned int authkeylen;
 684         unsigned int enckeylen;
 685
 686         if (!RTA_OK(rta, keylen))
 687                 goto badkey;
 688
 689         if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
 690                 goto badkey;
 691
 692         if (RTA_PAYLOAD(rta) < sizeof(*param))
 693                 goto badkey;
 694
 695         param = RTA_DATA(rta);
 696         enckeylen = be32_to_cpu(param->enckeylen);
 697
 698         key += RTA_ALIGN(rta->rta_len);
 699         keylen -= RTA_ALIGN(rta->rta_len);
 700
 701         if (keylen < enckeylen)
 702                 goto badkey;
 703
 704         authkeylen = keylen - enckeylen;
 705
 706         if (keylen > TALITOS_MAX_KEY_SIZE)
 707                 goto badkey;
 708
 709         memcpy(&ctx->key, key, keylen);
 710
 711         ctx->keylen = keylen;
 712         ctx->enckeylen = enckeylen;
 713         ctx->authkeylen = authkeylen;
 714
 715         return 0;
 716
 717 badkey:
 718         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
 719         return -EINVAL;
 720 }
 721
 722 /*
 723  * ipsec_esp_edesc - s/w-extended ipsec_esp descriptor
 724  * @src_nents: number of segments in input scatterlist
 725  * @dst_nents: number of segments in output scatterlist
 726  * @dma_len: length of dma mapped link_tbl space
 727  * @dma_link_tbl: bus physical address of link_tbl
 728  * @desc: h/w descriptor
 729  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
 730  *
 731  * if decrypting (with authcheck), or either one of src_nents or dst_nents
 732  * is greater than 1, an integrity check value is concatenated to the end
 733  * of link_tbl data
 734  */
 735 struct ipsec_esp_edesc {
 736         int src_nents;
 737         int dst_nents;
 738         int dma_len;
 739         dma_addr_t dma_link_tbl;
 740         struct talitos_desc desc;
 741         struct talitos_ptr link_tbl[0];
 742 };
 743
 744 static void ipsec_esp_unmap(struct device *dev,
 745                             struct ipsec_esp_edesc *edesc,
 746                             struct aead_request *areq)
 747 {
 748         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
 749         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
 750         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
 751         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
 752
 753         dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
 754
 755         if (areq->src != areq->dst) {
 756                 dma_unmap_sg(dev, areq->src, edesc->src_nents ? : 1,
 757                              DMA_TO_DEVICE);
 758                 dma_unmap_sg(dev, areq->dst, edesc->dst_nents ? : 1,
 759                              DMA_FROM_DEVICE);
 760         } else {
 761                 dma_unmap_sg(dev, areq->src, edesc->src_nents ? : 1,
 762                              DMA_BIDIRECTIONAL);
 763         }
 764
 765         if (edesc->dma_len)
 766                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 767                                  DMA_BIDIRECTIONAL);
 768 }
 769
 770 /*
 771  * ipsec_esp descriptor callbacks
 772  */
 773 static void ipsec_esp_encrypt_done(struct device *dev,
 774                                    struct talitos_desc *desc, void *context,
 775                                    int err)
 776 {
 777         struct aead_request *areq = context;
 778         struct ipsec_esp_edesc *edesc =
 779                  container_of(desc, struct ipsec_esp_edesc, desc);
 780         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
 781         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 782         struct scatterlist *sg;
 783         void *icvdata;
 784
 785         ipsec_esp_unmap(dev, edesc, areq);
 786
 787         /* copy the generated ICV to dst */
 788         if (edesc->dma_len) {
 789                 icvdata = &edesc->link_tbl[edesc->src_nents +
 790                                            edesc->dst_nents + 2];
 791                 sg = sg_last(areq->dst, edesc->dst_nents);
 792                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
 793                        icvdata, ctx->authsize);
 794         }
 795
 796         kfree(edesc);
 797
 798         aead_request_complete(areq, err);
 799 }
 800
 801 static void ipsec_esp_decrypt_done(struct device *dev,
 802                                    struct talitos_desc *desc, void *context,
 803                                    int err)
 804 {
 805         struct aead_request *req = context;
 806         struct ipsec_esp_edesc *edesc =
 807                  container_of(desc, struct ipsec_esp_edesc, desc);
 808         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
 809         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 810         struct scatterlist *sg;
 811         void *icvdata;
 812
 813         ipsec_esp_unmap(dev, edesc, req);
 814
 815         if (!err) {
 816                 /* auth check */
 817                 if (edesc->dma_len)
 818                         icvdata = &edesc->link_tbl[edesc->src_nents +
 819                                                    edesc->dst_nents + 2];
 820                 else
 821                         icvdata = &edesc->link_tbl[0];
 822
 823                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
 824                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
 825                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
 826         }
 827
 828         kfree(edesc);
 829
 830         aead_request_complete(req, err);
 831 }
 832
 833 /*
 834  * convert scatterlist to SEC h/w link table format
 835  * stop at cryptlen bytes
 836  */
 837 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
 838                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
 839 {
 840         int n_sg = sg_count;
 841
 842         while (n_sg--) {
 843                 link_tbl_ptr->ptr = cpu_to_be32(sg_dma_address(sg));
 844                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
 845                 link_tbl_ptr->j_extent = 0;
 846                 link_tbl_ptr++;
 847                 cryptlen -= sg_dma_len(sg);
 848                 sg = sg_next(sg);
 849         }
 850
 851         /* adjust (decrease) last one (or two) entry's len to cryptlen */
 852         link_tbl_ptr--;
 853         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
 854                 /* Empty this entry, and move to previous one */
 855                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
 856                 link_tbl_ptr->len = 0;
 857                 sg_count--;
 858                 link_tbl_ptr--;
 859         }
 860         link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
 861                                         + cryptlen);
 862
 863         /* tag end of link table */
 864         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 865
 866         return sg_count;
 867 }
 868
 869 /*
 870  * fill in and submit ipsec_esp descriptor
 871  */
 872 static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
 873                      u8 *giv, u64 seq,
 874                      void (*callback) (struct device *dev,
 875                                        struct talitos_desc *desc,
 876                                        void *context, int error))
 877 {
 878         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
 879         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
 880         struct device *dev = ctx->dev;
 881         struct talitos_desc *desc = &edesc->desc;
 882         unsigned int cryptlen = areq->cryptlen;
 883         unsigned int authsize = ctx->authsize;
 884         unsigned int ivsize;
 885         int sg_count, ret;
 886
 887         /* hmac key */
 888         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
 889                                0, DMA_TO_DEVICE);
 890         /* hmac data */
 891         map_single_talitos_ptr(dev, &desc->ptr[1], sg_virt(areq->src) -
 892                                sg_virt(areq->assoc), sg_virt(areq->assoc), 0,
 893                                DMA_TO_DEVICE);
 894         /* cipher iv */
 895         ivsize = crypto_aead_ivsize(aead);
 896         map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
 897                                DMA_TO_DEVICE);
 898
 899         /* cipher key */
 900         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
 901                                (char *)&ctx->key + ctx->authkeylen, 0,
 902                                DMA_TO_DEVICE);
 903
 904         /*
 905          * cipher in
 906          * map and adjust cipher len to aead request cryptlen.
 907          * extent is bytes of HMAC postpended to ciphertext,
 908          * typically 12 for ipsec
 909          */
 910         desc->ptr[4].len = cpu_to_be16(cryptlen);
 911         desc->ptr[4].j_extent = authsize;
 912
 913         if (areq->src == areq->dst)
 914                 sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ? : 1,
 915                                       DMA_BIDIRECTIONAL);
 916         else
 917                 sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ? : 1,
 918                                       DMA_TO_DEVICE);
 919
 920         if (sg_count == 1) {
 921                 desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
 922         } else {
 923                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
 924                                           &edesc->link_tbl[0]);
 925                 if (sg_count > 1) {
 926                         struct talitos_ptr *link_tbl_ptr =
 927                                 &edesc->link_tbl[sg_count-1];
 928                         struct scatterlist *sg;
 929                         struct talitos_private *priv = dev_get_drvdata(dev);
 930
 931                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
 932                         desc->ptr[4].ptr = cpu_to_be32(edesc->dma_link_tbl);
 933                         dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
 934                                                    edesc->dma_len, DMA_BIDIRECTIONAL);
 935                         /* If necessary for this SEC revision,
 936                          * add a link table entry for ICV.
 937                          */
 938                         if ((priv->features &
 939                              TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT) &&
 940                             (edesc->desc.hdr & DESC_HDR_MODE0_ENCRYPT) == 0) {
 941                                 link_tbl_ptr->j_extent = 0;
 942                                 link_tbl_ptr++;
 943                                 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 944                                 link_tbl_ptr->len = cpu_to_be16(authsize);
 945                                 sg = sg_last(areq->src, edesc->src_nents ? : 1);
 946                                 link_tbl_ptr->ptr = cpu_to_be32(
 947                                                 (char *)sg_dma_address(sg)
 948                                                 + sg->length - authsize);
 949                         }
 950                 } else {
 951                         /* Only one segment now, so no link tbl needed */
 952                         desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
 953                 }
 954         }
 955
 956         /* cipher out */
 957         desc->ptr[5].len = cpu_to_be16(cryptlen);
 958         desc->ptr[5].j_extent = authsize;
 959
 960         if (areq->src != areq->dst) {
 961                 sg_count = dma_map_sg(dev, areq->dst, edesc->dst_nents ? : 1,
 962                                       DMA_FROM_DEVICE);
 963         }
 964
 965         if (sg_count == 1) {
 966                 desc->ptr[5].ptr = cpu_to_be32(sg_dma_address(areq->dst));
 967         } else {
 968                 struct talitos_ptr *link_tbl_ptr =
 969                         &edesc->link_tbl[edesc->src_nents + 1];
 970
 971                 desc->ptr[5].ptr = cpu_to_be32((struct talitos_ptr *)
 972                                                edesc->dma_link_tbl +
 973                                                edesc->src_nents + 1);
 974                 if (areq->src == areq->dst) {
 975                         memcpy(link_tbl_ptr, &edesc->link_tbl[0],
 976                                edesc->src_nents * sizeof(struct talitos_ptr));
 977                 } else {
 978                         sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
 979                                                   link_tbl_ptr);
 980                 }
 981                 /* Add an entry to the link table for ICV data */
 982                 link_tbl_ptr += sg_count - 1;
 983                 link_tbl_ptr->j_extent = 0;
 984                 sg_count++;
 985                 link_tbl_ptr++;
 986                 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 987                 link_tbl_ptr->len = cpu_to_be16(authsize);
 988
 989                 /* icv data follows link tables */
 990                 link_tbl_ptr->ptr = cpu_to_be32((struct talitos_ptr *)
 991                                                 edesc->dma_link_tbl +
 992                                                 edesc->src_nents +
 993                                                 edesc->dst_nents + 2);
 994
 995                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
 996                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
 997                                            edesc->dma_len, DMA_BIDIRECTIONAL);
 998         }
 999
1000         /* iv out */
1001         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1002                                DMA_FROM_DEVICE);
1003
1004         ret = talitos_submit(dev, desc, callback, areq);
1005         if (ret != -EINPROGRESS) {
1006                 ipsec_esp_unmap(dev, edesc, areq);
1007                 kfree(edesc);
1008         }
1009         return ret;
1010 }
1011
1012
1013 /*
1014  * derive number of elements in scatterlist
1015  */
1016 static int sg_count(struct scatterlist *sg_list, int nbytes)
1017 {
1018         struct scatterlist *sg = sg_list;
1019         int sg_nents = 0;
1020
1021         while (nbytes) {
1022                 sg_nents++;
1023                 nbytes -= sg->length;
1024                 sg = sg_next(sg);
1025         }
1026
1027         return sg_nents;
1028 }
1029
1030 /*
1031  * allocate and map the ipsec_esp extended descriptor
1032  */
1033 static struct ipsec_esp_edesc *ipsec_esp_edesc_alloc(struct aead_request *areq,
1034                                                      int icv_stashing)
1035 {
1036         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1037         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1038         struct ipsec_esp_edesc *edesc;
1039         int src_nents, dst_nents, alloc_len, dma_len;
1040         gfp_t flags = areq->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1041                       GFP_ATOMIC;
1042
1043         if (areq->cryptlen + ctx->authsize > TALITOS_MAX_DATA_LEN) {
1044                 dev_err(ctx->dev, "cryptlen exceeds h/w max limit\n");
1045                 return ERR_PTR(-EINVAL);
1046         }
1047
1048         src_nents = sg_count(areq->src, areq->cryptlen + ctx->authsize);
1049         src_nents = (src_nents == 1) ? 0 : src_nents;
1050
1051         if (areq->dst == areq->src) {
1052                 dst_nents = src_nents;
1053         } else {
1054                 dst_nents = sg_count(areq->dst, areq->cryptlen + ctx->authsize);
1055                 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1056         }
1057
1058         /*
1059          * allocate space for base edesc plus the link tables,
1060          * allowing for two separate entries for ICV and generated ICV (+ 2),
1061          * and the ICV data itself
1062          */
1063         alloc_len = sizeof(struct ipsec_esp_edesc);
1064         if (src_nents || dst_nents) {
1065                 dma_len = (src_nents + dst_nents + 2) *
1066                                  sizeof(struct talitos_ptr) + ctx->authsize;
1067                 alloc_len += dma_len;
1068         } else {
1069                 dma_len = 0;
1070                 alloc_len += icv_stashing ? ctx->authsize : 0;
1071         }
1072
1073         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1074         if (!edesc) {
1075                 dev_err(ctx->dev, "could not allocate edescriptor\n");
1076                 return ERR_PTR(-ENOMEM);
1077         }
1078
1079         edesc->src_nents = src_nents;
1080         edesc->dst_nents = dst_nents;
1081         edesc->dma_len = dma_len;
1082         edesc->dma_link_tbl = dma_map_single(ctx->dev, &edesc->link_tbl[0],
1083                                              edesc->dma_len, DMA_BIDIRECTIONAL);
1084
1085         return edesc;
1086 }
1087
1088 static int aead_authenc_encrypt(struct aead_request *req)
1089 {
1090         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1091         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1092         struct ipsec_esp_edesc *edesc;
1093
1094         /* allocate extended descriptor */
1095         edesc = ipsec_esp_edesc_alloc(req, 0);
1096         if (IS_ERR(edesc))
1097                 return PTR_ERR(edesc);
1098
1099         /* set encrypt */
1100         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1101
1102         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1103 }
1104
1105 static int aead_authenc_decrypt(struct aead_request *req)
1106 {
1107         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1108         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1109         unsigned int authsize = ctx->authsize;
1110         struct ipsec_esp_edesc *edesc;
1111         struct scatterlist *sg;
1112         void *icvdata;
1113
1114         req->cryptlen -= authsize;
1115
1116         /* allocate extended descriptor */
1117         edesc = ipsec_esp_edesc_alloc(req, 1);
1118         if (IS_ERR(edesc))
1119                 return PTR_ERR(edesc);
1120
1121         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1122         if (edesc->dma_len)
1123                 icvdata = &edesc->link_tbl[edesc->src_nents +
1124                                            edesc->dst_nents + 2];
1125         else
1126                 icvdata = &edesc->link_tbl[0];
1127
1128         sg = sg_last(req->src, edesc->src_nents ? : 1);
1129
1130         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1131                ctx->authsize);
1132
1133         /* decrypt */
1134         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1135
1136         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_done);
1137 }
1138
1139 static int aead_authenc_givencrypt(
1140         struct aead_givcrypt_request *req)
1141 {
1142         struct aead_request *areq = &req->areq;
1143         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1144         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1145         struct ipsec_esp_edesc *edesc;
1146
1147         /* allocate extended descriptor */
1148         edesc = ipsec_esp_edesc_alloc(areq, 0);
1149         if (IS_ERR(edesc))
1150                 return PTR_ERR(edesc);
1151
1152         /* set encrypt */
1153         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1154
1155         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1156         /* avoid consecutive packets going out with same IV */
1157         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1158
1159         return ipsec_esp(edesc, areq, req->giv, req->seq,
1160                          ipsec_esp_encrypt_done);
1161 }
1162
1163 struct talitos_alg_template {
1164         char name[CRYPTO_MAX_ALG_NAME];
1165         char driver_name[CRYPTO_MAX_ALG_NAME];
1166         unsigned int blocksize;
1167         struct aead_alg aead;
1168         struct device *dev;
1169         __be32 desc_hdr_template;
1170 };
1171
1172 static struct talitos_alg_template driver_algs[] = {
1173         /* single-pass ipsec_esp descriptor */
1174         {
1175                 .name = "authenc(hmac(sha1),cbc(aes))",
1176                 .driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1177                 .blocksize = AES_BLOCK_SIZE,
1178                 .aead = {
1179                         .setkey = aead_authenc_setkey,
1180                         .setauthsize = aead_authenc_setauthsize,
1181                         .encrypt = aead_authenc_encrypt,
1182                         .decrypt = aead_authenc_decrypt,
1183                         .givencrypt = aead_authenc_givencrypt,
1184                         .geniv = "<built-in>",
1185                         .ivsize = AES_BLOCK_SIZE,
1186                         .maxauthsize = SHA1_DIGEST_SIZE,
1187                         },
1188                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1189                                      DESC_HDR_SEL0_AESU |
1190                                      DESC_HDR_MODE0_AESU_CBC |
1191                                      DESC_HDR_SEL1_MDEUA |
1192                                      DESC_HDR_MODE1_MDEU_INIT |
1193                                      DESC_HDR_MODE1_MDEU_PAD |
1194                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1195         },
1196         {
1197                 .name = "authenc(hmac(sha1),cbc(des3_ede))",
1198                 .driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1199                 .blocksize = DES3_EDE_BLOCK_SIZE,
1200                 .aead = {
1201                         .setkey = aead_authenc_setkey,
1202                         .setauthsize = aead_authenc_setauthsize,
1203                         .encrypt = aead_authenc_encrypt,
1204                         .decrypt = aead_authenc_decrypt,
1205                         .givencrypt = aead_authenc_givencrypt,
1206                         .geniv = "<built-in>",
1207                         .ivsize = DES3_EDE_BLOCK_SIZE,
1208                         .maxauthsize = SHA1_DIGEST_SIZE,
1209                         },
1210                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1211                                      DESC_HDR_SEL0_DEU |
1212                                      DESC_HDR_MODE0_DEU_CBC |
1213                                      DESC_HDR_MODE0_DEU_3DES |
1214                                      DESC_HDR_SEL1_MDEUA |
1215                                      DESC_HDR_MODE1_MDEU_INIT |
1216                                      DESC_HDR_MODE1_MDEU_PAD |
1217                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1218         },
1219         {
1220                 .name = "authenc(hmac(sha256),cbc(aes))",
1221                 .driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1222                 .blocksize = AES_BLOCK_SIZE,
1223                 .aead = {
1224                         .setkey = aead_authenc_setkey,
1225                         .setauthsize = aead_authenc_setauthsize,
1226                         .encrypt = aead_authenc_encrypt,
1227                         .decrypt = aead_authenc_decrypt,
1228                         .givencrypt = aead_authenc_givencrypt,
1229                         .geniv = "<built-in>",
1230                         .ivsize = AES_BLOCK_SIZE,
1231                         .maxauthsize = SHA256_DIGEST_SIZE,
1232                         },
1233                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1234                                      DESC_HDR_SEL0_AESU |
1235                                      DESC_HDR_MODE0_AESU_CBC |
1236                                      DESC_HDR_SEL1_MDEUA |
1237                                      DESC_HDR_MODE1_MDEU_INIT |
1238                                      DESC_HDR_MODE1_MDEU_PAD |
1239                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1240         },
1241         {
1242                 .name = "authenc(hmac(sha256),cbc(des3_ede))",
1243                 .driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1244                 .blocksize = DES3_EDE_BLOCK_SIZE,
1245                 .aead = {
1246                         .setkey = aead_authenc_setkey,
1247                         .setauthsize = aead_authenc_setauthsize,
1248                         .encrypt = aead_authenc_encrypt,
1249                         .decrypt = aead_authenc_decrypt,
1250                         .givencrypt = aead_authenc_givencrypt,
1251                         .geniv = "<built-in>",
1252                         .ivsize = DES3_EDE_BLOCK_SIZE,
1253                         .maxauthsize = SHA256_DIGEST_SIZE,
1254                         },
1255                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1256                                      DESC_HDR_SEL0_DEU |
1257                                      DESC_HDR_MODE0_DEU_CBC |
1258                                      DESC_HDR_MODE0_DEU_3DES |
1259                                      DESC_HDR_SEL1_MDEUA |
1260                                      DESC_HDR_MODE1_MDEU_INIT |
1261                                      DESC_HDR_MODE1_MDEU_PAD |
1262                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1263         },
1264         {
1265                 .name = "authenc(hmac(md5),cbc(aes))",
1266                 .driver_name = "authenc-hmac-md5-cbc-aes-talitos",
1267                 .blocksize = AES_BLOCK_SIZE,
1268                 .aead = {
1269                         .setkey = aead_authenc_setkey,
1270                         .setauthsize = aead_authenc_setauthsize,
1271                         .encrypt = aead_authenc_encrypt,
1272                         .decrypt = aead_authenc_decrypt,
1273                         .givencrypt = aead_authenc_givencrypt,
1274                         .geniv = "<built-in>",
1275                         .ivsize = AES_BLOCK_SIZE,
1276                         .maxauthsize = MD5_DIGEST_SIZE,
1277                         },
1278                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1279                                      DESC_HDR_SEL0_AESU |
1280                                      DESC_HDR_MODE0_AESU_CBC |
1281                                      DESC_HDR_SEL1_MDEUA |
1282                                      DESC_HDR_MODE1_MDEU_INIT |
1283                                      DESC_HDR_MODE1_MDEU_PAD |
1284                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
1285         },
1286         {
1287                 .name = "authenc(hmac(md5),cbc(des3_ede))",
1288                 .driver_name = "authenc-hmac-md5-cbc-3des-talitos",
1289                 .blocksize = DES3_EDE_BLOCK_SIZE,
1290                 .aead = {
1291                         .setkey = aead_authenc_setkey,
1292                         .setauthsize = aead_authenc_setauthsize,
1293                         .encrypt = aead_authenc_encrypt,
1294                         .decrypt = aead_authenc_decrypt,
1295                         .givencrypt = aead_authenc_givencrypt,
1296                         .geniv = "<built-in>",
1297                         .ivsize = DES3_EDE_BLOCK_SIZE,
1298                         .maxauthsize = MD5_DIGEST_SIZE,
1299                         },
1300                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1301                                      DESC_HDR_SEL0_DEU |
1302                                      DESC_HDR_MODE0_DEU_CBC |
1303                                      DESC_HDR_MODE0_DEU_3DES |
1304                                      DESC_HDR_SEL1_MDEUA |
1305                                      DESC_HDR_MODE1_MDEU_INIT |
1306                                      DESC_HDR_MODE1_MDEU_PAD |
1307                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
1308         }
1309 };
1310
1311 struct talitos_crypto_alg {
1312         struct list_head entry;
1313         struct device *dev;
1314         __be32 desc_hdr_template;
1315         struct crypto_alg crypto_alg;
1316 };
1317
1318 static int talitos_cra_init(struct crypto_tfm *tfm)
1319 {
1320         struct crypto_alg *alg = tfm->__crt_alg;
1321         struct talitos_crypto_alg *talitos_alg =
1322                  container_of(alg, struct talitos_crypto_alg, crypto_alg);
1323         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
1324
1325         /* update context with ptr to dev */
1326         ctx->dev = talitos_alg->dev;
1327         /* copy descriptor header template value */
1328         ctx->desc_hdr_template = talitos_alg->desc_hdr_template;
1329
1330         /* random first IV */
1331         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
1332
1333         return 0;
1334 }
1335
1336 /*
1337  * given the alg's descriptor header template, determine whether descriptor
1338  * type and primary/secondary execution units required match the hw
1339  * capabilities description provided in the device tree node.
1340  */
1341 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
1342 {
1343         struct talitos_private *priv = dev_get_drvdata(dev);
1344         int ret;
1345
1346         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
1347               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
1348
1349         if (SECONDARY_EU(desc_hdr_template))
1350                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
1351                               & priv->exec_units);
1352
1353         return ret;
1354 }
1355
1356 static int talitos_remove(struct of_device *ofdev)
1357 {
1358         struct device *dev = &ofdev->dev;
1359         struct talitos_private *priv = dev_get_drvdata(dev);
1360         struct talitos_crypto_alg *t_alg, *n;
1361         int i;
1362
1363         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
1364                 crypto_unregister_alg(&t_alg->crypto_alg);
1365                 list_del(&t_alg->entry);
1366                 kfree(t_alg);
1367         }
1368
1369         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
1370                 talitos_unregister_rng(dev);
1371
1372         kfree(priv->submit_count);
1373         kfree(priv->tail);
1374         kfree(priv->head);
1375
1376         if (priv->fifo)
1377                 for (i = 0; i < priv->num_channels; i++)
1378                         kfree(priv->fifo[i]);
1379
1380         kfree(priv->fifo);
1381         kfree(priv->head_lock);
1382         kfree(priv->tail_lock);
1383
1384         if (priv->irq != NO_IRQ) {
1385                 free_irq(priv->irq, dev);
1386                 irq_dispose_mapping(priv->irq);
1387         }
1388
1389         tasklet_kill(&priv->done_task);
1390
1391         iounmap(priv->reg);
1392
1393         dev_set_drvdata(dev, NULL);
1394
1395         kfree(priv);
1396
1397         return 0;
1398 }
1399
1400 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
1401                                                     struct talitos_alg_template
1402                                                            *template)
1403 {
1404         struct talitos_crypto_alg *t_alg;
1405         struct crypto_alg *alg;
1406
1407         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
1408         if (!t_alg)
1409                 return ERR_PTR(-ENOMEM);
1410
1411         alg = &t_alg->crypto_alg;
1412
1413         snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
1414         snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1415                  template->driver_name);
1416         alg->cra_module = THIS_MODULE;
1417         alg->cra_init = talitos_cra_init;
1418         alg->cra_priority = TALITOS_CRA_PRIORITY;
1419         alg->cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC;
1420         alg->cra_blocksize = template->blocksize;
1421         alg->cra_alignmask = 0;
1422         alg->cra_type = &crypto_aead_type;
1423         alg->cra_ctxsize = sizeof(struct talitos_ctx);
1424         alg->cra_u.aead = template->aead;
1425
1426         t_alg->desc_hdr_template = template->desc_hdr_template;
1427         t_alg->dev = dev;
1428
1429         return t_alg;
1430 }
1431
1432 static int talitos_probe(struct of_device *ofdev,
1433                          const struct of_device_id *match)
1434 {
1435         struct device *dev = &ofdev->dev;
1436         struct device_node *np = ofdev->node;
1437         struct talitos_private *priv;
1438         const unsigned int *prop;
1439         int i, err;
1440
1441         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
1442         if (!priv)
1443                 return -ENOMEM;
1444
1445         dev_set_drvdata(dev, priv);
1446
1447         priv->ofdev = ofdev;
1448
1449         INIT_LIST_HEAD(&priv->alg_list);
1450
1451         tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
1452
1453         priv->irq = irq_of_parse_and_map(np, 0);
1454
1455         if (priv->irq == NO_IRQ) {
1456                 dev_err(dev, "failed to map irq\n");
1457                 err = -EINVAL;
1458                 goto err_out;
1459         }
1460
1461         /* get the irq line */
1462         err = request_irq(priv->irq, talitos_interrupt, 0,
1463                           dev_driver_string(dev), dev);
1464         if (err) {
1465                 dev_err(dev, "failed to request irq %d\n", priv->irq);
1466                 irq_dispose_mapping(priv->irq);
1467                 priv->irq = NO_IRQ;
1468                 goto err_out;
1469         }
1470
1471         priv->reg = of_iomap(np, 0);
1472         if (!priv->reg) {
1473                 dev_err(dev, "failed to of_iomap\n");
1474                 err = -ENOMEM;
1475                 goto err_out;
1476         }
1477
1478         /* get SEC version capabilities from device tree */
1479         prop = of_get_property(np, "fsl,num-channels", NULL);
1480         if (prop)
1481                 priv->num_channels = *prop;
1482
1483         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
1484         if (prop)
1485                 priv->chfifo_len = *prop;
1486
1487         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
1488         if (prop)
1489                 priv->exec_units = *prop;
1490
1491         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
1492         if (prop)
1493                 priv->desc_types = *prop;
1494
1495         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
1496             !priv->exec_units || !priv->desc_types) {
1497                 dev_err(dev, "invalid property data in device tree node\n");
1498                 err = -EINVAL;
1499                 goto err_out;
1500         }
1501
1502         if (of_device_is_compatible(np, "fsl,sec3.0"))
1503                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
1504
1505         priv->head_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1506                                   GFP_KERNEL);
1507         priv->tail_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1508                                   GFP_KERNEL);
1509         if (!priv->head_lock || !priv->tail_lock) {
1510                 dev_err(dev, "failed to allocate fifo locks\n");
1511                 err = -ENOMEM;
1512                 goto err_out;
1513         }
1514
1515         for (i = 0; i < priv->num_channels; i++) {
1516                 spin_lock_init(&priv->head_lock[i]);
1517                 spin_lock_init(&priv->tail_lock[i]);
1518         }
1519
1520         priv->fifo = kmalloc(sizeof(struct talitos_request *) *
1521                              priv->num_channels, GFP_KERNEL);
1522         if (!priv->fifo) {
1523                 dev_err(dev, "failed to allocate request fifo\n");
1524                 err = -ENOMEM;
1525                 goto err_out;
1526         }
1527
1528         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
1529
1530         for (i = 0; i < priv->num_channels; i++) {
1531                 priv->fifo[i] = kzalloc(sizeof(struct talitos_request) *
1532                                         priv->fifo_len, GFP_KERNEL);
1533                 if (!priv->fifo[i]) {
1534                         dev_err(dev, "failed to allocate request fifo %d\n", i);
1535                         err = -ENOMEM;
1536                         goto err_out;
1537                 }
1538         }
1539
1540         priv->submit_count = kmalloc(sizeof(atomic_t) * priv->num_channels,
1541                                      GFP_KERNEL);
1542         if (!priv->submit_count) {
1543                 dev_err(dev, "failed to allocate fifo submit count space\n");
1544                 err = -ENOMEM;
1545                 goto err_out;
1546         }
1547         for (i = 0; i < priv->num_channels; i++)
1548                 atomic_set(&priv->submit_count[i], -priv->chfifo_len);
1549
1550         priv->head = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1551         priv->tail = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1552         if (!priv->head || !priv->tail) {
1553                 dev_err(dev, "failed to allocate request index space\n");
1554                 err = -ENOMEM;
1555                 goto err_out;
1556         }
1557
1558         /* reset and initialize the h/w */
1559         err = init_device(dev);
1560         if (err) {
1561                 dev_err(dev, "failed to initialize device\n");
1562                 goto err_out;
1563         }
1564
1565         /* register the RNG, if available */
1566         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
1567                 err = talitos_register_rng(dev);
1568                 if (err) {
1569                         dev_err(dev, "failed to register hwrng: %d\n", err);
1570                         goto err_out;
1571                 } else
1572                         dev_info(dev, "hwrng\n");
1573         }
1574
1575         /* register crypto algorithms the device supports */
1576         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
1577                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
1578                         struct talitos_crypto_alg *t_alg;
1579
1580                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
1581                         if (IS_ERR(t_alg)) {
1582                                 err = PTR_ERR(t_alg);
1583                                 goto err_out;
1584                         }
1585
1586                         err = crypto_register_alg(&t_alg->crypto_alg);
1587                         if (err) {
1588                                 dev_err(dev, "%s alg registration failed\n",
1589                                         t_alg->crypto_alg.cra_driver_name);
1590                                 kfree(t_alg);
1591                         } else {
1592                                 list_add_tail(&t_alg->entry, &priv->alg_list);
1593                                 dev_info(dev, "%s\n",
1594                                          t_alg->crypto_alg.cra_driver_name);
1595                         }
1596                 }
1597         }
1598
1599         return 0;
1600
1601 err_out:
1602         talitos_remove(ofdev);
1603
1604         return err;
1605 }
1606
1607 static struct of_device_id talitos_match[] = {
1608         {
1609                 .compatible = "fsl,sec2.0",
1610         },
1611         {},
1612 };
1613 MODULE_DEVICE_TABLE(of, talitos_match);
1614
1615 static struct of_platform_driver talitos_driver = {
1616         .name = "talitos",
1617         .match_table = talitos_match,
1618         .probe = talitos_probe,
1619         .remove = talitos_remove,
1620 };
1621
1622 static int __init talitos_init(void)
1623 {
1624         return of_register_platform_driver(&talitos_driver);
1625 }
1626 module_init(talitos_init);
1627
1628 static void __exit talitos_exit(void)
1629 {
1630         of_unregister_platform_driver(&talitos_driver);
1631 }
1632 module_exit(talitos_exit);
1633
1634 MODULE_LICENSE("GPL");
1635 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
1636 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");