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   1 /*
   2  * $Id: synclinkmp.c,v 4.34 2005/03/04 15:07:10 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/ioctl.h>
  60
  61 #include <asm/system.h>
  62 #include <asm/io.h>
  63 #include <asm/irq.h>
  64 #include <asm/dma.h>
  65 #include <linux/bitops.h>
  66 #include <asm/types.h>
  67 #include <linux/termios.h>
  68 #include <linux/workqueue.h>
  69 #include <linux/hdlc.h>
  70
  71 #ifdef CONFIG_HDLC_MODULE
  72 #define CONFIG_HDLC 1
  73 #endif
  74
  75 #define GET_USER(error,value,addr) error = get_user(value,addr)
  76 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  77 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  78 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  79
  80 #include <asm/uaccess.h>
  81
  82 #include "linux/synclink.h"
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 138
 139 struct  _input_signal_events {
 140         int     ri_up;
 141         int     ri_down;
 142         int     dsr_up;
 143         int     dsr_down;
 144         int     dcd_up;
 145         int     dcd_down;
 146         int     cts_up;
 147         int     cts_down;
 148 };
 149
 150 /*
 151  * Device instance data structure
 152  */
 153 typedef struct _synclinkmp_info {
 154         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 155         int                     magic;
 156         int                     flags;
 157         int                     count;          /* count of opens */
 158         int                     line;
 159         unsigned short          close_delay;
 160         unsigned short          closing_wait;   /* time to wait before closing */
 161
 162         struct mgsl_icount      icount;
 163
 164         struct tty_struct       *tty;
 165         int                     timeout;
 166         int                     x_char;         /* xon/xoff character */
 167         int                     blocked_open;   /* # of blocked opens */
 168         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 169         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 170         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 171         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 172         unsigned char           *tx_buf;
 173         int                     tx_put;
 174         int                     tx_get;
 175         int                     tx_count;
 176
 177         wait_queue_head_t       open_wait;
 178         wait_queue_head_t       close_wait;
 179
 180         wait_queue_head_t       status_event_wait_q;
 181         wait_queue_head_t       event_wait_q;
 182         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 183         struct _synclinkmp_info *next_device;   /* device list link */
 184         struct timer_list       status_timer;   /* input signal status check timer */
 185
 186         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 187         struct work_struct task;                        /* task structure for scheduling bh */
 188
 189         u32 max_frame_size;                     /* as set by device config */
 190
 191         u32 pending_bh;
 192
 193         int bh_running;                         /* Protection from multiple */
 194         int isr_overflow;
 195         int bh_requested;
 196
 197         int dcd_chkcount;                       /* check counts to prevent */
 198         int cts_chkcount;                       /* too many IRQs if a signal */
 199         int dsr_chkcount;                       /* is floating */
 200         int ri_chkcount;
 201
 202         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 203         unsigned long buffer_list_phys;
 204
 205         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 206         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 207         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 208         unsigned int current_rx_buf;
 209
 210         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 211         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 212         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 213         unsigned int last_tx_buf;
 214
 215         unsigned char *tmp_rx_buf;
 216         unsigned int tmp_rx_buf_count;
 217
 218         int rx_enabled;
 219         int rx_overflow;
 220
 221         int tx_enabled;
 222         int tx_active;
 223         u32 idle_mode;
 224
 225         unsigned char ie0_value;
 226         unsigned char ie1_value;
 227         unsigned char ie2_value;
 228         unsigned char ctrlreg_value;
 229         unsigned char old_signals;
 230
 231         char device_name[25];                   /* device instance name */
 232
 233         int port_count;
 234         int adapter_num;
 235         int port_num;
 236
 237         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 238
 239         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 240
 241         unsigned int irq_level;                 /* interrupt level */
 242         unsigned long irq_flags;
 243         int irq_requested;                      /* nonzero if IRQ requested */
 244
 245         MGSL_PARAMS params;                     /* communications parameters */
 246
 247         unsigned char serial_signals;           /* current serial signal states */
 248
 249         int irq_occurred;                       /* for diagnostics use */
 250         unsigned int init_error;                /* Initialization startup error */
 251
 252         u32 last_mem_alloc;
 253         unsigned char* memory_base;             /* shared memory address (PCI only) */
 254         u32 phys_memory_base;
 255         int shared_mem_requested;
 256
 257         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 258         u32 phys_sca_base;
 259         u32 sca_offset;
 260         int sca_base_requested;
 261
 262         unsigned char* lcr_base;                /* local config registers (PCI only) */
 263         u32 phys_lcr_base;
 264         u32 lcr_offset;
 265         int lcr_mem_requested;
 266
 267         unsigned char* statctrl_base;           /* status/control register memory */
 268         u32 phys_statctrl_base;
 269         u32 statctrl_offset;
 270         int sca_statctrl_requested;
 271
 272         u32 misc_ctrl_value;
 273         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 274         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 275         BOOLEAN drop_rts_on_tx_done;
 276
 277         struct  _input_signal_events    input_signal_events;
 278
 279         /* SPPP/Cisco HDLC device parts */
 280         int netcount;
 281         int dosyncppp;
 282         spinlock_t netlock;
 283
 284 #ifdef CONFIG_HDLC
 285         struct net_device *netdev;
 286 #endif
 287
 288 } SLMP_INFO;
 289
 290 #define MGSL_MAGIC 0x5401
 291
 292 /*
 293  * define serial signal status change macros
 294  */
 295 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 296 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 297 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 298 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 299
 300 /* Common Register macros */
 301 #define LPR     0x00
 302 #define PABR0   0x02
 303 #define PABR1   0x03
 304 #define WCRL    0x04
 305 #define WCRM    0x05
 306 #define WCRH    0x06
 307 #define DPCR    0x08
 308 #define DMER    0x09
 309 #define ISR0    0x10
 310 #define ISR1    0x11
 311 #define ISR2    0x12
 312 #define IER0    0x14
 313 #define IER1    0x15
 314 #define IER2    0x16
 315 #define ITCR    0x18
 316 #define INTVR   0x1a
 317 #define IMVR    0x1c
 318
 319 /* MSCI Register macros */
 320 #define TRB     0x20
 321 #define TRBL    0x20
 322 #define TRBH    0x21
 323 #define SR0     0x22
 324 #define SR1     0x23
 325 #define SR2     0x24
 326 #define SR3     0x25
 327 #define FST     0x26
 328 #define IE0     0x28
 329 #define IE1     0x29
 330 #define IE2     0x2a
 331 #define FIE     0x2b
 332 #define CMD     0x2c
 333 #define MD0     0x2e
 334 #define MD1     0x2f
 335 #define MD2     0x30
 336 #define CTL     0x31
 337 #define SA0     0x32
 338 #define SA1     0x33
 339 #define IDL     0x34
 340 #define TMC     0x35
 341 #define RXS     0x36
 342 #define TXS     0x37
 343 #define TRC0    0x38
 344 #define TRC1    0x39
 345 #define RRC     0x3a
 346 #define CST0    0x3c
 347 #define CST1    0x3d
 348
 349 /* Timer Register Macros */
 350 #define TCNT    0x60
 351 #define TCNTL   0x60
 352 #define TCNTH   0x61
 353 #define TCONR   0x62
 354 #define TCONRL  0x62
 355 #define TCONRH  0x63
 356 #define TMCS    0x64
 357 #define TEPR    0x65
 358
 359 /* DMA Controller Register macros */
 360 #define DARL    0x80
 361 #define DARH    0x81
 362 #define DARB    0x82
 363 #define BAR     0x80
 364 #define BARL    0x80
 365 #define BARH    0x81
 366 #define BARB    0x82
 367 #define SAR     0x84
 368 #define SARL    0x84
 369 #define SARH    0x85
 370 #define SARB    0x86
 371 #define CPB     0x86
 372 #define CDA     0x88
 373 #define CDAL    0x88
 374 #define CDAH    0x89
 375 #define EDA     0x8a
 376 #define EDAL    0x8a
 377 #define EDAH    0x8b
 378 #define BFL     0x8c
 379 #define BFLL    0x8c
 380 #define BFLH    0x8d
 381 #define BCR     0x8e
 382 #define BCRL    0x8e
 383 #define BCRH    0x8f
 384 #define DSR     0x90
 385 #define DMR     0x91
 386 #define FCT     0x93
 387 #define DIR     0x94
 388 #define DCMD    0x95
 389
 390 /* combine with timer or DMA register address */
 391 #define TIMER0  0x00
 392 #define TIMER1  0x08
 393 #define TIMER2  0x10
 394 #define TIMER3  0x18
 395 #define RXDMA   0x00
 396 #define TXDMA   0x20
 397
 398 /* SCA Command Codes */
 399 #define NOOP            0x00
 400 #define TXRESET         0x01
 401 #define TXENABLE        0x02
 402 #define TXDISABLE       0x03
 403 #define TXCRCINIT       0x04
 404 #define TXCRCEXCL       0x05
 405 #define TXEOM           0x06
 406 #define TXABORT         0x07
 407 #define MPON            0x08
 408 #define TXBUFCLR        0x09
 409 #define RXRESET         0x11
 410 #define RXENABLE        0x12
 411 #define RXDISABLE       0x13
 412 #define RXCRCINIT       0x14
 413 #define RXREJECT        0x15
 414 #define SEARCHMP        0x16
 415 #define RXCRCEXCL       0x17
 416 #define RXCRCCALC       0x18
 417 #define CHRESET         0x21
 418 #define HUNT            0x31
 419
 420 /* DMA command codes */
 421 #define SWABORT         0x01
 422 #define FEICLEAR        0x02
 423
 424 /* IE0 */
 425 #define TXINTE          BIT7
 426 #define RXINTE          BIT6
 427 #define TXRDYE          BIT1
 428 #define RXRDYE          BIT0
 429
 430 /* IE1 & SR1 */
 431 #define UDRN    BIT7
 432 #define IDLE    BIT6
 433 #define SYNCD   BIT4
 434 #define FLGD    BIT4
 435 #define CCTS    BIT3
 436 #define CDCD    BIT2
 437 #define BRKD    BIT1
 438 #define ABTD    BIT1
 439 #define GAPD    BIT1
 440 #define BRKE    BIT0
 441 #define IDLD    BIT0
 442
 443 /* IE2 & SR2 */
 444 #define EOM     BIT7
 445 #define PMP     BIT6
 446 #define SHRT    BIT6
 447 #define PE      BIT5
 448 #define ABT     BIT5
 449 #define FRME    BIT4
 450 #define RBIT    BIT4
 451 #define OVRN    BIT3
 452 #define CRCE    BIT2
 453
 454
 455 /*
 456  * Global linked list of SyncLink devices
 457  */
 458 static SLMP_INFO *synclinkmp_device_list = NULL;
 459 static int synclinkmp_adapter_count = -1;
 460 static int synclinkmp_device_count = 0;
 461
 462 /*
 463  * Set this param to non-zero to load eax with the
 464  * .text section address and breakpoint on module load.
 465  * This is useful for use with gdb and add-symbol-file command.
 466  */
 467 static int break_on_load=0;
 468
 469 /*
 470  * Driver major number, defaults to zero to get auto
 471  * assigned major number. May be forced as module parameter.
 472  */
 473 static int ttymajor=0;
 474
 475 /*
 476  * Array of user specified options for ISA adapters.
 477  */
 478 static int debug_level = 0;
 479 static int maxframe[MAX_DEVICES] = {0,};
 480 static int dosyncppp[MAX_DEVICES] = {0,};
 481
 482 module_param(break_on_load, bool, 0);
 483 module_param(ttymajor, int, 0);
 484 module_param(debug_level, int, 0);
 485 module_param_array(maxframe, int, NULL, 0);
 486 module_param_array(dosyncppp, int, NULL, 0);
 487
 488 static char *driver_name = "SyncLink MultiPort driver";
 489 static char *driver_version = "$Revision: 4.34 $";
 490
 491 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 492 static void synclinkmp_remove_one(struct pci_dev *dev);
 493
 494 static struct pci_device_id synclinkmp_pci_tbl[] = {
 495         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 496         { 0, }, /* terminate list */
 497 };
 498 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 499
 500 MODULE_LICENSE("GPL");
 501
 502 static struct pci_driver synclinkmp_pci_driver = {
 503         .name           = "synclinkmp",
 504         .id_table       = synclinkmp_pci_tbl,
 505         .probe          = synclinkmp_init_one,
 506         .remove         = __devexit_p(synclinkmp_remove_one),
 507 };
 508
 509
 510 static struct tty_driver *serial_driver;
 511
 512 /* number of characters left in xmit buffer before we ask for more */
 513 #define WAKEUP_CHARS 256
 514
 515
 516 /* tty callbacks */
 517
 518 static int  open(struct tty_struct *tty, struct file * filp);
 519 static void close(struct tty_struct *tty, struct file * filp);
 520 static void hangup(struct tty_struct *tty);
 521 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 522
 523 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 524 static void put_char(struct tty_struct *tty, unsigned char ch);
 525 static void send_xchar(struct tty_struct *tty, char ch);
 526 static void wait_until_sent(struct tty_struct *tty, int timeout);
 527 static int  write_room(struct tty_struct *tty);
 528 static void flush_chars(struct tty_struct *tty);
 529 static void flush_buffer(struct tty_struct *tty);
 530 static void tx_hold(struct tty_struct *tty);
 531 static void tx_release(struct tty_struct *tty);
 532
 533 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 534 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 535 static int  chars_in_buffer(struct tty_struct *tty);
 536 static void throttle(struct tty_struct * tty);
 537 static void unthrottle(struct tty_struct * tty);
 538 static void set_break(struct tty_struct *tty, int break_state);
 539
 540 #ifdef CONFIG_HDLC
 541 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 542 static void hdlcdev_tx_done(SLMP_INFO *info);
 543 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 544 static int  hdlcdev_init(SLMP_INFO *info);
 545 static void hdlcdev_exit(SLMP_INFO *info);
 546 #endif
 547
 548 /* ioctl handlers */
 549
 550 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 551 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 552 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 553 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 554 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 555 static int  tx_enable(SLMP_INFO *info, int enable);
 556 static int  tx_abort(SLMP_INFO *info);
 557 static int  rx_enable(SLMP_INFO *info, int enable);
 558 static int  map_status(int signals);
 559 static int  modem_input_wait(SLMP_INFO *info,int arg);
 560 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 561 static int  tiocmget(struct tty_struct *tty, struct file *file);
 562 static int  tiocmset(struct tty_struct *tty, struct file *file,
 563                      unsigned int set, unsigned int clear);
 564 static void set_break(struct tty_struct *tty, int break_state);
 565
 566 static void add_device(SLMP_INFO *info);
 567 static void device_init(int adapter_num, struct pci_dev *pdev);
 568 static int  claim_resources(SLMP_INFO *info);
 569 static void release_resources(SLMP_INFO *info);
 570
 571 static int  startup(SLMP_INFO *info);
 572 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 573 static void shutdown(SLMP_INFO *info);
 574 static void program_hw(SLMP_INFO *info);
 575 static void change_params(SLMP_INFO *info);
 576
 577 static int  init_adapter(SLMP_INFO *info);
 578 static int  register_test(SLMP_INFO *info);
 579 static int  irq_test(SLMP_INFO *info);
 580 static int  loopback_test(SLMP_INFO *info);
 581 static int  adapter_test(SLMP_INFO *info);
 582 static int  memory_test(SLMP_INFO *info);
 583
 584 static void reset_adapter(SLMP_INFO *info);
 585 static void reset_port(SLMP_INFO *info);
 586 static void async_mode(SLMP_INFO *info);
 587 static void hdlc_mode(SLMP_INFO *info);
 588
 589 static void rx_stop(SLMP_INFO *info);
 590 static void rx_start(SLMP_INFO *info);
 591 static void rx_reset_buffers(SLMP_INFO *info);
 592 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 593 static int  rx_get_frame(SLMP_INFO *info);
 594
 595 static void tx_start(SLMP_INFO *info);
 596 static void tx_stop(SLMP_INFO *info);
 597 static void tx_load_fifo(SLMP_INFO *info);
 598 static void tx_set_idle(SLMP_INFO *info);
 599 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 600
 601 static void get_signals(SLMP_INFO *info);
 602 static void set_signals(SLMP_INFO *info);
 603 static void enable_loopback(SLMP_INFO *info, int enable);
 604 static void set_rate(SLMP_INFO *info, u32 data_rate);
 605
 606 static int  bh_action(SLMP_INFO *info);
 607 static void bh_handler(void* Context);
 608 static void bh_receive(SLMP_INFO *info);
 609 static void bh_transmit(SLMP_INFO *info);
 610 static void bh_status(SLMP_INFO *info);
 611 static void isr_timer(SLMP_INFO *info);
 612 static void isr_rxint(SLMP_INFO *info);
 613 static void isr_rxrdy(SLMP_INFO *info);
 614 static void isr_txint(SLMP_INFO *info);
 615 static void isr_txrdy(SLMP_INFO *info);
 616 static void isr_rxdmaok(SLMP_INFO *info);
 617 static void isr_rxdmaerror(SLMP_INFO *info);
 618 static void isr_txdmaok(SLMP_INFO *info);
 619 static void isr_txdmaerror(SLMP_INFO *info);
 620 static void isr_io_pin(SLMP_INFO *info, u16 status);
 621
 622 static int  alloc_dma_bufs(SLMP_INFO *info);
 623 static void free_dma_bufs(SLMP_INFO *info);
 624 static int  alloc_buf_list(SLMP_INFO *info);
 625 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 626 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 627 static void free_tmp_rx_buf(SLMP_INFO *info);
 628
 629 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 630 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 631 static void tx_timeout(unsigned long context);
 632 static void status_timeout(unsigned long context);
 633
 634 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 635 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 636 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 637 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 638 static unsigned char read_status_reg(SLMP_INFO * info);
 639 static void write_control_reg(SLMP_INFO * info);
 640
 641
 642 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 643 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 644 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 645
 646 static u32 misc_ctrl_value = 0x007e4040;
 647 static u32 lcr1_brdr_value = 0x00800029;
 648
 649 static u32 read_ahead_count = 8;
 650
 651 /* DPCR, DMA Priority Control
 652  *
 653  * 07..05  Not used, must be 0
 654  * 04      BRC, bus release condition: 0=all transfers complete
 655  *              1=release after 1 xfer on all channels
 656  * 03      CCC, channel change condition: 0=every cycle
 657  *              1=after each channel completes all xfers
 658  * 02..00  PR<2..0>, priority 100=round robin
 659  *
 660  * 00000100 = 0x00
 661  */
 662 static unsigned char dma_priority = 0x04;
 663
 664 // Number of bytes that can be written to shared RAM
 665 // in a single write operation
 666 static u32 sca_pci_load_interval = 64;
 667
 668 /*
 669  * 1st function defined in .text section. Calling this function in
 670  * init_module() followed by a breakpoint allows a remote debugger
 671  * (gdb) to get the .text address for the add-symbol-file command.
 672  * This allows remote debugging of dynamically loadable modules.
 673  */
 674 static void* synclinkmp_get_text_ptr(void);
 675 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 676
 677 static inline int sanity_check(SLMP_INFO *info,
 678                                char *name, const char *routine)
 679 {
 680 #ifdef SANITY_CHECK
 681         static const char *badmagic =
 682                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 683         static const char *badinfo =
 684                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 685
 686         if (!info) {
 687                 printk(badinfo, name, routine);
 688                 return 1;
 689         }
 690         if (info->magic != MGSL_MAGIC) {
 691                 printk(badmagic, name, routine);
 692                 return 1;
 693         }
 694 #else
 695         if (!info)
 696                 return 1;
 697 #endif
 698         return 0;
 699 }
 700
 701 /**
 702  * line discipline callback wrappers
 703  *
 704  * The wrappers maintain line discipline references
 705  * while calling into the line discipline.
 706  *
 707  * ldisc_receive_buf  - pass receive data to line discipline
 708  */
 709
 710 static void ldisc_receive_buf(struct tty_struct *tty,
 711                               const __u8 *data, char *flags, int count)
 712 {
 713         struct tty_ldisc *ld;
 714         if (!tty)
 715                 return;
 716         ld = tty_ldisc_ref(tty);
 717         if (ld) {
 718                 if (ld->receive_buf)
 719                         ld->receive_buf(tty, data, flags, count);
 720                 tty_ldisc_deref(ld);
 721         }
 722 }
 723
 724 /* tty callbacks */
 725
 726 /* Called when a port is opened.  Init and enable port.
 727  */
 728 static int open(struct tty_struct *tty, struct file *filp)
 729 {
 730         SLMP_INFO *info;
 731         int retval, line;
 732         unsigned long flags;
 733
 734         line = tty->index;
 735         if ((line < 0) || (line >= synclinkmp_device_count)) {
 736                 printk("%s(%d): open with invalid line #%d.\n",
 737                         __FILE__,__LINE__,line);
 738                 return -ENODEV;
 739         }
 740
 741         info = synclinkmp_device_list;
 742         while(info && info->line != line)
 743                 info = info->next_device;
 744         if (sanity_check(info, tty->name, "open"))
 745                 return -ENODEV;
 746         if ( info->init_error ) {
 747                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 748                         __FILE__,__LINE__,info->device_name,info->init_error);
 749                 return -ENODEV;
 750         }
 751
 752         tty->driver_data = info;
 753         info->tty = tty;
 754
 755         if (debug_level >= DEBUG_LEVEL_INFO)
 756                 printk("%s(%d):%s open(), old ref count = %d\n",
 757                          __FILE__,__LINE__,tty->driver->name, info->count);
 758
 759         /* If port is closing, signal caller to try again */
 760         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 761                 if (info->flags & ASYNC_CLOSING)
 762                         interruptible_sleep_on(&info->close_wait);
 763                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 764                         -EAGAIN : -ERESTARTSYS);
 765                 goto cleanup;
 766         }
 767
 768         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 769
 770         spin_lock_irqsave(&info->netlock, flags);
 771         if (info->netcount) {
 772                 retval = -EBUSY;
 773                 spin_unlock_irqrestore(&info->netlock, flags);
 774                 goto cleanup;
 775         }
 776         info->count++;
 777         spin_unlock_irqrestore(&info->netlock, flags);
 778
 779         if (info->count == 1) {
 780                 /* 1st open on this device, init hardware */
 781                 retval = startup(info);
 782                 if (retval < 0)
 783                         goto cleanup;
 784         }
 785
 786         retval = block_til_ready(tty, filp, info);
 787         if (retval) {
 788                 if (debug_level >= DEBUG_LEVEL_INFO)
 789                         printk("%s(%d):%s block_til_ready() returned %d\n",
 790                                  __FILE__,__LINE__, info->device_name, retval);
 791                 goto cleanup;
 792         }
 793
 794         if (debug_level >= DEBUG_LEVEL_INFO)
 795                 printk("%s(%d):%s open() success\n",
 796                          __FILE__,__LINE__, info->device_name);
 797         retval = 0;
 798
 799 cleanup:
 800         if (retval) {
 801                 if (tty->count == 1)
 802                         info->tty = NULL; /* tty layer will release tty struct */
 803                 if(info->count)
 804                         info->count--;
 805         }
 806
 807         return retval;
 808 }
 809
 810 /* Called when port is closed. Wait for remaining data to be
 811  * sent. Disable port and free resources.
 812  */
 813 static void close(struct tty_struct *tty, struct file *filp)
 814 {
 815         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 816
 817         if (sanity_check(info, tty->name, "close"))
 818                 return;
 819
 820         if (debug_level >= DEBUG_LEVEL_INFO)
 821                 printk("%s(%d):%s close() entry, count=%d\n",
 822                          __FILE__,__LINE__, info->device_name, info->count);
 823
 824         if (!info->count)
 825                 return;
 826
 827         if (tty_hung_up_p(filp))
 828                 goto cleanup;
 829
 830         if ((tty->count == 1) && (info->count != 1)) {
 831                 /*
 832                  * tty->count is 1 and the tty structure will be freed.
 833                  * info->count should be one in this case.
 834                  * if it's not, correct it so that the port is shutdown.
 835                  */
 836                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 837                        "info->count is %d\n",
 838                          __FILE__,__LINE__, info->device_name, info->count);
 839                 info->count = 1;
 840         }
 841
 842         info->count--;
 843
 844         /* if at least one open remaining, leave hardware active */
 845         if (info->count)
 846                 goto cleanup;
 847
 848         info->flags |= ASYNC_CLOSING;
 849
 850         /* set tty->closing to notify line discipline to
 851          * only process XON/XOFF characters. Only the N_TTY
 852          * discipline appears to use this (ppp does not).
 853          */
 854         tty->closing = 1;
 855
 856         /* wait for transmit data to clear all layers */
 857
 858         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 859                 if (debug_level >= DEBUG_LEVEL_INFO)
 860                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 861                                  __FILE__,__LINE__, info->device_name );
 862                 tty_wait_until_sent(tty, info->closing_wait);
 863         }
 864
 865         if (info->flags & ASYNC_INITIALIZED)
 866                 wait_until_sent(tty, info->timeout);
 867
 868         if (tty->driver->flush_buffer)
 869                 tty->driver->flush_buffer(tty);
 870
 871         tty_ldisc_flush(tty);
 872
 873         shutdown(info);
 874
 875         tty->closing = 0;
 876         info->tty = NULL;
 877
 878         if (info->blocked_open) {
 879                 if (info->close_delay) {
 880                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 881                 }
 882                 wake_up_interruptible(&info->open_wait);
 883         }
 884
 885         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 886
 887         wake_up_interruptible(&info->close_wait);
 888
 889 cleanup:
 890         if (debug_level >= DEBUG_LEVEL_INFO)
 891                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 892                         tty->driver->name, info->count);
 893 }
 894
 895 /* Called by tty_hangup() when a hangup is signaled.
 896  * This is the same as closing all open descriptors for the port.
 897  */
 898 static void hangup(struct tty_struct *tty)
 899 {
 900         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 901
 902         if (debug_level >= DEBUG_LEVEL_INFO)
 903                 printk("%s(%d):%s hangup()\n",
 904                          __FILE__,__LINE__, info->device_name );
 905
 906         if (sanity_check(info, tty->name, "hangup"))
 907                 return;
 908
 909         flush_buffer(tty);
 910         shutdown(info);
 911
 912         info->count = 0;
 913         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 914         info->tty = NULL;
 915
 916         wake_up_interruptible(&info->open_wait);
 917 }
 918
 919 /* Set new termios settings
 920  */
 921 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 922 {
 923         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 924         unsigned long flags;
 925
 926         if (debug_level >= DEBUG_LEVEL_INFO)
 927                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 928                         tty->driver->name );
 929
 930         /* just return if nothing has changed */
 931         if ((tty->termios->c_cflag == old_termios->c_cflag)
 932             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 933                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 934           return;
 935
 936         change_params(info);
 937
 938         /* Handle transition to B0 status */
 939         if (old_termios->c_cflag & CBAUD &&
 940             !(tty->termios->c_cflag & CBAUD)) {
 941                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 942                 spin_lock_irqsave(&info->lock,flags);
 943                 set_signals(info);
 944                 spin_unlock_irqrestore(&info->lock,flags);
 945         }
 946
 947         /* Handle transition away from B0 status */
 948         if (!(old_termios->c_cflag & CBAUD) &&
 949             tty->termios->c_cflag & CBAUD) {
 950                 info->serial_signals |= SerialSignal_DTR;
 951                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 952                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 953                         info->serial_signals |= SerialSignal_RTS;
 954                 }
 955                 spin_lock_irqsave(&info->lock,flags);
 956                 set_signals(info);
 957                 spin_unlock_irqrestore(&info->lock,flags);
 958         }
 959
 960         /* Handle turning off CRTSCTS */
 961         if (old_termios->c_cflag & CRTSCTS &&
 962             !(tty->termios->c_cflag & CRTSCTS)) {
 963                 tty->hw_stopped = 0;
 964                 tx_release(tty);
 965         }
 966 }
 967
 968 /* Send a block of data
 969  *
 970  * Arguments:
 971  *
 972  *      tty             pointer to tty information structure
 973  *      buf             pointer to buffer containing send data
 974  *      count           size of send data in bytes
 975  *
 976  * Return Value:        number of characters written
 977  */
 978 static int write(struct tty_struct *tty,
 979                  const unsigned char *buf, int count)
 980 {
 981         int     c, ret = 0;
 982         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 983         unsigned long flags;
 984
 985         if (debug_level >= DEBUG_LEVEL_INFO)
 986                 printk("%s(%d):%s write() count=%d\n",
 987                        __FILE__,__LINE__,info->device_name,count);
 988
 989         if (sanity_check(info, tty->name, "write"))
 990                 goto cleanup;
 991
 992         if (!tty || !info->tx_buf)
 993                 goto cleanup;
 994
 995         if (info->params.mode == MGSL_MODE_HDLC) {
 996                 if (count > info->max_frame_size) {
 997                         ret = -EIO;
 998                         goto cleanup;
 999                 }
1000                 if (info->tx_active)
1001                         goto cleanup;
1002                 if (info->tx_count) {
1003                         /* send accumulated data from send_char() calls */
1004                         /* as frame and wait before accepting more data. */
1005                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1006                         goto start;
1007                 }
1008                 ret = info->tx_count = count;
1009                 tx_load_dma_buffer(info, buf, count);
1010                 goto start;
1011         }
1012
1013         for (;;) {
1014                 c = min_t(int, count,
1015                         min(info->max_frame_size - info->tx_count - 1,
1016                             info->max_frame_size - info->tx_put));
1017                 if (c <= 0)
1018                         break;
1019
1020                 memcpy(info->tx_buf + info->tx_put, buf, c);
1021
1022                 spin_lock_irqsave(&info->lock,flags);
1023                 info->tx_put += c;
1024                 if (info->tx_put >= info->max_frame_size)
1025                         info->tx_put -= info->max_frame_size;
1026                 info->tx_count += c;
1027                 spin_unlock_irqrestore(&info->lock,flags);
1028
1029                 buf += c;
1030                 count -= c;
1031                 ret += c;
1032         }
1033
1034         if (info->params.mode == MGSL_MODE_HDLC) {
1035                 if (count) {
1036                         ret = info->tx_count = 0;
1037                         goto cleanup;
1038                 }
1039                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1040         }
1041 start:
1042         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1043                 spin_lock_irqsave(&info->lock,flags);
1044                 if (!info->tx_active)
1045                         tx_start(info);
1046                 spin_unlock_irqrestore(&info->lock,flags);
1047         }
1048
1049 cleanup:
1050         if (debug_level >= DEBUG_LEVEL_INFO)
1051                 printk( "%s(%d):%s write() returning=%d\n",
1052                         __FILE__,__LINE__,info->device_name,ret);
1053         return ret;
1054 }
1055
1056 /* Add a character to the transmit buffer.
1057  */
1058 static void put_char(struct tty_struct *tty, unsigned char ch)
1059 {
1060         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1061         unsigned long flags;
1062
1063         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1064                 printk( "%s(%d):%s put_char(%d)\n",
1065                         __FILE__,__LINE__,info->device_name,ch);
1066         }
1067
1068         if (sanity_check(info, tty->name, "put_char"))
1069                 return;
1070
1071         if (!tty || !info->tx_buf)
1072                 return;
1073
1074         spin_lock_irqsave(&info->lock,flags);
1075
1076         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1077              !info->tx_active ) {
1078
1079                 if (info->tx_count < info->max_frame_size - 1) {
1080                         info->tx_buf[info->tx_put++] = ch;
1081                         if (info->tx_put >= info->max_frame_size)
1082                                 info->tx_put -= info->max_frame_size;
1083                         info->tx_count++;
1084                 }
1085         }
1086
1087         spin_unlock_irqrestore(&info->lock,flags);
1088 }
1089
1090 /* Send a high-priority XON/XOFF character
1091  */
1092 static void send_xchar(struct tty_struct *tty, char ch)
1093 {
1094         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1095         unsigned long flags;
1096
1097         if (debug_level >= DEBUG_LEVEL_INFO)
1098                 printk("%s(%d):%s send_xchar(%d)\n",
1099                          __FILE__,__LINE__, info->device_name, ch );
1100
1101         if (sanity_check(info, tty->name, "send_xchar"))
1102                 return;
1103
1104         info->x_char = ch;
1105         if (ch) {
1106                 /* Make sure transmit interrupts are on */
1107                 spin_lock_irqsave(&info->lock,flags);
1108                 if (!info->tx_enabled)
1109                         tx_start(info);
1110                 spin_unlock_irqrestore(&info->lock,flags);
1111         }
1112 }
1113
1114 /* Wait until the transmitter is empty.
1115  */
1116 static void wait_until_sent(struct tty_struct *tty, int timeout)
1117 {
1118         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1119         unsigned long orig_jiffies, char_time;
1120
1121         if (!info )
1122                 return;
1123
1124         if (debug_level >= DEBUG_LEVEL_INFO)
1125                 printk("%s(%d):%s wait_until_sent() entry\n",
1126                          __FILE__,__LINE__, info->device_name );
1127
1128         if (sanity_check(info, tty->name, "wait_until_sent"))
1129                 return;
1130
1131         if (!(info->flags & ASYNC_INITIALIZED))
1132                 goto exit;
1133
1134         orig_jiffies = jiffies;
1135
1136         /* Set check interval to 1/5 of estimated time to
1137          * send a character, and make it at least 1. The check
1138          * interval should also be less than the timeout.
1139          * Note: use tight timings here to satisfy the NIST-PCTS.
1140          */
1141
1142         if ( info->params.data_rate ) {
1143                 char_time = info->timeout/(32 * 5);
1144                 if (!char_time)
1145                         char_time++;
1146         } else
1147                 char_time = 1;
1148
1149         if (timeout)
1150                 char_time = min_t(unsigned long, char_time, timeout);
1151
1152         if ( info->params.mode == MGSL_MODE_HDLC ) {
1153                 while (info->tx_active) {
1154                         msleep_interruptible(jiffies_to_msecs(char_time));
1155                         if (signal_pending(current))
1156                                 break;
1157                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1158                                 break;
1159                 }
1160         } else {
1161                 //TODO: determine if there is something similar to USC16C32
1162                 //      TXSTATUS_ALL_SENT status
1163                 while ( info->tx_active && info->tx_enabled) {
1164                         msleep_interruptible(jiffies_to_msecs(char_time));
1165                         if (signal_pending(current))
1166                                 break;
1167                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1168                                 break;
1169                 }
1170         }
1171
1172 exit:
1173         if (debug_level >= DEBUG_LEVEL_INFO)
1174                 printk("%s(%d):%s wait_until_sent() exit\n",
1175                          __FILE__,__LINE__, info->device_name );
1176 }
1177
1178 /* Return the count of free bytes in transmit buffer
1179  */
1180 static int write_room(struct tty_struct *tty)
1181 {
1182         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1183         int ret;
1184
1185         if (sanity_check(info, tty->name, "write_room"))
1186                 return 0;
1187
1188         if (info->params.mode == MGSL_MODE_HDLC) {
1189                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1190         } else {
1191                 ret = info->max_frame_size - info->tx_count - 1;
1192                 if (ret < 0)
1193                         ret = 0;
1194         }
1195
1196         if (debug_level >= DEBUG_LEVEL_INFO)
1197                 printk("%s(%d):%s write_room()=%d\n",
1198                        __FILE__, __LINE__, info->device_name, ret);
1199
1200         return ret;
1201 }
1202
1203 /* enable transmitter and send remaining buffered characters
1204  */
1205 static void flush_chars(struct tty_struct *tty)
1206 {
1207         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1208         unsigned long flags;
1209
1210         if ( debug_level >= DEBUG_LEVEL_INFO )
1211                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1212                         __FILE__,__LINE__,info->device_name,info->tx_count);
1213
1214         if (sanity_check(info, tty->name, "flush_chars"))
1215                 return;
1216
1217         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1218             !info->tx_buf)
1219                 return;
1220
1221         if ( debug_level >= DEBUG_LEVEL_INFO )
1222                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1223                         __FILE__,__LINE__,info->device_name );
1224
1225         spin_lock_irqsave(&info->lock,flags);
1226
1227         if (!info->tx_active) {
1228                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1229                         info->tx_count ) {
1230                         /* operating in synchronous (frame oriented) mode */
1231                         /* copy data from circular tx_buf to */
1232                         /* transmit DMA buffer. */
1233                         tx_load_dma_buffer(info,
1234                                  info->tx_buf,info->tx_count);
1235                 }
1236                 tx_start(info);
1237         }
1238
1239         spin_unlock_irqrestore(&info->lock,flags);
1240 }
1241
1242 /* Discard all data in the send buffer
1243  */
1244 static void flush_buffer(struct tty_struct *tty)
1245 {
1246         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1247         unsigned long flags;
1248
1249         if (debug_level >= DEBUG_LEVEL_INFO)
1250                 printk("%s(%d):%s flush_buffer() entry\n",
1251                          __FILE__,__LINE__, info->device_name );
1252
1253         if (sanity_check(info, tty->name, "flush_buffer"))
1254                 return;
1255
1256         spin_lock_irqsave(&info->lock,flags);
1257         info->tx_count = info->tx_put = info->tx_get = 0;
1258         del_timer(&info->tx_timer);
1259         spin_unlock_irqrestore(&info->lock,flags);
1260
1261         wake_up_interruptible(&tty->write_wait);
1262         tty_wakeup(tty);
1263 }
1264
1265 /* throttle (stop) transmitter
1266  */
1267 static void tx_hold(struct tty_struct *tty)
1268 {
1269         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1270         unsigned long flags;
1271
1272         if (sanity_check(info, tty->name, "tx_hold"))
1273                 return;
1274
1275         if ( debug_level >= DEBUG_LEVEL_INFO )
1276                 printk("%s(%d):%s tx_hold()\n",
1277                         __FILE__,__LINE__,info->device_name);
1278
1279         spin_lock_irqsave(&info->lock,flags);
1280         if (info->tx_enabled)
1281                 tx_stop(info);
1282         spin_unlock_irqrestore(&info->lock,flags);
1283 }
1284
1285 /* release (start) transmitter
1286  */
1287 static void tx_release(struct tty_struct *tty)
1288 {
1289         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1290         unsigned long flags;
1291
1292         if (sanity_check(info, tty->name, "tx_release"))
1293                 return;
1294
1295         if ( debug_level >= DEBUG_LEVEL_INFO )
1296                 printk("%s(%d):%s tx_release()\n",
1297                         __FILE__,__LINE__,info->device_name);
1298
1299         spin_lock_irqsave(&info->lock,flags);
1300         if (!info->tx_enabled)
1301                 tx_start(info);
1302         spin_unlock_irqrestore(&info->lock,flags);
1303 }
1304
1305 /* Service an IOCTL request
1306  *
1307  * Arguments:
1308  *
1309  *      tty     pointer to tty instance data
1310  *      file    pointer to associated file object for device
1311  *      cmd     IOCTL command code
1312  *      arg     command argument/context
1313  *
1314  * Return Value:        0 if success, otherwise error code
1315  */
1316 static int ioctl(struct tty_struct *tty, struct file *file,
1317                  unsigned int cmd, unsigned long arg)
1318 {
1319         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1320         int error;
1321         struct mgsl_icount cnow;        /* kernel counter temps */
1322         struct serial_icounter_struct __user *p_cuser;  /* user space */
1323         unsigned long flags;
1324         void __user *argp = (void __user *)arg;
1325
1326         if (debug_level >= DEBUG_LEVEL_INFO)
1327                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1328                         info->device_name, cmd );
1329
1330         if (sanity_check(info, tty->name, "ioctl"))
1331                 return -ENODEV;
1332
1333         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1334             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1335                 if (tty->flags & (1 << TTY_IO_ERROR))
1336                     return -EIO;
1337         }
1338
1339         switch (cmd) {
1340         case MGSL_IOCGPARAMS:
1341                 return get_params(info, argp);
1342         case MGSL_IOCSPARAMS:
1343                 return set_params(info, argp);
1344         case MGSL_IOCGTXIDLE:
1345                 return get_txidle(info, argp);
1346         case MGSL_IOCSTXIDLE:
1347                 return set_txidle(info, (int)arg);
1348         case MGSL_IOCTXENABLE:
1349                 return tx_enable(info, (int)arg);
1350         case MGSL_IOCRXENABLE:
1351                 return rx_enable(info, (int)arg);
1352         case MGSL_IOCTXABORT:
1353                 return tx_abort(info);
1354         case MGSL_IOCGSTATS:
1355                 return get_stats(info, argp);
1356         case MGSL_IOCWAITEVENT:
1357                 return wait_mgsl_event(info, argp);
1358         case MGSL_IOCLOOPTXDONE:
1359                 return 0; // TODO: Not supported, need to document
1360                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1361                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1362                  */
1363         case TIOCMIWAIT:
1364                 return modem_input_wait(info,(int)arg);
1365
1366                 /*
1367                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1368                  * Return: write counters to the user passed counter struct
1369                  * NB: both 1->0 and 0->1 transitions are counted except for
1370                  *     RI where only 0->1 is counted.
1371                  */
1372         case TIOCGICOUNT:
1373                 spin_lock_irqsave(&info->lock,flags);
1374                 cnow = info->icount;
1375                 spin_unlock_irqrestore(&info->lock,flags);
1376                 p_cuser = argp;
1377                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1378                 if (error) return error;
1379                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1380                 if (error) return error;
1381                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1382                 if (error) return error;
1383                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1384                 if (error) return error;
1385                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1386                 if (error) return error;
1387                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1388                 if (error) return error;
1389                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1390                 if (error) return error;
1391                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1392                 if (error) return error;
1393                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1394                 if (error) return error;
1395                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1396                 if (error) return error;
1397                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1398                 if (error) return error;
1399                 return 0;
1400         default:
1401                 return -ENOIOCTLCMD;
1402         }
1403         return 0;
1404 }
1405
1406 /*
1407  * /proc fs routines....
1408  */
1409
1410 static inline int line_info(char *buf, SLMP_INFO *info)
1411 {
1412         char    stat_buf[30];
1413         int     ret;
1414         unsigned long flags;
1415
1416         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1417                        "\tIRQ=%d MaxFrameSize=%u\n",
1418                 info->device_name,
1419                 info->phys_sca_base,
1420                 info->phys_memory_base,
1421                 info->phys_statctrl_base,
1422                 info->phys_lcr_base,
1423                 info->irq_level,
1424                 info->max_frame_size );
1425
1426         /* output current serial signal states */
1427         spin_lock_irqsave(&info->lock,flags);
1428         get_signals(info);
1429         spin_unlock_irqrestore(&info->lock,flags);
1430
1431         stat_buf[0] = 0;
1432         stat_buf[1] = 0;
1433         if (info->serial_signals & SerialSignal_RTS)
1434                 strcat(stat_buf, "|RTS");
1435         if (info->serial_signals & SerialSignal_CTS)
1436                 strcat(stat_buf, "|CTS");
1437         if (info->serial_signals & SerialSignal_DTR)
1438                 strcat(stat_buf, "|DTR");
1439         if (info->serial_signals & SerialSignal_DSR)
1440                 strcat(stat_buf, "|DSR");
1441         if (info->serial_signals & SerialSignal_DCD)
1442                 strcat(stat_buf, "|CD");
1443         if (info->serial_signals & SerialSignal_RI)
1444                 strcat(stat_buf, "|RI");
1445
1446         if (info->params.mode == MGSL_MODE_HDLC) {
1447                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1448                               info->icount.txok, info->icount.rxok);
1449                 if (info->icount.txunder)
1450                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1451                 if (info->icount.txabort)
1452                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1453                 if (info->icount.rxshort)
1454                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1455                 if (info->icount.rxlong)
1456                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1457                 if (info->icount.rxover)
1458                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1459                 if (info->icount.rxcrc)
1460                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1461         } else {
1462                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1463                               info->icount.tx, info->icount.rx);
1464                 if (info->icount.frame)
1465                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1466                 if (info->icount.parity)
1467                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1468                 if (info->icount.brk)
1469                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1470                 if (info->icount.overrun)
1471                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1472         }
1473
1474         /* Append serial signal status to end */
1475         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1476
1477         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1478          info->tx_active,info->bh_requested,info->bh_running,
1479          info->pending_bh);
1480
1481         return ret;
1482 }
1483
1484 /* Called to print information about devices
1485  */
1486 int read_proc(char *page, char **start, off_t off, int count,
1487               int *eof, void *data)
1488 {
1489         int len = 0, l;
1490         off_t   begin = 0;
1491         SLMP_INFO *info;
1492
1493         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1494
1495         info = synclinkmp_device_list;
1496         while( info ) {
1497                 l = line_info(page + len, info);
1498                 len += l;
1499                 if (len+begin > off+count)
1500                         goto done;
1501                 if (len+begin < off) {
1502                         begin += len;
1503                         len = 0;
1504                 }
1505                 info = info->next_device;
1506         }
1507
1508         *eof = 1;
1509 done:
1510         if (off >= len+begin)
1511                 return 0;
1512         *start = page + (off-begin);
1513         return ((count < begin+len-off) ? count : begin+len-off);
1514 }
1515
1516 /* Return the count of bytes in transmit buffer
1517  */
1518 static int chars_in_buffer(struct tty_struct *tty)
1519 {
1520         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1521
1522         if (sanity_check(info, tty->name, "chars_in_buffer"))
1523                 return 0;
1524
1525         if (debug_level >= DEBUG_LEVEL_INFO)
1526                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1527                        __FILE__, __LINE__, info->device_name, info->tx_count);
1528
1529         return info->tx_count;
1530 }
1531
1532 /* Signal remote device to throttle send data (our receive data)
1533  */
1534 static void throttle(struct tty_struct * tty)
1535 {
1536         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1537         unsigned long flags;
1538
1539         if (debug_level >= DEBUG_LEVEL_INFO)
1540                 printk("%s(%d):%s throttle() entry\n",
1541                          __FILE__,__LINE__, info->device_name );
1542
1543         if (sanity_check(info, tty->name, "throttle"))
1544                 return;
1545
1546         if (I_IXOFF(tty))
1547                 send_xchar(tty, STOP_CHAR(tty));
1548
1549         if (tty->termios->c_cflag & CRTSCTS) {
1550                 spin_lock_irqsave(&info->lock,flags);
1551                 info->serial_signals &= ~SerialSignal_RTS;
1552                 set_signals(info);
1553                 spin_unlock_irqrestore(&info->lock,flags);
1554         }
1555 }
1556
1557 /* Signal remote device to stop throttling send data (our receive data)
1558  */
1559 static void unthrottle(struct tty_struct * tty)
1560 {
1561         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1562         unsigned long flags;
1563
1564         if (debug_level >= DEBUG_LEVEL_INFO)
1565                 printk("%s(%d):%s unthrottle() entry\n",
1566                          __FILE__,__LINE__, info->device_name );
1567
1568         if (sanity_check(info, tty->name, "unthrottle"))
1569                 return;
1570
1571         if (I_IXOFF(tty)) {
1572                 if (info->x_char)
1573                         info->x_char = 0;
1574                 else
1575                         send_xchar(tty, START_CHAR(tty));
1576         }
1577
1578         if (tty->termios->c_cflag & CRTSCTS) {
1579                 spin_lock_irqsave(&info->lock,flags);
1580                 info->serial_signals |= SerialSignal_RTS;
1581                 set_signals(info);
1582                 spin_unlock_irqrestore(&info->lock,flags);
1583         }
1584 }
1585
1586 /* set or clear transmit break condition
1587  * break_state  -1=set break condition, 0=clear
1588  */
1589 static void set_break(struct tty_struct *tty, int break_state)
1590 {
1591         unsigned char RegValue;
1592         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1593         unsigned long flags;
1594
1595         if (debug_level >= DEBUG_LEVEL_INFO)
1596                 printk("%s(%d):%s set_break(%d)\n",
1597                          __FILE__,__LINE__, info->device_name, break_state);
1598
1599         if (sanity_check(info, tty->name, "set_break"))
1600                 return;
1601
1602         spin_lock_irqsave(&info->lock,flags);
1603         RegValue = read_reg(info, CTL);
1604         if (break_state == -1)
1605                 RegValue |= BIT3;
1606         else
1607                 RegValue &= ~BIT3;
1608         write_reg(info, CTL, RegValue);
1609         spin_unlock_irqrestore(&info->lock,flags);
1610 }
1611
1612 #ifdef CONFIG_HDLC
1613
1614 /**
1615  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1616  * set encoding and frame check sequence (FCS) options
1617  *
1618  * dev       pointer to network device structure
1619  * encoding  serial encoding setting
1620  * parity    FCS setting
1621  *
1622  * returns 0 if success, otherwise error code
1623  */
1624 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1625                           unsigned short parity)
1626 {
1627         SLMP_INFO *info = dev_to_port(dev);
1628         unsigned char  new_encoding;
1629         unsigned short new_crctype;
1630
1631         /* return error if TTY interface open */
1632         if (info->count)
1633                 return -EBUSY;
1634
1635         switch (encoding)
1636         {
1637         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1638         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1639         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1640         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1641         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1642         default: return -EINVAL;
1643         }
1644
1645         switch (parity)
1646         {
1647         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1648         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1649         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1650         default: return -EINVAL;
1651         }
1652
1653         info->params.encoding = new_encoding;
1654         info->params.crc_type = new_crctype;;
1655
1656         /* if network interface up, reprogram hardware */
1657         if (info->netcount)
1658                 program_hw(info);
1659
1660         return 0;
1661 }
1662
1663 /**
1664  * called by generic HDLC layer to send frame
1665  *
1666  * skb  socket buffer containing HDLC frame
1667  * dev  pointer to network device structure
1668  *
1669  * returns 0 if success, otherwise error code
1670  */
1671 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1672 {
1673         SLMP_INFO *info = dev_to_port(dev);
1674         struct net_device_stats *stats = hdlc_stats(dev);
1675         unsigned long flags;
1676
1677         if (debug_level >= DEBUG_LEVEL_INFO)
1678                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1679
1680         /* stop sending until this frame completes */
1681         netif_stop_queue(dev);
1682
1683         /* copy data to device buffers */
1684         info->tx_count = skb->len;
1685         tx_load_dma_buffer(info, skb->data, skb->len);
1686
1687         /* update network statistics */
1688         stats->tx_packets++;
1689         stats->tx_bytes += skb->len;
1690
1691         /* done with socket buffer, so free it */
1692         dev_kfree_skb(skb);
1693
1694         /* save start time for transmit timeout detection */
1695         dev->trans_start = jiffies;
1696
1697         /* start hardware transmitter if necessary */
1698         spin_lock_irqsave(&info->lock,flags);
1699         if (!info->tx_active)
1700                 tx_start(info);
1701         spin_unlock_irqrestore(&info->lock,flags);
1702
1703         return 0;
1704 }
1705
1706 /**
1707  * called by network layer when interface enabled
1708  * claim resources and initialize hardware
1709  *
1710  * dev  pointer to network device structure
1711  *
1712  * returns 0 if success, otherwise error code
1713  */
1714 static int hdlcdev_open(struct net_device *dev)
1715 {
1716         SLMP_INFO *info = dev_to_port(dev);
1717         int rc;
1718         unsigned long flags;
1719
1720         if (debug_level >= DEBUG_LEVEL_INFO)
1721                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1722
1723         /* generic HDLC layer open processing */
1724         if ((rc = hdlc_open(dev)))
1725                 return rc;
1726
1727         /* arbitrate between network and tty opens */
1728         spin_lock_irqsave(&info->netlock, flags);
1729         if (info->count != 0 || info->netcount != 0) {
1730                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1731                 spin_unlock_irqrestore(&info->netlock, flags);
1732                 return -EBUSY;
1733         }
1734         info->netcount=1;
1735         spin_unlock_irqrestore(&info->netlock, flags);
1736
1737         /* claim resources and init adapter */
1738         if ((rc = startup(info)) != 0) {
1739                 spin_lock_irqsave(&info->netlock, flags);
1740                 info->netcount=0;
1741                 spin_unlock_irqrestore(&info->netlock, flags);
1742                 return rc;
1743         }
1744
1745         /* assert DTR and RTS, apply hardware settings */
1746         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1747         program_hw(info);
1748
1749         /* enable network layer transmit */
1750         dev->trans_start = jiffies;
1751         netif_start_queue(dev);
1752
1753         /* inform generic HDLC layer of current DCD status */
1754         spin_lock_irqsave(&info->lock, flags);
1755         get_signals(info);
1756         spin_unlock_irqrestore(&info->lock, flags);
1757         hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
1758
1759         return 0;
1760 }
1761
1762 /**
1763  * called by network layer when interface is disabled
1764  * shutdown hardware and release resources
1765  *
1766  * dev  pointer to network device structure
1767  *
1768  * returns 0 if success, otherwise error code
1769  */
1770 static int hdlcdev_close(struct net_device *dev)
1771 {
1772         SLMP_INFO *info = dev_to_port(dev);
1773         unsigned long flags;
1774
1775         if (debug_level >= DEBUG_LEVEL_INFO)
1776                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1777
1778         netif_stop_queue(dev);
1779
1780         /* shutdown adapter and release resources */
1781         shutdown(info);
1782
1783         hdlc_close(dev);
1784
1785         spin_lock_irqsave(&info->netlock, flags);
1786         info->netcount=0;
1787         spin_unlock_irqrestore(&info->netlock, flags);
1788
1789         return 0;
1790 }
1791
1792 /**
1793  * called by network layer to process IOCTL call to network device
1794  *
1795  * dev  pointer to network device structure
1796  * ifr  pointer to network interface request structure
1797  * cmd  IOCTL command code
1798  *
1799  * returns 0 if success, otherwise error code
1800  */
1801 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1802 {
1803         const size_t size = sizeof(sync_serial_settings);
1804         sync_serial_settings new_line;
1805         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1806         SLMP_INFO *info = dev_to_port(dev);
1807         unsigned int flags;
1808
1809         if (debug_level >= DEBUG_LEVEL_INFO)
1810                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1811
1812         /* return error if TTY interface open */
1813         if (info->count)
1814                 return -EBUSY;
1815
1816         if (cmd != SIOCWANDEV)
1817                 return hdlc_ioctl(dev, ifr, cmd);
1818
1819         switch(ifr->ifr_settings.type) {
1820         case IF_GET_IFACE: /* return current sync_serial_settings */
1821
1822                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1823                 if (ifr->ifr_settings.size < size) {
1824                         ifr->ifr_settings.size = size; /* data size wanted */
1825                         return -ENOBUFS;
1826                 }
1827
1828                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1829                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1830                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1831                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1832
1833                 switch (flags){
1834                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1835                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1836                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1837                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1838                 default: new_line.clock_type = CLOCK_DEFAULT;
1839                 }
1840
1841                 new_line.clock_rate = info->params.clock_speed;
1842                 new_line.loopback   = info->params.loopback ? 1:0;
1843
1844                 if (copy_to_user(line, &new_line, size))
1845                         return -EFAULT;
1846                 return 0;
1847
1848         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1849
1850                 if(!capable(CAP_NET_ADMIN))
1851                         return -EPERM;
1852                 if (copy_from_user(&new_line, line, size))
1853                         return -EFAULT;
1854
1855                 switch (new_line.clock_type)
1856                 {
1857                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1858                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1859                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1860                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1861                 case CLOCK_DEFAULT:  flags = info->params.flags &
1862                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1863                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1864                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1865                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1866                 default: return -EINVAL;
1867                 }
1868
1869                 if (new_line.loopback != 0 && new_line.loopback != 1)
1870                         return -EINVAL;
1871
1872                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1873                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1874                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1875                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1876                 info->params.flags |= flags;
1877
1878                 info->params.loopback = new_line.loopback;
1879
1880                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1881                         info->params.clock_speed = new_line.clock_rate;
1882                 else
1883                         info->params.clock_speed = 0;
1884
1885                 /* if network interface up, reprogram hardware */
1886                 if (info->netcount)
1887                         program_hw(info);
1888                 return 0;
1889
1890         default:
1891                 return hdlc_ioctl(dev, ifr, cmd);
1892         }
1893 }
1894
1895 /**
1896  * called by network layer when transmit timeout is detected
1897  *
1898  * dev  pointer to network device structure
1899  */
1900 static void hdlcdev_tx_timeout(struct net_device *dev)
1901 {
1902         SLMP_INFO *info = dev_to_port(dev);
1903         struct net_device_stats *stats = hdlc_stats(dev);
1904         unsigned long flags;
1905
1906         if (debug_level >= DEBUG_LEVEL_INFO)
1907                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1908
1909         stats->tx_errors++;
1910         stats->tx_aborted_errors++;
1911
1912         spin_lock_irqsave(&info->lock,flags);
1913         tx_stop(info);
1914         spin_unlock_irqrestore(&info->lock,flags);
1915
1916         netif_wake_queue(dev);
1917 }
1918
1919 /**
1920  * called by device driver when transmit completes
1921  * reenable network layer transmit if stopped
1922  *
1923  * info  pointer to device instance information
1924  */
1925 static void hdlcdev_tx_done(SLMP_INFO *info)
1926 {
1927         if (netif_queue_stopped(info->netdev))
1928                 netif_wake_queue(info->netdev);
1929 }
1930
1931 /**
1932  * called by device driver when frame received
1933  * pass frame to network layer
1934  *
1935  * info  pointer to device instance information
1936  * buf   pointer to buffer contianing frame data
1937  * size  count of data bytes in buf
1938  */
1939 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1940 {
1941         struct sk_buff *skb = dev_alloc_skb(size);
1942         struct net_device *dev = info->netdev;
1943         struct net_device_stats *stats = hdlc_stats(dev);
1944
1945         if (debug_level >= DEBUG_LEVEL_INFO)
1946                 printk("hdlcdev_rx(%s)\n",dev->name);
1947
1948         if (skb == NULL) {
1949                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1950                 stats->rx_dropped++;
1951                 return;
1952         }
1953
1954         memcpy(skb_put(skb, size),buf,size);
1955
1956         skb->protocol = hdlc_type_trans(skb, info->netdev);
1957
1958         stats->rx_packets++;
1959         stats->rx_bytes += size;
1960
1961         netif_rx(skb);
1962
1963         info->netdev->last_rx = jiffies;
1964 }
1965
1966 /**
1967  * called by device driver when adding device instance
1968  * do generic HDLC initialization
1969  *
1970  * info  pointer to device instance information
1971  *
1972  * returns 0 if success, otherwise error code
1973  */
1974 static int hdlcdev_init(SLMP_INFO *info)
1975 {
1976         int rc;
1977         struct net_device *dev;
1978         hdlc_device *hdlc;
1979
1980         /* allocate and initialize network and HDLC layer objects */
1981
1982         if (!(dev = alloc_hdlcdev(info))) {
1983                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1984                 return -ENOMEM;
1985         }
1986
1987         /* for network layer reporting purposes only */
1988         dev->mem_start = info->phys_sca_base;
1989         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1990         dev->irq       = info->irq_level;
1991
1992         /* network layer callbacks and settings */
1993         dev->do_ioctl       = hdlcdev_ioctl;
1994         dev->open           = hdlcdev_open;
1995         dev->stop           = hdlcdev_close;
1996         dev->tx_timeout     = hdlcdev_tx_timeout;
1997         dev->watchdog_timeo = 10*HZ;
1998         dev->tx_queue_len   = 50;
1999
2000         /* generic HDLC layer callbacks and settings */
2001         hdlc         = dev_to_hdlc(dev);
2002         hdlc->attach = hdlcdev_attach;
2003         hdlc->xmit   = hdlcdev_xmit;
2004
2005         /* register objects with HDLC layer */
2006         if ((rc = register_hdlc_device(dev))) {
2007                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2008                 free_netdev(dev);
2009                 return rc;
2010         }
2011
2012         info->netdev = dev;
2013         return 0;
2014 }
2015
2016 /**
2017  * called by device driver when removing device instance
2018  * do generic HDLC cleanup
2019  *
2020  * info  pointer to device instance information
2021  */
2022 static void hdlcdev_exit(SLMP_INFO *info)
2023 {
2024         unregister_hdlc_device(info->netdev);
2025         free_netdev(info->netdev);
2026         info->netdev = NULL;
2027 }
2028
2029 #endif /* CONFIG_HDLC */
2030
2031
2032 /* Return next bottom half action to perform.
2033  * Return Value:        BH action code or 0 if nothing to do.
2034  */
2035 int bh_action(SLMP_INFO *info)
2036 {
2037         unsigned long flags;
2038         int rc = 0;
2039
2040         spin_lock_irqsave(&info->lock,flags);
2041
2042         if (info->pending_bh & BH_RECEIVE) {
2043                 info->pending_bh &= ~BH_RECEIVE;
2044                 rc = BH_RECEIVE;
2045         } else if (info->pending_bh & BH_TRANSMIT) {
2046                 info->pending_bh &= ~BH_TRANSMIT;
2047                 rc = BH_TRANSMIT;
2048         } else if (info->pending_bh & BH_STATUS) {
2049                 info->pending_bh &= ~BH_STATUS;
2050                 rc = BH_STATUS;
2051         }
2052
2053         if (!rc) {
2054                 /* Mark BH routine as complete */
2055                 info->bh_running   = 0;
2056                 info->bh_requested = 0;
2057         }
2058
2059         spin_unlock_irqrestore(&info->lock,flags);
2060
2061         return rc;
2062 }
2063
2064 /* Perform bottom half processing of work items queued by ISR.
2065  */
2066 void bh_handler(void* Context)
2067 {
2068         SLMP_INFO *info = (SLMP_INFO*)Context;
2069         int action;
2070
2071         if (!info)
2072                 return;
2073
2074         if ( debug_level >= DEBUG_LEVEL_BH )
2075                 printk( "%s(%d):%s bh_handler() entry\n",
2076                         __FILE__,__LINE__,info->device_name);
2077
2078         info->bh_running = 1;
2079
2080         while((action = bh_action(info)) != 0) {
2081
2082                 /* Process work item */
2083                 if ( debug_level >= DEBUG_LEVEL_BH )
2084                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2085                                 __FILE__,__LINE__,info->device_name, action);
2086
2087                 switch (action) {
2088
2089                 case BH_RECEIVE:
2090                         bh_receive(info);
2091                         break;
2092                 case BH_TRANSMIT:
2093                         bh_transmit(info);
2094                         break;
2095                 case BH_STATUS:
2096                         bh_status(info);
2097                         break;
2098                 default:
2099                         /* unknown work item ID */
2100                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2101                                 __FILE__,__LINE__,info->device_name,action);
2102                         break;
2103                 }
2104         }
2105
2106         if ( debug_level >= DEBUG_LEVEL_BH )
2107                 printk( "%s(%d):%s bh_handler() exit\n",
2108                         __FILE__,__LINE__,info->device_name);
2109 }
2110
2111 void bh_receive(SLMP_INFO *info)
2112 {
2113         if ( debug_level >= DEBUG_LEVEL_BH )
2114                 printk( "%s(%d):%s bh_receive()\n",
2115                         __FILE__,__LINE__,info->device_name);
2116
2117         while( rx_get_frame(info) );
2118 }
2119
2120 void bh_transmit(SLMP_INFO *info)
2121 {
2122         struct tty_struct *tty = info->tty;
2123
2124         if ( debug_level >= DEBUG_LEVEL_BH )
2125                 printk( "%s(%d):%s bh_transmit() entry\n",
2126                         __FILE__,__LINE__,info->device_name);
2127
2128         if (tty) {
2129                 tty_wakeup(tty);
2130                 wake_up_interruptible(&tty->write_wait);
2131         }
2132 }
2133
2134 void bh_status(SLMP_INFO *info)
2135 {
2136         if ( debug_level >= DEBUG_LEVEL_BH )
2137                 printk( "%s(%d):%s bh_status() entry\n",
2138                         __FILE__,__LINE__,info->device_name);
2139
2140         info->ri_chkcount = 0;
2141         info->dsr_chkcount = 0;
2142         info->dcd_chkcount = 0;
2143         info->cts_chkcount = 0;
2144 }
2145
2146 void isr_timer(SLMP_INFO * info)
2147 {
2148         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2149
2150         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2151         write_reg(info, IER2, 0);
2152
2153         /* TMCS, Timer Control/Status Register
2154          *
2155          * 07      CMF, Compare match flag (read only) 1=match
2156          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2157          * 05      Reserved, must be 0
2158          * 04      TME, Timer Enable
2159          * 03..00  Reserved, must be 0
2160          *
2161          * 0000 0000
2162          */
2163         write_reg(info, (unsigned char)(timer + TMCS), 0);
2164
2165         info->irq_occurred = TRUE;
2166
2167         if ( debug_level >= DEBUG_LEVEL_ISR )
2168                 printk("%s(%d):%s isr_timer()\n",
2169                         __FILE__,__LINE__,info->device_name);
2170 }
2171
2172 void isr_rxint(SLMP_INFO * info)
2173 {
2174         struct tty_struct *tty = info->tty;
2175         struct  mgsl_icount *icount = &info->icount;
2176         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2177         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2178
2179         /* clear status bits */
2180         if (status)
2181                 write_reg(info, SR1, status);
2182
2183         if (status2)
2184                 write_reg(info, SR2, status2);
2185
2186         if ( debug_level >= DEBUG_LEVEL_ISR )
2187                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2188                         __FILE__,__LINE__,info->device_name,status,status2);
2189
2190         if (info->params.mode == MGSL_MODE_ASYNC) {
2191                 if (status & BRKD) {
2192                         icount->brk++;
2193
2194                         /* process break detection if tty control
2195                          * is not set to ignore it
2196                          */
2197                         if ( tty ) {
2198                                 if (!(status & info->ignore_status_mask1)) {
2199                                         if (info->read_status_mask1 & BRKD) {
2200                                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
2201                                                 if (info->flags & ASYNC_SAK)
2202                                                         do_SAK(tty);
2203                                         }
2204                                 }
2205                         }
2206                 }
2207         }
2208         else {
2209                 if (status & (FLGD|IDLD)) {
2210                         if (status & FLGD)
2211                                 info->icount.exithunt++;
2212                         else if (status & IDLD)
2213                                 info->icount.rxidle++;
2214                         wake_up_interruptible(&info->event_wait_q);
2215                 }
2216         }
2217
2218         if (status & CDCD) {
2219                 /* simulate a common modem status change interrupt
2220                  * for our handler
2221                  */
2222                 get_signals( info );
2223                 isr_io_pin(info,
2224                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2225         }
2226 }
2227
2228 /*
2229  * handle async rx data interrupts
2230  */
2231 void isr_rxrdy(SLMP_INFO * info)
2232 {
2233         u16 status;
2234         unsigned char DataByte;
2235         struct tty_struct *tty = info->tty;
2236         struct  mgsl_icount *icount = &info->icount;
2237
2238         if ( debug_level >= DEBUG_LEVEL_ISR )
2239                 printk("%s(%d):%s isr_rxrdy\n",
2240                         __FILE__,__LINE__,info->device_name);
2241
2242         while((status = read_reg(info,CST0)) & BIT0)
2243         {
2244                 DataByte = read_reg(info,TRB);
2245
2246                 if ( tty ) {
2247                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2248                                 continue;
2249
2250                         *tty->flip.char_buf_ptr = DataByte;
2251                         *tty->flip.flag_buf_ptr = 0;
2252                 }
2253
2254                 icount->rx++;
2255
2256                 if ( status & (PE + FRME + OVRN) ) {
2257                         printk("%s(%d):%s rxerr=%04X\n",
2258                                 __FILE__,__LINE__,info->device_name,status);
2259
2260                         /* update error statistics */
2261                         if (status & PE)
2262                                 icount->parity++;
2263                         else if (status & FRME)
2264                                 icount->frame++;
2265                         else if (status & OVRN)
2266                                 icount->overrun++;
2267
2268                         /* discard char if tty control flags say so */
2269                         if (status & info->ignore_status_mask2)
2270                                 continue;
2271
2272                         status &= info->read_status_mask2;
2273
2274                         if ( tty ) {
2275                                 if (status & PE)
2276                                         *tty->flip.flag_buf_ptr = TTY_PARITY;
2277                                 else if (status & FRME)
2278                                         *tty->flip.flag_buf_ptr = TTY_FRAME;
2279                                 if (status & OVRN) {
2280                                         /* Overrun is special, since it's
2281                                          * reported immediately, and doesn't
2282                                          * affect the current character
2283                                          */
2284                                         if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2285                                                 tty->flip.count++;
2286                                                 tty->flip.flag_buf_ptr++;
2287                                                 tty->flip.char_buf_ptr++;
2288                                                 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2289                                         }
2290                                 }
2291                         }
2292                 }       /* end of if (error) */
2293
2294                 if ( tty ) {
2295                         tty->flip.flag_buf_ptr++;
2296                         tty->flip.char_buf_ptr++;
2297                         tty->flip.count++;
2298                 }
2299         }
2300
2301         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2302                 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2303                         __FILE__,__LINE__,info->device_name,
2304                         tty ? tty->flip.count : 0);
2305                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2306                         __FILE__,__LINE__,info->device_name,
2307                         icount->rx,icount->brk,icount->parity,
2308                         icount->frame,icount->overrun);
2309         }
2310
2311         if ( tty && tty->flip.count )
2312                 tty_flip_buffer_push(tty);
2313 }
2314
2315 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2316 {
2317         if ( debug_level >= DEBUG_LEVEL_ISR )
2318                 printk("%s(%d):%s isr_txeom status=%02x\n",
2319                         __FILE__,__LINE__,info->device_name,status);
2320
2321         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2322         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2323         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2324
2325         if (status & UDRN) {
2326                 write_reg(info, CMD, TXRESET);
2327                 write_reg(info, CMD, TXENABLE);
2328         } else
2329                 write_reg(info, CMD, TXBUFCLR);
2330
2331         /* disable and clear tx interrupts */
2332         info->ie0_value &= ~TXRDYE;
2333         info->ie1_value &= ~(IDLE + UDRN);
2334         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2335         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2336
2337         if ( info->tx_active ) {
2338                 if (info->params.mode != MGSL_MODE_ASYNC) {
2339                         if (status & UDRN)
2340                                 info->icount.txunder++;
2341                         else if (status & IDLE)
2342                                 info->icount.txok++;
2343                 }
2344
2345                 info->tx_active = 0;
2346                 info->tx_count = info->tx_put = info->tx_get = 0;
2347
2348                 del_timer(&info->tx_timer);
2349
2350                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2351                         info->serial_signals &= ~SerialSignal_RTS;
2352                         info->drop_rts_on_tx_done = 0;
2353                         set_signals(info);
2354                 }
2355
2356 #ifdef CONFIG_HDLC
2357                 if (info->netcount)
2358                         hdlcdev_tx_done(info);
2359                 else
2360 #endif
2361                 {
2362                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2363                                 tx_stop(info);
2364                                 return;
2365                         }
2366                         info->pending_bh |= BH_TRANSMIT;
2367                 }
2368         }
2369 }
2370
2371
2372 /*
2373  * handle tx status interrupts
2374  */
2375 void isr_txint(SLMP_INFO * info)
2376 {
2377         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2378
2379         /* clear status bits */
2380         write_reg(info, SR1, status);
2381
2382         if ( debug_level >= DEBUG_LEVEL_ISR )
2383                 printk("%s(%d):%s isr_txint status=%02x\n",
2384                         __FILE__,__LINE__,info->device_name,status);
2385
2386         if (status & (UDRN + IDLE))
2387                 isr_txeom(info, status);
2388
2389         if (status & CCTS) {
2390                 /* simulate a common modem status change interrupt
2391                  * for our handler
2392                  */
2393                 get_signals( info );
2394                 isr_io_pin(info,
2395                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2396
2397         }
2398 }
2399
2400 /*
2401  * handle async tx data interrupts
2402  */
2403 void isr_txrdy(SLMP_INFO * info)
2404 {
2405         if ( debug_level >= DEBUG_LEVEL_ISR )
2406                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2407                         __FILE__,__LINE__,info->device_name,info->tx_count);
2408
2409         if (info->params.mode != MGSL_MODE_ASYNC) {
2410                 /* disable TXRDY IRQ, enable IDLE IRQ */
2411                 info->ie0_value &= ~TXRDYE;
2412                 info->ie1_value |= IDLE;
2413                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2414                 return;
2415         }
2416
2417         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2418                 tx_stop(info);
2419                 return;
2420         }
2421
2422         if ( info->tx_count )
2423                 tx_load_fifo( info );
2424         else {
2425                 info->tx_active = 0;
2426                 info->ie0_value &= ~TXRDYE;
2427                 write_reg(info, IE0, info->ie0_value);
2428         }
2429
2430         if (info->tx_count < WAKEUP_CHARS)
2431                 info->pending_bh |= BH_TRANSMIT;
2432 }
2433
2434 void isr_rxdmaok(SLMP_INFO * info)
2435 {
2436         /* BIT7 = EOT (end of transfer)
2437          * BIT6 = EOM (end of message/frame)
2438          */
2439         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2440
2441         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2442         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2443
2444         if ( debug_level >= DEBUG_LEVEL_ISR )
2445                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2446                         __FILE__,__LINE__,info->device_name,status);
2447
2448         info->pending_bh |= BH_RECEIVE;
2449 }
2450
2451 void isr_rxdmaerror(SLMP_INFO * info)
2452 {
2453         /* BIT5 = BOF (buffer overflow)
2454          * BIT4 = COF (counter overflow)
2455          */
2456         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2457
2458         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2459         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2460
2461         if ( debug_level >= DEBUG_LEVEL_ISR )
2462                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2463                         __FILE__,__LINE__,info->device_name,status);
2464
2465         info->rx_overflow = TRUE;
2466         info->pending_bh |= BH_RECEIVE;
2467 }
2468
2469 void isr_txdmaok(SLMP_INFO * info)
2470 {
2471         unsigned char status_reg1 = read_reg(info, SR1);
2472
2473         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2474         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2475         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2476
2477         if ( debug_level >= DEBUG_LEVEL_ISR )
2478                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2479                         __FILE__,__LINE__,info->device_name,status_reg1);
2480
2481         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2482         write_reg16(info, TRC0, 0);
2483         info->ie0_value |= TXRDYE;
2484         write_reg(info, IE0, info->ie0_value);
2485 }
2486
2487 void isr_txdmaerror(SLMP_INFO * info)
2488 {
2489         /* BIT5 = BOF (buffer overflow)
2490          * BIT4 = COF (counter overflow)
2491          */
2492         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2493
2494         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2495         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2496
2497         if ( debug_level >= DEBUG_LEVEL_ISR )
2498                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2499                         __FILE__,__LINE__,info->device_name,status);
2500 }
2501
2502 /* handle input serial signal changes
2503  */
2504 void isr_io_pin( SLMP_INFO *info, u16 status )
2505 {
2506         struct  mgsl_icount *icount;
2507
2508         if ( debug_level >= DEBUG_LEVEL_ISR )
2509                 printk("%s(%d):isr_io_pin status=%04X\n",
2510                         __FILE__,__LINE__,status);
2511
2512         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2513                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2514                 icount = &info->icount;
2515                 /* update input line counters */
2516                 if (status & MISCSTATUS_RI_LATCHED) {
2517                         icount->rng++;
2518                         if ( status & SerialSignal_RI )
2519                                 info->input_signal_events.ri_up++;
2520                         else
2521                                 info->input_signal_events.ri_down++;
2522                 }
2523                 if (status & MISCSTATUS_DSR_LATCHED) {
2524                         icount->dsr++;
2525                         if ( status & SerialSignal_DSR )
2526                                 info->input_signal_events.dsr_up++;
2527                         else
2528                                 info->input_signal_events.dsr_down++;
2529                 }
2530                 if (status & MISCSTATUS_DCD_LATCHED) {
2531                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2532                                 info->ie1_value &= ~CDCD;
2533                                 write_reg(info, IE1, info->ie1_value);
2534                         }
2535                         icount->dcd++;
2536                         if (status & SerialSignal_DCD) {
2537                                 info->input_signal_events.dcd_up++;
2538                         } else
2539                                 info->input_signal_events.dcd_down++;
2540 #ifdef CONFIG_HDLC
2541                         if (info->netcount)
2542                                 hdlc_set_carrier(status & SerialSignal_DCD, info->netdev);
2543 #endif
2544                 }
2545                 if (status & MISCSTATUS_CTS_LATCHED)
2546                 {
2547                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2548                                 info->ie1_value &= ~CCTS;
2549                                 write_reg(info, IE1, info->ie1_value);
2550                         }
2551                         icount->cts++;
2552                         if ( status & SerialSignal_CTS )
2553                                 info->input_signal_events.cts_up++;
2554                         else
2555                                 info->input_signal_events.cts_down++;
2556                 }
2557                 wake_up_interruptible(&info->status_event_wait_q);
2558                 wake_up_interruptible(&info->event_wait_q);
2559
2560                 if ( (info->flags & ASYNC_CHECK_CD) &&
2561                      (status & MISCSTATUS_DCD_LATCHED) ) {
2562                         if ( debug_level >= DEBUG_LEVEL_ISR )
2563                                 printk("%s CD now %s...", info->device_name,
2564                                        (status & SerialSignal_DCD) ? "on" : "off");
2565                         if (status & SerialSignal_DCD)
2566                                 wake_up_interruptible(&info->open_wait);
2567                         else {
2568                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2569                                         printk("doing serial hangup...");
2570                                 if (info->tty)
2571                                         tty_hangup(info->tty);
2572                         }
2573                 }
2574
2575                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2576                      (status & MISCSTATUS_CTS_LATCHED) ) {
2577                         if ( info->tty ) {
2578                                 if (info->tty->hw_stopped) {
2579                                         if (status & SerialSignal_CTS) {
2580                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2581                                                         printk("CTS tx start...");
2582                                                 info->tty->hw_stopped = 0;
2583                                                 tx_start(info);
2584                                                 info->pending_bh |= BH_TRANSMIT;
2585                                                 return;
2586                                         }
2587                                 } else {
2588                                         if (!(status & SerialSignal_CTS)) {
2589                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2590                                                         printk("CTS tx stop...");
2591                                                 info->tty->hw_stopped = 1;
2592                                                 tx_stop(info);
2593                                         }
2594                                 }
2595                         }
2596                 }
2597         }
2598
2599         info->pending_bh |= BH_STATUS;
2600 }
2601
2602 /* Interrupt service routine entry point.
2603  *
2604  * Arguments:
2605  *      irq             interrupt number that caused interrupt
2606  *      dev_id          device ID supplied during interrupt registration
2607  *      regs            interrupted processor context
2608  */
2609 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2610                                         struct pt_regs *regs)
2611 {
2612         SLMP_INFO * info;
2613         unsigned char status, status0, status1=0;
2614         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2615         unsigned char timerstatus0, timerstatus1=0;
2616         unsigned char shift;
2617         unsigned int i;
2618         unsigned short tmp;
2619
2620         if ( debug_level >= DEBUG_LEVEL_ISR )
2621                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2622                         __FILE__,__LINE__,irq);
2623
2624         info = (SLMP_INFO *)dev_id;
2625         if (!info)
2626                 return IRQ_NONE;
2627
2628         spin_lock(&info->lock);
2629
2630         for(;;) {
2631
2632                 /* get status for SCA0 (ports 0-1) */
2633                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2634                 status0 = (unsigned char)tmp;
2635                 dmastatus0 = (unsigned char)(tmp>>8);
2636                 timerstatus0 = read_reg(info, ISR2);
2637
2638                 if ( debug_level >= DEBUG_LEVEL_ISR )
2639                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2640                                 __FILE__,__LINE__,info->device_name,
2641                                 status0,dmastatus0,timerstatus0);
2642
2643                 if (info->port_count == 4) {
2644                         /* get status for SCA1 (ports 2-3) */
2645                         tmp = read_reg16(info->port_array[2], ISR0);
2646                         status1 = (unsigned char)tmp;
2647                         dmastatus1 = (unsigned char)(tmp>>8);
2648                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2649
2650                         if ( debug_level >= DEBUG_LEVEL_ISR )
2651                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2652                                         __FILE__,__LINE__,info->device_name,
2653                                         status1,dmastatus1,timerstatus1);
2654                 }
2655
2656                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2657                          !status1 && !dmastatus1 && !timerstatus1)
2658                         break;
2659
2660                 for(i=0; i < info->port_count ; i++) {
2661                         if (info->port_array[i] == NULL)
2662                                 continue;
2663                         if (i < 2) {
2664                                 status = status0;
2665                                 dmastatus = dmastatus0;
2666                         } else {
2667                                 status = status1;
2668                                 dmastatus = dmastatus1;
2669                         }
2670
2671                         shift = i & 1 ? 4 :0;
2672
2673                         if (status & BIT0 << shift)
2674                                 isr_rxrdy(info->port_array[i]);
2675                         if (status & BIT1 << shift)
2676                                 isr_txrdy(info->port_array[i]);
2677                         if (status & BIT2 << shift)
2678                                 isr_rxint(info->port_array[i]);
2679                         if (status & BIT3 << shift)
2680                                 isr_txint(info->port_array[i]);
2681
2682                         if (dmastatus & BIT0 << shift)
2683                                 isr_rxdmaerror(info->port_array[i]);
2684                         if (dmastatus & BIT1 << shift)
2685                                 isr_rxdmaok(info->port_array[i]);
2686                         if (dmastatus & BIT2 << shift)
2687                                 isr_txdmaerror(info->port_array[i]);
2688                         if (dmastatus & BIT3 << shift)
2689                                 isr_txdmaok(info->port_array[i]);
2690                 }
2691
2692                 if (timerstatus0 & (BIT5 | BIT4))
2693                         isr_timer(info->port_array[0]);
2694                 if (timerstatus0 & (BIT7 | BIT6))
2695                         isr_timer(info->port_array[1]);
2696                 if (timerstatus1 & (BIT5 | BIT4))
2697                         isr_timer(info->port_array[2]);
2698                 if (timerstatus1 & (BIT7 | BIT6))
2699                         isr_timer(info->port_array[3]);
2700         }
2701
2702         for(i=0; i < info->port_count ; i++) {
2703                 SLMP_INFO * port = info->port_array[i];
2704
2705                 /* Request bottom half processing if there's something
2706                  * for it to do and the bh is not already running.
2707                  *
2708                  * Note: startup adapter diags require interrupts.
2709                  * do not request bottom half processing if the
2710                  * device is not open in a normal mode.
2711                  */
2712                 if ( port && (port->count || port->netcount) &&
2713                      port->pending_bh && !port->bh_running &&
2714                      !port->bh_requested ) {
2715                         if ( debug_level >= DEBUG_LEVEL_ISR )
2716                                 printk("%s(%d):%s queueing bh task.\n",
2717                                         __FILE__,__LINE__,port->device_name);
2718                         schedule_work(&port->task);
2719                         port->bh_requested = 1;
2720                 }
2721         }
2722
2723         spin_unlock(&info->lock);
2724
2725         if ( debug_level >= DEBUG_LEVEL_ISR )
2726                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2727                         __FILE__,__LINE__,irq);
2728         return IRQ_HANDLED;
2729 }
2730
2731 /* Initialize and start device.
2732  */
2733 static int startup(SLMP_INFO * info)
2734 {
2735         if ( debug_level >= DEBUG_LEVEL_INFO )
2736                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2737
2738         if (info->flags & ASYNC_INITIALIZED)
2739                 return 0;
2740
2741         if (!info->tx_buf) {
2742                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2743                 if (!info->tx_buf) {
2744                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2745                                 __FILE__,__LINE__,info->device_name);
2746                         return -ENOMEM;
2747                 }
2748         }
2749
2750         info->pending_bh = 0;
2751
2752         /* program hardware for current parameters */
2753         reset_port(info);
2754
2755         change_params(info);
2756
2757         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2758         add_timer(&info->status_timer);
2759
2760         if (info->tty)
2761                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2762
2763         info->flags |= ASYNC_INITIALIZED;
2764
2765         return 0;
2766 }
2767
2768 /* Called by close() and hangup() to shutdown hardware
2769  */
2770 static void shutdown(SLMP_INFO * info)
2771 {
2772         unsigned long flags;
2773
2774         if (!(info->flags & ASYNC_INITIALIZED))
2775                 return;
2776
2777         if (debug_level >= DEBUG_LEVEL_INFO)
2778                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2779                          __FILE__,__LINE__, info->device_name );
2780
2781         /* clear status wait queue because status changes */
2782         /* can't happen after shutting down the hardware */
2783         wake_up_interruptible(&info->status_event_wait_q);
2784         wake_up_interruptible(&info->event_wait_q);
2785
2786         del_timer(&info->tx_timer);
2787         del_timer(&info->status_timer);
2788
2789         if (info->tx_buf) {
2790                 kfree(info->tx_buf);
2791                 info->tx_buf = NULL;
2792         }
2793
2794         spin_lock_irqsave(&info->lock,flags);
2795
2796         reset_port(info);
2797
2798         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2799                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2800                 set_signals(info);
2801         }
2802
2803         spin_unlock_irqrestore(&info->lock,flags);
2804
2805         if (info->tty)
2806                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2807
2808         info->flags &= ~ASYNC_INITIALIZED;
2809 }
2810
2811 static void program_hw(SLMP_INFO *info)
2812 {
2813         unsigned long flags;
2814
2815         spin_lock_irqsave(&info->lock,flags);
2816
2817         rx_stop(info);
2818         tx_stop(info);
2819
2820         info->tx_count = info->tx_put = info->tx_get = 0;
2821
2822         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2823                 hdlc_mode(info);
2824         else
2825                 async_mode(info);
2826
2827         set_signals(info);
2828
2829         info->dcd_chkcount = 0;
2830         info->cts_chkcount = 0;
2831         info->ri_chkcount = 0;
2832         info->dsr_chkcount = 0;
2833
2834         info->ie1_value |= (CDCD|CCTS);
2835         write_reg(info, IE1, info->ie1_value);
2836
2837         get_signals(info);
2838
2839         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2840                 rx_start(info);
2841
2842         spin_unlock_irqrestore(&info->lock,flags);
2843 }
2844
2845 /* Reconfigure adapter based on new parameters
2846  */
2847 static void change_params(SLMP_INFO *info)
2848 {
2849         unsigned cflag;
2850         int bits_per_char;
2851
2852         if (!info->tty || !info->tty->termios)
2853                 return;
2854
2855         if (debug_level >= DEBUG_LEVEL_INFO)
2856                 printk("%s(%d):%s change_params()\n",
2857                          __FILE__,__LINE__, info->device_name );
2858
2859         cflag = info->tty->termios->c_cflag;
2860
2861         /* if B0 rate (hangup) specified then negate DTR and RTS */
2862         /* otherwise assert DTR and RTS */
2863         if (cflag & CBAUD)
2864                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2865         else
2866                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2867
2868         /* byte size and parity */
2869
2870         switch (cflag & CSIZE) {
2871               case CS5: info->params.data_bits = 5; break;
2872               case CS6: info->params.data_bits = 6; break;
2873               case CS7: info->params.data_bits = 7; break;
2874               case CS8: info->params.data_bits = 8; break;
2875               /* Never happens, but GCC is too dumb to figure it out */
2876               default:  info->params.data_bits = 7; break;
2877               }
2878
2879         if (cflag & CSTOPB)
2880                 info->params.stop_bits = 2;
2881         else
2882                 info->params.stop_bits = 1;
2883
2884         info->params.parity = ASYNC_PARITY_NONE;
2885         if (cflag & PARENB) {
2886                 if (cflag & PARODD)
2887                         info->params.parity = ASYNC_PARITY_ODD;
2888                 else
2889                         info->params.parity = ASYNC_PARITY_EVEN;
2890 #ifdef CMSPAR
2891                 if (cflag & CMSPAR)
2892                         info->params.parity = ASYNC_PARITY_SPACE;
2893 #endif
2894         }
2895
2896         /* calculate number of jiffies to transmit a full
2897          * FIFO (32 bytes) at specified data rate
2898          */
2899         bits_per_char = info->params.data_bits +
2900                         info->params.stop_bits + 1;
2901
2902         /* if port data rate is set to 460800 or less then
2903          * allow tty settings to override, otherwise keep the
2904          * current data rate.
2905          */
2906         if (info->params.data_rate <= 460800) {
2907                 info->params.data_rate = tty_get_baud_rate(info->tty);
2908         }
2909
2910         if ( info->params.data_rate ) {
2911                 info->timeout = (32*HZ*bits_per_char) /
2912                                 info->params.data_rate;
2913         }
2914         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2915
2916         if (cflag & CRTSCTS)
2917                 info->flags |= ASYNC_CTS_FLOW;
2918         else
2919                 info->flags &= ~ASYNC_CTS_FLOW;
2920
2921         if (cflag & CLOCAL)
2922                 info->flags &= ~ASYNC_CHECK_CD;
2923         else
2924                 info->flags |= ASYNC_CHECK_CD;
2925
2926         /* process tty input control flags */
2927
2928         info->read_status_mask2 = OVRN;
2929         if (I_INPCK(info->tty))
2930                 info->read_status_mask2 |= PE | FRME;
2931         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2932                 info->read_status_mask1 |= BRKD;
2933         if (I_IGNPAR(info->tty))
2934                 info->ignore_status_mask2 |= PE | FRME;
2935         if (I_IGNBRK(info->tty)) {
2936                 info->ignore_status_mask1 |= BRKD;
2937                 /* If ignoring parity and break indicators, ignore
2938                  * overruns too.  (For real raw support).
2939                  */
2940                 if (I_IGNPAR(info->tty))
2941                         info->ignore_status_mask2 |= OVRN;
2942         }
2943
2944         program_hw(info);
2945 }
2946
2947 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2948 {
2949         int err;
2950
2951         if (debug_level >= DEBUG_LEVEL_INFO)
2952                 printk("%s(%d):%s get_params()\n",
2953                          __FILE__,__LINE__, info->device_name);
2954
2955         COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2956         if (err) {
2957                 if ( debug_level >= DEBUG_LEVEL_INFO )
2958                         printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2959                                 __FILE__,__LINE__,info->device_name);
2960                 return -EFAULT;
2961         }
2962
2963         return 0;
2964 }
2965
2966 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2967 {
2968         int err;
2969         if (debug_level >= DEBUG_LEVEL_INFO)
2970                 printk("%s(%d):%s get_params()\n",
2971                          __FILE__,__LINE__, info->device_name);
2972
2973         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2974         if (err) {
2975                 if ( debug_level >= DEBUG_LEVEL_INFO )
2976                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2977                                 __FILE__,__LINE__,info->device_name);
2978                 return -EFAULT;
2979         }
2980
2981         return 0;
2982 }
2983
2984 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2985 {
2986         unsigned long flags;
2987         MGSL_PARAMS tmp_params;
2988         int err;
2989
2990         if (debug_level >= DEBUG_LEVEL_INFO)
2991                 printk("%s(%d):%s set_params\n",
2992                         __FILE__,__LINE__,info->device_name );
2993         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2994         if (err) {
2995                 if ( debug_level >= DEBUG_LEVEL_INFO )
2996                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2997                                 __FILE__,__LINE__,info->device_name);
2998                 return -EFAULT;
2999         }
3000
3001         spin_lock_irqsave(&info->lock,flags);
3002         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
3003         spin_unlock_irqrestore(&info->lock,flags);
3004
3005         change_params(info);
3006
3007         return 0;
3008 }
3009
3010 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3011 {
3012         int err;
3013
3014         if (debug_level >= DEBUG_LEVEL_INFO)
3015                 printk("%s(%d):%s get_txidle()=%d\n",
3016                          __FILE__,__LINE__, info->device_name, info->idle_mode);
3017
3018         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3019         if (err) {
3020                 if ( debug_level >= DEBUG_LEVEL_INFO )
3021                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3022                                 __FILE__,__LINE__,info->device_name);
3023                 return -EFAULT;
3024         }
3025
3026         return 0;
3027 }
3028
3029 static int set_txidle(SLMP_INFO * info, int idle_mode)
3030 {
3031         unsigned long flags;
3032
3033         if (debug_level >= DEBUG_LEVEL_INFO)
3034                 printk("%s(%d):%s set_txidle(%d)\n",
3035                         __FILE__,__LINE__,info->device_name, idle_mode );
3036
3037         spin_lock_irqsave(&info->lock,flags);
3038         info->idle_mode = idle_mode;
3039         tx_set_idle( info );
3040         spin_unlock_irqrestore(&info->lock,flags);
3041         return 0;
3042 }
3043
3044 static int tx_enable(SLMP_INFO * info, int enable)
3045 {
3046         unsigned long flags;
3047
3048         if (debug_level >= DEBUG_LEVEL_INFO)
3049                 printk("%s(%d):%s tx_enable(%d)\n",
3050                         __FILE__,__LINE__,info->device_name, enable);
3051
3052         spin_lock_irqsave(&info->lock,flags);
3053         if ( enable ) {
3054                 if ( !info->tx_enabled ) {
3055                         tx_start(info);
3056                 }
3057         } else {
3058                 if ( info->tx_enabled )
3059                         tx_stop(info);
3060         }
3061         spin_unlock_irqrestore(&info->lock,flags);
3062         return 0;
3063 }
3064
3065 /* abort send HDLC frame
3066  */
3067 static int tx_abort(SLMP_INFO * info)
3068 {
3069         unsigned long flags;
3070
3071         if (debug_level >= DEBUG_LEVEL_INFO)
3072                 printk("%s(%d):%s tx_abort()\n",
3073                         __FILE__,__LINE__,info->device_name);
3074
3075         spin_lock_irqsave(&info->lock,flags);
3076         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3077                 info->ie1_value &= ~UDRN;
3078                 info->ie1_value |= IDLE;
3079                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3080                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3081
3082                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3083                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3084
3085                 write_reg(info, CMD, TXABORT);
3086         }
3087         spin_unlock_irqrestore(&info->lock,flags);
3088         return 0;
3089 }
3090
3091 static int rx_enable(SLMP_INFO * info, int enable)
3092 {
3093         unsigned long flags;
3094
3095         if (debug_level >= DEBUG_LEVEL_INFO)
3096                 printk("%s(%d):%s rx_enable(%d)\n",
3097                         __FILE__,__LINE__,info->device_name,enable);
3098
3099         spin_lock_irqsave(&info->lock,flags);
3100         if ( enable ) {
3101                 if ( !info->rx_enabled )
3102                         rx_start(info);
3103         } else {
3104                 if ( info->rx_enabled )
3105                         rx_stop(info);
3106         }
3107         spin_unlock_irqrestore(&info->lock,flags);
3108         return 0;
3109 }
3110
3111 static int map_status(int signals)
3112 {
3113         /* Map status bits to API event bits */
3114
3115         return ((signals & SerialSignal_DSR) ? MgslEvent_DsrActive : MgslEvent_DsrInactive) +
3116                ((signals & SerialSignal_CTS) ? MgslEvent_CtsActive : MgslEvent_CtsInactive) +
3117                ((signals & SerialSignal_DCD) ? MgslEvent_DcdActive : MgslEvent_DcdInactive) +
3118                ((signals & SerialSignal_RI)  ? MgslEvent_RiActive : MgslEvent_RiInactive);
3119 }
3120
3121 /* wait for specified event to occur
3122  */
3123 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3124 {
3125         unsigned long flags;
3126         int s;
3127         int rc=0;
3128         struct mgsl_icount cprev, cnow;
3129         int events;
3130         int mask;
3131         struct  _input_signal_events oldsigs, newsigs;
3132         DECLARE_WAITQUEUE(wait, current);
3133
3134         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3135         if (rc) {
3136                 return  -EFAULT;
3137         }
3138
3139         if (debug_level >= DEBUG_LEVEL_INFO)
3140                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3141                         __FILE__,__LINE__,info->device_name,mask);
3142
3143         spin_lock_irqsave(&info->lock,flags);
3144
3145         /* return immediately if state matches requested events */
3146         get_signals(info);
3147         s = map_status(info->serial_signals);
3148
3149         events = mask &
3150                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3151                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3152                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3153                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3154         if (events) {
3155                 spin_unlock_irqrestore(&info->lock,flags);
3156                 goto exit;
3157         }
3158
3159         /* save current irq counts */
3160         cprev = info->icount;
3161         oldsigs = info->input_signal_events;
3162
3163         /* enable hunt and idle irqs if needed */
3164         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3165                 unsigned char oldval = info->ie1_value;
3166                 unsigned char newval = oldval +
3167                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3168                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3169                 if ( oldval != newval ) {
3170                         info->ie1_value = newval;
3171                         write_reg(info, IE1, info->ie1_value);
3172                 }
3173         }
3174
3175         set_current_state(TASK_INTERRUPTIBLE);
3176         add_wait_queue(&info->event_wait_q, &wait);
3177
3178         spin_unlock_irqrestore(&info->lock,flags);
3179
3180         for(;;) {
3181                 schedule();
3182                 if (signal_pending(current)) {
3183                         rc = -ERESTARTSYS;
3184                         break;
3185                 }
3186
3187                 /* get current irq counts */
3188                 spin_lock_irqsave(&info->lock,flags);
3189                 cnow = info->icount;
3190                 newsigs = info->input_signal_events;
3191                 set_current_state(TASK_INTERRUPTIBLE);
3192                 spin_unlock_irqrestore(&info->lock,flags);
3193
3194                 /* if no change, wait aborted for some reason */
3195                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3196                     newsigs.dsr_down == oldsigs.dsr_down &&
3197                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3198                     newsigs.dcd_down == oldsigs.dcd_down &&
3199                     newsigs.cts_up   == oldsigs.cts_up   &&
3200                     newsigs.cts_down == oldsigs.cts_down &&
3201                     newsigs.ri_up    == oldsigs.ri_up    &&
3202                     newsigs.ri_down  == oldsigs.ri_down  &&
3203                     cnow.exithunt    == cprev.exithunt   &&
3204                     cnow.rxidle      == cprev.rxidle) {
3205                         rc = -EIO;
3206                         break;
3207                 }
3208
3209                 events = mask &
3210                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3211                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3212                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3213                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3214                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3215                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3216                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3217                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3218                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3219                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3220                 if (events)
3221                         break;
3222
3223                 cprev = cnow;
3224                 oldsigs = newsigs;
3225         }
3226
3227         remove_wait_queue(&info->event_wait_q, &wait);
3228         set_current_state(TASK_RUNNING);
3229
3230
3231         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3232                 spin_lock_irqsave(&info->lock,flags);
3233                 if (!waitqueue_active(&info->event_wait_q)) {
3234                         /* disable enable exit hunt mode/idle rcvd IRQs */
3235                         info->ie1_value &= ~(FLGD|IDLD);
3236                         write_reg(info, IE1, info->ie1_value);
3237                 }
3238                 spin_unlock_irqrestore(&info->lock,flags);
3239         }
3240 exit:
3241         if ( rc == 0 )
3242                 PUT_USER(rc, events, mask_ptr);
3243
3244         return rc;
3245 }
3246
3247 static int modem_input_wait(SLMP_INFO *info,int arg)
3248 {
3249         unsigned long flags;
3250         int rc;
3251         struct mgsl_icount cprev, cnow;
3252         DECLARE_WAITQUEUE(wait, current);
3253
3254         /* save current irq counts */
3255         spin_lock_irqsave(&info->lock,flags);
3256         cprev = info->icount;
3257         add_wait_queue(&info->status_event_wait_q, &wait);
3258         set_current_state(TASK_INTERRUPTIBLE);
3259         spin_unlock_irqrestore(&info->lock,flags);
3260
3261         for(;;) {
3262                 schedule();
3263                 if (signal_pending(current)) {
3264                         rc = -ERESTARTSYS;
3265                         break;
3266                 }
3267
3268                 /* get new irq counts */
3269                 spin_lock_irqsave(&info->lock,flags);
3270                 cnow = info->icount;
3271                 set_current_state(TASK_INTERRUPTIBLE);
3272                 spin_unlock_irqrestore(&info->lock,flags);
3273
3274                 /* if no change, wait aborted for some reason */
3275                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3276                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3277                         rc = -EIO;
3278                         break;
3279                 }
3280
3281                 /* check for change in caller specified modem input */
3282                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3283                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3284                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3285                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3286                         rc = 0;
3287                         break;
3288                 }
3289
3290                 cprev = cnow;
3291         }
3292         remove_wait_queue(&info->status_event_wait_q, &wait);
3293         set_current_state(TASK_RUNNING);
3294         return rc;
3295 }
3296
3297 /* return the state of the serial control and status signals
3298  */
3299 static int tiocmget(struct tty_struct *tty, struct file *file)
3300 {
3301         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3302         unsigned int result;
3303         unsigned long flags;
3304
3305         spin_lock_irqsave(&info->lock,flags);
3306         get_signals(info);
3307         spin_unlock_irqrestore(&info->lock,flags);
3308
3309         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3310                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3311                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3312                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3313                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3314                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3315
3316         if (debug_level >= DEBUG_LEVEL_INFO)
3317                 printk("%s(%d):%s tiocmget() value=%08X\n",
3318                          __FILE__,__LINE__, info->device_name, result );
3319         return result;
3320 }
3321
3322 /* set modem control signals (DTR/RTS)
3323  */
3324 static int tiocmset(struct tty_struct *tty, struct file *file,
3325                     unsigned int set, unsigned int clear)
3326 {
3327         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3328         unsigned long flags;
3329
3330         if (debug_level >= DEBUG_LEVEL_INFO)
3331                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3332                         __FILE__,__LINE__,info->device_name, set, clear);
3333
3334         if (set & TIOCM_RTS)
3335                 info->serial_signals |= SerialSignal_RTS;
3336         if (set & TIOCM_DTR)
3337                 info->serial_signals |= SerialSignal_DTR;
3338         if (clear & TIOCM_RTS)
3339                 info->serial_signals &= ~SerialSignal_RTS;
3340         if (clear & TIOCM_DTR)
3341                 info->serial_signals &= ~SerialSignal_DTR;
3342
3343         spin_lock_irqsave(&info->lock,flags);
3344         set_signals(info);
3345         spin_unlock_irqrestore(&info->lock,flags);
3346
3347         return 0;
3348 }
3349
3350
3351
3352 /* Block the current process until the specified port is ready to open.
3353  */
3354 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3355                            SLMP_INFO *info)
3356 {
3357         DECLARE_WAITQUEUE(wait, current);
3358         int             retval;
3359         int             do_clocal = 0, extra_count = 0;
3360         unsigned long   flags;
3361
3362         if (debug_level >= DEBUG_LEVEL_INFO)
3363                 printk("%s(%d):%s block_til_ready()\n",
3364                          __FILE__,__LINE__, tty->driver->name );
3365
3366         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3367                 /* nonblock mode is set or port is not enabled */
3368                 /* just verify that callout device is not active */
3369                 info->flags |= ASYNC_NORMAL_ACTIVE;
3370                 return 0;
3371         }
3372
3373         if (tty->termios->c_cflag & CLOCAL)
3374                 do_clocal = 1;
3375
3376         /* Wait for carrier detect and the line to become
3377          * free (i.e., not in use by the callout).  While we are in
3378          * this loop, info->count is dropped by one, so that
3379          * close() knows when to free things.  We restore it upon
3380          * exit, either normal or abnormal.
3381          */
3382
3383         retval = 0;
3384         add_wait_queue(&info->open_wait, &wait);
3385
3386         if (debug_level >= DEBUG_LEVEL_INFO)
3387                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3388                          __FILE__,__LINE__, tty->driver->name, info->count );
3389
3390         spin_lock_irqsave(&info->lock, flags);
3391         if (!tty_hung_up_p(filp)) {
3392                 extra_count = 1;
3393                 info->count--;
3394         }
3395         spin_unlock_irqrestore(&info->lock, flags);
3396         info->blocked_open++;
3397
3398         while (1) {
3399                 if ((tty->termios->c_cflag & CBAUD)) {
3400                         spin_lock_irqsave(&info->lock,flags);
3401                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3402                         set_signals(info);
3403                         spin_unlock_irqrestore(&info->lock,flags);
3404                 }
3405
3406                 set_current_state(TASK_INTERRUPTIBLE);
3407
3408                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3409                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3410                                         -EAGAIN : -ERESTARTSYS;
3411                         break;
3412                 }
3413
3414                 spin_lock_irqsave(&info->lock,flags);
3415                 get_signals(info);
3416                 spin_unlock_irqrestore(&info->lock,flags);
3417
3418                 if (!(info->flags & ASYNC_CLOSING) &&
3419                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3420                         break;
3421                 }
3422
3423                 if (signal_pending(current)) {
3424                         retval = -ERESTARTSYS;
3425                         break;
3426                 }
3427
3428                 if (debug_level >= DEBUG_LEVEL_INFO)
3429                         printk("%s(%d):%s block_til_ready() count=%d\n",
3430                                  __FILE__,__LINE__, tty->driver->name, info->count );
3431
3432                 schedule();
3433         }
3434
3435         set_current_state(TASK_RUNNING);
3436         remove_wait_queue(&info->open_wait, &wait);
3437
3438         if (extra_count)
3439                 info->count++;
3440         info->blocked_open--;
3441
3442         if (debug_level >= DEBUG_LEVEL_INFO)
3443                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3444                          __FILE__,__LINE__, tty->driver->name, info->count );
3445
3446         if (!retval)
3447                 info->flags |= ASYNC_NORMAL_ACTIVE;
3448
3449         return retval;
3450 }
3451
3452 int alloc_dma_bufs(SLMP_INFO *info)
3453 {
3454         unsigned short BuffersPerFrame;
3455         unsigned short BufferCount;
3456
3457         // Force allocation to start at 64K boundary for each port.
3458         // This is necessary because *all* buffer descriptors for a port
3459         // *must* be in the same 64K block. All descriptors on a port
3460         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3461         // into the CBP register.
3462         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3463
3464         /* Calculate the number of DMA buffers necessary to hold the */
3465         /* largest allowable frame size. Note: If the max frame size is */
3466         /* not an even multiple of the DMA buffer size then we need to */
3467         /* round the buffer count per frame up one. */
3468
3469         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3470         if ( info->max_frame_size % SCABUFSIZE )
3471                 BuffersPerFrame++;
3472
3473         /* calculate total number of data buffers (SCABUFSIZE) possible
3474          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3475          * for the descriptor list (BUFFERLISTSIZE).
3476          */
3477         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3478
3479         /* limit number of buffers to maximum amount of descriptors */
3480         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3481                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3482
3483         /* use enough buffers to transmit one max size frame */
3484         info->tx_buf_count = BuffersPerFrame + 1;
3485
3486         /* never use more than half the available buffers for transmit */
3487         if (info->tx_buf_count > (BufferCount/2))
3488                 info->tx_buf_count = BufferCount/2;
3489
3490         if (info->tx_buf_count > SCAMAXDESC)
3491                 info->tx_buf_count = SCAMAXDESC;
3492
3493         /* use remaining buffers for receive */
3494         info->rx_buf_count = BufferCount - info->tx_buf_count;
3495
3496         if (info->rx_buf_count > SCAMAXDESC)
3497                 info->rx_buf_count = SCAMAXDESC;
3498
3499         if ( debug_level >= DEBUG_LEVEL_INFO )
3500                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3501                         __FILE__,__LINE__, info->device_name,
3502                         info->tx_buf_count,info->rx_buf_count);
3503
3504         if ( alloc_buf_list( info ) < 0 ||
3505                 alloc_frame_bufs(info,
3506                                         info->rx_buf_list,
3507                                         info->rx_buf_list_ex,
3508                                         info->rx_buf_count) < 0 ||
3509                 alloc_frame_bufs(info,
3510                                         info->tx_buf_list,
3511                                         info->tx_buf_list_ex,
3512                                         info->tx_buf_count) < 0 ||
3513                 alloc_tmp_rx_buf(info) < 0 ) {
3514                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3515                         __FILE__,__LINE__, info->device_name);
3516                 return -ENOMEM;
3517         }
3518
3519         rx_reset_buffers( info );
3520
3521         return 0;
3522 }
3523
3524 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3525  */
3526 int alloc_buf_list(SLMP_INFO *info)
3527 {
3528         unsigned int i;
3529
3530         /* build list in adapter shared memory */
3531         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3532         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3533         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3534
3535         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3536
3537         /* Save virtual address pointers to the receive and */
3538         /* transmit buffer lists. (Receive 1st). These pointers will */
3539         /* be used by the processor to access the lists. */
3540         info->rx_buf_list = (SCADESC *)info->buffer_list;
3541
3542         info->tx_buf_list = (SCADESC *)info->buffer_list;
3543         info->tx_buf_list += info->rx_buf_count;
3544
3545         /* Build links for circular buffer entry lists (tx and rx)
3546          *
3547          * Note: links are physical addresses read by the SCA device
3548          * to determine the next buffer entry to use.
3549          */
3550
3551         for ( i = 0; i < info->rx_buf_count; i++ ) {
3552                 /* calculate and store physical address of this buffer entry */
3553                 info->rx_buf_list_ex[i].phys_entry =
3554                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3555
3556                 /* calculate and store physical address of */
3557                 /* next entry in cirular list of entries */
3558                 info->rx_buf_list[i].next = info->buffer_list_phys;
3559                 if ( i < info->rx_buf_count - 1 )
3560                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3561
3562                 info->rx_buf_list[i].length = SCABUFSIZE;
3563         }
3564
3565         for ( i = 0; i < info->tx_buf_count; i++ ) {
3566                 /* calculate and store physical address of this buffer entry */
3567                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3568                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3569
3570                 /* calculate and store physical address of */
3571                 /* next entry in cirular list of entries */
3572
3573                 info->tx_buf_list[i].next = info->buffer_list_phys +
3574                         info->rx_buf_count * sizeof(SCADESC);
3575
3576                 if ( i < info->tx_buf_count - 1 )
3577                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3578         }
3579
3580         return 0;
3581 }
3582
3583 /* Allocate the frame DMA buffers used by the specified buffer list.
3584  */
3585 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3586 {
3587         int i;
3588         unsigned long phys_addr;
3589
3590         for ( i = 0; i < count; i++ ) {
3591                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3592                 phys_addr = info->port_array[0]->last_mem_alloc;
3593                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3594
3595                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3596                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3597         }
3598
3599         return 0;
3600 }
3601
3602 void free_dma_bufs(SLMP_INFO *info)
3603 {
3604         info->buffer_list = NULL;
3605         info->rx_buf_list = NULL;
3606         info->tx_buf_list = NULL;
3607 }
3608
3609 /* allocate buffer large enough to hold max_frame_size.
3610  * This buffer is used to pass an assembled frame to the line discipline.
3611  */
3612 int alloc_tmp_rx_buf(SLMP_INFO *info)
3613 {
3614         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3615         if (info->tmp_rx_buf == NULL)
3616                 return -ENOMEM;
3617         return 0;
3618 }
3619
3620 void free_tmp_rx_buf(SLMP_INFO *info)
3621 {
3622         if (info->tmp_rx_buf)
3623                 kfree(info->tmp_rx_buf);
3624         info->tmp_rx_buf = NULL;
3625 }
3626
3627 int claim_resources(SLMP_INFO *info)
3628 {
3629         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3630                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3631                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3632                 info->init_error = DiagStatus_AddressConflict;
3633                 goto errout;
3634         }
3635         else
3636                 info->shared_mem_requested = 1;
3637
3638         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3639                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3640                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3641                 info->init_error = DiagStatus_AddressConflict;
3642                 goto errout;
3643         }
3644         else
3645                 info->lcr_mem_requested = 1;
3646
3647         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3648                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3649                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3650                 info->init_error = DiagStatus_AddressConflict;
3651                 goto errout;
3652         }
3653         else
3654                 info->sca_base_requested = 1;
3655
3656         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3657                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3658                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3659                 info->init_error = DiagStatus_AddressConflict;
3660                 goto errout;
3661         }
3662         else
3663                 info->sca_statctrl_requested = 1;
3664
3665         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3666         if (!info->memory_base) {
3667                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3668                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3669                 info->init_error = DiagStatus_CantAssignPciResources;
3670                 goto errout;
3671         }
3672
3673         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3674         if (!info->lcr_base) {
3675                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3676                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3677                 info->init_error = DiagStatus_CantAssignPciResources;
3678                 goto errout;
3679         }
3680         info->lcr_base += info->lcr_offset;
3681
3682         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3683         if (!info->sca_base) {
3684                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3685                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3686                 info->init_error = DiagStatus_CantAssignPciResources;
3687                 goto errout;
3688         }
3689         info->sca_base += info->sca_offset;
3690
3691         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3692         if (!info->statctrl_base) {
3693                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3694                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3695                 info->init_error = DiagStatus_CantAssignPciResources;
3696                 goto errout;
3697         }
3698         info->statctrl_base += info->statctrl_offset;
3699
3700         if ( !memory_test(info) ) {
3701                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3702                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3703                 info->init_error = DiagStatus_MemoryError;
3704                 goto errout;
3705         }
3706
3707         return 0;
3708
3709 errout:
3710         release_resources( info );
3711         return -ENODEV;
3712 }
3713
3714 void release_resources(SLMP_INFO *info)
3715 {
3716         if ( debug_level >= DEBUG_LEVEL_INFO )
3717                 printk( "%s(%d):%s release_resources() entry\n",
3718                         __FILE__,__LINE__,info->device_name );
3719
3720         if ( info->irq_requested ) {
3721                 free_irq(info->irq_level, info);
3722                 info->irq_requested = 0;
3723         }
3724
3725         if ( info->shared_mem_requested ) {
3726                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3727                 info->shared_mem_requested = 0;
3728         }
3729         if ( info->lcr_mem_requested ) {
3730                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3731                 info->lcr_mem_requested = 0;
3732         }
3733         if ( info->sca_base_requested ) {
3734                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3735                 info->sca_base_requested = 0;
3736         }
3737         if ( info->sca_statctrl_requested ) {
3738                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3739                 info->sca_statctrl_requested = 0;
3740         }
3741
3742         if (info->memory_base){
3743                 iounmap(info->memory_base);
3744                 info->memory_base = NULL;
3745         }
3746
3747         if (info->sca_base) {
3748                 iounmap(info->sca_base - info->sca_offset);
3749                 info->sca_base=NULL;
3750         }
3751
3752         if (info->statctrl_base) {
3753                 iounmap(info->statctrl_base - info->statctrl_offset);
3754                 info->statctrl_base=NULL;
3755         }
3756
3757         if (info->lcr_base){
3758                 iounmap(info->lcr_base - info->lcr_offset);
3759                 info->lcr_base = NULL;
3760         }
3761
3762         if ( debug_level >= DEBUG_LEVEL_INFO )
3763                 printk( "%s(%d):%s release_resources() exit\n",
3764                         __FILE__,__LINE__,info->device_name );
3765 }
3766
3767 /* Add the specified device instance data structure to the
3768  * global linked list of devices and increment the device count.
3769  */
3770 void add_device(SLMP_INFO *info)
3771 {
3772         info->next_device = NULL;
3773         info->line = synclinkmp_device_count;
3774         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3775
3776         if (info->line < MAX_DEVICES) {
3777                 if (maxframe[info->line])
3778                         info->max_frame_size = maxframe[info->line];
3779                 info->dosyncppp = dosyncppp[info->line];
3780         }
3781
3782         synclinkmp_device_count++;
3783
3784         if ( !synclinkmp_device_list )
3785                 synclinkmp_device_list = info;
3786         else {
3787                 SLMP_INFO *current_dev = synclinkmp_device_list;
3788                 while( current_dev->next_device )
3789                         current_dev = current_dev->next_device;
3790                 current_dev->next_device = info;
3791         }
3792
3793         if ( info->max_frame_size < 4096 )
3794                 info->max_frame_size = 4096;
3795         else if ( info->max_frame_size > 65535 )
3796                 info->max_frame_size = 65535;
3797
3798         printk( "SyncLink MultiPort %s: "
3799                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3800                 info->device_name,
3801                 info->phys_sca_base,
3802                 info->phys_memory_base,
3803                 info->phys_statctrl_base,
3804                 info->phys_lcr_base,
3805                 info->irq_level,
3806                 info->max_frame_size );
3807
3808 #ifdef CONFIG_HDLC
3809         hdlcdev_init(info);
3810 #endif
3811 }
3812
3813 /* Allocate and initialize a device instance structure
3814  *
3815  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3816  */
3817 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3818 {
3819         SLMP_INFO *info;
3820
3821         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3822                  GFP_KERNEL);
3823
3824         if (!info) {
3825                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3826                         __FILE__,__LINE__, adapter_num, port_num);
3827         } else {
3828                 memset(info, 0, sizeof(SLMP_INFO));
3829                 info->magic = MGSL_MAGIC;
3830                 INIT_WORK(&info->task, bh_handler, info);
3831                 info->max_frame_size = 4096;
3832                 info->close_delay = 5*HZ/10;
3833                 info->closing_wait = 30*HZ;
3834                 init_waitqueue_head(&info->open_wait);
3835                 init_waitqueue_head(&info->close_wait);
3836                 init_waitqueue_head(&info->status_event_wait_q);
3837                 init_waitqueue_head(&info->event_wait_q);
3838                 spin_lock_init(&info->netlock);
3839                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3840                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3841                 info->adapter_num = adapter_num;
3842                 info->port_num = port_num;
3843
3844                 /* Copy configuration info to device instance data */
3845                 info->irq_level = pdev->irq;
3846                 info->phys_lcr_base = pci_resource_start(pdev,0);
3847                 info->phys_sca_base = pci_resource_start(pdev,2);
3848                 info->phys_memory_base = pci_resource_start(pdev,3);
3849                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3850
3851                 /* Because veremap only works on page boundaries we must map
3852                  * a larger area than is actually implemented for the LCR
3853                  * memory range. We map a full page starting at the page boundary.
3854                  */
3855                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3856                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3857
3858                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3859                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3860
3861                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3862                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3863
3864                 info->bus_type = MGSL_BUS_TYPE_PCI;
3865                 info->irq_flags = SA_SHIRQ;
3866
3867                 init_timer(&info->tx_timer);
3868                 info->tx_timer.data = (unsigned long)info;
3869                 info->tx_timer.function = tx_timeout;
3870
3871                 init_timer(&info->status_timer);
3872                 info->status_timer.data = (unsigned long)info;
3873                 info->status_timer.function = status_timeout;
3874
3875                 /* Store the PCI9050 misc control register value because a flaw
3876                  * in the PCI9050 prevents LCR registers from being read if
3877                  * BIOS assigns an LCR base address with bit 7 set.
3878                  *
3879                  * Only the misc control register is accessed for which only
3880                  * write access is needed, so set an initial value and change
3881                  * bits to the device instance data as we write the value
3882                  * to the actual misc control register.
3883                  */
3884                 info->misc_ctrl_value = 0x087e4546;
3885
3886                 /* initial port state is unknown - if startup errors
3887                  * occur, init_error will be set to indicate the
3888                  * problem. Once the port is fully initialized,
3889                  * this value will be set to 0 to indicate the
3890                  * port is available.
3891                  */
3892                 info->init_error = -1;
3893         }
3894
3895         return info;
3896 }
3897
3898 void device_init(int adapter_num, struct pci_dev *pdev)
3899 {
3900         SLMP_INFO *port_array[SCA_MAX_PORTS];
3901         int port;
3902
3903         /* allocate device instances for up to SCA_MAX_PORTS devices */
3904         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3905                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3906                 if( port_array[port] == NULL ) {
3907                         for ( --port; port >= 0; --port )
3908                                 kfree(port_array[port]);
3909                         return;
3910                 }
3911         }
3912
3913         /* give copy of port_array to all ports and add to device list  */
3914         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3915                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3916                 add_device( port_array[port] );
3917                 spin_lock_init(&port_array[port]->lock);
3918         }
3919
3920         /* Allocate and claim adapter resources */
3921         if ( !claim_resources(port_array[0]) ) {
3922
3923                 alloc_dma_bufs(port_array[0]);
3924
3925                 /* copy resource information from first port to others */
3926                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3927                         port_array[port]->lock  = port_array[0]->lock;
3928                         port_array[port]->irq_level     = port_array[0]->irq_level;
3929                         port_array[port]->memory_base   = port_array[0]->memory_base;
3930                         port_array[port]->sca_base      = port_array[0]->sca_base;
3931                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3932                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3933                         alloc_dma_bufs(port_array[port]);
3934                 }
3935
3936                 if ( request_irq(port_array[0]->irq_level,
3937                                         synclinkmp_interrupt,
3938                                         port_array[0]->irq_flags,
3939                                         port_array[0]->device_name,
3940                                         port_array[0]) < 0 ) {
3941                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3942                                 __FILE__,__LINE__,
3943                                 port_array[0]->device_name,
3944                                 port_array[0]->irq_level );
3945                 }
3946                 else {
3947                         port_array[0]->irq_requested = 1;
3948                         adapter_test(port_array[0]);
3949                 }
3950         }
3951 }
3952
3953 static struct tty_operations ops = {
3954         .open = open,
3955         .close = close,
3956         .write = write,
3957         .put_char = put_char,
3958         .flush_chars = flush_chars,
3959         .write_room = write_room,
3960         .chars_in_buffer = chars_in_buffer,
3961         .flush_buffer = flush_buffer,
3962         .ioctl = ioctl,
3963         .throttle = throttle,
3964         .unthrottle = unthrottle,
3965         .send_xchar = send_xchar,
3966         .break_ctl = set_break,
3967         .wait_until_sent = wait_until_sent,
3968         .read_proc = read_proc,
3969         .set_termios = set_termios,
3970         .stop = tx_hold,
3971         .start = tx_release,
3972         .hangup = hangup,
3973         .tiocmget = tiocmget,
3974         .tiocmset = tiocmset,
3975 };
3976
3977 static void synclinkmp_cleanup(void)
3978 {
3979         int rc;
3980         SLMP_INFO *info;
3981         SLMP_INFO *tmp;
3982
3983         printk("Unloading %s %s\n", driver_name, driver_version);
3984
3985         if (serial_driver) {
3986                 if ((rc = tty_unregister_driver(serial_driver)))
3987                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3988                                __FILE__,__LINE__,rc);
3989                 put_tty_driver(serial_driver);
3990         }
3991
3992         /* reset devices */
3993         info = synclinkmp_device_list;
3994         while(info) {
3995                 reset_port(info);
3996                 info = info->next_device;
3997         }
3998
3999         /* release devices */
4000         info = synclinkmp_device_list;
4001         while(info) {
4002 #ifdef CONFIG_HDLC
4003                 hdlcdev_exit(info);
4004 #endif
4005                 free_dma_bufs(info);
4006                 free_tmp_rx_buf(info);
4007                 if ( info->port_num == 0 ) {
4008                         if (info->sca_base)
4009                                 write_reg(info, LPR, 1); /* set low power mode */
4010                         release_resources(info);
4011                 }
4012                 tmp = info;
4013                 info = info->next_device;
4014                 kfree(tmp);
4015         }
4016
4017         pci_unregister_driver(&synclinkmp_pci_driver);
4018 }
4019
4020 /* Driver initialization entry point.
4021  */
4022
4023 static int __init synclinkmp_init(void)
4024 {
4025         int rc;
4026
4027         if (break_on_load) {
4028                 synclinkmp_get_text_ptr();
4029                 BREAKPOINT();
4030         }
4031
4032         printk("%s %s\n", driver_name, driver_version);
4033
4034         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4035                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4036                 return rc;
4037         }
4038
4039         serial_driver = alloc_tty_driver(128);
4040         if (!serial_driver) {
4041                 rc = -ENOMEM;
4042                 goto error;
4043         }
4044
4045         /* Initialize the tty_driver structure */
4046
4047         serial_driver->owner = THIS_MODULE;
4048         serial_driver->driver_name = "synclinkmp";
4049         serial_driver->name = "ttySLM";
4050         serial_driver->major = ttymajor;
4051         serial_driver->minor_start = 64;
4052         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4053         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4054         serial_driver->init_termios = tty_std_termios;
4055         serial_driver->init_termios.c_cflag =
4056                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4057         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4058         tty_set_operations(serial_driver, &ops);
4059         if ((rc = tty_register_driver(serial_driver)) < 0) {
4060                 printk("%s(%d):Couldn't register serial driver\n",
4061                         __FILE__,__LINE__);
4062                 put_tty_driver(serial_driver);
4063                 serial_driver = NULL;
4064                 goto error;
4065         }
4066
4067         printk("%s %s, tty major#%d\n",
4068                 driver_name, driver_version,
4069                 serial_driver->major);
4070
4071         return 0;
4072
4073 error:
4074         synclinkmp_cleanup();
4075         return rc;
4076 }
4077
4078 static void __exit synclinkmp_exit(void)
4079 {
4080         synclinkmp_cleanup();
4081 }
4082
4083 module_init(synclinkmp_init);
4084 module_exit(synclinkmp_exit);
4085
4086 /* Set the port for internal loopback mode.
4087  * The TxCLK and RxCLK signals are generated from the BRG and
4088  * the TxD is looped back to the RxD internally.
4089  */
4090 void enable_loopback(SLMP_INFO *info, int enable)
4091 {
4092         if (enable) {
4093                 /* MD2 (Mode Register 2)
4094                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4095                  */
4096                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4097
4098                 /* degate external TxC clock source */
4099                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4100                 write_control_reg(info);
4101
4102                 /* RXS/TXS (Rx/Tx clock source)
4103                  * 07      Reserved, must be 0
4104                  * 06..04  Clock Source, 100=BRG
4105                  * 03..00  Clock Divisor, 0000=1
4106                  */
4107                 write_reg(info, RXS, 0x40);
4108                 write_reg(info, TXS, 0x40);
4109
4110         } else {
4111                 /* MD2 (Mode Register 2)
4112                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4113                  */
4114                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4115
4116                 /* RXS/TXS (Rx/Tx clock source)
4117                  * 07      Reserved, must be 0
4118                  * 06..04  Clock Source, 000=RxC/TxC Pin
4119                  * 03..00  Clock Divisor, 0000=1
4120                  */
4121                 write_reg(info, RXS, 0x00);
4122                 write_reg(info, TXS, 0x00);
4123         }
4124
4125         /* set LinkSpeed if available, otherwise default to 2Mbps */
4126         if (info->params.clock_speed)
4127                 set_rate(info, info->params.clock_speed);
4128         else
4129                 set_rate(info, 3686400);
4130 }
4131
4132 /* Set the baud rate register to the desired speed
4133  *
4134  *      data_rate       data rate of clock in bits per second
4135  *                      A data rate of 0 disables the AUX clock.
4136  */
4137 void set_rate( SLMP_INFO *info, u32 data_rate )
4138 {
4139         u32 TMCValue;
4140         unsigned char BRValue;
4141         u32 Divisor=0;
4142
4143         /* fBRG = fCLK/(TMC * 2^BR)
4144          */
4145         if (data_rate != 0) {
4146                 Divisor = 14745600/data_rate;
4147                 if (!Divisor)
4148                         Divisor = 1;
4149
4150                 TMCValue = Divisor;
4151
4152                 BRValue = 0;
4153                 if (TMCValue != 1 && TMCValue != 2) {
4154                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4155                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4156                          * 50/50 duty cycle.
4157                          */
4158                         BRValue = 1;
4159                         TMCValue >>= 1;
4160                 }
4161
4162                 /* while TMCValue is too big for TMC register, divide
4163                  * by 2 and increment BR exponent.
4164                  */
4165                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4166                         TMCValue >>= 1;
4167
4168                 write_reg(info, TXS,
4169                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4170                 write_reg(info, RXS,
4171                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4172                 write_reg(info, TMC, (unsigned char)TMCValue);
4173         }
4174         else {
4175                 write_reg(info, TXS,0);
4176                 write_reg(info, RXS,0);
4177                 write_reg(info, TMC, 0);
4178         }
4179 }
4180
4181 /* Disable receiver
4182  */
4183 void rx_stop(SLMP_INFO *info)
4184 {
4185         if (debug_level >= DEBUG_LEVEL_ISR)
4186                 printk("%s(%d):%s rx_stop()\n",
4187                          __FILE__,__LINE__, info->device_name );
4188
4189         write_reg(info, CMD, RXRESET);
4190
4191         info->ie0_value &= ~RXRDYE;
4192         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4193
4194         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4195         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4196         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4197
4198         info->rx_enabled = 0;
4199         info->rx_overflow = 0;
4200 }
4201
4202 /* enable the receiver
4203  */
4204 void rx_start(SLMP_INFO *info)
4205 {
4206         int i;
4207
4208         if (debug_level >= DEBUG_LEVEL_ISR)
4209                 printk("%s(%d):%s rx_start()\n",
4210                          __FILE__,__LINE__, info->device_name );
4211
4212         write_reg(info, CMD, RXRESET);
4213
4214         if ( info->params.mode == MGSL_MODE_HDLC ) {
4215                 /* HDLC, disabe IRQ on rxdata */
4216                 info->ie0_value &= ~RXRDYE;
4217                 write_reg(info, IE0, info->ie0_value);
4218
4219                 /* Reset all Rx DMA buffers and program rx dma */
4220                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4221                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4222
4223                 for (i = 0; i < info->rx_buf_count; i++) {
4224                         info->rx_buf_list[i].status = 0xff;
4225
4226                         // throttle to 4 shared memory writes at a time to prevent
4227                         // hogging local bus (keep latency time for DMA requests low).
4228                         if (!(i % 4))
4229                                 read_status_reg(info);
4230                 }
4231                 info->current_rx_buf = 0;
4232
4233                 /* set current/1st descriptor address */
4234                 write_reg16(info, RXDMA + CDA,
4235                         info->rx_buf_list_ex[0].phys_entry);
4236
4237                 /* set new last rx descriptor address */
4238                 write_reg16(info, RXDMA + EDA,
4239                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4240
4241                 /* set buffer length (shared by all rx dma data buffers) */
4242                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4243
4244                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4245                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4246         } else {
4247                 /* async, enable IRQ on rxdata */
4248                 info->ie0_value |= RXRDYE;
4249                 write_reg(info, IE0, info->ie0_value);
4250         }
4251
4252         write_reg(info, CMD, RXENABLE);
4253
4254         info->rx_overflow = FALSE;
4255         info->rx_enabled = 1;
4256 }
4257
4258 /* Enable the transmitter and send a transmit frame if
4259  * one is loaded in the DMA buffers.
4260  */
4261 void tx_start(SLMP_INFO *info)
4262 {
4263         if (debug_level >= DEBUG_LEVEL_ISR)
4264                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4265                          __FILE__,__LINE__, info->device_name,info->tx_count );
4266
4267         if (!info->tx_enabled ) {
4268                 write_reg(info, CMD, TXRESET);
4269                 write_reg(info, CMD, TXENABLE);
4270                 info->tx_enabled = TRUE;
4271         }
4272
4273         if ( info->tx_count ) {
4274
4275                 /* If auto RTS enabled and RTS is inactive, then assert */
4276                 /* RTS and set a flag indicating that the driver should */
4277                 /* negate RTS when the transmission completes. */
4278
4279                 info->drop_rts_on_tx_done = 0;
4280
4281                 if (info->params.mode != MGSL_MODE_ASYNC) {
4282
4283                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4284                                 get_signals( info );
4285                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4286                                         info->serial_signals |= SerialSignal_RTS;
4287                                         set_signals( info );
4288                                         info->drop_rts_on_tx_done = 1;
4289                                 }
4290                         }
4291
4292                         write_reg16(info, TRC0,
4293                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4294
4295                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4296                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4297
4298                         /* set TX CDA (current descriptor address) */
4299                         write_reg16(info, TXDMA + CDA,
4300                                 info->tx_buf_list_ex[0].phys_entry);
4301
4302                         /* set TX EDA (last descriptor address) */
4303                         write_reg16(info, TXDMA + EDA,
4304                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4305
4306                         /* enable underrun IRQ */
4307                         info->ie1_value &= ~IDLE;
4308                         info->ie1_value |= UDRN;
4309                         write_reg(info, IE1, info->ie1_value);
4310                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4311
4312                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4313                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4314
4315                         info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4316                         add_timer(&info->tx_timer);
4317                 }
4318                 else {
4319                         tx_load_fifo(info);
4320                         /* async, enable IRQ on txdata */
4321                         info->ie0_value |= TXRDYE;
4322                         write_reg(info, IE0, info->ie0_value);
4323                 }
4324
4325                 info->tx_active = 1;
4326         }
4327 }
4328
4329 /* stop the transmitter and DMA
4330  */
4331 void tx_stop( SLMP_INFO *info )
4332 {
4333         if (debug_level >= DEBUG_LEVEL_ISR)
4334                 printk("%s(%d):%s tx_stop()\n",
4335                          __FILE__,__LINE__, info->device_name );
4336
4337         del_timer(&info->tx_timer);
4338
4339         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4340         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4341
4342         write_reg(info, CMD, TXRESET);
4343
4344         info->ie1_value &= ~(UDRN + IDLE);
4345         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4346         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4347
4348         info->ie0_value &= ~TXRDYE;
4349         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4350
4351         info->tx_enabled = 0;
4352         info->tx_active  = 0;
4353 }
4354
4355 /* Fill the transmit FIFO until the FIFO is full or
4356  * there is no more data to load.
4357  */
4358 void tx_load_fifo(SLMP_INFO *info)
4359 {
4360         u8 TwoBytes[2];
4361
4362         /* do nothing is now tx data available and no XON/XOFF pending */
4363
4364         if ( !info->tx_count && !info->x_char )
4365                 return;
4366
4367         /* load the Transmit FIFO until FIFOs full or all data sent */
4368
4369         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4370
4371                 /* there is more space in the transmit FIFO and */
4372                 /* there is more data in transmit buffer */
4373
4374                 if ( (info->tx_count > 1) && !info->x_char ) {
4375                         /* write 16-bits */
4376                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4377                         if (info->tx_get >= info->max_frame_size)
4378                                 info->tx_get -= info->max_frame_size;
4379                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4380                         if (info->tx_get >= info->max_frame_size)
4381                                 info->tx_get -= info->max_frame_size;
4382
4383                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4384
4385                         info->tx_count -= 2;
4386                         info->icount.tx += 2;
4387                 } else {
4388                         /* only 1 byte left to transmit or 1 FIFO slot left */
4389
4390                         if (info->x_char) {
4391                                 /* transmit pending high priority char */
4392                                 write_reg(info, TRB, info->x_char);
4393                                 info->x_char = 0;
4394                         } else {
4395                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4396                                 if (info->tx_get >= info->max_frame_size)
4397                                         info->tx_get -= info->max_frame_size;
4398                                 info->tx_count--;
4399                         }
4400                         info->icount.tx++;
4401                 }
4402         }
4403 }
4404
4405 /* Reset a port to a known state
4406  */
4407 void reset_port(SLMP_INFO *info)
4408 {
4409         if (info->sca_base) {
4410
4411                 tx_stop(info);
4412                 rx_stop(info);
4413
4414                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4415                 set_signals(info);
4416
4417                 /* disable all port interrupts */
4418                 info->ie0_value = 0;
4419                 info->ie1_value = 0;
4420                 info->ie2_value = 0;
4421                 write_reg(info, IE0, info->ie0_value);
4422                 write_reg(info, IE1, info->ie1_value);
4423                 write_reg(info, IE2, info->ie2_value);
4424
4425                 write_reg(info, CMD, CHRESET);
4426         }
4427 }
4428
4429 /* Reset all the ports to a known state.
4430  */
4431 void reset_adapter(SLMP_INFO *info)
4432 {
4433         int i;
4434
4435         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4436                 if (info->port_array[i])
4437                         reset_port(info->port_array[i]);
4438         }
4439 }
4440
4441 /* Program port for asynchronous communications.
4442  */
4443 void async_mode(SLMP_INFO *info)
4444 {
4445
4446         unsigned char RegValue;
4447
4448         tx_stop(info);
4449         rx_stop(info);
4450
4451         /* MD0, Mode Register 0
4452          *
4453          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4454          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4455          * 03      Reserved, must be 0
4456          * 02      CRCCC, CRC Calculation, 0=disabled
4457          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4458          *
4459          * 0000 0000
4460          */
4461         RegValue = 0x00;
4462         if (info->params.stop_bits != 1)
4463                 RegValue |= BIT1;
4464         write_reg(info, MD0, RegValue);
4465
4466         /* MD1, Mode Register 1
4467          *
4468          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4469          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4470          * 03..02  RXCHR<1..0>, rx char size
4471          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4472          *
4473          * 0100 0000
4474          */
4475         RegValue = 0x40;
4476         switch (info->params.data_bits) {
4477         case 7: RegValue |= BIT4 + BIT2; break;
4478         case 6: RegValue |= BIT5 + BIT3; break;
4479         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4480         }
4481         if (info->params.parity != ASYNC_PARITY_NONE) {
4482                 RegValue |= BIT1;
4483                 if (info->params.parity == ASYNC_PARITY_ODD)
4484                         RegValue |= BIT0;
4485         }
4486         write_reg(info, MD1, RegValue);
4487
4488         /* MD2, Mode Register 2
4489          *
4490          * 07..02  Reserved, must be 0
4491          * 01..00  CNCT<1..0> Channel connection, 0=normal
4492          *
4493          * 0000 0000
4494          */
4495         RegValue = 0x00;
4496         write_reg(info, MD2, RegValue);
4497
4498         /* RXS, Receive clock source
4499          *
4500          * 07      Reserved, must be 0
4501          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4502          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4503          */
4504         RegValue=BIT6;
4505         write_reg(info, RXS, RegValue);
4506
4507         /* TXS, Transmit clock source
4508          *
4509          * 07      Reserved, must be 0
4510          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4511          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4512          */
4513         RegValue=BIT6;
4514         write_reg(info, TXS, RegValue);
4515
4516         /* Control Register
4517          *
4518          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4519          */
4520         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4521         write_control_reg(info);
4522
4523         tx_set_idle(info);
4524
4525         /* RRC Receive Ready Control 0
4526          *
4527          * 07..05  Reserved, must be 0
4528          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4529          */
4530         write_reg(info, RRC, 0x00);
4531
4532         /* TRC0 Transmit Ready Control 0
4533          *
4534          * 07..05  Reserved, must be 0
4535          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4536          */
4537         write_reg(info, TRC0, 0x10);
4538
4539         /* TRC1 Transmit Ready Control 1
4540          *
4541          * 07..05  Reserved, must be 0
4542          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4543          */
4544         write_reg(info, TRC1, 0x1e);
4545
4546         /* CTL, MSCI control register
4547          *
4548          * 07..06  Reserved, set to 0
4549          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4550          * 04      IDLC, idle control, 0=mark 1=idle register
4551          * 03      BRK, break, 0=off 1 =on (async)
4552          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4553          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4554          * 00      RTS, RTS output control, 0=active 1=inactive
4555          *
4556          * 0001 0001
4557          */
4558         RegValue = 0x10;
4559         if (!(info->serial_signals & SerialSignal_RTS))
4560                 RegValue |= 0x01;
4561         write_reg(info, CTL, RegValue);
4562
4563         /* enable status interrupts */
4564         info->ie0_value |= TXINTE + RXINTE;
4565         write_reg(info, IE0, info->ie0_value);
4566
4567         /* enable break detect interrupt */
4568         info->ie1_value = BRKD;
4569         write_reg(info, IE1, info->ie1_value);
4570
4571         /* enable rx overrun interrupt */
4572         info->ie2_value = OVRN;
4573         write_reg(info, IE2, info->ie2_value);
4574
4575         set_rate( info, info->params.data_rate * 16 );
4576
4577         if (info->params.loopback)
4578                 enable_loopback(info,1);
4579 }
4580
4581 /* Program the SCA for HDLC communications.
4582  */
4583 void hdlc_mode(SLMP_INFO *info)
4584 {
4585         unsigned char RegValue;
4586         u32 DpllDivisor;
4587
4588         // Can't use DPLL because SCA outputs recovered clock on RxC when
4589         // DPLL mode selected. This causes output contention with RxC receiver.
4590         // Use of DPLL would require external hardware to disable RxC receiver
4591         // when DPLL mode selected.
4592         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4593
4594         /* disable DMA interrupts */
4595         write_reg(info, TXDMA + DIR, 0);
4596         write_reg(info, RXDMA + DIR, 0);
4597
4598         /* MD0, Mode Register 0
4599          *
4600          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4601          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4602          * 03      Reserved, must be 0
4603          * 02      CRCCC, CRC Calculation, 1=enabled
4604          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4605          * 00      CRC0, CRC initial value, 1 = all 1s
4606          *
4607          * 1000 0001
4608          */
4609         RegValue = 0x81;
4610         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4611                 RegValue |= BIT4;
4612         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4613                 RegValue |= BIT4;
4614         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4615                 RegValue |= BIT2 + BIT1;
4616         write_reg(info, MD0, RegValue);
4617
4618         /* MD1, Mode Register 1
4619          *
4620          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4621          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4622          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4623          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4624          *
4625          * 0000 0000
4626          */
4627         RegValue = 0x00;
4628         write_reg(info, MD1, RegValue);
4629
4630         /* MD2, Mode Register 2
4631          *
4632          * 07      NRZFM, 0=NRZ, 1=FM
4633          * 06..05  CODE<1..0> Encoding, 00=NRZ
4634          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4635          * 02      Reserved, must be 0
4636          * 01..00  CNCT<1..0> Channel connection, 0=normal
4637          *
4638          * 0000 0000
4639          */
4640         RegValue = 0x00;
4641         switch(info->params.encoding) {
4642         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4643         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4644         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4645         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4646 #if 0
4647         case HDLC_ENCODING_NRZB:                                        /* not supported */
4648         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4649         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4650 #endif
4651         }
4652         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4653                 DpllDivisor = 16;
4654                 RegValue |= BIT3;
4655         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4656                 DpllDivisor = 8;
4657         } else {
4658                 DpllDivisor = 32;
4659                 RegValue |= BIT4;
4660         }
4661         write_reg(info, MD2, RegValue);
4662
4663
4664         /* RXS, Receive clock source
4665          *
4666          * 07      Reserved, must be 0
4667          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4668          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4669          */
4670         RegValue=0;
4671         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4672                 RegValue |= BIT6;
4673         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4674                 RegValue |= BIT6 + BIT5;
4675         write_reg(info, RXS, RegValue);
4676
4677         /* TXS, Transmit clock source
4678          *
4679          * 07      Reserved, must be 0
4680          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4681          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4682          */
4683         RegValue=0;
4684         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4685                 RegValue |= BIT6;
4686         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4687                 RegValue |= BIT6 + BIT5;
4688         write_reg(info, TXS, RegValue);
4689
4690         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4691                 set_rate(info, info->params.clock_speed * DpllDivisor);
4692         else
4693                 set_rate(info, info->params.clock_speed);
4694
4695         /* GPDATA (General Purpose I/O Data Register)
4696          *
4697          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4698          */
4699         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4700                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4701         else
4702                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4703         write_control_reg(info);
4704
4705         /* RRC Receive Ready Control 0
4706          *
4707          * 07..05  Reserved, must be 0
4708          * 04..00  RRC<4..0> Rx FIFO trigger active
4709          */
4710         write_reg(info, RRC, rx_active_fifo_level);
4711
4712         /* TRC0 Transmit Ready Control 0
4713          *
4714          * 07..05  Reserved, must be 0
4715          * 04..00  TRC<4..0> Tx FIFO trigger active
4716          */
4717         write_reg(info, TRC0, tx_active_fifo_level);
4718
4719         /* TRC1 Transmit Ready Control 1
4720          *
4721          * 07..05  Reserved, must be 0
4722          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4723          */
4724         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4725
4726         /* DMR, DMA Mode Register
4727          *
4728          * 07..05  Reserved, must be 0
4729          * 04      TMOD, Transfer Mode: 1=chained-block
4730          * 03      Reserved, must be 0
4731          * 02      NF, Number of Frames: 1=multi-frame
4732          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4733          * 00      Reserved, must be 0
4734          *
4735          * 0001 0100
4736          */
4737         write_reg(info, TXDMA + DMR, 0x14);
4738         write_reg(info, RXDMA + DMR, 0x14);
4739
4740         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4741         write_reg(info, RXDMA + CPB,
4742                 (unsigned char)(info->buffer_list_phys >> 16));
4743
4744         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4745         write_reg(info, TXDMA + CPB,
4746                 (unsigned char)(info->buffer_list_phys >> 16));
4747
4748         /* enable status interrupts. other code enables/disables
4749          * the individual sources for these two interrupt classes.
4750          */
4751         info->ie0_value |= TXINTE + RXINTE;
4752         write_reg(info, IE0, info->ie0_value);
4753
4754         /* CTL, MSCI control register
4755          *
4756          * 07..06  Reserved, set to 0
4757          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4758          * 04      IDLC, idle control, 0=mark 1=idle register
4759          * 03      BRK, break, 0=off 1 =on (async)
4760          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4761          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4762          * 00      RTS, RTS output control, 0=active 1=inactive
4763          *
4764          * 0001 0001
4765          */
4766         RegValue = 0x10;
4767         if (!(info->serial_signals & SerialSignal_RTS))
4768                 RegValue |= 0x01;
4769         write_reg(info, CTL, RegValue);
4770
4771         /* preamble not supported ! */
4772
4773         tx_set_idle(info);
4774         tx_stop(info);
4775         rx_stop(info);
4776
4777         set_rate(info, info->params.clock_speed);
4778
4779         if (info->params.loopback)
4780                 enable_loopback(info,1);
4781 }
4782
4783 /* Set the transmit HDLC idle mode
4784  */
4785 void tx_set_idle(SLMP_INFO *info)
4786 {
4787         unsigned char RegValue = 0xff;
4788
4789         /* Map API idle mode to SCA register bits */
4790         switch(info->idle_mode) {
4791         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4792         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4793         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4794         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4795         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4796         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4797         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4798         }
4799
4800         write_reg(info, IDL, RegValue);
4801 }
4802
4803 /* Query the adapter for the state of the V24 status (input) signals.
4804  */
4805 void get_signals(SLMP_INFO *info)
4806 {
4807         u16 status = read_reg(info, SR3);
4808         u16 gpstatus = read_status_reg(info);
4809         u16 testbit;
4810
4811         /* clear all serial signals except DTR and RTS */
4812         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4813
4814         /* set serial signal bits to reflect MISR */
4815
4816         if (!(status & BIT3))
4817                 info->serial_signals |= SerialSignal_CTS;
4818
4819         if ( !(status & BIT2))
4820                 info->serial_signals |= SerialSignal_DCD;
4821
4822         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4823         if (!(gpstatus & testbit))
4824                 info->serial_signals |= SerialSignal_RI;
4825
4826         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4827         if (!(gpstatus & testbit))
4828                 info->serial_signals |= SerialSignal_DSR;
4829 }
4830
4831 /* Set the state of DTR and RTS based on contents of
4832  * serial_signals member of device context.
4833  */
4834 void set_signals(SLMP_INFO *info)
4835 {
4836         unsigned char RegValue;
4837         u16 EnableBit;
4838
4839         RegValue = read_reg(info, CTL);
4840         if (info->serial_signals & SerialSignal_RTS)
4841                 RegValue &= ~BIT0;
4842         else
4843                 RegValue |= BIT0;
4844         write_reg(info, CTL, RegValue);
4845
4846         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4847         EnableBit = BIT1 << (info->port_num*2);
4848         if (info->serial_signals & SerialSignal_DTR)
4849                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4850         else
4851                 info->port_array[0]->ctrlreg_value |= EnableBit;
4852         write_control_reg(info);
4853 }
4854
4855 /*******************/
4856 /* DMA Buffer Code */
4857 /*******************/
4858
4859 /* Set the count for all receive buffers to SCABUFSIZE
4860  * and set the current buffer to the first buffer. This effectively
4861  * makes all buffers free and discards any data in buffers.
4862  */
4863 void rx_reset_buffers(SLMP_INFO *info)
4864 {
4865         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4866 }
4867
4868 /* Free the buffers used by a received frame
4869  *
4870  * info   pointer to device instance data
4871  * first  index of 1st receive buffer of frame
4872  * last   index of last receive buffer of frame
4873  */
4874 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4875 {
4876         int done = 0;
4877
4878         while(!done) {
4879                 /* reset current buffer for reuse */
4880                 info->rx_buf_list[first].status = 0xff;
4881
4882                 if (first == last) {
4883                         done = 1;
4884                         /* set new last rx descriptor address */
4885                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4886                 }
4887
4888                 first++;
4889                 if (first == info->rx_buf_count)
4890                         first = 0;
4891         }
4892
4893         /* set current buffer to next buffer after last buffer of frame */
4894         info->current_rx_buf = first;
4895 }
4896
4897 /* Return a received frame from the receive DMA buffers.
4898  * Only frames received without errors are returned.
4899  *
4900  * Return Value:        1 if frame returned, otherwise 0
4901  */
4902 int rx_get_frame(SLMP_INFO *info)
4903 {
4904         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4905         unsigned short status;
4906         unsigned int framesize = 0;
4907         int ReturnCode = 0;
4908         unsigned long flags;
4909         struct tty_struct *tty = info->tty;
4910         unsigned char addr_field = 0xff;
4911         SCADESC *desc;
4912         SCADESC_EX *desc_ex;
4913
4914 CheckAgain:
4915         /* assume no frame returned, set zero length */
4916         framesize = 0;
4917         addr_field = 0xff;
4918
4919         /*
4920          * current_rx_buf points to the 1st buffer of the next available
4921          * receive frame. To find the last buffer of the frame look for
4922          * a non-zero status field in the buffer entries. (The status
4923          * field is set by the 16C32 after completing a receive frame.
4924          */
4925         StartIndex = EndIndex = info->current_rx_buf;
4926
4927         for ( ;; ) {
4928                 desc = &info->rx_buf_list[EndIndex];
4929                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4930
4931                 if (desc->status == 0xff)
4932                         goto Cleanup;   /* current desc still in use, no frames available */
4933
4934                 if (framesize == 0 && info->params.addr_filter != 0xff)
4935                         addr_field = desc_ex->virt_addr[0];
4936
4937                 framesize += desc->length;
4938
4939                 /* Status != 0 means last buffer of frame */
4940                 if (desc->status)
4941                         break;
4942
4943                 EndIndex++;
4944                 if (EndIndex == info->rx_buf_count)
4945                         EndIndex = 0;
4946
4947                 if (EndIndex == info->current_rx_buf) {
4948                         /* all buffers have been 'used' but none mark      */
4949                         /* the end of a frame. Reset buffers and receiver. */
4950                         if ( info->rx_enabled ){
4951                                 spin_lock_irqsave(&info->lock,flags);
4952                                 rx_start(info);
4953                                 spin_unlock_irqrestore(&info->lock,flags);
4954                         }
4955                         goto Cleanup;
4956                 }
4957
4958         }
4959
4960         /* check status of receive frame */
4961
4962         /* frame status is byte stored after frame data
4963          *
4964          * 7 EOM (end of msg), 1 = last buffer of frame
4965          * 6 Short Frame, 1 = short frame
4966          * 5 Abort, 1 = frame aborted
4967          * 4 Residue, 1 = last byte is partial
4968          * 3 Overrun, 1 = overrun occurred during frame reception
4969          * 2 CRC,     1 = CRC error detected
4970          *
4971          */
4972         status = desc->status;
4973
4974         /* ignore CRC bit if not using CRC (bit is undefined) */
4975         /* Note:CRC is not save to data buffer */
4976         if (info->params.crc_type == HDLC_CRC_NONE)
4977                 status &= ~BIT2;
4978
4979         if (framesize == 0 ||
4980                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4981                 /* discard 0 byte frames, this seems to occur sometime
4982                  * when remote is idling flags.
4983                  */
4984                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4985                 goto CheckAgain;
4986         }
4987
4988         if (framesize < 2)
4989                 status |= BIT6;
4990
4991         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4992                 /* received frame has errors,
4993                  * update counts and mark frame size as 0
4994                  */
4995                 if (status & BIT6)
4996                         info->icount.rxshort++;
4997                 else if (status & BIT5)
4998                         info->icount.rxabort++;
4999                 else if (status & BIT3)
5000                         info->icount.rxover++;
5001                 else
5002                         info->icount.rxcrc++;
5003
5004                 framesize = 0;
5005 #ifdef CONFIG_HDLC
5006                 {
5007                         struct net_device_stats *stats = hdlc_stats(info->netdev);
5008                         stats->rx_errors++;
5009                         stats->rx_frame_errors++;
5010                 }
5011 #endif
5012         }
5013
5014         if ( debug_level >= DEBUG_LEVEL_BH )
5015                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
5016                         __FILE__,__LINE__,info->device_name,status,framesize);
5017
5018         if ( debug_level >= DEBUG_LEVEL_DATA )
5019                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
5020                         min_t(int, framesize,SCABUFSIZE),0);
5021
5022         if (framesize) {
5023                 if (framesize > info->max_frame_size)
5024                         info->icount.rxlong++;
5025                 else {
5026                         /* copy dma buffer(s) to contiguous intermediate buffer */
5027                         int copy_count = framesize;
5028                         int index = StartIndex;
5029                         unsigned char *ptmp = info->tmp_rx_buf;
5030                         info->tmp_rx_buf_count = framesize;
5031
5032                         info->icount.rxok++;
5033
5034                         while(copy_count) {
5035                                 int partial_count = min(copy_count,SCABUFSIZE);
5036                                 memcpy( ptmp,
5037                                         info->rx_buf_list_ex[index].virt_addr,
5038                                         partial_count );
5039                                 ptmp += partial_count;
5040                                 copy_count -= partial_count;
5041
5042                                 if ( ++index == info->rx_buf_count )
5043                                         index = 0;
5044                         }
5045
5046 #ifdef CONFIG_HDLC
5047                         if (info->netcount)
5048                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5049                         else
5050 #endif
5051                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5052                                                   info->flag_buf, framesize);
5053                 }
5054         }
5055         /* Free the buffers used by this frame. */
5056         rx_free_frame_buffers( info, StartIndex, EndIndex );
5057
5058         ReturnCode = 1;
5059
5060 Cleanup:
5061         if ( info->rx_enabled && info->rx_overflow ) {
5062                 /* Receiver is enabled, but needs to restarted due to
5063                  * rx buffer overflow. If buffers are empty, restart receiver.
5064                  */
5065                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5066                         spin_lock_irqsave(&info->lock,flags);
5067                         rx_start(info);
5068                         spin_unlock_irqrestore(&info->lock,flags);
5069                 }
5070         }
5071
5072         return ReturnCode;
5073 }
5074
5075 /* load the transmit DMA buffer with data
5076  */
5077 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5078 {
5079         unsigned short copy_count;
5080         unsigned int i = 0;
5081         SCADESC *desc;
5082         SCADESC_EX *desc_ex;
5083
5084         if ( debug_level >= DEBUG_LEVEL_DATA )
5085                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5086
5087         /* Copy source buffer to one or more DMA buffers, starting with
5088          * the first transmit dma buffer.
5089          */
5090         for(i=0;;)
5091         {
5092                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5093
5094                 desc = &info->tx_buf_list[i];
5095                 desc_ex = &info->tx_buf_list_ex[i];
5096
5097                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5098
5099                 desc->length = copy_count;
5100                 desc->status = 0;
5101
5102                 buf += copy_count;
5103                 count -= copy_count;
5104
5105                 if (!count)
5106                         break;
5107
5108                 i++;
5109                 if (i >= info->tx_buf_count)
5110                         i = 0;
5111         }
5112
5113         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5114         info->last_tx_buf = ++i;
5115 }
5116
5117 int register_test(SLMP_INFO *info)
5118 {
5119         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5120         static unsigned int count = sizeof(testval)/sizeof(unsigned char);
5121         unsigned int i;
5122         int rc = TRUE;
5123         unsigned long flags;
5124
5125         spin_lock_irqsave(&info->lock,flags);
5126         reset_port(info);
5127
5128         /* assume failure */
5129         info->init_error = DiagStatus_AddressFailure;
5130
5131         /* Write bit patterns to various registers but do it out of */
5132         /* sync, then read back and verify values. */
5133
5134         for (i = 0 ; i < count ; i++) {
5135                 write_reg(info, TMC, testval[i]);
5136                 write_reg(info, IDL, testval[(i+1)%count]);
5137                 write_reg(info, SA0, testval[(i+2)%count]);
5138                 write_reg(info, SA1, testval[(i+3)%count]);
5139
5140                 if ( (read_reg(info, TMC) != testval[i]) ||
5141                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5142                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5143                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5144                 {
5145                         rc = FALSE;
5146                         break;
5147                 }
5148         }
5149
5150         reset_port(info);
5151         spin_unlock_irqrestore(&info->lock,flags);
5152
5153         return rc;
5154 }
5155
5156 int irq_test(SLMP_INFO *info)
5157 {
5158         unsigned long timeout;
5159         unsigned long flags;
5160
5161         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5162
5163         spin_lock_irqsave(&info->lock,flags);
5164         reset_port(info);
5165
5166         /* assume failure */
5167         info->init_error = DiagStatus_IrqFailure;
5168         info->irq_occurred = FALSE;
5169
5170         /* setup timer0 on SCA0 to interrupt */
5171
5172         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5173         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5174
5175         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5176         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5177
5178
5179         /* TMCS, Timer Control/Status Register
5180          *
5181          * 07      CMF, Compare match flag (read only) 1=match
5182          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5183          * 05      Reserved, must be 0
5184          * 04      TME, Timer Enable
5185          * 03..00  Reserved, must be 0
5186          *
5187          * 0101 0000
5188          */
5189         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5190
5191         spin_unlock_irqrestore(&info->lock,flags);
5192
5193         timeout=100;
5194         while( timeout-- && !info->irq_occurred ) {
5195                 msleep_interruptible(10);
5196         }
5197
5198         spin_lock_irqsave(&info->lock,flags);
5199         reset_port(info);
5200         spin_unlock_irqrestore(&info->lock,flags);
5201
5202         return info->irq_occurred;
5203 }
5204
5205 /* initialize individual SCA device (2 ports)
5206  */
5207 static int sca_init(SLMP_INFO *info)
5208 {
5209         /* set wait controller to single mem partition (low), no wait states */
5210         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5211         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5212         write_reg(info, WCRL, 0);       /* wait controller low range */
5213         write_reg(info, WCRM, 0);       /* wait controller mid range */
5214         write_reg(info, WCRH, 0);       /* wait controller high range */
5215
5216         /* DPCR, DMA Priority Control
5217          *
5218          * 07..05  Not used, must be 0
5219          * 04      BRC, bus release condition: 0=all transfers complete
5220          * 03      CCC, channel change condition: 0=every cycle
5221          * 02..00  PR<2..0>, priority 100=round robin
5222          *
5223          * 00000100 = 0x04
5224          */
5225         write_reg(info, DPCR, dma_priority);
5226
5227         /* DMA Master Enable, BIT7: 1=enable all channels */
5228         write_reg(info, DMER, 0x80);
5229
5230         /* enable all interrupt classes */
5231         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5232         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5233         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5234
5235         /* ITCR, interrupt control register
5236          * 07      IPC, interrupt priority, 0=MSCI->DMA
5237          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5238          * 04      VOS, Vector Output, 0=unmodified vector
5239          * 03..00  Reserved, must be 0
5240          */
5241         write_reg(info, ITCR, 0);
5242
5243         return TRUE;
5244 }
5245
5246 /* initialize adapter hardware
5247  */
5248 int init_adapter(SLMP_INFO *info)
5249 {
5250         int i;
5251
5252         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5253         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5254         u32 readval;
5255
5256         info->misc_ctrl_value |= BIT30;
5257         *MiscCtrl = info->misc_ctrl_value;
5258
5259         /*
5260          * Force at least 170ns delay before clearing
5261          * reset bit. Each read from LCR takes at least
5262          * 30ns so 10 times for 300ns to be safe.
5263          */
5264         for(i=0;i<10;i++)
5265                 readval = *MiscCtrl;
5266
5267         info->misc_ctrl_value &= ~BIT30;
5268         *MiscCtrl = info->misc_ctrl_value;
5269
5270         /* init control reg (all DTRs off, all clksel=input) */
5271         info->ctrlreg_value = 0xaa;
5272         write_control_reg(info);
5273
5274         {
5275                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5276                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5277
5278                 switch(read_ahead_count)
5279                 {
5280                 case 16:
5281                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5282                         break;
5283                 case 8:
5284                         lcr1_brdr_value |= BIT5 + BIT4;
5285                         break;
5286                 case 4:
5287                         lcr1_brdr_value |= BIT5 + BIT3;
5288                         break;
5289                 case 0:
5290                         lcr1_brdr_value |= BIT5;
5291                         break;
5292                 }
5293
5294                 *LCR1BRDR = lcr1_brdr_value;
5295                 *MiscCtrl = misc_ctrl_value;
5296         }
5297
5298         sca_init(info->port_array[0]);
5299         sca_init(info->port_array[2]);
5300
5301         return TRUE;
5302 }
5303
5304 /* Loopback an HDLC frame to test the hardware
5305  * interrupt and DMA functions.
5306  */
5307 int loopback_test(SLMP_INFO *info)
5308 {
5309 #define TESTFRAMESIZE 20
5310
5311         unsigned long timeout;
5312         u16 count = TESTFRAMESIZE;
5313         unsigned char buf[TESTFRAMESIZE];
5314         int rc = FALSE;
5315         unsigned long flags;
5316
5317         struct tty_struct *oldtty = info->tty;
5318         u32 speed = info->params.clock_speed;
5319
5320         info->params.clock_speed = 3686400;
5321         info->tty = NULL;
5322
5323         /* assume failure */
5324         info->init_error = DiagStatus_DmaFailure;
5325
5326         /* build and send transmit frame */
5327         for (count = 0; count < TESTFRAMESIZE;++count)
5328                 buf[count] = (unsigned char)count;
5329
5330         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5331
5332         /* program hardware for HDLC and enabled receiver */
5333         spin_lock_irqsave(&info->lock,flags);
5334         hdlc_mode(info);
5335         enable_loopback(info,1);
5336         rx_start(info);
5337         info->tx_count = count;
5338         tx_load_dma_buffer(info,buf,count);
5339         tx_start(info);
5340         spin_unlock_irqrestore(&info->lock,flags);
5341
5342         /* wait for receive complete */
5343         /* Set a timeout for waiting for interrupt. */
5344         for ( timeout = 100; timeout; --timeout ) {
5345                 msleep_interruptible(10);
5346
5347                 if (rx_get_frame(info)) {
5348                         rc = TRUE;
5349                         break;
5350                 }
5351         }
5352
5353         /* verify received frame length and contents */
5354         if (rc == TRUE &&
5355                 ( info->tmp_rx_buf_count != count ||
5356                   memcmp(buf, info->tmp_rx_buf,count))) {
5357                 rc = FALSE;
5358         }
5359
5360         spin_lock_irqsave(&info->lock,flags);
5361         reset_adapter(info);
5362         spin_unlock_irqrestore(&info->lock,flags);
5363
5364         info->params.clock_speed = speed;
5365         info->tty = oldtty;
5366
5367         return rc;
5368 }
5369
5370 /* Perform diagnostics on hardware
5371  */
5372 int adapter_test( SLMP_INFO *info )
5373 {
5374         unsigned long flags;
5375         if ( debug_level >= DEBUG_LEVEL_INFO )
5376                 printk( "%s(%d):Testing device %s\n",
5377                         __FILE__,__LINE__,info->device_name );
5378
5379         spin_lock_irqsave(&info->lock,flags);
5380         init_adapter(info);
5381         spin_unlock_irqrestore(&info->lock,flags);
5382
5383         info->port_array[0]->port_count = 0;
5384
5385         if ( register_test(info->port_array[0]) &&
5386                 register_test(info->port_array[1])) {
5387
5388                 info->port_array[0]->port_count = 2;
5389
5390                 if ( register_test(info->port_array[2]) &&
5391                         register_test(info->port_array[3]) )
5392                         info->port_array[0]->port_count += 2;
5393         }
5394         else {
5395                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5396                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5397                 return -ENODEV;
5398         }
5399
5400         if ( !irq_test(info->port_array[0]) ||
5401                 !irq_test(info->port_array[1]) ||
5402                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5403                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5404                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5405                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5406                 return -ENODEV;
5407         }
5408
5409         if (!loopback_test(info->port_array[0]) ||
5410                 !loopback_test(info->port_array[1]) ||
5411                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5412                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5413                 printk( "%s(%d):DMA test failure for device %s\n",
5414                         __FILE__,__LINE__,info->device_name);
5415                 return -ENODEV;
5416         }
5417
5418         if ( debug_level >= DEBUG_LEVEL_INFO )
5419                 printk( "%s(%d):device %s passed diagnostics\n",
5420                         __FILE__,__LINE__,info->device_name );
5421
5422         info->port_array[0]->init_error = 0;
5423         info->port_array[1]->init_error = 0;
5424         if ( info->port_count > 2 ) {
5425                 info->port_array[2]->init_error = 0;
5426                 info->port_array[3]->init_error = 0;
5427         }
5428
5429         return 0;
5430 }
5431
5432 /* Test the shared memory on a PCI adapter.
5433  */
5434 int memory_test(SLMP_INFO *info)
5435 {
5436         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5437                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5438         unsigned long count = sizeof(testval)/sizeof(unsigned long);
5439         unsigned long i;
5440         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5441         unsigned long * addr = (unsigned long *)info->memory_base;
5442
5443         /* Test data lines with test pattern at one location. */
5444
5445         for ( i = 0 ; i < count ; i++ ) {
5446                 *addr = testval[i];
5447                 if ( *addr != testval[i] )
5448                         return FALSE;
5449         }
5450
5451         /* Test address lines with incrementing pattern over */
5452         /* entire address range. */
5453
5454         for ( i = 0 ; i < limit ; i++ ) {
5455                 *addr = i * 4;
5456                 addr++;
5457         }
5458
5459         addr = (unsigned long *)info->memory_base;
5460
5461         for ( i = 0 ; i < limit ; i++ ) {
5462                 if ( *addr != i * 4 )
5463                         return FALSE;
5464                 addr++;
5465         }
5466
5467         memset( info->memory_base, 0, SCA_MEM_SIZE );
5468         return TRUE;
5469 }
5470
5471 /* Load data into PCI adapter shared memory.
5472  *
5473  * The PCI9050 releases control of the local bus
5474  * after completing the current read or write operation.
5475  *
5476  * While the PCI9050 write FIFO not empty, the
5477  * PCI9050 treats all of the writes as a single transaction
5478  * and does not release the bus. This causes DMA latency problems
5479  * at high speeds when copying large data blocks to the shared memory.
5480  *
5481  * This function breaks a write into multiple transations by
5482  * interleaving a read which flushes the write FIFO and 'completes'
5483  * the write transation. This allows any pending DMA request to gain control
5484  * of the local bus in a timely fasion.
5485  */
5486 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5487 {
5488         /* A load interval of 16 allows for 4 32-bit writes at */
5489         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5490
5491         unsigned short interval = count / sca_pci_load_interval;
5492         unsigned short i;
5493
5494         for ( i = 0 ; i < interval ; i++ )
5495         {
5496                 memcpy(dest, src, sca_pci_load_interval);
5497                 read_status_reg(info);
5498                 dest += sca_pci_load_interval;
5499                 src += sca_pci_load_interval;
5500         }
5501
5502         memcpy(dest, src, count % sca_pci_load_interval);
5503 }
5504
5505 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5506 {
5507         int i;
5508         int linecount;
5509         if (xmit)
5510                 printk("%s tx data:\n",info->device_name);
5511         else
5512                 printk("%s rx data:\n",info->device_name);
5513
5514         while(count) {
5515                 if (count > 16)
5516                         linecount = 16;
5517                 else
5518                         linecount = count;
5519
5520                 for(i=0;i<linecount;i++)
5521                         printk("%02X ",(unsigned char)data[i]);
5522                 for(;i<17;i++)
5523                         printk("   ");
5524                 for(i=0;i<linecount;i++) {
5525                         if (data[i]>=040 && data[i]<=0176)
5526                                 printk("%c",data[i]);
5527                         else
5528                                 printk(".");
5529                 }
5530                 printk("\n");
5531
5532                 data  += linecount;
5533                 count -= linecount;
5534         }
5535 }       /* end of trace_block() */
5536
5537 /* called when HDLC frame times out
5538  * update stats and do tx completion processing
5539  */
5540 void tx_timeout(unsigned long context)
5541 {
5542         SLMP_INFO *info = (SLMP_INFO*)context;
5543         unsigned long flags;
5544
5545         if ( debug_level >= DEBUG_LEVEL_INFO )
5546                 printk( "%s(%d):%s tx_timeout()\n",
5547                         __FILE__,__LINE__,info->device_name);
5548         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5549                 info->icount.txtimeout++;
5550         }
5551         spin_lock_irqsave(&info->lock,flags);
5552         info->tx_active = 0;
5553         info->tx_count = info->tx_put = info->tx_get = 0;
5554
5555         spin_unlock_irqrestore(&info->lock,flags);
5556
5557 #ifdef CONFIG_HDLC
5558         if (info->netcount)
5559                 hdlcdev_tx_done(info);
5560         else
5561 #endif
5562                 bh_transmit(info);
5563 }
5564
5565 /* called to periodically check the DSR/RI modem signal input status
5566  */
5567 void status_timeout(unsigned long context)
5568 {
5569         u16 status = 0;
5570         SLMP_INFO *info = (SLMP_INFO*)context;
5571         unsigned long flags;
5572         unsigned char delta;
5573
5574
5575         spin_lock_irqsave(&info->lock,flags);
5576         get_signals(info);
5577         spin_unlock_irqrestore(&info->lock,flags);
5578
5579         /* check for DSR/RI state change */
5580
5581         delta = info->old_signals ^ info->serial_signals;
5582         info->old_signals = info->serial_signals;
5583
5584         if (delta & SerialSignal_DSR)
5585                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5586
5587         if (delta & SerialSignal_RI)
5588                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5589
5590         if (delta & SerialSignal_DCD)
5591                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5592
5593         if (delta & SerialSignal_CTS)
5594                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5595
5596         if (status)
5597                 isr_io_pin(info,status);
5598
5599         info->status_timer.data = (unsigned long)info;
5600         info->status_timer.function = status_timeout;
5601         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5602         add_timer(&info->status_timer);
5603 }
5604
5605
5606 /* Register Access Routines -
5607  * All registers are memory mapped
5608  */
5609 #define CALC_REGADDR() \
5610         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5611         if (info->port_num > 1) \
5612                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5613         if ( info->port_num & 1) { \
5614                 if (Addr > 0x7f) \
5615                         RegAddr += 0x40;        /* DMA access */ \
5616                 else if (Addr > 0x1f && Addr < 0x60) \
5617                         RegAddr += 0x20;        /* MSCI access */ \
5618         }
5619
5620
5621 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5622 {
5623         CALC_REGADDR();
5624         return *RegAddr;
5625 }
5626 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5627 {
5628         CALC_REGADDR();
5629         *RegAddr = Value;
5630 }
5631
5632 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5633 {
5634         CALC_REGADDR();
5635         return *((u16 *)RegAddr);
5636 }
5637
5638 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5639 {
5640         CALC_REGADDR();
5641         *((u16 *)RegAddr) = Value;
5642 }
5643
5644 unsigned char read_status_reg(SLMP_INFO * info)
5645 {
5646         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5647         return *RegAddr;
5648 }
5649
5650 void write_control_reg(SLMP_INFO * info)
5651 {
5652         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5653         *RegAddr = info->port_array[0]->ctrlreg_value;
5654 }
5655
5656
5657 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5658                                           const struct pci_device_id *ent)
5659 {
5660         if (pci_enable_device(dev)) {
5661                 printk("error enabling pci device %p\n", dev);
5662                 return -EIO;
5663         }
5664         device_init( ++synclinkmp_adapter_count, dev );
5665         return 0;
5666 }
5667
5668 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5669 {
5670 }