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   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76 #include <linux/synclink.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  86 #define SYNCLINK_GENERIC_HDLC 1
  87 #else
  88 #define SYNCLINK_GENERIC_HDLC 0
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.50 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 32
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {0,}, /* terminate list */
 108 };
 109 MODULE_DEVICE_TABLE(pci, pci_table);
 110
 111 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 112 static void remove_one(struct pci_dev *dev);
 113 static struct pci_driver pci_driver = {
 114         .name           = "synclink_gt",
 115         .id_table       = pci_table,
 116         .probe          = init_one,
 117         .remove         = __devexit_p(remove_one),
 118 };
 119
 120 static bool pci_registered;
 121
 122 /*
 123  * module configuration and status
 124  */
 125 static struct slgt_info *slgt_device_list;
 126 static int slgt_device_count;
 127
 128 static int ttymajor;
 129 static int debug_level;
 130 static int maxframe[MAX_DEVICES];
 131
 132 module_param(ttymajor, int, 0);
 133 module_param(debug_level, int, 0);
 134 module_param_array(maxframe, int, NULL, 0);
 135
 136 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 137 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 138 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 139
 140 /*
 141  * tty support and callbacks
 142  */
 143 static struct tty_driver *serial_driver;
 144
 145 static int  open(struct tty_struct *tty, struct file * filp);
 146 static void close(struct tty_struct *tty, struct file * filp);
 147 static void hangup(struct tty_struct *tty);
 148 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 149
 150 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 151 static int put_char(struct tty_struct *tty, unsigned char ch);
 152 static void send_xchar(struct tty_struct *tty, char ch);
 153 static void wait_until_sent(struct tty_struct *tty, int timeout);
 154 static int  write_room(struct tty_struct *tty);
 155 static void flush_chars(struct tty_struct *tty);
 156 static void flush_buffer(struct tty_struct *tty);
 157 static void tx_hold(struct tty_struct *tty);
 158 static void tx_release(struct tty_struct *tty);
 159
 160 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 161 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 162 static int  chars_in_buffer(struct tty_struct *tty);
 163 static void throttle(struct tty_struct * tty);
 164 static void unthrottle(struct tty_struct * tty);
 165 static void set_break(struct tty_struct *tty, int break_state);
 166
 167 /*
 168  * generic HDLC support and callbacks
 169  */
 170 #if SYNCLINK_GENERIC_HDLC
 171 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 172 static void hdlcdev_tx_done(struct slgt_info *info);
 173 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 174 static int  hdlcdev_init(struct slgt_info *info);
 175 static void hdlcdev_exit(struct slgt_info *info);
 176 #endif
 177
 178
 179 /*
 180  * device specific structures, macros and functions
 181  */
 182
 183 #define SLGT_MAX_PORTS 4
 184 #define SLGT_REG_SIZE  256
 185
 186 /*
 187  * conditional wait facility
 188  */
 189 struct cond_wait {
 190         struct cond_wait *next;
 191         wait_queue_head_t q;
 192         wait_queue_t wait;
 193         unsigned int data;
 194 };
 195 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 196 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 197 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 198 static void flush_cond_wait(struct cond_wait **head);
 199
 200 /*
 201  * DMA buffer descriptor and access macros
 202  */
 203 struct slgt_desc
 204 {
 205         __le16 count;
 206         __le16 status;
 207         __le32 pbuf;  /* physical address of data buffer */
 208         __le32 next;  /* physical address of next descriptor */
 209
 210         /* driver book keeping */
 211         char *buf;          /* virtual  address of data buffer */
 212         unsigned int pdesc; /* physical address of this descriptor */
 213         dma_addr_t buf_dma_addr;
 214 };
 215
 216 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 217 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 218 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 219 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 220 #define desc_count(a)      (le16_to_cpu((a).count))
 221 #define desc_status(a)     (le16_to_cpu((a).status))
 222 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 223 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 224 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 225 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 226 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 227
 228 struct _input_signal_events {
 229         int ri_up;
 230         int ri_down;
 231         int dsr_up;
 232         int dsr_down;
 233         int dcd_up;
 234         int dcd_down;
 235         int cts_up;
 236         int cts_down;
 237 };
 238
 239 /*
 240  * device instance data structure
 241  */
 242 struct slgt_info {
 243         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 244         struct tty_port port;
 245
 246         struct slgt_info *next_device;  /* device list link */
 247
 248         int magic;
 249
 250         char device_name[25];
 251         struct pci_dev *pdev;
 252
 253         int port_count;  /* count of ports on adapter */
 254         int adapter_num; /* adapter instance number */
 255         int port_num;    /* port instance number */
 256
 257         /* array of pointers to port contexts on this adapter */
 258         struct slgt_info *port_array[SLGT_MAX_PORTS];
 259
 260         int                     line;           /* tty line instance number */
 261
 262         struct mgsl_icount      icount;
 263
 264         int                     timeout;
 265         int                     x_char;         /* xon/xoff character */
 266         unsigned int            read_status_mask;
 267         unsigned int            ignore_status_mask;
 268
 269         wait_queue_head_t       status_event_wait_q;
 270         wait_queue_head_t       event_wait_q;
 271         struct timer_list       tx_timer;
 272         struct timer_list       rx_timer;
 273
 274         unsigned int            gpio_present;
 275         struct cond_wait        *gpio_wait_q;
 276
 277         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 278
 279         struct work_struct task;
 280         u32 pending_bh;
 281         bool bh_requested;
 282         bool bh_running;
 283
 284         int isr_overflow;
 285         bool irq_requested;     /* true if IRQ requested */
 286         bool irq_occurred;      /* for diagnostics use */
 287
 288         /* device configuration */
 289
 290         unsigned int bus_type;
 291         unsigned int irq_level;
 292         unsigned long irq_flags;
 293
 294         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 295         u32 phys_reg_addr;
 296         bool reg_addr_requested;
 297
 298         MGSL_PARAMS params;       /* communications parameters */
 299         u32 idle_mode;
 300         u32 max_frame_size;       /* as set by device config */
 301
 302         unsigned int raw_rx_size;
 303         unsigned int if_mode;
 304
 305         /* device status */
 306
 307         bool rx_enabled;
 308         bool rx_restart;
 309
 310         bool tx_enabled;
 311         bool tx_active;
 312
 313         unsigned char signals;    /* serial signal states */
 314         int init_error;  /* initialization error */
 315
 316         unsigned char *tx_buf;
 317         int tx_count;
 318
 319         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 320         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 321         bool drop_rts_on_tx_done;
 322         struct  _input_signal_events    input_signal_events;
 323
 324         int dcd_chkcount;       /* check counts to prevent */
 325         int cts_chkcount;       /* too many IRQs if a signal */
 326         int dsr_chkcount;       /* is floating */
 327         int ri_chkcount;
 328
 329         char *bufs;             /* virtual address of DMA buffer lists */
 330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332         unsigned int rbuf_count;
 333         struct slgt_desc *rbufs;
 334         unsigned int rbuf_current;
 335         unsigned int rbuf_index;
 336
 337         unsigned int tbuf_count;
 338         struct slgt_desc *tbufs;
 339         unsigned int tbuf_current;
 340         unsigned int tbuf_start;
 341
 342         unsigned char *tmp_rbuf;
 343         unsigned int tmp_rbuf_count;
 344
 345         /* SPPP/Cisco HDLC device parts */
 346
 347         int netcount;
 348         spinlock_t netlock;
 349 #if SYNCLINK_GENERIC_HDLC
 350         struct net_device *netdev;
 351 #endif
 352
 353 };
 354
 355 static MGSL_PARAMS default_params = {
 356         .mode            = MGSL_MODE_HDLC,
 357         .loopback        = 0,
 358         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 359         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 360         .clock_speed     = 0,
 361         .addr_filter     = 0xff,
 362         .crc_type        = HDLC_CRC_16_CCITT,
 363         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 364         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 365         .data_rate       = 9600,
 366         .data_bits       = 8,
 367         .stop_bits       = 1,
 368         .parity          = ASYNC_PARITY_NONE
 369 };
 370
 371
 372 #define BH_RECEIVE  1
 373 #define BH_TRANSMIT 2
 374 #define BH_STATUS   4
 375 #define IO_PIN_SHUTDOWN_LIMIT 100
 376
 377 #define DMABUFSIZE 256
 378 #define DESC_LIST_SIZE 4096
 379
 380 #define MASK_PARITY  BIT1
 381 #define MASK_FRAMING BIT0
 382 #define MASK_BREAK   BIT14
 383 #define MASK_OVERRUN BIT4
 384
 385 #define GSR   0x00 /* global status */
 386 #define JCR   0x04 /* JTAG control */
 387 #define IODR  0x08 /* GPIO direction */
 388 #define IOER  0x0c /* GPIO interrupt enable */
 389 #define IOVR  0x10 /* GPIO value */
 390 #define IOSR  0x14 /* GPIO interrupt status */
 391 #define TDR   0x80 /* tx data */
 392 #define RDR   0x80 /* rx data */
 393 #define TCR   0x82 /* tx control */
 394 #define TIR   0x84 /* tx idle */
 395 #define TPR   0x85 /* tx preamble */
 396 #define RCR   0x86 /* rx control */
 397 #define VCR   0x88 /* V.24 control */
 398 #define CCR   0x89 /* clock control */
 399 #define BDR   0x8a /* baud divisor */
 400 #define SCR   0x8c /* serial control */
 401 #define SSR   0x8e /* serial status */
 402 #define RDCSR 0x90 /* rx DMA control/status */
 403 #define TDCSR 0x94 /* tx DMA control/status */
 404 #define RDDAR 0x98 /* rx DMA descriptor address */
 405 #define TDDAR 0x9c /* tx DMA descriptor address */
 406
 407 #define RXIDLE      BIT14
 408 #define RXBREAK     BIT14
 409 #define IRQ_TXDATA  BIT13
 410 #define IRQ_TXIDLE  BIT12
 411 #define IRQ_TXUNDER BIT11 /* HDLC */
 412 #define IRQ_RXDATA  BIT10
 413 #define IRQ_RXIDLE  BIT9  /* HDLC */
 414 #define IRQ_RXBREAK BIT9  /* async */
 415 #define IRQ_RXOVER  BIT8
 416 #define IRQ_DSR     BIT7
 417 #define IRQ_CTS     BIT6
 418 #define IRQ_DCD     BIT5
 419 #define IRQ_RI      BIT4
 420 #define IRQ_ALL     0x3ff0
 421 #define IRQ_MASTER  BIT0
 422
 423 #define slgt_irq_on(info, mask) \
 424         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 425 #define slgt_irq_off(info, mask) \
 426         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 427
 428 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 429 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 430 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 431 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 432 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 434
 435 static void  msc_set_vcr(struct slgt_info *info);
 436
 437 static int  startup(struct slgt_info *info);
 438 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 439 static void shutdown(struct slgt_info *info);
 440 static void program_hw(struct slgt_info *info);
 441 static void change_params(struct slgt_info *info);
 442
 443 static int  register_test(struct slgt_info *info);
 444 static int  irq_test(struct slgt_info *info);
 445 static int  loopback_test(struct slgt_info *info);
 446 static int  adapter_test(struct slgt_info *info);
 447
 448 static void reset_adapter(struct slgt_info *info);
 449 static void reset_port(struct slgt_info *info);
 450 static void async_mode(struct slgt_info *info);
 451 static void sync_mode(struct slgt_info *info);
 452
 453 static void rx_stop(struct slgt_info *info);
 454 static void rx_start(struct slgt_info *info);
 455 static void reset_rbufs(struct slgt_info *info);
 456 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 457 static void rdma_reset(struct slgt_info *info);
 458 static bool rx_get_frame(struct slgt_info *info);
 459 static bool rx_get_buf(struct slgt_info *info);
 460
 461 static void tx_start(struct slgt_info *info);
 462 static void tx_stop(struct slgt_info *info);
 463 static void tx_set_idle(struct slgt_info *info);
 464 static unsigned int free_tbuf_count(struct slgt_info *info);
 465 static void reset_tbufs(struct slgt_info *info);
 466 static void tdma_reset(struct slgt_info *info);
 467 static void tdma_start(struct slgt_info *info);
 468 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 469
 470 static void get_signals(struct slgt_info *info);
 471 static void set_signals(struct slgt_info *info);
 472 static void enable_loopback(struct slgt_info *info);
 473 static void set_rate(struct slgt_info *info, u32 data_rate);
 474
 475 static int  bh_action(struct slgt_info *info);
 476 static void bh_handler(struct work_struct *work);
 477 static void bh_transmit(struct slgt_info *info);
 478 static void isr_serial(struct slgt_info *info);
 479 static void isr_rdma(struct slgt_info *info);
 480 static void isr_txeom(struct slgt_info *info, unsigned short status);
 481 static void isr_tdma(struct slgt_info *info);
 482
 483 static int  alloc_dma_bufs(struct slgt_info *info);
 484 static void free_dma_bufs(struct slgt_info *info);
 485 static int  alloc_desc(struct slgt_info *info);
 486 static void free_desc(struct slgt_info *info);
 487 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 488 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 489
 490 static int  alloc_tmp_rbuf(struct slgt_info *info);
 491 static void free_tmp_rbuf(struct slgt_info *info);
 492
 493 static void tx_timeout(unsigned long context);
 494 static void rx_timeout(unsigned long context);
 495
 496 /*
 497  * ioctl handlers
 498  */
 499 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 500 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 501 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 502 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 503 static int  set_txidle(struct slgt_info *info, int idle_mode);
 504 static int  tx_enable(struct slgt_info *info, int enable);
 505 static int  tx_abort(struct slgt_info *info);
 506 static int  rx_enable(struct slgt_info *info, int enable);
 507 static int  modem_input_wait(struct slgt_info *info,int arg);
 508 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 509 static int  tiocmget(struct tty_struct *tty, struct file *file);
 510 static int  tiocmset(struct tty_struct *tty, struct file *file,
 511                      unsigned int set, unsigned int clear);
 512 static void set_break(struct tty_struct *tty, int break_state);
 513 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 514 static int  set_interface(struct slgt_info *info, int if_mode);
 515 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 516 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 517 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 518
 519 /*
 520  * driver functions
 521  */
 522 static void add_device(struct slgt_info *info);
 523 static void device_init(int adapter_num, struct pci_dev *pdev);
 524 static int  claim_resources(struct slgt_info *info);
 525 static void release_resources(struct slgt_info *info);
 526
 527 /*
 528  * DEBUG OUTPUT CODE
 529  */
 530 #ifndef DBGINFO
 531 #define DBGINFO(fmt)
 532 #endif
 533 #ifndef DBGERR
 534 #define DBGERR(fmt)
 535 #endif
 536 #ifndef DBGBH
 537 #define DBGBH(fmt)
 538 #endif
 539 #ifndef DBGISR
 540 #define DBGISR(fmt)
 541 #endif
 542
 543 #ifdef DBGDATA
 544 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 545 {
 546         int i;
 547         int linecount;
 548         printk("%s %s data:\n",info->device_name, label);
 549         while(count) {
 550                 linecount = (count > 16) ? 16 : count;
 551                 for(i=0; i < linecount; i++)
 552                         printk("%02X ",(unsigned char)data[i]);
 553                 for(;i<17;i++)
 554                         printk("   ");
 555                 for(i=0;i<linecount;i++) {
 556                         if (data[i]>=040 && data[i]<=0176)
 557                                 printk("%c",data[i]);
 558                         else
 559                                 printk(".");
 560                 }
 561                 printk("\n");
 562                 data  += linecount;
 563                 count -= linecount;
 564         }
 565 }
 566 #else
 567 #define DBGDATA(info, buf, size, label)
 568 #endif
 569
 570 #ifdef DBGTBUF
 571 static void dump_tbufs(struct slgt_info *info)
 572 {
 573         int i;
 574         printk("tbuf_current=%d\n", info->tbuf_current);
 575         for (i=0 ; i < info->tbuf_count ; i++) {
 576                 printk("%d: count=%04X status=%04X\n",
 577                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 578         }
 579 }
 580 #else
 581 #define DBGTBUF(info)
 582 #endif
 583
 584 #ifdef DBGRBUF
 585 static void dump_rbufs(struct slgt_info *info)
 586 {
 587         int i;
 588         printk("rbuf_current=%d\n", info->rbuf_current);
 589         for (i=0 ; i < info->rbuf_count ; i++) {
 590                 printk("%d: count=%04X status=%04X\n",
 591                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 592         }
 593 }
 594 #else
 595 #define DBGRBUF(info)
 596 #endif
 597
 598 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 599 {
 600 #ifdef SANITY_CHECK
 601         if (!info) {
 602                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 603                 return 1;
 604         }
 605         if (info->magic != MGSL_MAGIC) {
 606                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 607                 return 1;
 608         }
 609 #else
 610         if (!info)
 611                 return 1;
 612 #endif
 613         return 0;
 614 }
 615
 616 /**
 617  * line discipline callback wrappers
 618  *
 619  * The wrappers maintain line discipline references
 620  * while calling into the line discipline.
 621  *
 622  * ldisc_receive_buf  - pass receive data to line discipline
 623  */
 624 static void ldisc_receive_buf(struct tty_struct *tty,
 625                               const __u8 *data, char *flags, int count)
 626 {
 627         struct tty_ldisc *ld;
 628         if (!tty)
 629                 return;
 630         ld = tty_ldisc_ref(tty);
 631         if (ld) {
 632                 if (ld->ops->receive_buf)
 633                         ld->ops->receive_buf(tty, data, flags, count);
 634                 tty_ldisc_deref(ld);
 635         }
 636 }
 637
 638 /* tty callbacks */
 639
 640 static int open(struct tty_struct *tty, struct file *filp)
 641 {
 642         struct slgt_info *info;
 643         int retval, line;
 644         unsigned long flags;
 645
 646         line = tty->index;
 647         if ((line < 0) || (line >= slgt_device_count)) {
 648                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 649                 return -ENODEV;
 650         }
 651
 652         info = slgt_device_list;
 653         while(info && info->line != line)
 654                 info = info->next_device;
 655         if (sanity_check(info, tty->name, "open"))
 656                 return -ENODEV;
 657         if (info->init_error) {
 658                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 659                 return -ENODEV;
 660         }
 661
 662         tty->driver_data = info;
 663         info->port.tty = tty;
 664
 665         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 666
 667         /* If port is closing, signal caller to try again */
 668         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 669                 if (info->port.flags & ASYNC_CLOSING)
 670                         interruptible_sleep_on(&info->port.close_wait);
 671                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 672                         -EAGAIN : -ERESTARTSYS);
 673                 goto cleanup;
 674         }
 675
 676         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 677
 678         spin_lock_irqsave(&info->netlock, flags);
 679         if (info->netcount) {
 680                 retval = -EBUSY;
 681                 spin_unlock_irqrestore(&info->netlock, flags);
 682                 goto cleanup;
 683         }
 684         info->port.count++;
 685         spin_unlock_irqrestore(&info->netlock, flags);
 686
 687         if (info->port.count == 1) {
 688                 /* 1st open on this device, init hardware */
 689                 retval = startup(info);
 690                 if (retval < 0)
 691                         goto cleanup;
 692         }
 693
 694         retval = block_til_ready(tty, filp, info);
 695         if (retval) {
 696                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 697                 goto cleanup;
 698         }
 699
 700         retval = 0;
 701
 702 cleanup:
 703         if (retval) {
 704                 if (tty->count == 1)
 705                         info->port.tty = NULL; /* tty layer will release tty struct */
 706                 if(info->port.count)
 707                         info->port.count--;
 708         }
 709
 710         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 711         return retval;
 712 }
 713
 714 static void close(struct tty_struct *tty, struct file *filp)
 715 {
 716         struct slgt_info *info = tty->driver_data;
 717
 718         if (sanity_check(info, tty->name, "close"))
 719                 return;
 720         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 721
 722         if (!info->port.count)
 723                 return;
 724
 725         if (tty_hung_up_p(filp))
 726                 goto cleanup;
 727
 728         if ((tty->count == 1) && (info->port.count != 1)) {
 729                 /*
 730                  * tty->count is 1 and the tty structure will be freed.
 731                  * info->port.count should be one in this case.
 732                  * if it's not, correct it so that the port is shutdown.
 733                  */
 734                 DBGERR(("%s close: bad refcount; tty->count=1, "
 735                        "info->port.count=%d\n", info->device_name, info->port.count));
 736                 info->port.count = 1;
 737         }
 738
 739         info->port.count--;
 740
 741         /* if at least one open remaining, leave hardware active */
 742         if (info->port.count)
 743                 goto cleanup;
 744
 745         info->port.flags |= ASYNC_CLOSING;
 746
 747         /* set tty->closing to notify line discipline to
 748          * only process XON/XOFF characters. Only the N_TTY
 749          * discipline appears to use this (ppp does not).
 750          */
 751         tty->closing = 1;
 752
 753         /* wait for transmit data to clear all layers */
 754
 755         if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 756                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 757                 tty_wait_until_sent(tty, info->port.closing_wait);
 758         }
 759
 760         if (info->port.flags & ASYNC_INITIALIZED)
 761                 wait_until_sent(tty, info->timeout);
 762         flush_buffer(tty);
 763         tty_ldisc_flush(tty);
 764
 765         shutdown(info);
 766
 767         tty->closing = 0;
 768         info->port.tty = NULL;
 769
 770         if (info->port.blocked_open) {
 771                 if (info->port.close_delay) {
 772                         msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
 773                 }
 774                 wake_up_interruptible(&info->port.open_wait);
 775         }
 776
 777         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 778
 779         wake_up_interruptible(&info->port.close_wait);
 780
 781 cleanup:
 782         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 783 }
 784
 785 static void hangup(struct tty_struct *tty)
 786 {
 787         struct slgt_info *info = tty->driver_data;
 788
 789         if (sanity_check(info, tty->name, "hangup"))
 790                 return;
 791         DBGINFO(("%s hangup\n", info->device_name));
 792
 793         flush_buffer(tty);
 794         shutdown(info);
 795
 796         info->port.count = 0;
 797         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 798         info->port.tty = NULL;
 799
 800         wake_up_interruptible(&info->port.open_wait);
 801 }
 802
 803 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 804 {
 805         struct slgt_info *info = tty->driver_data;
 806         unsigned long flags;
 807
 808         DBGINFO(("%s set_termios\n", tty->driver->name));
 809
 810         change_params(info);
 811
 812         /* Handle transition to B0 status */
 813         if (old_termios->c_cflag & CBAUD &&
 814             !(tty->termios->c_cflag & CBAUD)) {
 815                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 816                 spin_lock_irqsave(&info->lock,flags);
 817                 set_signals(info);
 818                 spin_unlock_irqrestore(&info->lock,flags);
 819         }
 820
 821         /* Handle transition away from B0 status */
 822         if (!(old_termios->c_cflag & CBAUD) &&
 823             tty->termios->c_cflag & CBAUD) {
 824                 info->signals |= SerialSignal_DTR;
 825                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 826                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 827                         info->signals |= SerialSignal_RTS;
 828                 }
 829                 spin_lock_irqsave(&info->lock,flags);
 830                 set_signals(info);
 831                 spin_unlock_irqrestore(&info->lock,flags);
 832         }
 833
 834         /* Handle turning off CRTSCTS */
 835         if (old_termios->c_cflag & CRTSCTS &&
 836             !(tty->termios->c_cflag & CRTSCTS)) {
 837                 tty->hw_stopped = 0;
 838                 tx_release(tty);
 839         }
 840 }
 841
 842 static int write(struct tty_struct *tty,
 843                  const unsigned char *buf, int count)
 844 {
 845         int ret = 0;
 846         struct slgt_info *info = tty->driver_data;
 847         unsigned long flags;
 848
 849         if (sanity_check(info, tty->name, "write"))
 850                 goto cleanup;
 851         DBGINFO(("%s write count=%d\n", info->device_name, count));
 852
 853         if (!info->tx_buf)
 854                 goto cleanup;
 855
 856         if (count > info->max_frame_size) {
 857                 ret = -EIO;
 858                 goto cleanup;
 859         }
 860
 861         if (!count)
 862                 goto cleanup;
 863
 864         if (info->params.mode == MGSL_MODE_RAW ||
 865             info->params.mode == MGSL_MODE_MONOSYNC ||
 866             info->params.mode == MGSL_MODE_BISYNC) {
 867                 unsigned int bufs_needed = (count/DMABUFSIZE);
 868                 unsigned int bufs_free = free_tbuf_count(info);
 869                 if (count % DMABUFSIZE)
 870                         ++bufs_needed;
 871                 if (bufs_needed > bufs_free)
 872                         goto cleanup;
 873         } else {
 874                 if (info->tx_active)
 875                         goto cleanup;
 876                 if (info->tx_count) {
 877                         /* send accumulated data from send_char() calls */
 878                         /* as frame and wait before accepting more data. */
 879                         tx_load(info, info->tx_buf, info->tx_count);
 880                         goto start;
 881                 }
 882         }
 883
 884         ret = info->tx_count = count;
 885         tx_load(info, buf, count);
 886         goto start;
 887
 888 start:
 889         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 890                 spin_lock_irqsave(&info->lock,flags);
 891                 if (!info->tx_active)
 892                         tx_start(info);
 893                 else
 894                         tdma_start(info);
 895                 spin_unlock_irqrestore(&info->lock,flags);
 896         }
 897
 898 cleanup:
 899         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 900         return ret;
 901 }
 902
 903 static int put_char(struct tty_struct *tty, unsigned char ch)
 904 {
 905         struct slgt_info *info = tty->driver_data;
 906         unsigned long flags;
 907         int ret = 0;
 908
 909         if (sanity_check(info, tty->name, "put_char"))
 910                 return 0;
 911         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 912         if (!info->tx_buf)
 913                 return 0;
 914         spin_lock_irqsave(&info->lock,flags);
 915         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 916                 info->tx_buf[info->tx_count++] = ch;
 917                 ret = 1;
 918         }
 919         spin_unlock_irqrestore(&info->lock,flags);
 920         return ret;
 921 }
 922
 923 static void send_xchar(struct tty_struct *tty, char ch)
 924 {
 925         struct slgt_info *info = tty->driver_data;
 926         unsigned long flags;
 927
 928         if (sanity_check(info, tty->name, "send_xchar"))
 929                 return;
 930         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 931         info->x_char = ch;
 932         if (ch) {
 933                 spin_lock_irqsave(&info->lock,flags);
 934                 if (!info->tx_enabled)
 935                         tx_start(info);
 936                 spin_unlock_irqrestore(&info->lock,flags);
 937         }
 938 }
 939
 940 static void wait_until_sent(struct tty_struct *tty, int timeout)
 941 {
 942         struct slgt_info *info = tty->driver_data;
 943         unsigned long orig_jiffies, char_time;
 944
 945         if (!info )
 946                 return;
 947         if (sanity_check(info, tty->name, "wait_until_sent"))
 948                 return;
 949         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 950         if (!(info->port.flags & ASYNC_INITIALIZED))
 951                 goto exit;
 952
 953         orig_jiffies = jiffies;
 954
 955         /* Set check interval to 1/5 of estimated time to
 956          * send a character, and make it at least 1. The check
 957          * interval should also be less than the timeout.
 958          * Note: use tight timings here to satisfy the NIST-PCTS.
 959          */
 960
 961         lock_kernel();
 962
 963         if (info->params.data_rate) {
 964                 char_time = info->timeout/(32 * 5);
 965                 if (!char_time)
 966                         char_time++;
 967         } else
 968                 char_time = 1;
 969
 970         if (timeout)
 971                 char_time = min_t(unsigned long, char_time, timeout);
 972
 973         while (info->tx_active) {
 974                 msleep_interruptible(jiffies_to_msecs(char_time));
 975                 if (signal_pending(current))
 976                         break;
 977                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 978                         break;
 979         }
 980         unlock_kernel();
 981
 982 exit:
 983         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 984 }
 985
 986 static int write_room(struct tty_struct *tty)
 987 {
 988         struct slgt_info *info = tty->driver_data;
 989         int ret;
 990
 991         if (sanity_check(info, tty->name, "write_room"))
 992                 return 0;
 993         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 994         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 995         return ret;
 996 }
 997
 998 static void flush_chars(struct tty_struct *tty)
 999 {
1000         struct slgt_info *info = tty->driver_data;
1001         unsigned long flags;
1002
1003         if (sanity_check(info, tty->name, "flush_chars"))
1004                 return;
1005         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1006
1007         if (info->tx_count <= 0 || tty->stopped ||
1008             tty->hw_stopped || !info->tx_buf)
1009                 return;
1010
1011         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1012
1013         spin_lock_irqsave(&info->lock,flags);
1014         if (!info->tx_active && info->tx_count) {
1015                 tx_load(info, info->tx_buf,info->tx_count);
1016                 tx_start(info);
1017         }
1018         spin_unlock_irqrestore(&info->lock,flags);
1019 }
1020
1021 static void flush_buffer(struct tty_struct *tty)
1022 {
1023         struct slgt_info *info = tty->driver_data;
1024         unsigned long flags;
1025
1026         if (sanity_check(info, tty->name, "flush_buffer"))
1027                 return;
1028         DBGINFO(("%s flush_buffer\n", info->device_name));
1029
1030         spin_lock_irqsave(&info->lock,flags);
1031         if (!info->tx_active)
1032                 info->tx_count = 0;
1033         spin_unlock_irqrestore(&info->lock,flags);
1034
1035         tty_wakeup(tty);
1036 }
1037
1038 /*
1039  * throttle (stop) transmitter
1040  */
1041 static void tx_hold(struct tty_struct *tty)
1042 {
1043         struct slgt_info *info = tty->driver_data;
1044         unsigned long flags;
1045
1046         if (sanity_check(info, tty->name, "tx_hold"))
1047                 return;
1048         DBGINFO(("%s tx_hold\n", info->device_name));
1049         spin_lock_irqsave(&info->lock,flags);
1050         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1051                 tx_stop(info);
1052         spin_unlock_irqrestore(&info->lock,flags);
1053 }
1054
1055 /*
1056  * release (start) transmitter
1057  */
1058 static void tx_release(struct tty_struct *tty)
1059 {
1060         struct slgt_info *info = tty->driver_data;
1061         unsigned long flags;
1062
1063         if (sanity_check(info, tty->name, "tx_release"))
1064                 return;
1065         DBGINFO(("%s tx_release\n", info->device_name));
1066         spin_lock_irqsave(&info->lock,flags);
1067         if (!info->tx_active && info->tx_count) {
1068                 tx_load(info, info->tx_buf, info->tx_count);
1069                 tx_start(info);
1070         }
1071         spin_unlock_irqrestore(&info->lock,flags);
1072 }
1073
1074 /*
1075  * Service an IOCTL request
1076  *
1077  * Arguments
1078  *
1079  *      tty     pointer to tty instance data
1080  *      file    pointer to associated file object for device
1081  *      cmd     IOCTL command code
1082  *      arg     command argument/context
1083  *
1084  * Return 0 if success, otherwise error code
1085  */
1086 static int ioctl(struct tty_struct *tty, struct file *file,
1087                  unsigned int cmd, unsigned long arg)
1088 {
1089         struct slgt_info *info = tty->driver_data;
1090         struct mgsl_icount cnow;        /* kernel counter temps */
1091         struct serial_icounter_struct __user *p_cuser;  /* user space */
1092         unsigned long flags;
1093         void __user *argp = (void __user *)arg;
1094         int ret;
1095
1096         if (sanity_check(info, tty->name, "ioctl"))
1097                 return -ENODEV;
1098         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1099
1100         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1101             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1102                 if (tty->flags & (1 << TTY_IO_ERROR))
1103                     return -EIO;
1104         }
1105
1106         lock_kernel();
1107
1108         switch (cmd) {
1109         case MGSL_IOCGPARAMS:
1110                 ret = get_params(info, argp);
1111                 break;
1112         case MGSL_IOCSPARAMS:
1113                 ret = set_params(info, argp);
1114                 break;
1115         case MGSL_IOCGTXIDLE:
1116                 ret = get_txidle(info, argp);
1117                 break;
1118         case MGSL_IOCSTXIDLE:
1119                 ret = set_txidle(info, (int)arg);
1120                 break;
1121         case MGSL_IOCTXENABLE:
1122                 ret = tx_enable(info, (int)arg);
1123                 break;
1124         case MGSL_IOCRXENABLE:
1125                 ret = rx_enable(info, (int)arg);
1126                 break;
1127         case MGSL_IOCTXABORT:
1128                 ret = tx_abort(info);
1129                 break;
1130         case MGSL_IOCGSTATS:
1131                 ret = get_stats(info, argp);
1132                 break;
1133         case MGSL_IOCWAITEVENT:
1134                 ret = wait_mgsl_event(info, argp);
1135                 break;
1136         case TIOCMIWAIT:
1137                 ret = modem_input_wait(info,(int)arg);
1138                 break;
1139         case MGSL_IOCGIF:
1140                 ret = get_interface(info, argp);
1141                 break;
1142         case MGSL_IOCSIF:
1143                 ret = set_interface(info,(int)arg);
1144                 break;
1145         case MGSL_IOCSGPIO:
1146                 ret = set_gpio(info, argp);
1147                 break;
1148         case MGSL_IOCGGPIO:
1149                 ret = get_gpio(info, argp);
1150                 break;
1151         case MGSL_IOCWAITGPIO:
1152                 ret = wait_gpio(info, argp);
1153                 break;
1154         case TIOCGICOUNT:
1155                 spin_lock_irqsave(&info->lock,flags);
1156                 cnow = info->icount;
1157                 spin_unlock_irqrestore(&info->lock,flags);
1158                 p_cuser = argp;
1159                 if (put_user(cnow.cts, &p_cuser->cts) ||
1160                     put_user(cnow.dsr, &p_cuser->dsr) ||
1161                     put_user(cnow.rng, &p_cuser->rng) ||
1162                     put_user(cnow.dcd, &p_cuser->dcd) ||
1163                     put_user(cnow.rx, &p_cuser->rx) ||
1164                     put_user(cnow.tx, &p_cuser->tx) ||
1165                     put_user(cnow.frame, &p_cuser->frame) ||
1166                     put_user(cnow.overrun, &p_cuser->overrun) ||
1167                     put_user(cnow.parity, &p_cuser->parity) ||
1168                     put_user(cnow.brk, &p_cuser->brk) ||
1169                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1170                         ret = -EFAULT;
1171                 ret = 0;
1172                 break;
1173         default:
1174                 ret = -ENOIOCTLCMD;
1175         }
1176         unlock_kernel();
1177         return ret;
1178 }
1179
1180 /*
1181  * support for 32 bit ioctl calls on 64 bit systems
1182  */
1183 #ifdef CONFIG_COMPAT
1184 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1185 {
1186         struct MGSL_PARAMS32 tmp_params;
1187
1188         DBGINFO(("%s get_params32\n", info->device_name));
1189         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1190         tmp_params.loopback        = info->params.loopback;
1191         tmp_params.flags           = info->params.flags;
1192         tmp_params.encoding        = info->params.encoding;
1193         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1194         tmp_params.addr_filter     = info->params.addr_filter;
1195         tmp_params.crc_type        = info->params.crc_type;
1196         tmp_params.preamble_length = info->params.preamble_length;
1197         tmp_params.preamble        = info->params.preamble;
1198         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1199         tmp_params.data_bits       = info->params.data_bits;
1200         tmp_params.stop_bits       = info->params.stop_bits;
1201         tmp_params.parity          = info->params.parity;
1202         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1203                 return -EFAULT;
1204         return 0;
1205 }
1206
1207 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1208 {
1209         struct MGSL_PARAMS32 tmp_params;
1210
1211         DBGINFO(("%s set_params32\n", info->device_name));
1212         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1213                 return -EFAULT;
1214
1215         spin_lock(&info->lock);
1216         info->params.mode            = tmp_params.mode;
1217         info->params.loopback        = tmp_params.loopback;
1218         info->params.flags           = tmp_params.flags;
1219         info->params.encoding        = tmp_params.encoding;
1220         info->params.clock_speed     = tmp_params.clock_speed;
1221         info->params.addr_filter     = tmp_params.addr_filter;
1222         info->params.crc_type        = tmp_params.crc_type;
1223         info->params.preamble_length = tmp_params.preamble_length;
1224         info->params.preamble        = tmp_params.preamble;
1225         info->params.data_rate       = tmp_params.data_rate;
1226         info->params.data_bits       = tmp_params.data_bits;
1227         info->params.stop_bits       = tmp_params.stop_bits;
1228         info->params.parity          = tmp_params.parity;
1229         spin_unlock(&info->lock);
1230
1231         change_params(info);
1232
1233         return 0;
1234 }
1235
1236 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1237                          unsigned int cmd, unsigned long arg)
1238 {
1239         struct slgt_info *info = tty->driver_data;
1240         int rc = -ENOIOCTLCMD;
1241
1242         if (sanity_check(info, tty->name, "compat_ioctl"))
1243                 return -ENODEV;
1244         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1245
1246         switch (cmd) {
1247
1248         case MGSL_IOCSPARAMS32:
1249                 rc = set_params32(info, compat_ptr(arg));
1250                 break;
1251
1252         case MGSL_IOCGPARAMS32:
1253                 rc = get_params32(info, compat_ptr(arg));
1254                 break;
1255
1256         case MGSL_IOCGPARAMS:
1257         case MGSL_IOCSPARAMS:
1258         case MGSL_IOCGTXIDLE:
1259         case MGSL_IOCGSTATS:
1260         case MGSL_IOCWAITEVENT:
1261         case MGSL_IOCGIF:
1262         case MGSL_IOCSGPIO:
1263         case MGSL_IOCGGPIO:
1264         case MGSL_IOCWAITGPIO:
1265         case TIOCGICOUNT:
1266                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1267                 break;
1268
1269         case MGSL_IOCSTXIDLE:
1270         case MGSL_IOCTXENABLE:
1271         case MGSL_IOCRXENABLE:
1272         case MGSL_IOCTXABORT:
1273         case TIOCMIWAIT:
1274         case MGSL_IOCSIF:
1275                 rc = ioctl(tty, file, cmd, arg);
1276                 break;
1277         }
1278
1279         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1280         return rc;
1281 }
1282 #else
1283 #define slgt_compat_ioctl NULL
1284 #endif /* ifdef CONFIG_COMPAT */
1285
1286 /*
1287  * proc fs support
1288  */
1289 static inline int line_info(char *buf, struct slgt_info *info)
1290 {
1291         char stat_buf[30];
1292         int ret;
1293         unsigned long flags;
1294
1295         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1296                       info->device_name, info->phys_reg_addr,
1297                       info->irq_level, info->max_frame_size);
1298
1299         /* output current serial signal states */
1300         spin_lock_irqsave(&info->lock,flags);
1301         get_signals(info);
1302         spin_unlock_irqrestore(&info->lock,flags);
1303
1304         stat_buf[0] = 0;
1305         stat_buf[1] = 0;
1306         if (info->signals & SerialSignal_RTS)
1307                 strcat(stat_buf, "|RTS");
1308         if (info->signals & SerialSignal_CTS)
1309                 strcat(stat_buf, "|CTS");
1310         if (info->signals & SerialSignal_DTR)
1311                 strcat(stat_buf, "|DTR");
1312         if (info->signals & SerialSignal_DSR)
1313                 strcat(stat_buf, "|DSR");
1314         if (info->signals & SerialSignal_DCD)
1315                 strcat(stat_buf, "|CD");
1316         if (info->signals & SerialSignal_RI)
1317                 strcat(stat_buf, "|RI");
1318
1319         if (info->params.mode != MGSL_MODE_ASYNC) {
1320                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1321                                info->icount.txok, info->icount.rxok);
1322                 if (info->icount.txunder)
1323                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1324                 if (info->icount.txabort)
1325                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1326                 if (info->icount.rxshort)
1327                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1328                 if (info->icount.rxlong)
1329                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1330                 if (info->icount.rxover)
1331                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1332                 if (info->icount.rxcrc)
1333                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1334         } else {
1335                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1336                                info->icount.tx, info->icount.rx);
1337                 if (info->icount.frame)
1338                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1339                 if (info->icount.parity)
1340                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1341                 if (info->icount.brk)
1342                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1343                 if (info->icount.overrun)
1344                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1345         }
1346
1347         /* Append serial signal status to end */
1348         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1349
1350         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1351                        info->tx_active,info->bh_requested,info->bh_running,
1352                        info->pending_bh);
1353
1354         return ret;
1355 }
1356
1357 /* Called to print information about devices
1358  */
1359 static int read_proc(char *page, char **start, off_t off, int count,
1360                      int *eof, void *data)
1361 {
1362         int len = 0, l;
1363         off_t   begin = 0;
1364         struct slgt_info *info;
1365
1366         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1367
1368         info = slgt_device_list;
1369         while( info ) {
1370                 l = line_info(page + len, info);
1371                 len += l;
1372                 if (len+begin > off+count)
1373                         goto done;
1374                 if (len+begin < off) {
1375                         begin += len;
1376                         len = 0;
1377                 }
1378                 info = info->next_device;
1379         }
1380
1381         *eof = 1;
1382 done:
1383         if (off >= len+begin)
1384                 return 0;
1385         *start = page + (off-begin);
1386         return ((count < begin+len-off) ? count : begin+len-off);
1387 }
1388
1389 /*
1390  * return count of bytes in transmit buffer
1391  */
1392 static int chars_in_buffer(struct tty_struct *tty)
1393 {
1394         struct slgt_info *info = tty->driver_data;
1395         if (sanity_check(info, tty->name, "chars_in_buffer"))
1396                 return 0;
1397         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1398         return info->tx_count;
1399 }
1400
1401 /*
1402  * signal remote device to throttle send data (our receive data)
1403  */
1404 static void throttle(struct tty_struct * tty)
1405 {
1406         struct slgt_info *info = tty->driver_data;
1407         unsigned long flags;
1408
1409         if (sanity_check(info, tty->name, "throttle"))
1410                 return;
1411         DBGINFO(("%s throttle\n", info->device_name));
1412         if (I_IXOFF(tty))
1413                 send_xchar(tty, STOP_CHAR(tty));
1414         if (tty->termios->c_cflag & CRTSCTS) {
1415                 spin_lock_irqsave(&info->lock,flags);
1416                 info->signals &= ~SerialSignal_RTS;
1417                 set_signals(info);
1418                 spin_unlock_irqrestore(&info->lock,flags);
1419         }
1420 }
1421
1422 /*
1423  * signal remote device to stop throttling send data (our receive data)
1424  */
1425 static void unthrottle(struct tty_struct * tty)
1426 {
1427         struct slgt_info *info = tty->driver_data;
1428         unsigned long flags;
1429
1430         if (sanity_check(info, tty->name, "unthrottle"))
1431                 return;
1432         DBGINFO(("%s unthrottle\n", info->device_name));
1433         if (I_IXOFF(tty)) {
1434                 if (info->x_char)
1435                         info->x_char = 0;
1436                 else
1437                         send_xchar(tty, START_CHAR(tty));
1438         }
1439         if (tty->termios->c_cflag & CRTSCTS) {
1440                 spin_lock_irqsave(&info->lock,flags);
1441                 info->signals |= SerialSignal_RTS;
1442                 set_signals(info);
1443                 spin_unlock_irqrestore(&info->lock,flags);
1444         }
1445 }
1446
1447 /*
1448  * set or clear transmit break condition
1449  * break_state  -1=set break condition, 0=clear
1450  */
1451 static void set_break(struct tty_struct *tty, int break_state)
1452 {
1453         struct slgt_info *info = tty->driver_data;
1454         unsigned short value;
1455         unsigned long flags;
1456
1457         if (sanity_check(info, tty->name, "set_break"))
1458                 return;
1459         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1460
1461         spin_lock_irqsave(&info->lock,flags);
1462         value = rd_reg16(info, TCR);
1463         if (break_state == -1)
1464                 value |= BIT6;
1465         else
1466                 value &= ~BIT6;
1467         wr_reg16(info, TCR, value);
1468         spin_unlock_irqrestore(&info->lock,flags);
1469 }
1470
1471 #if SYNCLINK_GENERIC_HDLC
1472
1473 /**
1474  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1475  * set encoding and frame check sequence (FCS) options
1476  *
1477  * dev       pointer to network device structure
1478  * encoding  serial encoding setting
1479  * parity    FCS setting
1480  *
1481  * returns 0 if success, otherwise error code
1482  */
1483 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1484                           unsigned short parity)
1485 {
1486         struct slgt_info *info = dev_to_port(dev);
1487         unsigned char  new_encoding;
1488         unsigned short new_crctype;
1489
1490         /* return error if TTY interface open */
1491         if (info->port.count)
1492                 return -EBUSY;
1493
1494         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1495
1496         switch (encoding)
1497         {
1498         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1499         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1500         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1501         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1502         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1503         default: return -EINVAL;
1504         }
1505
1506         switch (parity)
1507         {
1508         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1509         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1510         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1511         default: return -EINVAL;
1512         }
1513
1514         info->params.encoding = new_encoding;
1515         info->params.crc_type = new_crctype;
1516
1517         /* if network interface up, reprogram hardware */
1518         if (info->netcount)
1519                 program_hw(info);
1520
1521         return 0;
1522 }
1523
1524 /**
1525  * called by generic HDLC layer to send frame
1526  *
1527  * skb  socket buffer containing HDLC frame
1528  * dev  pointer to network device structure
1529  *
1530  * returns 0 if success, otherwise error code
1531  */
1532 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1533 {
1534         struct slgt_info *info = dev_to_port(dev);
1535         unsigned long flags;
1536
1537         DBGINFO(("%s hdlc_xmit\n", dev->name));
1538
1539         /* stop sending until this frame completes */
1540         netif_stop_queue(dev);
1541
1542         /* copy data to device buffers */
1543         info->tx_count = skb->len;
1544         tx_load(info, skb->data, skb->len);
1545
1546         /* update network statistics */
1547         dev->stats.tx_packets++;
1548         dev->stats.tx_bytes += skb->len;
1549
1550         /* done with socket buffer, so free it */
1551         dev_kfree_skb(skb);
1552
1553         /* save start time for transmit timeout detection */
1554         dev->trans_start = jiffies;
1555
1556         /* start hardware transmitter if necessary */
1557         spin_lock_irqsave(&info->lock,flags);
1558         if (!info->tx_active)
1559                 tx_start(info);
1560         spin_unlock_irqrestore(&info->lock,flags);
1561
1562         return 0;
1563 }
1564
1565 /**
1566  * called by network layer when interface enabled
1567  * claim resources and initialize hardware
1568  *
1569  * dev  pointer to network device structure
1570  *
1571  * returns 0 if success, otherwise error code
1572  */
1573 static int hdlcdev_open(struct net_device *dev)
1574 {
1575         struct slgt_info *info = dev_to_port(dev);
1576         int rc;
1577         unsigned long flags;
1578
1579         if (!try_module_get(THIS_MODULE))
1580                 return -EBUSY;
1581
1582         DBGINFO(("%s hdlcdev_open\n", dev->name));
1583
1584         /* generic HDLC layer open processing */
1585         if ((rc = hdlc_open(dev)))
1586                 return rc;
1587
1588         /* arbitrate between network and tty opens */
1589         spin_lock_irqsave(&info->netlock, flags);
1590         if (info->port.count != 0 || info->netcount != 0) {
1591                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1592                 spin_unlock_irqrestore(&info->netlock, flags);
1593                 return -EBUSY;
1594         }
1595         info->netcount=1;
1596         spin_unlock_irqrestore(&info->netlock, flags);
1597
1598         /* claim resources and init adapter */
1599         if ((rc = startup(info)) != 0) {
1600                 spin_lock_irqsave(&info->netlock, flags);
1601                 info->netcount=0;
1602                 spin_unlock_irqrestore(&info->netlock, flags);
1603                 return rc;
1604         }
1605
1606         /* assert DTR and RTS, apply hardware settings */
1607         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1608         program_hw(info);
1609
1610         /* enable network layer transmit */
1611         dev->trans_start = jiffies;
1612         netif_start_queue(dev);
1613
1614         /* inform generic HDLC layer of current DCD status */
1615         spin_lock_irqsave(&info->lock, flags);
1616         get_signals(info);
1617         spin_unlock_irqrestore(&info->lock, flags);
1618         if (info->signals & SerialSignal_DCD)
1619                 netif_carrier_on(dev);
1620         else
1621                 netif_carrier_off(dev);
1622         return 0;
1623 }
1624
1625 /**
1626  * called by network layer when interface is disabled
1627  * shutdown hardware and release resources
1628  *
1629  * dev  pointer to network device structure
1630  *
1631  * returns 0 if success, otherwise error code
1632  */
1633 static int hdlcdev_close(struct net_device *dev)
1634 {
1635         struct slgt_info *info = dev_to_port(dev);
1636         unsigned long flags;
1637
1638         DBGINFO(("%s hdlcdev_close\n", dev->name));
1639
1640         netif_stop_queue(dev);
1641
1642         /* shutdown adapter and release resources */
1643         shutdown(info);
1644
1645         hdlc_close(dev);
1646
1647         spin_lock_irqsave(&info->netlock, flags);
1648         info->netcount=0;
1649         spin_unlock_irqrestore(&info->netlock, flags);
1650
1651         module_put(THIS_MODULE);
1652         return 0;
1653 }
1654
1655 /**
1656  * called by network layer to process IOCTL call to network device
1657  *
1658  * dev  pointer to network device structure
1659  * ifr  pointer to network interface request structure
1660  * cmd  IOCTL command code
1661  *
1662  * returns 0 if success, otherwise error code
1663  */
1664 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1665 {
1666         const size_t size = sizeof(sync_serial_settings);
1667         sync_serial_settings new_line;
1668         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1669         struct slgt_info *info = dev_to_port(dev);
1670         unsigned int flags;
1671
1672         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1673
1674         /* return error if TTY interface open */
1675         if (info->port.count)
1676                 return -EBUSY;
1677
1678         if (cmd != SIOCWANDEV)
1679                 return hdlc_ioctl(dev, ifr, cmd);
1680
1681         switch(ifr->ifr_settings.type) {
1682         case IF_GET_IFACE: /* return current sync_serial_settings */
1683
1684                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1685                 if (ifr->ifr_settings.size < size) {
1686                         ifr->ifr_settings.size = size; /* data size wanted */
1687                         return -ENOBUFS;
1688                 }
1689
1690                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1691                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1692                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1693                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1694
1695                 switch (flags){
1696                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1697                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1698                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1699                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1700                 default: new_line.clock_type = CLOCK_DEFAULT;
1701                 }
1702
1703                 new_line.clock_rate = info->params.clock_speed;
1704                 new_line.loopback   = info->params.loopback ? 1:0;
1705
1706                 if (copy_to_user(line, &new_line, size))
1707                         return -EFAULT;
1708                 return 0;
1709
1710         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1711
1712                 if(!capable(CAP_NET_ADMIN))
1713                         return -EPERM;
1714                 if (copy_from_user(&new_line, line, size))
1715                         return -EFAULT;
1716
1717                 switch (new_line.clock_type)
1718                 {
1719                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1720                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1721                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1722                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1723                 case CLOCK_DEFAULT:  flags = info->params.flags &
1724                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1725                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1726                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1727                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1728                 default: return -EINVAL;
1729                 }
1730
1731                 if (new_line.loopback != 0 && new_line.loopback != 1)
1732                         return -EINVAL;
1733
1734                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1735                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1736                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1737                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1738                 info->params.flags |= flags;
1739
1740                 info->params.loopback = new_line.loopback;
1741
1742                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1743                         info->params.clock_speed = new_line.clock_rate;
1744                 else
1745                         info->params.clock_speed = 0;
1746
1747                 /* if network interface up, reprogram hardware */
1748                 if (info->netcount)
1749                         program_hw(info);
1750                 return 0;
1751
1752         default:
1753                 return hdlc_ioctl(dev, ifr, cmd);
1754         }
1755 }
1756
1757 /**
1758  * called by network layer when transmit timeout is detected
1759  *
1760  * dev  pointer to network device structure
1761  */
1762 static void hdlcdev_tx_timeout(struct net_device *dev)
1763 {
1764         struct slgt_info *info = dev_to_port(dev);
1765         unsigned long flags;
1766
1767         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1768
1769         dev->stats.tx_errors++;
1770         dev->stats.tx_aborted_errors++;
1771
1772         spin_lock_irqsave(&info->lock,flags);
1773         tx_stop(info);
1774         spin_unlock_irqrestore(&info->lock,flags);
1775
1776         netif_wake_queue(dev);
1777 }
1778
1779 /**
1780  * called by device driver when transmit completes
1781  * reenable network layer transmit if stopped
1782  *
1783  * info  pointer to device instance information
1784  */
1785 static void hdlcdev_tx_done(struct slgt_info *info)
1786 {
1787         if (netif_queue_stopped(info->netdev))
1788                 netif_wake_queue(info->netdev);
1789 }
1790
1791 /**
1792  * called by device driver when frame received
1793  * pass frame to network layer
1794  *
1795  * info  pointer to device instance information
1796  * buf   pointer to buffer contianing frame data
1797  * size  count of data bytes in buf
1798  */
1799 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1800 {
1801         struct sk_buff *skb = dev_alloc_skb(size);
1802         struct net_device *dev = info->netdev;
1803
1804         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1805
1806         if (skb == NULL) {
1807                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1808                 dev->stats.rx_dropped++;
1809                 return;
1810         }
1811
1812         memcpy(skb_put(skb, size), buf, size);
1813
1814         skb->protocol = hdlc_type_trans(skb, dev);
1815
1816         dev->stats.rx_packets++;
1817         dev->stats.rx_bytes += size;
1818
1819         netif_rx(skb);
1820
1821         dev->last_rx = jiffies;
1822 }
1823
1824 /**
1825  * called by device driver when adding device instance
1826  * do generic HDLC initialization
1827  *
1828  * info  pointer to device instance information
1829  *
1830  * returns 0 if success, otherwise error code
1831  */
1832 static int hdlcdev_init(struct slgt_info *info)
1833 {
1834         int rc;
1835         struct net_device *dev;
1836         hdlc_device *hdlc;
1837
1838         /* allocate and initialize network and HDLC layer objects */
1839
1840         if (!(dev = alloc_hdlcdev(info))) {
1841                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1842                 return -ENOMEM;
1843         }
1844
1845         /* for network layer reporting purposes only */
1846         dev->mem_start = info->phys_reg_addr;
1847         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1848         dev->irq       = info->irq_level;
1849
1850         /* network layer callbacks and settings */
1851         dev->do_ioctl       = hdlcdev_ioctl;
1852         dev->open           = hdlcdev_open;
1853         dev->stop           = hdlcdev_close;
1854         dev->tx_timeout     = hdlcdev_tx_timeout;
1855         dev->watchdog_timeo = 10*HZ;
1856         dev->tx_queue_len   = 50;
1857
1858         /* generic HDLC layer callbacks and settings */
1859         hdlc         = dev_to_hdlc(dev);
1860         hdlc->attach = hdlcdev_attach;
1861         hdlc->xmit   = hdlcdev_xmit;
1862
1863         /* register objects with HDLC layer */
1864         if ((rc = register_hdlc_device(dev))) {
1865                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1866                 free_netdev(dev);
1867                 return rc;
1868         }
1869
1870         info->netdev = dev;
1871         return 0;
1872 }
1873
1874 /**
1875  * called by device driver when removing device instance
1876  * do generic HDLC cleanup
1877  *
1878  * info  pointer to device instance information
1879  */
1880 static void hdlcdev_exit(struct slgt_info *info)
1881 {
1882         unregister_hdlc_device(info->netdev);
1883         free_netdev(info->netdev);
1884         info->netdev = NULL;
1885 }
1886
1887 #endif /* ifdef CONFIG_HDLC */
1888
1889 /*
1890  * get async data from rx DMA buffers
1891  */
1892 static void rx_async(struct slgt_info *info)
1893 {
1894         struct tty_struct *tty = info->port.tty;
1895         struct mgsl_icount *icount = &info->icount;
1896         unsigned int start, end;
1897         unsigned char *p;
1898         unsigned char status;
1899         struct slgt_desc *bufs = info->rbufs;
1900         int i, count;
1901         int chars = 0;
1902         int stat;
1903         unsigned char ch;
1904
1905         start = end = info->rbuf_current;
1906
1907         while(desc_complete(bufs[end])) {
1908                 count = desc_count(bufs[end]) - info->rbuf_index;
1909                 p     = bufs[end].buf + info->rbuf_index;
1910
1911                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1912                 DBGDATA(info, p, count, "rx");
1913
1914                 for(i=0 ; i < count; i+=2, p+=2) {
1915                         ch = *p;
1916                         icount->rx++;
1917
1918                         stat = 0;
1919
1920                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1921                                 if (status & BIT1)
1922                                         icount->parity++;
1923                                 else if (status & BIT0)
1924                                         icount->frame++;
1925                                 /* discard char if tty control flags say so */
1926                                 if (status & info->ignore_status_mask)
1927                                         continue;
1928                                 if (status & BIT1)
1929                                         stat = TTY_PARITY;
1930                                 else if (status & BIT0)
1931                                         stat = TTY_FRAME;
1932                         }
1933                         if (tty) {
1934                                 tty_insert_flip_char(tty, ch, stat);
1935                                 chars++;
1936                         }
1937                 }
1938
1939                 if (i < count) {
1940                         /* receive buffer not completed */
1941                         info->rbuf_index += i;
1942                         mod_timer(&info->rx_timer, jiffies + 1);
1943                         break;
1944                 }
1945
1946                 info->rbuf_index = 0;
1947                 free_rbufs(info, end, end);
1948
1949                 if (++end == info->rbuf_count)
1950                         end = 0;
1951
1952                 /* if entire list searched then no frame available */
1953                 if (end == start)
1954                         break;
1955         }
1956
1957         if (tty && chars)
1958                 tty_flip_buffer_push(tty);
1959 }
1960
1961 /*
1962  * return next bottom half action to perform
1963  */
1964 static int bh_action(struct slgt_info *info)
1965 {
1966         unsigned long flags;
1967         int rc;
1968
1969         spin_lock_irqsave(&info->lock,flags);
1970
1971         if (info->pending_bh & BH_RECEIVE) {
1972                 info->pending_bh &= ~BH_RECEIVE;
1973                 rc = BH_RECEIVE;
1974         } else if (info->pending_bh & BH_TRANSMIT) {
1975                 info->pending_bh &= ~BH_TRANSMIT;
1976                 rc = BH_TRANSMIT;
1977         } else if (info->pending_bh & BH_STATUS) {
1978                 info->pending_bh &= ~BH_STATUS;
1979                 rc = BH_STATUS;
1980         } else {
1981                 /* Mark BH routine as complete */
1982                 info->bh_running = false;
1983                 info->bh_requested = false;
1984                 rc = 0;
1985         }
1986
1987         spin_unlock_irqrestore(&info->lock,flags);
1988
1989         return rc;
1990 }
1991
1992 /*
1993  * perform bottom half processing
1994  */
1995 static void bh_handler(struct work_struct *work)
1996 {
1997         struct slgt_info *info = container_of(work, struct slgt_info, task);
1998         int action;
1999
2000         if (!info)
2001                 return;
2002         info->bh_running = true;
2003
2004         while((action = bh_action(info))) {
2005                 switch (action) {
2006                 case BH_RECEIVE:
2007                         DBGBH(("%s bh receive\n", info->device_name));
2008                         switch(info->params.mode) {
2009                         case MGSL_MODE_ASYNC:
2010                                 rx_async(info);
2011                                 break;
2012                         case MGSL_MODE_HDLC:
2013                                 while(rx_get_frame(info));
2014                                 break;
2015                         case MGSL_MODE_RAW:
2016                         case MGSL_MODE_MONOSYNC:
2017                         case MGSL_MODE_BISYNC:
2018                                 while(rx_get_buf(info));
2019                                 break;
2020                         }
2021                         /* restart receiver if rx DMA buffers exhausted */
2022                         if (info->rx_restart)
2023                                 rx_start(info);
2024                         break;
2025                 case BH_TRANSMIT:
2026                         bh_transmit(info);
2027                         break;
2028                 case BH_STATUS:
2029                         DBGBH(("%s bh status\n", info->device_name));
2030                         info->ri_chkcount = 0;
2031                         info->dsr_chkcount = 0;
2032                         info->dcd_chkcount = 0;
2033                         info->cts_chkcount = 0;
2034                         break;
2035                 default:
2036                         DBGBH(("%s unknown action\n", info->device_name));
2037                         break;
2038                 }
2039         }
2040         DBGBH(("%s bh_handler exit\n", info->device_name));
2041 }
2042
2043 static void bh_transmit(struct slgt_info *info)
2044 {
2045         struct tty_struct *tty = info->port.tty;
2046
2047         DBGBH(("%s bh_transmit\n", info->device_name));
2048         if (tty)
2049                 tty_wakeup(tty);
2050 }
2051
2052 static void dsr_change(struct slgt_info *info, unsigned short status)
2053 {
2054         if (status & BIT3) {
2055                 info->signals |= SerialSignal_DSR;
2056                 info->input_signal_events.dsr_up++;
2057         } else {
2058                 info->signals &= ~SerialSignal_DSR;
2059                 info->input_signal_events.dsr_down++;
2060         }
2061         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2062         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2063                 slgt_irq_off(info, IRQ_DSR);
2064                 return;
2065         }
2066         info->icount.dsr++;
2067         wake_up_interruptible(&info->status_event_wait_q);
2068         wake_up_interruptible(&info->event_wait_q);
2069         info->pending_bh |= BH_STATUS;
2070 }
2071
2072 static void cts_change(struct slgt_info *info, unsigned short status)
2073 {
2074         if (status & BIT2) {
2075                 info->signals |= SerialSignal_CTS;
2076                 info->input_signal_events.cts_up++;
2077         } else {
2078                 info->signals &= ~SerialSignal_CTS;
2079                 info->input_signal_events.cts_down++;
2080         }
2081         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2082         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2083                 slgt_irq_off(info, IRQ_CTS);
2084                 return;
2085         }
2086         info->icount.cts++;
2087         wake_up_interruptible(&info->status_event_wait_q);
2088         wake_up_interruptible(&info->event_wait_q);
2089         info->pending_bh |= BH_STATUS;
2090
2091         if (info->port.flags & ASYNC_CTS_FLOW) {
2092                 if (info->port.tty) {
2093                         if (info->port.tty->hw_stopped) {
2094                                 if (info->signals & SerialSignal_CTS) {
2095                                         info->port.tty->hw_stopped = 0;
2096                                         info->pending_bh |= BH_TRANSMIT;
2097                                         return;
2098                                 }
2099                         } else {
2100                                 if (!(info->signals & SerialSignal_CTS))
2101                                         info->port.tty->hw_stopped = 1;
2102                         }
2103                 }
2104         }
2105 }
2106
2107 static void dcd_change(struct slgt_info *info, unsigned short status)
2108 {
2109         if (status & BIT1) {
2110                 info->signals |= SerialSignal_DCD;
2111                 info->input_signal_events.dcd_up++;
2112         } else {
2113                 info->signals &= ~SerialSignal_DCD;
2114                 info->input_signal_events.dcd_down++;
2115         }
2116         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2117         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2118                 slgt_irq_off(info, IRQ_DCD);
2119                 return;
2120         }
2121         info->icount.dcd++;
2122 #if SYNCLINK_GENERIC_HDLC
2123         if (info->netcount) {
2124                 if (info->signals & SerialSignal_DCD)
2125                         netif_carrier_on(info->netdev);
2126                 else
2127                         netif_carrier_off(info->netdev);
2128         }
2129 #endif
2130         wake_up_interruptible(&info->status_event_wait_q);
2131         wake_up_interruptible(&info->event_wait_q);
2132         info->pending_bh |= BH_STATUS;
2133
2134         if (info->port.flags & ASYNC_CHECK_CD) {
2135                 if (info->signals & SerialSignal_DCD)
2136                         wake_up_interruptible(&info->port.open_wait);
2137                 else {
2138                         if (info->port.tty)
2139                                 tty_hangup(info->port.tty);
2140                 }
2141         }
2142 }
2143
2144 static void ri_change(struct slgt_info *info, unsigned short status)
2145 {
2146         if (status & BIT0) {
2147                 info->signals |= SerialSignal_RI;
2148                 info->input_signal_events.ri_up++;
2149         } else {
2150                 info->signals &= ~SerialSignal_RI;
2151                 info->input_signal_events.ri_down++;
2152         }
2153         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2154         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2155                 slgt_irq_off(info, IRQ_RI);
2156                 return;
2157         }
2158         info->icount.rng++;
2159         wake_up_interruptible(&info->status_event_wait_q);
2160         wake_up_interruptible(&info->event_wait_q);
2161         info->pending_bh |= BH_STATUS;
2162 }
2163
2164 static void isr_serial(struct slgt_info *info)
2165 {
2166         unsigned short status = rd_reg16(info, SSR);
2167
2168         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2169
2170         wr_reg16(info, SSR, status); /* clear pending */
2171
2172         info->irq_occurred = true;
2173
2174         if (info->params.mode == MGSL_MODE_ASYNC) {
2175                 if (status & IRQ_TXIDLE) {
2176                         if (info->tx_count)
2177                                 isr_txeom(info, status);
2178                 }
2179                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2180                         info->icount.brk++;
2181                         /* process break detection if tty control allows */
2182                         if (info->port.tty) {
2183                                 if (!(status & info->ignore_status_mask)) {
2184                                         if (info->read_status_mask & MASK_BREAK) {
2185                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2186                                                 if (info->port.flags & ASYNC_SAK)
2187                                                         do_SAK(info->port.tty);
2188                                         }
2189                                 }
2190                         }
2191                 }
2192         } else {
2193                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2194                         isr_txeom(info, status);
2195
2196                 if (status & IRQ_RXIDLE) {
2197                         if (status & RXIDLE)
2198                                 info->icount.rxidle++;
2199                         else
2200                                 info->icount.exithunt++;
2201                         wake_up_interruptible(&info->event_wait_q);
2202                 }
2203
2204                 if (status & IRQ_RXOVER)
2205                         rx_start(info);
2206         }
2207
2208         if (status & IRQ_DSR)
2209                 dsr_change(info, status);
2210         if (status & IRQ_CTS)
2211                 cts_change(info, status);
2212         if (status & IRQ_DCD)
2213                 dcd_change(info, status);
2214         if (status & IRQ_RI)
2215                 ri_change(info, status);
2216 }
2217
2218 static void isr_rdma(struct slgt_info *info)
2219 {
2220         unsigned int status = rd_reg32(info, RDCSR);
2221
2222         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2223
2224         /* RDCSR (rx DMA control/status)
2225          *
2226          * 31..07  reserved
2227          * 06      save status byte to DMA buffer
2228          * 05      error
2229          * 04      eol (end of list)
2230          * 03      eob (end of buffer)
2231          * 02      IRQ enable
2232          * 01      reset
2233          * 00      enable
2234          */
2235         wr_reg32(info, RDCSR, status);  /* clear pending */
2236
2237         if (status & (BIT5 + BIT4)) {
2238                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2239                 info->rx_restart = true;
2240         }
2241         info->pending_bh |= BH_RECEIVE;
2242 }
2243
2244 static void isr_tdma(struct slgt_info *info)
2245 {
2246         unsigned int status = rd_reg32(info, TDCSR);
2247
2248         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2249
2250         /* TDCSR (tx DMA control/status)
2251          *
2252          * 31..06  reserved
2253          * 05      error
2254          * 04      eol (end of list)
2255          * 03      eob (end of buffer)
2256          * 02      IRQ enable
2257          * 01      reset
2258          * 00      enable
2259          */
2260         wr_reg32(info, TDCSR, status);  /* clear pending */
2261
2262         if (status & (BIT5 + BIT4 + BIT3)) {
2263                 // another transmit buffer has completed
2264                 // run bottom half to get more send data from user
2265                 info->pending_bh |= BH_TRANSMIT;
2266         }
2267 }
2268
2269 static void isr_txeom(struct slgt_info *info, unsigned short status)
2270 {
2271         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2272
2273         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2274         tdma_reset(info);
2275         reset_tbufs(info);
2276         if (status & IRQ_TXUNDER) {
2277                 unsigned short val = rd_reg16(info, TCR);
2278                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2279                 wr_reg16(info, TCR, val); /* clear reset bit */
2280         }
2281
2282         if (info->tx_active) {
2283                 if (info->params.mode != MGSL_MODE_ASYNC) {
2284                         if (status & IRQ_TXUNDER)
2285                                 info->icount.txunder++;
2286                         else if (status & IRQ_TXIDLE)
2287                                 info->icount.txok++;
2288                 }
2289
2290                 info->tx_active = false;
2291                 info->tx_count = 0;
2292
2293                 del_timer(&info->tx_timer);
2294
2295                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2296                         info->signals &= ~SerialSignal_RTS;
2297                         info->drop_rts_on_tx_done = false;
2298                         set_signals(info);
2299                 }
2300
2301 #if SYNCLINK_GENERIC_HDLC
2302                 if (info->netcount)
2303                         hdlcdev_tx_done(info);
2304                 else
2305 #endif
2306                 {
2307                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2308                                 tx_stop(info);
2309                                 return;
2310                         }
2311                         info->pending_bh |= BH_TRANSMIT;
2312                 }
2313         }
2314 }
2315
2316 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2317 {
2318         struct cond_wait *w, *prev;
2319
2320         /* wake processes waiting for specific transitions */
2321         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2322                 if (w->data & changed) {
2323                         w->data = state;
2324                         wake_up_interruptible(&w->q);
2325                         if (prev != NULL)
2326                                 prev->next = w->next;
2327                         else
2328                                 info->gpio_wait_q = w->next;
2329                 } else
2330                         prev = w;
2331         }
2332 }
2333
2334 /* interrupt service routine
2335  *
2336  *      irq     interrupt number
2337  *      dev_id  device ID supplied during interrupt registration
2338  */
2339 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2340 {
2341         struct slgt_info *info = dev_id;
2342         unsigned int gsr;
2343         unsigned int i;
2344
2345         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2346
2347         spin_lock(&info->lock);
2348
2349         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2350                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2351                 info->irq_occurred = true;
2352                 for(i=0; i < info->port_count ; i++) {
2353                         if (info->port_array[i] == NULL)
2354                                 continue;
2355                         if (gsr & (BIT8 << i))
2356                                 isr_serial(info->port_array[i]);
2357                         if (gsr & (BIT16 << (i*2)))
2358                                 isr_rdma(info->port_array[i]);
2359                         if (gsr & (BIT17 << (i*2)))
2360                                 isr_tdma(info->port_array[i]);
2361                 }
2362         }
2363
2364         if (info->gpio_present) {
2365                 unsigned int state;
2366                 unsigned int changed;
2367                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2368                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2369                         /* read latched state of GPIO signals */
2370                         state = rd_reg32(info, IOVR);
2371                         /* clear pending GPIO interrupt bits */
2372                         wr_reg32(info, IOSR, changed);
2373                         for (i=0 ; i < info->port_count ; i++) {
2374                                 if (info->port_array[i] != NULL)
2375                                         isr_gpio(info->port_array[i], changed, state);
2376                         }
2377                 }
2378         }
2379
2380         for(i=0; i < info->port_count ; i++) {
2381                 struct slgt_info *port = info->port_array[i];
2382
2383                 if (port && (port->port.count || port->netcount) &&
2384                     port->pending_bh && !port->bh_running &&
2385                     !port->bh_requested) {
2386                         DBGISR(("%s bh queued\n", port->device_name));
2387                         schedule_work(&port->task);
2388                         port->bh_requested = true;
2389                 }
2390         }
2391
2392         spin_unlock(&info->lock);
2393
2394         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2395         return IRQ_HANDLED;
2396 }
2397
2398 static int startup(struct slgt_info *info)
2399 {
2400         DBGINFO(("%s startup\n", info->device_name));
2401
2402         if (info->port.flags & ASYNC_INITIALIZED)
2403                 return 0;
2404
2405         if (!info->tx_buf) {
2406                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2407                 if (!info->tx_buf) {
2408                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2409                         return -ENOMEM;
2410                 }
2411         }
2412
2413         info->pending_bh = 0;
2414
2415         memset(&info->icount, 0, sizeof(info->icount));
2416
2417         /* program hardware for current parameters */
2418         change_params(info);
2419
2420         if (info->port.tty)
2421                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2422
2423         info->port.flags |= ASYNC_INITIALIZED;
2424
2425         return 0;
2426 }
2427
2428 /*
2429  *  called by close() and hangup() to shutdown hardware
2430  */
2431 static void shutdown(struct slgt_info *info)
2432 {
2433         unsigned long flags;
2434
2435         if (!(info->port.flags & ASYNC_INITIALIZED))
2436                 return;
2437
2438         DBGINFO(("%s shutdown\n", info->device_name));
2439
2440         /* clear status wait queue because status changes */
2441         /* can't happen after shutting down the hardware */
2442         wake_up_interruptible(&info->status_event_wait_q);
2443         wake_up_interruptible(&info->event_wait_q);
2444
2445         del_timer_sync(&info->tx_timer);
2446         del_timer_sync(&info->rx_timer);
2447
2448         kfree(info->tx_buf);
2449         info->tx_buf = NULL;
2450
2451         spin_lock_irqsave(&info->lock,flags);
2452
2453         tx_stop(info);
2454         rx_stop(info);
2455
2456         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2457
2458         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2459                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2460                 set_signals(info);
2461         }
2462
2463         flush_cond_wait(&info->gpio_wait_q);
2464
2465         spin_unlock_irqrestore(&info->lock,flags);
2466
2467         if (info->port.tty)
2468                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2469
2470         info->port.flags &= ~ASYNC_INITIALIZED;
2471 }
2472
2473 static void program_hw(struct slgt_info *info)
2474 {
2475         unsigned long flags;
2476
2477         spin_lock_irqsave(&info->lock,flags);
2478
2479         rx_stop(info);
2480         tx_stop(info);
2481
2482         if (info->params.mode != MGSL_MODE_ASYNC ||
2483             info->netcount)
2484                 sync_mode(info);
2485         else
2486                 async_mode(info);
2487
2488         set_signals(info);
2489
2490         info->dcd_chkcount = 0;
2491         info->cts_chkcount = 0;
2492         info->ri_chkcount = 0;
2493         info->dsr_chkcount = 0;
2494
2495         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2496         get_signals(info);
2497
2498         if (info->netcount ||
2499             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2500                 rx_start(info);
2501
2502         spin_unlock_irqrestore(&info->lock,flags);
2503 }
2504
2505 /*
2506  * reconfigure adapter based on new parameters
2507  */
2508 static void change_params(struct slgt_info *info)
2509 {
2510         unsigned cflag;
2511         int bits_per_char;
2512
2513         if (!info->port.tty || !info->port.tty->termios)
2514                 return;
2515         DBGINFO(("%s change_params\n", info->device_name));
2516
2517         cflag = info->port.tty->termios->c_cflag;
2518
2519         /* if B0 rate (hangup) specified then negate DTR and RTS */
2520         /* otherwise assert DTR and RTS */
2521         if (cflag & CBAUD)
2522                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2523         else
2524                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2525
2526         /* byte size and parity */
2527
2528         switch (cflag & CSIZE) {
2529         case CS5: info->params.data_bits = 5; break;
2530         case CS6: info->params.data_bits = 6; break;
2531         case CS7: info->params.data_bits = 7; break;
2532         case CS8: info->params.data_bits = 8; break;
2533         default:  info->params.data_bits = 7; break;
2534         }
2535
2536         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2537
2538         if (cflag & PARENB)
2539                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2540         else
2541                 info->params.parity = ASYNC_PARITY_NONE;
2542
2543         /* calculate number of jiffies to transmit a full
2544          * FIFO (32 bytes) at specified data rate
2545          */
2546         bits_per_char = info->params.data_bits +
2547                         info->params.stop_bits + 1;
2548
2549         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2550
2551         if (info->params.data_rate) {
2552                 info->timeout = (32*HZ*bits_per_char) /
2553                                 info->params.data_rate;
2554         }
2555         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2556
2557         if (cflag & CRTSCTS)
2558                 info->port.flags |= ASYNC_CTS_FLOW;
2559         else
2560                 info->port.flags &= ~ASYNC_CTS_FLOW;
2561
2562         if (cflag & CLOCAL)
2563                 info->port.flags &= ~ASYNC_CHECK_CD;
2564         else
2565                 info->port.flags |= ASYNC_CHECK_CD;
2566
2567         /* process tty input control flags */
2568
2569         info->read_status_mask = IRQ_RXOVER;
2570         if (I_INPCK(info->port.tty))
2571                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2572         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2573                 info->read_status_mask |= MASK_BREAK;
2574         if (I_IGNPAR(info->port.tty))
2575                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2576         if (I_IGNBRK(info->port.tty)) {
2577                 info->ignore_status_mask |= MASK_BREAK;
2578                 /* If ignoring parity and break indicators, ignore
2579                  * overruns too.  (For real raw support).
2580                  */
2581                 if (I_IGNPAR(info->port.tty))
2582                         info->ignore_status_mask |= MASK_OVERRUN;
2583         }
2584
2585         program_hw(info);
2586 }
2587
2588 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2589 {
2590         DBGINFO(("%s get_stats\n",  info->device_name));
2591         if (!user_icount) {
2592                 memset(&info->icount, 0, sizeof(info->icount));
2593         } else {
2594                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2595                         return -EFAULT;
2596         }
2597         return 0;
2598 }
2599
2600 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2601 {
2602         DBGINFO(("%s get_params\n", info->device_name));
2603         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2604                 return -EFAULT;
2605         return 0;
2606 }
2607
2608 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2609 {
2610         unsigned long flags;
2611         MGSL_PARAMS tmp_params;
2612
2613         DBGINFO(("%s set_params\n", info->device_name));
2614         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2615                 return -EFAULT;
2616
2617         spin_lock_irqsave(&info->lock, flags);
2618         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2619         spin_unlock_irqrestore(&info->lock, flags);
2620
2621         change_params(info);
2622
2623         return 0;
2624 }
2625
2626 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2627 {
2628         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2629         if (put_user(info->idle_mode, idle_mode))
2630                 return -EFAULT;
2631         return 0;
2632 }
2633
2634 static int set_txidle(struct slgt_info *info, int idle_mode)
2635 {
2636         unsigned long flags;
2637         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2638         spin_lock_irqsave(&info->lock,flags);
2639         info->idle_mode = idle_mode;
2640         if (info->params.mode != MGSL_MODE_ASYNC)
2641                 tx_set_idle(info);
2642         spin_unlock_irqrestore(&info->lock,flags);
2643         return 0;
2644 }
2645
2646 static int tx_enable(struct slgt_info *info, int enable)
2647 {
2648         unsigned long flags;
2649         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2650         spin_lock_irqsave(&info->lock,flags);
2651         if (enable) {
2652                 if (!info->tx_enabled)
2653                         tx_start(info);
2654         } else {
2655                 if (info->tx_enabled)
2656                         tx_stop(info);
2657         }
2658         spin_unlock_irqrestore(&info->lock,flags);
2659         return 0;
2660 }
2661
2662 /*
2663  * abort transmit HDLC frame
2664  */
2665 static int tx_abort(struct slgt_info *info)
2666 {
2667         unsigned long flags;
2668         DBGINFO(("%s tx_abort\n", info->device_name));
2669         spin_lock_irqsave(&info->lock,flags);
2670         tdma_reset(info);
2671         spin_unlock_irqrestore(&info->lock,flags);
2672         return 0;
2673 }
2674
2675 static int rx_enable(struct slgt_info *info, int enable)
2676 {
2677         unsigned long flags;
2678         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2679         spin_lock_irqsave(&info->lock,flags);
2680         if (enable) {
2681                 if (!info->rx_enabled)
2682                         rx_start(info);
2683                 else if (enable == 2) {
2684                         /* force hunt mode (write 1 to RCR[3]) */
2685                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2686                 }
2687         } else {
2688                 if (info->rx_enabled)
2689                         rx_stop(info);
2690         }
2691         spin_unlock_irqrestore(&info->lock,flags);
2692         return 0;
2693 }
2694
2695 /*
2696  *  wait for specified event to occur
2697  */
2698 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2699 {
2700         unsigned long flags;
2701         int s;
2702         int rc=0;
2703         struct mgsl_icount cprev, cnow;
2704         int events;
2705         int mask;
2706         struct  _input_signal_events oldsigs, newsigs;
2707         DECLARE_WAITQUEUE(wait, current);
2708
2709         if (get_user(mask, mask_ptr))
2710                 return -EFAULT;
2711
2712         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2713
2714         spin_lock_irqsave(&info->lock,flags);
2715
2716         /* return immediately if state matches requested events */
2717         get_signals(info);
2718         s = info->signals;
2719
2720         events = mask &
2721                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2722                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2723                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2724                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2725         if (events) {
2726                 spin_unlock_irqrestore(&info->lock,flags);
2727                 goto exit;
2728         }
2729
2730         /* save current irq counts */
2731         cprev = info->icount;
2732         oldsigs = info->input_signal_events;
2733
2734         /* enable hunt and idle irqs if needed */
2735         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2736                 unsigned short val = rd_reg16(info, SCR);
2737                 if (!(val & IRQ_RXIDLE))
2738                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2739         }
2740
2741         set_current_state(TASK_INTERRUPTIBLE);
2742         add_wait_queue(&info->event_wait_q, &wait);
2743
2744         spin_unlock_irqrestore(&info->lock,flags);
2745
2746         for(;;) {
2747                 schedule();
2748                 if (signal_pending(current)) {
2749                         rc = -ERESTARTSYS;
2750                         break;
2751                 }
2752
2753                 /* get current irq counts */
2754                 spin_lock_irqsave(&info->lock,flags);
2755                 cnow = info->icount;
2756                 newsigs = info->input_signal_events;
2757                 set_current_state(TASK_INTERRUPTIBLE);
2758                 spin_unlock_irqrestore(&info->lock,flags);
2759
2760                 /* if no change, wait aborted for some reason */
2761                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2762                     newsigs.dsr_down == oldsigs.dsr_down &&
2763                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2764                     newsigs.dcd_down == oldsigs.dcd_down &&
2765                     newsigs.cts_up   == oldsigs.cts_up   &&
2766                     newsigs.cts_down == oldsigs.cts_down &&
2767                     newsigs.ri_up    == oldsigs.ri_up    &&
2768                     newsigs.ri_down  == oldsigs.ri_down  &&
2769                     cnow.exithunt    == cprev.exithunt   &&
2770                     cnow.rxidle      == cprev.rxidle) {
2771                         rc = -EIO;
2772                         break;
2773                 }
2774
2775                 events = mask &
2776                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2777                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2778                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2779                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2780                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2781                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2782                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2783                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2784                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2785                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2786                 if (events)
2787                         break;
2788
2789                 cprev = cnow;
2790                 oldsigs = newsigs;
2791         }
2792
2793         remove_wait_queue(&info->event_wait_q, &wait);
2794         set_current_state(TASK_RUNNING);
2795
2796
2797         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2798                 spin_lock_irqsave(&info->lock,flags);
2799                 if (!waitqueue_active(&info->event_wait_q)) {
2800                         /* disable enable exit hunt mode/idle rcvd IRQs */
2801                         wr_reg16(info, SCR,
2802                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2803                 }
2804                 spin_unlock_irqrestore(&info->lock,flags);
2805         }
2806 exit:
2807         if (rc == 0)
2808                 rc = put_user(events, mask_ptr);
2809         return rc;
2810 }
2811
2812 static int get_interface(struct slgt_info *info, int __user *if_mode)
2813 {
2814         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2815         if (put_user(info->if_mode, if_mode))
2816                 return -EFAULT;
2817         return 0;
2818 }
2819
2820 static int set_interface(struct slgt_info *info, int if_mode)
2821 {
2822         unsigned long flags;
2823         unsigned short val;
2824
2825         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2826         spin_lock_irqsave(&info->lock,flags);
2827         info->if_mode = if_mode;
2828
2829         msc_set_vcr(info);
2830
2831         /* TCR (tx control) 07  1=RTS driver control */
2832         val = rd_reg16(info, TCR);
2833         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2834                 val |= BIT7;
2835         else
2836                 val &= ~BIT7;
2837         wr_reg16(info, TCR, val);
2838
2839         spin_unlock_irqrestore(&info->lock,flags);
2840         return 0;
2841 }
2842
2843 /*
2844  * set general purpose IO pin state and direction
2845  *
2846  * user_gpio fields:
2847  * state   each bit indicates a pin state
2848  * smask   set bit indicates pin state to set
2849  * dir     each bit indicates a pin direction (0=input, 1=output)
2850  * dmask   set bit indicates pin direction to set
2851  */
2852 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2853 {
2854         unsigned long flags;
2855         struct gpio_desc gpio;
2856         __u32 data;
2857
2858         if (!info->gpio_present)
2859                 return -EINVAL;
2860         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2861                 return -EFAULT;
2862         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2863                  info->device_name, gpio.state, gpio.smask,
2864                  gpio.dir, gpio.dmask));
2865
2866         spin_lock_irqsave(&info->lock,flags);
2867         if (gpio.dmask) {
2868                 data = rd_reg32(info, IODR);
2869                 data |= gpio.dmask & gpio.dir;
2870                 data &= ~(gpio.dmask & ~gpio.dir);
2871                 wr_reg32(info, IODR, data);
2872         }
2873         if (gpio.smask) {
2874                 data = rd_reg32(info, IOVR);
2875                 data |= gpio.smask & gpio.state;
2876                 data &= ~(gpio.smask & ~gpio.state);
2877                 wr_reg32(info, IOVR, data);
2878         }
2879         spin_unlock_irqrestore(&info->lock,flags);
2880
2881         return 0;
2882 }
2883
2884 /*
2885  * get general purpose IO pin state and direction
2886  */
2887 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2888 {
2889         struct gpio_desc gpio;
2890         if (!info->gpio_present)
2891                 return -EINVAL;
2892         gpio.state = rd_reg32(info, IOVR);
2893         gpio.smask = 0xffffffff;
2894         gpio.dir   = rd_reg32(info, IODR);
2895         gpio.dmask = 0xffffffff;
2896         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2897                 return -EFAULT;
2898         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2899                  info->device_name, gpio.state, gpio.dir));
2900         return 0;
2901 }
2902
2903 /*
2904  * conditional wait facility
2905  */
2906 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2907 {
2908         init_waitqueue_head(&w->q);
2909         init_waitqueue_entry(&w->wait, current);
2910         w->data = data;
2911 }
2912
2913 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2914 {
2915         set_current_state(TASK_INTERRUPTIBLE);
2916         add_wait_queue(&w->q, &w->wait);
2917         w->next = *head;
2918         *head = w;
2919 }
2920
2921 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2922 {
2923         struct cond_wait *w, *prev;
2924         remove_wait_queue(&cw->q, &cw->wait);
2925         set_current_state(TASK_RUNNING);
2926         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2927                 if (w == cw) {
2928                         if (prev != NULL)
2929                                 prev->next = w->next;
2930                         else
2931                                 *head = w->next;
2932                         break;
2933                 }
2934         }
2935 }
2936
2937 static void flush_cond_wait(struct cond_wait **head)
2938 {
2939         while (*head != NULL) {
2940                 wake_up_interruptible(&(*head)->q);
2941                 *head = (*head)->next;
2942         }
2943 }
2944
2945 /*
2946  * wait for general purpose I/O pin(s) to enter specified state
2947  *
2948  * user_gpio fields:
2949  * state - bit indicates target pin state
2950  * smask - set bit indicates watched pin
2951  *
2952  * The wait ends when at least one watched pin enters the specified
2953  * state. When 0 (no error) is returned, user_gpio->state is set to the
2954  * state of all GPIO pins when the wait ends.
2955  *
2956  * Note: Each pin may be a dedicated input, dedicated output, or
2957  * configurable input/output. The number and configuration of pins
2958  * varies with the specific adapter model. Only input pins (dedicated
2959  * or configured) can be monitored with this function.
2960  */
2961 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2962 {
2963         unsigned long flags;
2964         int rc = 0;
2965         struct gpio_desc gpio;
2966         struct cond_wait wait;
2967         u32 state;
2968
2969         if (!info->gpio_present)
2970                 return -EINVAL;
2971         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2972                 return -EFAULT;
2973         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2974                  info->device_name, gpio.state, gpio.smask));
2975         /* ignore output pins identified by set IODR bit */
2976         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2977                 return -EINVAL;
2978         init_cond_wait(&wait, gpio.smask);
2979
2980         spin_lock_irqsave(&info->lock, flags);
2981         /* enable interrupts for watched pins */
2982         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2983         /* get current pin states */
2984         state = rd_reg32(info, IOVR);
2985
2986         if (gpio.smask & ~(state ^ gpio.state)) {
2987                 /* already in target state */
2988                 gpio.state = state;
2989         } else {
2990                 /* wait for target state */
2991                 add_cond_wait(&info->gpio_wait_q, &wait);
2992                 spin_unlock_irqrestore(&info->lock, flags);
2993                 schedule();
2994                 if (signal_pending(current))
2995                         rc = -ERESTARTSYS;
2996                 else
2997                         gpio.state = wait.data;
2998                 spin_lock_irqsave(&info->lock, flags);
2999                 remove_cond_wait(&info->gpio_wait_q, &wait);
3000         }
3001
3002         /* disable all GPIO interrupts if no waiting processes */
3003         if (info->gpio_wait_q == NULL)
3004                 wr_reg32(info, IOER, 0);
3005         spin_unlock_irqrestore(&info->lock,flags);
3006
3007         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3008                 rc = -EFAULT;
3009         return rc;
3010 }
3011
3012 static int modem_input_wait(struct slgt_info *info,int arg)
3013 {
3014         unsigned long flags;
3015         int rc;
3016         struct mgsl_icount cprev, cnow;
3017         DECLARE_WAITQUEUE(wait, current);
3018
3019         /* save current irq counts */
3020         spin_lock_irqsave(&info->lock,flags);
3021         cprev = info->icount;
3022         add_wait_queue(&info->status_event_wait_q, &wait);
3023         set_current_state(TASK_INTERRUPTIBLE);
3024         spin_unlock_irqrestore(&info->lock,flags);
3025
3026         for(;;) {
3027                 schedule();
3028                 if (signal_pending(current)) {
3029                         rc = -ERESTARTSYS;
3030                         break;
3031                 }
3032
3033                 /* get new irq counts */
3034                 spin_lock_irqsave(&info->lock,flags);
3035                 cnow = info->icount;
3036                 set_current_state(TASK_INTERRUPTIBLE);
3037                 spin_unlock_irqrestore(&info->lock,flags);
3038
3039                 /* if no change, wait aborted for some reason */
3040                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3041                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3042                         rc = -EIO;
3043                         break;
3044                 }
3045
3046                 /* check for change in caller specified modem input */
3047                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3048                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3049                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3050                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3051                         rc = 0;
3052                         break;
3053                 }
3054
3055                 cprev = cnow;
3056         }
3057         remove_wait_queue(&info->status_event_wait_q, &wait);
3058         set_current_state(TASK_RUNNING);
3059         return rc;
3060 }
3061
3062 /*
3063  *  return state of serial control and status signals
3064  */
3065 static int tiocmget(struct tty_struct *tty, struct file *file)
3066 {
3067         struct slgt_info *info = tty->driver_data;
3068         unsigned int result;
3069         unsigned long flags;
3070
3071         spin_lock_irqsave(&info->lock,flags);
3072         get_signals(info);
3073         spin_unlock_irqrestore(&info->lock,flags);
3074
3075         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3076                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3077                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3078                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3079                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3080                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3081
3082         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3083         return result;
3084 }
3085
3086 /*
3087  * set modem control signals (DTR/RTS)
3088  *
3089  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3090  *              TIOCMSET = set/clear signal values
3091  *      value   bit mask for command
3092  */
3093 static int tiocmset(struct tty_struct *tty, struct file *file,
3094                     unsigned int set, unsigned int clear)
3095 {
3096         struct slgt_info *info = tty->driver_data;
3097         unsigned long flags;
3098
3099         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3100
3101         if (set & TIOCM_RTS)
3102                 info->signals |= SerialSignal_RTS;
3103         if (set & TIOCM_DTR)
3104                 info->signals |= SerialSignal_DTR;
3105         if (clear & TIOCM_RTS)
3106                 info->signals &= ~SerialSignal_RTS;
3107         if (clear & TIOCM_DTR)
3108                 info->signals &= ~SerialSignal_DTR;
3109
3110         spin_lock_irqsave(&info->lock,flags);
3111         set_signals(info);
3112         spin_unlock_irqrestore(&info->lock,flags);
3113         return 0;
3114 }
3115
3116 /*
3117  *  block current process until the device is ready to open
3118  */
3119 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3120                            struct slgt_info *info)
3121 {
3122         DECLARE_WAITQUEUE(wait, current);
3123         int             retval;
3124         bool            do_clocal = false;
3125         bool            extra_count = false;
3126         unsigned long   flags;
3127
3128         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3129
3130         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3131                 /* nonblock mode is set or port is not enabled */
3132                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3133                 return 0;
3134         }
3135
3136         if (tty->termios->c_cflag & CLOCAL)
3137                 do_clocal = true;
3138
3139         /* Wait for carrier detect and the line to become
3140          * free (i.e., not in use by the callout).  While we are in
3141          * this loop, info->port.count is dropped by one, so that
3142          * close() knows when to free things.  We restore it upon
3143          * exit, either normal or abnormal.
3144          */
3145
3146         retval = 0;
3147         add_wait_queue(&info->port.open_wait, &wait);
3148
3149         spin_lock_irqsave(&info->lock, flags);
3150         if (!tty_hung_up_p(filp)) {
3151                 extra_count = true;
3152                 info->port.count--;
3153         }
3154         spin_unlock_irqrestore(&info->lock, flags);
3155         info->port.blocked_open++;
3156
3157         while (1) {
3158                 if ((tty->termios->c_cflag & CBAUD)) {
3159                         spin_lock_irqsave(&info->lock,flags);
3160                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3161                         set_signals(info);
3162                         spin_unlock_irqrestore(&info->lock,flags);
3163                 }
3164
3165                 set_current_state(TASK_INTERRUPTIBLE);
3166
3167                 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3168                         retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3169                                         -EAGAIN : -ERESTARTSYS;
3170                         break;
3171                 }
3172
3173                 spin_lock_irqsave(&info->lock,flags);
3174                 get_signals(info);
3175                 spin_unlock_irqrestore(&info->lock,flags);
3176
3177                 if (!(info->port.flags & ASYNC_CLOSING) &&
3178                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3179                         break;
3180                 }
3181
3182                 if (signal_pending(current)) {
3183                         retval = -ERESTARTSYS;
3184                         break;
3185                 }
3186
3187                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3188                 schedule();
3189         }
3190
3191         set_current_state(TASK_RUNNING);
3192         remove_wait_queue(&info->port.open_wait, &wait);
3193
3194         if (extra_count)
3195                 info->port.count++;
3196         info->port.blocked_open--;
3197
3198         if (!retval)
3199                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3200
3201         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3202         return retval;
3203 }
3204
3205 static int alloc_tmp_rbuf(struct slgt_info *info)
3206 {
3207         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3208         if (info->tmp_rbuf == NULL)
3209                 return -ENOMEM;
3210         return 0;
3211 }
3212
3213 static void free_tmp_rbuf(struct slgt_info *info)
3214 {
3215         kfree(info->tmp_rbuf);
3216         info->tmp_rbuf = NULL;
3217 }
3218
3219 /*
3220  * allocate DMA descriptor lists.
3221  */
3222 static int alloc_desc(struct slgt_info *info)
3223 {
3224         unsigned int i;
3225         unsigned int pbufs;
3226
3227         /* allocate memory to hold descriptor lists */
3228         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3229         if (info->bufs == NULL)
3230                 return -ENOMEM;
3231
3232         memset(info->bufs, 0, DESC_LIST_SIZE);
3233
3234         info->rbufs = (struct slgt_desc*)info->bufs;
3235         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3236
3237         pbufs = (unsigned int)info->bufs_dma_addr;
3238
3239         /*
3240          * Build circular lists of descriptors
3241          */
3242
3243         for (i=0; i < info->rbuf_count; i++) {
3244                 /* physical address of this descriptor */
3245                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3246
3247                 /* physical address of next descriptor */
3248                 if (i == info->rbuf_count - 1)
3249                         info->rbufs[i].next = cpu_to_le32(pbufs);
3250                 else
3251                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3252                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3253         }
3254
3255         for (i=0; i < info->tbuf_count; i++) {
3256                 /* physical address of this descriptor */
3257                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3258
3259                 /* physical address of next descriptor */
3260                 if (i == info->tbuf_count - 1)
3261                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3262                 else
3263                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3264         }
3265
3266         return 0;
3267 }
3268
3269 static void free_desc(struct slgt_info *info)
3270 {
3271         if (info->bufs != NULL) {
3272                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3273                 info->bufs  = NULL;
3274                 info->rbufs = NULL;
3275                 info->tbufs = NULL;
3276         }
3277 }
3278
3279 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3280 {
3281         int i;
3282         for (i=0; i < count; i++) {
3283                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3284                         return -ENOMEM;
3285                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3286         }
3287         return 0;
3288 }
3289
3290 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3291 {
3292         int i;
3293         for (i=0; i < count; i++) {
3294                 if (bufs[i].buf == NULL)
3295                         continue;
3296                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3297                 bufs[i].buf = NULL;
3298         }
3299 }
3300
3301 static int alloc_dma_bufs(struct slgt_info *info)
3302 {
3303         info->rbuf_count = 32;
3304         info->tbuf_count = 32;
3305
3306         if (alloc_desc(info) < 0 ||
3307             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3308             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3309             alloc_tmp_rbuf(info) < 0) {
3310                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3311                 return -ENOMEM;
3312         }
3313         reset_rbufs(info);
3314         return 0;
3315 }
3316
3317 static void free_dma_bufs(struct slgt_info *info)
3318 {
3319         if (info->bufs) {
3320                 free_bufs(info, info->rbufs, info->rbuf_count);
3321                 free_bufs(info, info->tbufs, info->tbuf_count);
3322                 free_desc(info);
3323         }
3324         free_tmp_rbuf(info);
3325 }
3326
3327 static int claim_resources(struct slgt_info *info)
3328 {
3329         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3330                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3331                         info->device_name, info->phys_reg_addr));
3332                 info->init_error = DiagStatus_AddressConflict;
3333                 goto errout;
3334         }
3335         else
3336                 info->reg_addr_requested = true;
3337
3338         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3339         if (!info->reg_addr) {
3340                 DBGERR(("%s cant map device registers, addr=%08X\n",
3341                         info->device_name, info->phys_reg_addr));
3342                 info->init_error = DiagStatus_CantAssignPciResources;
3343                 goto errout;
3344         }
3345         return 0;
3346
3347 errout:
3348         release_resources(info);
3349         return -ENODEV;
3350 }
3351
3352 static void release_resources(struct slgt_info *info)
3353 {
3354         if (info->irq_requested) {
3355                 free_irq(info->irq_level, info);
3356                 info->irq_requested = false;
3357         }
3358
3359         if (info->reg_addr_requested) {
3360                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3361                 info->reg_addr_requested = false;
3362         }
3363
3364         if (info->reg_addr) {
3365                 iounmap(info->reg_addr);
3366                 info->reg_addr = NULL;
3367         }
3368 }
3369
3370 /* Add the specified device instance data structure to the
3371  * global linked list of devices and increment the device count.
3372  */
3373 static void add_device(struct slgt_info *info)
3374 {
3375         char *devstr;
3376
3377         info->next_device = NULL;
3378         info->line = slgt_device_count;
3379         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3380
3381         if (info->line < MAX_DEVICES) {
3382                 if (maxframe[info->line])
3383                         info->max_frame_size = maxframe[info->line];
3384         }
3385
3386         slgt_device_count++;
3387
3388         if (!slgt_device_list)
3389                 slgt_device_list = info;
3390         else {
3391                 struct slgt_info *current_dev = slgt_device_list;
3392                 while(current_dev->next_device)
3393                         current_dev = current_dev->next_device;
3394                 current_dev->next_device = info;
3395         }
3396
3397         if (info->max_frame_size < 4096)
3398                 info->max_frame_size = 4096;
3399         else if (info->max_frame_size > 65535)
3400                 info->max_frame_size = 65535;
3401
3402         switch(info->pdev->device) {
3403         case SYNCLINK_GT_DEVICE_ID:
3404                 devstr = "GT";
3405                 break;
3406         case SYNCLINK_GT2_DEVICE_ID:
3407                 devstr = "GT2";
3408                 break;
3409         case SYNCLINK_GT4_DEVICE_ID:
3410                 devstr = "GT4";
3411                 break;
3412         case SYNCLINK_AC_DEVICE_ID:
3413                 devstr = "AC";
3414                 info->params.mode = MGSL_MODE_ASYNC;
3415                 break;
3416         default:
3417                 devstr = "(unknown model)";
3418         }
3419         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3420                 devstr, info->device_name, info->phys_reg_addr,
3421                 info->irq_level, info->max_frame_size);
3422
3423 #if SYNCLINK_GENERIC_HDLC
3424         hdlcdev_init(info);
3425 #endif
3426 }
3427
3428 /*
3429  *  allocate device instance structure, return NULL on failure
3430  */
3431 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3432 {
3433         struct slgt_info *info;
3434
3435         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3436
3437         if (!info) {
3438                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3439                         driver_name, adapter_num, port_num));
3440         } else {
3441                 tty_port_init(&info->port);
3442                 info->magic = MGSL_MAGIC;
3443                 INIT_WORK(&info->task, bh_handler);
3444                 info->max_frame_size = 4096;
3445                 info->raw_rx_size = DMABUFSIZE;
3446                 info->port.close_delay = 5*HZ/10;
3447                 info->port.closing_wait = 30*HZ;
3448                 init_waitqueue_head(&info->status_event_wait_q);
3449                 init_waitqueue_head(&info->event_wait_q);
3450                 spin_lock_init(&info->netlock);
3451                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3452                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3453                 info->adapter_num = adapter_num;
3454                 info->port_num = port_num;
3455
3456                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3457                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3458
3459                 /* Copy configuration info to device instance data */
3460                 info->pdev = pdev;
3461                 info->irq_level = pdev->irq;
3462                 info->phys_reg_addr = pci_resource_start(pdev,0);
3463
3464                 info->bus_type = MGSL_BUS_TYPE_PCI;
3465                 info->irq_flags = IRQF_SHARED;
3466
3467                 info->init_error = -1; /* assume error, set to 0 on successful init */
3468         }
3469
3470         return info;
3471 }
3472
3473 static void device_init(int adapter_num, struct pci_dev *pdev)
3474 {
3475         struct slgt_info *port_array[SLGT_MAX_PORTS];
3476         int i;
3477         int port_count = 1;
3478
3479         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3480                 port_count = 2;
3481         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3482                 port_count = 4;
3483
3484         /* allocate device instances for all ports */
3485         for (i=0; i < port_count; ++i) {
3486                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3487                 if (port_array[i] == NULL) {
3488                         for (--i; i >= 0; --i)
3489                                 kfree(port_array[i]);
3490                         return;
3491                 }
3492         }
3493
3494         /* give copy of port_array to all ports and add to device list  */
3495         for (i=0; i < port_count; ++i) {
3496                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3497                 add_device(port_array[i]);
3498                 port_array[i]->port_count = port_count;
3499                 spin_lock_init(&port_array[i]->lock);
3500         }
3501
3502         /* Allocate and claim adapter resources */
3503         if (!claim_resources(port_array[0])) {
3504
3505                 alloc_dma_bufs(port_array[0]);
3506
3507                 /* copy resource information from first port to others */
3508                 for (i = 1; i < port_count; ++i) {
3509                         port_array[i]->lock      = port_array[0]->lock;
3510                         port_array[i]->irq_level = port_array[0]->irq_level;
3511                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3512                         alloc_dma_bufs(port_array[i]);
3513                 }
3514
3515                 if (request_irq(port_array[0]->irq_level,
3516                                         slgt_interrupt,
3517                                         port_array[0]->irq_flags,
3518                                         port_array[0]->device_name,
3519                                         port_array[0]) < 0) {
3520                         DBGERR(("%s request_irq failed IRQ=%d\n",
3521                                 port_array[0]->device_name,
3522                                 port_array[0]->irq_level));
3523                 } else {
3524                         port_array[0]->irq_requested = true;
3525                         adapter_test(port_array[0]);
3526                         for (i=1 ; i < port_count ; i++) {
3527                                 port_array[i]->init_error = port_array[0]->init_error;
3528                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3529                         }
3530                 }
3531         }
3532
3533         for (i=0; i < port_count; ++i)
3534                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3535 }
3536
3537 static int __devinit init_one(struct pci_dev *dev,
3538                               const struct pci_device_id *ent)
3539 {
3540         if (pci_enable_device(dev)) {
3541                 printk("error enabling pci device %p\n", dev);
3542                 return -EIO;
3543         }
3544         pci_set_master(dev);
3545         device_init(slgt_device_count, dev);
3546         return 0;
3547 }
3548
3549 static void __devexit remove_one(struct pci_dev *dev)
3550 {
3551 }
3552
3553 static const struct tty_operations ops = {
3554         .open = open,
3555         .close = close,
3556         .write = write,
3557         .put_char = put_char,
3558         .flush_chars = flush_chars,
3559         .write_room = write_room,
3560         .chars_in_buffer = chars_in_buffer,
3561         .flush_buffer = flush_buffer,
3562         .ioctl = ioctl,
3563         .compat_ioctl = slgt_compat_ioctl,
3564         .throttle = throttle,
3565         .unthrottle = unthrottle,
3566         .send_xchar = send_xchar,
3567         .break_ctl = set_break,
3568         .wait_until_sent = wait_until_sent,
3569         .read_proc = read_proc,
3570         .set_termios = set_termios,
3571         .stop = tx_hold,
3572         .start = tx_release,
3573         .hangup = hangup,
3574         .tiocmget = tiocmget,
3575         .tiocmset = tiocmset,
3576 };
3577
3578 static void slgt_cleanup(void)
3579 {
3580         int rc;
3581         struct slgt_info *info;
3582         struct slgt_info *tmp;
3583
3584         printk("unload %s %s\n", driver_name, driver_version);
3585
3586         if (serial_driver) {
3587                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3588                         tty_unregister_device(serial_driver, info->line);
3589                 if ((rc = tty_unregister_driver(serial_driver)))
3590                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3591                 put_tty_driver(serial_driver);
3592         }
3593
3594         /* reset devices */
3595         info = slgt_device_list;
3596         while(info) {
3597                 reset_port(info);
3598                 info = info->next_device;
3599         }
3600
3601         /* release devices */
3602         info = slgt_device_list;
3603         while(info) {
3604 #if SYNCLINK_GENERIC_HDLC
3605                 hdlcdev_exit(info);
3606 #endif
3607                 free_dma_bufs(info);
3608                 free_tmp_rbuf(info);
3609                 if (info->port_num == 0)
3610                         release_resources(info);
3611                 tmp = info;
3612                 info = info->next_device;
3613                 kfree(tmp);
3614         }
3615
3616         if (pci_registered)
3617                 pci_unregister_driver(&pci_driver);
3618 }
3619
3620 /*
3621  *  Driver initialization entry point.
3622  */
3623 static int __init slgt_init(void)
3624 {
3625         int rc;
3626
3627         printk("%s %s\n", driver_name, driver_version);
3628
3629         serial_driver = alloc_tty_driver(MAX_DEVICES);
3630         if (!serial_driver) {
3631                 printk("%s can't allocate tty driver\n", driver_name);
3632                 return -ENOMEM;
3633         }
3634
3635         /* Initialize the tty_driver structure */
3636
3637         serial_driver->owner = THIS_MODULE;
3638         serial_driver->driver_name = tty_driver_name;
3639         serial_driver->name = tty_dev_prefix;
3640         serial_driver->major = ttymajor;
3641         serial_driver->minor_start = 64;
3642         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3643         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3644         serial_driver->init_termios = tty_std_termios;
3645         serial_driver->init_termios.c_cflag =
3646                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3647         serial_driver->init_termios.c_ispeed = 9600;
3648         serial_driver->init_termios.c_ospeed = 9600;
3649         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3650         tty_set_operations(serial_driver, &ops);
3651         if ((rc = tty_register_driver(serial_driver)) < 0) {
3652                 DBGERR(("%s can't register serial driver\n", driver_name));
3653                 put_tty_driver(serial_driver);
3654                 serial_driver = NULL;
3655                 goto error;
3656         }
3657
3658         printk("%s %s, tty major#%d\n",
3659                 driver_name, driver_version,
3660                 serial_driver->major);
3661
3662         slgt_device_count = 0;
3663         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3664                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3665                 goto error;
3666         }
3667         pci_registered = true;
3668
3669         if (!slgt_device_list)
3670                 printk("%s no devices found\n",driver_name);
3671
3672         return 0;
3673
3674 error:
3675         slgt_cleanup();
3676         return rc;
3677 }
3678
3679 static void __exit slgt_exit(void)
3680 {
3681         slgt_cleanup();
3682 }
3683
3684 module_init(slgt_init);
3685 module_exit(slgt_exit);
3686
3687 /*
3688  * register access routines
3689  */
3690
3691 #define CALC_REGADDR() \
3692         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3693         if (addr >= 0x80) \
3694                 reg_addr += (info->port_num) * 32;
3695
3696 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3697 {
3698         CALC_REGADDR();
3699         return readb((void __iomem *)reg_addr);
3700 }
3701
3702 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3703 {
3704         CALC_REGADDR();
3705         writeb(value, (void __iomem *)reg_addr);
3706 }
3707
3708 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3709 {
3710         CALC_REGADDR();
3711         return readw((void __iomem *)reg_addr);
3712 }
3713
3714 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3715 {
3716         CALC_REGADDR();
3717         writew(value, (void __iomem *)reg_addr);
3718 }
3719
3720 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3721 {
3722         CALC_REGADDR();
3723         return readl((void __iomem *)reg_addr);
3724 }
3725
3726 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3727 {
3728         CALC_REGADDR();
3729         writel(value, (void __iomem *)reg_addr);
3730 }
3731
3732 static void rdma_reset(struct slgt_info *info)
3733 {
3734         unsigned int i;
3735
3736         /* set reset bit */
3737         wr_reg32(info, RDCSR, BIT1);
3738
3739         /* wait for enable bit cleared */
3740         for(i=0 ; i < 1000 ; i++)
3741                 if (!(rd_reg32(info, RDCSR) & BIT0))
3742                         break;
3743 }
3744
3745 static void tdma_reset(struct slgt_info *info)
3746 {
3747         unsigned int i;
3748
3749         /* set reset bit */
3750         wr_reg32(info, TDCSR, BIT1);
3751
3752         /* wait for enable bit cleared */
3753         for(i=0 ; i < 1000 ; i++)
3754                 if (!(rd_reg32(info, TDCSR) & BIT0))
3755                         break;
3756 }
3757
3758 /*
3759  * enable internal loopback
3760  * TxCLK and RxCLK are generated from BRG
3761  * and TxD is looped back to RxD internally.
3762  */
3763 static void enable_loopback(struct slgt_info *info)
3764 {
3765         /* SCR (serial control) BIT2=looopback enable */
3766         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3767
3768         if (info->params.mode != MGSL_MODE_ASYNC) {
3769                 /* CCR (clock control)
3770                  * 07..05  tx clock source (010 = BRG)
3771                  * 04..02  rx clock source (010 = BRG)
3772                  * 01      auxclk enable   (0 = disable)
3773                  * 00      BRG enable      (1 = enable)
3774                  *
3775                  * 0100 1001
3776                  */
3777                 wr_reg8(info, CCR, 0x49);
3778
3779                 /* set speed if available, otherwise use default */
3780                 if (info->params.clock_speed)
3781                         set_rate(info, info->params.clock_speed);
3782                 else
3783                         set_rate(info, 3686400);
3784         }
3785 }
3786
3787 /*
3788  *  set baud rate generator to specified rate
3789  */
3790 static void set_rate(struct slgt_info *info, u32 rate)
3791 {
3792         unsigned int div;
3793         static unsigned int osc = 14745600;
3794
3795         /* div = osc/rate - 1
3796          *
3797          * Round div up if osc/rate is not integer to
3798          * force to next slowest rate.
3799          */
3800
3801         if (rate) {
3802                 div = osc/rate;
3803                 if (!(osc % rate) && div)
3804                         div--;
3805                 wr_reg16(info, BDR, (unsigned short)div);
3806         }
3807 }
3808
3809 static void rx_stop(struct slgt_info *info)
3810 {
3811         unsigned short val;
3812
3813         /* disable and reset receiver */
3814         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3815         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3816         wr_reg16(info, RCR, val);                  /* clear reset bit */
3817
3818         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3819
3820         /* clear pending rx interrupts */
3821         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3822
3823         rdma_reset(info);
3824
3825         info->rx_enabled = false;
3826         info->rx_restart = false;
3827 }
3828
3829 static void rx_start(struct slgt_info *info)
3830 {
3831         unsigned short val;
3832
3833         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3834
3835         /* clear pending rx overrun IRQ */
3836         wr_reg16(info, SSR, IRQ_RXOVER);
3837
3838         /* reset and disable receiver */
3839         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3840         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3841         wr_reg16(info, RCR, val);                  /* clear reset bit */
3842
3843         rdma_reset(info);
3844         reset_rbufs(info);
3845
3846         /* set 1st descriptor address */
3847         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3848
3849         if (info->params.mode != MGSL_MODE_ASYNC) {
3850                 /* enable rx DMA and DMA interrupt */
3851                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3852         } else {
3853                 /* enable saving of rx status, rx DMA and DMA interrupt */
3854                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3855         }
3856
3857         slgt_irq_on(info, IRQ_RXOVER);
3858
3859         /* enable receiver */
3860         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3861
3862         info->rx_restart = false;
3863         info->rx_enabled = true;
3864 }
3865
3866 static void tx_start(struct slgt_info *info)
3867 {
3868         if (!info->tx_enabled) {
3869                 wr_reg16(info, TCR,
3870                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3871                 info->tx_enabled = true;
3872         }
3873
3874         if (info->tx_count) {
3875                 info->drop_rts_on_tx_done = false;
3876
3877                 if (info->params.mode != MGSL_MODE_ASYNC) {
3878                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3879                                 get_signals(info);
3880                                 if (!(info->signals & SerialSignal_RTS)) {
3881                                         info->signals |= SerialSignal_RTS;
3882                                         set_signals(info);
3883                                         info->drop_rts_on_tx_done = true;
3884                                 }
3885                         }
3886
3887                         slgt_irq_off(info, IRQ_TXDATA);
3888                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3889                         /* clear tx idle and underrun status bits */
3890                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3891                         if (info->params.mode == MGSL_MODE_HDLC)
3892                                 mod_timer(&info->tx_timer, jiffies +
3893                                                 msecs_to_jiffies(5000));
3894                 } else {
3895                         slgt_irq_off(info, IRQ_TXDATA);
3896                         slgt_irq_on(info, IRQ_TXIDLE);
3897                         /* clear tx idle status bit */
3898                         wr_reg16(info, SSR, IRQ_TXIDLE);
3899                 }
3900                 tdma_start(info);
3901                 info->tx_active = true;
3902         }
3903 }
3904
3905 /*
3906  * start transmit DMA if inactive and there are unsent buffers
3907  */
3908 static void tdma_start(struct slgt_info *info)
3909 {
3910         unsigned int i;
3911
3912         if (rd_reg32(info, TDCSR) & BIT0)
3913                 return;
3914
3915         /* transmit DMA inactive, check for unsent buffers */
3916         i = info->tbuf_start;
3917         while (!desc_count(info->tbufs[i])) {
3918                 if (++i == info->tbuf_count)
3919                         i = 0;
3920                 if (i == info->tbuf_current)
3921                         return;
3922         }
3923         info->tbuf_start = i;
3924
3925         /* there are unsent buffers, start transmit DMA */
3926
3927         /* reset needed if previous error condition */
3928         tdma_reset(info);
3929
3930         /* set 1st descriptor address */
3931         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3932         switch(info->params.mode) {
3933         case MGSL_MODE_RAW:
3934         case MGSL_MODE_MONOSYNC:
3935         case MGSL_MODE_BISYNC:
3936                 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3937                 break;
3938         default:
3939                 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3940         }
3941 }
3942
3943 static void tx_stop(struct slgt_info *info)
3944 {
3945         unsigned short val;
3946
3947         del_timer(&info->tx_timer);
3948
3949         tdma_reset(info);
3950
3951         /* reset and disable transmitter */
3952         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3953         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3954
3955         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3956
3957         /* clear tx idle and underrun status bit */
3958         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3959
3960         reset_tbufs(info);
3961
3962         info->tx_enabled = false;
3963         info->tx_active = false;
3964 }
3965
3966 static void reset_port(struct slgt_info *info)
3967 {
3968         if (!info->reg_addr)
3969                 return;
3970
3971         tx_stop(info);
3972         rx_stop(info);
3973
3974         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3975         set_signals(info);
3976
3977         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3978 }
3979
3980 static void reset_adapter(struct slgt_info *info)
3981 {
3982         int i;
3983         for (i=0; i < info->port_count; ++i) {
3984                 if (info->port_array[i])
3985                         reset_port(info->port_array[i]);
3986         }
3987 }
3988
3989 static void async_mode(struct slgt_info *info)
3990 {
3991         unsigned short val;
3992
3993         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3994         tx_stop(info);
3995         rx_stop(info);
3996
3997         /* TCR (tx control)
3998          *
3999          * 15..13  mode, 010=async
4000          * 12..10  encoding, 000=NRZ
4001          * 09      parity enable
4002          * 08      1=odd parity, 0=even parity
4003          * 07      1=RTS driver control
4004          * 06      1=break enable
4005          * 05..04  character length
4006          *         00=5 bits
4007          *         01=6 bits
4008          *         10=7 bits
4009          *         11=8 bits
4010          * 03      0=1 stop bit, 1=2 stop bits
4011          * 02      reset
4012          * 01      enable
4013          * 00      auto-CTS enable
4014          */
4015         val = 0x4000;
4016
4017         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4018                 val |= BIT7;
4019
4020         if (info->params.parity != ASYNC_PARITY_NONE) {
4021                 val |= BIT9;
4022                 if (info->params.parity == ASYNC_PARITY_ODD)
4023                         val |= BIT8;
4024         }
4025
4026         switch (info->params.data_bits)
4027         {
4028         case 6: val |= BIT4; break;
4029         case 7: val |= BIT5; break;
4030         case 8: val |= BIT5 + BIT4; break;
4031         }
4032
4033         if (info->params.stop_bits != 1)
4034                 val |= BIT3;
4035
4036         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4037                 val |= BIT0;
4038
4039         wr_reg16(info, TCR, val);
4040
4041         /* RCR (rx control)
4042          *
4043          * 15..13  mode, 010=async
4044          * 12..10  encoding, 000=NRZ
4045          * 09      parity enable
4046          * 08      1=odd parity, 0=even parity
4047          * 07..06  reserved, must be 0
4048          * 05..04  character length
4049          *         00=5 bits
4050          *         01=6 bits
4051          *         10=7 bits
4052          *         11=8 bits
4053          * 03      reserved, must be zero
4054          * 02      reset
4055          * 01      enable
4056          * 00      auto-DCD enable
4057          */
4058         val = 0x4000;
4059
4060         if (info->params.parity != ASYNC_PARITY_NONE) {
4061                 val |= BIT9;
4062                 if (info->params.parity == ASYNC_PARITY_ODD)
4063                         val |= BIT8;
4064         }
4065
4066         switch (info->params.data_bits)
4067         {
4068         case 6: val |= BIT4; break;
4069         case 7: val |= BIT5; break;
4070         case 8: val |= BIT5 + BIT4; break;
4071         }
4072
4073         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4074                 val |= BIT0;
4075
4076         wr_reg16(info, RCR, val);
4077
4078         /* CCR (clock control)
4079          *
4080          * 07..05  011 = tx clock source is BRG/16
4081          * 04..02  010 = rx clock source is BRG
4082          * 01      0 = auxclk disabled
4083          * 00      1 = BRG enabled
4084          *
4085          * 0110 1001
4086          */
4087         wr_reg8(info, CCR, 0x69);
4088
4089         msc_set_vcr(info);
4090
4091         /* SCR (serial control)
4092          *
4093          * 15  1=tx req on FIFO half empty
4094          * 14  1=rx req on FIFO half full
4095          * 13  tx data  IRQ enable
4096          * 12  tx idle  IRQ enable
4097          * 11  rx break on IRQ enable
4098          * 10  rx data  IRQ enable
4099          * 09  rx break off IRQ enable
4100          * 08  overrun  IRQ enable
4101          * 07  DSR      IRQ enable
4102          * 06  CTS      IRQ enable
4103          * 05  DCD      IRQ enable
4104          * 04  RI       IRQ enable
4105          * 03  reserved, must be zero
4106          * 02  1=txd->rxd internal loopback enable
4107          * 01  reserved, must be zero
4108          * 00  1=master IRQ enable
4109          */
4110         val = BIT15 + BIT14 + BIT0;
4111         wr_reg16(info, SCR, val);
4112
4113         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4114
4115         set_rate(info, info->params.data_rate * 16);
4116
4117         if (info->params.loopback)
4118                 enable_loopback(info);
4119 }
4120
4121 static void sync_mode(struct slgt_info *info)
4122 {
4123         unsigned short val;
4124
4125         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4126         tx_stop(info);
4127         rx_stop(info);
4128
4129         /* TCR (tx control)
4130          *
4131          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4132          * 12..10  encoding
4133          * 09      CRC enable
4134          * 08      CRC32
4135          * 07      1=RTS driver control
4136          * 06      preamble enable
4137          * 05..04  preamble length
4138          * 03      share open/close flag
4139          * 02      reset
4140          * 01      enable
4141          * 00      auto-CTS enable
4142          */
4143         val = 0;
4144
4145         switch(info->params.mode) {
4146         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4147         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4148         case MGSL_MODE_RAW:      val |= BIT13; break;
4149         }
4150         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4151                 val |= BIT7;
4152
4153         switch(info->params.encoding)
4154         {
4155         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4156         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4157         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4158         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4159         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4160         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4161         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4162         }
4163
4164         switch (info->params.crc_type & HDLC_CRC_MASK)
4165         {
4166         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4167         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4168         }
4169
4170         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4171                 val |= BIT6;
4172
4173         switch (info->params.preamble_length)
4174         {
4175         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4176         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4177         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4178         }
4179
4180         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4181                 val |= BIT0;
4182
4183         wr_reg16(info, TCR, val);
4184
4185         /* TPR (transmit preamble) */
4186
4187         switch (info->params.preamble)
4188         {
4189         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4190         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4191         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4192         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4193         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4194         default:                          val = 0x7e; break;
4195         }
4196         wr_reg8(info, TPR, (unsigned char)val);
4197
4198         /* RCR (rx control)
4199          *
4200          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4201          * 12..10  encoding
4202          * 09      CRC enable
4203          * 08      CRC32
4204          * 07..03  reserved, must be 0
4205          * 02      reset
4206          * 01      enable
4207          * 00      auto-DCD enable
4208          */
4209         val = 0;
4210
4211         switch(info->params.mode) {
4212         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4213         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4214         case MGSL_MODE_RAW:      val |= BIT13; break;
4215         }
4216
4217         switch(info->params.encoding)
4218         {
4219         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4220         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4221         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4222         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4223         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4224         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4225         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4226         }
4227
4228         switch (info->params.crc_type & HDLC_CRC_MASK)
4229         {
4230         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4231         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4232         }
4233
4234         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4235                 val |= BIT0;
4236
4237         wr_reg16(info, RCR, val);
4238
4239         /* CCR (clock control)
4240          *
4241          * 07..05  tx clock source
4242          * 04..02  rx clock source
4243          * 01      auxclk enable
4244          * 00      BRG enable
4245          */
4246         val = 0;
4247
4248         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4249         {
4250                 // when RxC source is DPLL, BRG generates 16X DPLL
4251                 // reference clock, so take TxC from BRG/16 to get
4252                 // transmit clock at actual data rate
4253                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4254                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4255                 else
4256                         val |= BIT6;    /* 010, txclk = BRG */
4257         }
4258         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4259                 val |= BIT7;    /* 100, txclk = DPLL Input */
4260         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4261                 val |= BIT5;    /* 001, txclk = RXC Input */
4262
4263         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4264                 val |= BIT3;    /* 010, rxclk = BRG */
4265         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4266                 val |= BIT4;    /* 100, rxclk = DPLL */
4267         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4268                 val |= BIT2;    /* 001, rxclk = TXC Input */
4269
4270         if (info->params.clock_speed)
4271                 val |= BIT1 + BIT0;
4272
4273         wr_reg8(info, CCR, (unsigned char)val);
4274
4275         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4276         {
4277                 // program DPLL mode
4278                 switch(info->params.encoding)
4279                 {
4280                 case HDLC_ENCODING_BIPHASE_MARK:
4281                 case HDLC_ENCODING_BIPHASE_SPACE:
4282                         val = BIT7; break;
4283                 case HDLC_ENCODING_BIPHASE_LEVEL:
4284                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4285                         val = BIT7 + BIT6; break;
4286                 default: val = BIT6;    // NRZ encodings
4287                 }
4288                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4289
4290                 // DPLL requires a 16X reference clock from BRG
4291                 set_rate(info, info->params.clock_speed * 16);
4292         }
4293         else
4294                 set_rate(info, info->params.clock_speed);
4295
4296         tx_set_idle(info);
4297
4298         msc_set_vcr(info);
4299
4300         /* SCR (serial control)
4301          *
4302          * 15  1=tx req on FIFO half empty
4303          * 14  1=rx req on FIFO half full
4304          * 13  tx data  IRQ enable
4305          * 12  tx idle  IRQ enable
4306          * 11  underrun IRQ enable
4307          * 10  rx data  IRQ enable
4308          * 09  rx idle  IRQ enable
4309          * 08  overrun  IRQ enable
4310          * 07  DSR      IRQ enable
4311          * 06  CTS      IRQ enable
4312          * 05  DCD      IRQ enable
4313          * 04  RI       IRQ enable
4314          * 03  reserved, must be zero
4315          * 02  1=txd->rxd internal loopback enable
4316          * 01  reserved, must be zero
4317          * 00  1=master IRQ enable
4318          */
4319         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4320
4321         if (info->params.loopback)
4322                 enable_loopback(info);
4323 }
4324
4325 /*
4326  *  set transmit idle mode
4327  */
4328 static void tx_set_idle(struct slgt_info *info)
4329 {
4330         unsigned char val;
4331         unsigned short tcr;
4332
4333         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4334          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4335          */
4336         tcr = rd_reg16(info, TCR);
4337         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4338                 /* disable preamble, set idle size to 16 bits */
4339                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4340                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4341                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4342         } else if (!(tcr & BIT6)) {
4343                 /* preamble is disabled, set idle size to 8 bits */
4344                 tcr &= ~(BIT5 + BIT4);
4345         }
4346         wr_reg16(info, TCR, tcr);
4347
4348         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4349                 /* LSB of custom tx idle specified in tx idle register */
4350                 val = (unsigned char)(info->idle_mode & 0xff);
4351         } else {
4352                 /* standard 8 bit idle patterns */
4353                 switch(info->idle_mode)
4354                 {
4355                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4356                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4357                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4358                 case HDLC_TXIDLE_ZEROS:
4359                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4360                 default:                         val = 0xff;
4361                 }
4362         }
4363
4364         wr_reg8(info, TIR, val);
4365 }
4366
4367 /*
4368  * get state of V24 status (input) signals
4369  */
4370 static void get_signals(struct slgt_info *info)
4371 {
4372         unsigned short status = rd_reg16(info, SSR);
4373
4374         /* clear all serial signals except DTR and RTS */
4375         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4376
4377         if (status & BIT3)
4378                 info->signals |= SerialSignal_DSR;
4379         if (status & BIT2)
4380                 info->signals |= SerialSignal_CTS;
4381         if (status & BIT1)
4382                 info->signals |= SerialSignal_DCD;
4383         if (status & BIT0)
4384                 info->signals |= SerialSignal_RI;
4385 }
4386
4387 /*
4388  * set V.24 Control Register based on current configuration
4389  */
4390 static void msc_set_vcr(struct slgt_info *info)
4391 {
4392         unsigned char val = 0;
4393
4394         /* VCR (V.24 control)
4395          *
4396          * 07..04  serial IF select
4397          * 03      DTR
4398          * 02      RTS
4399          * 01      LL
4400          * 00      RL
4401          */
4402
4403         switch(info->if_mode & MGSL_INTERFACE_MASK)
4404         {
4405         case MGSL_INTERFACE_RS232:
4406                 val |= BIT5; /* 0010 */
4407                 break;
4408         case MGSL_INTERFACE_V35:
4409                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4410                 break;
4411         case MGSL_INTERFACE_RS422:
4412                 val |= BIT6; /* 0100 */
4413                 break;
4414         }
4415
4416         if (info->signals & SerialSignal_DTR)
4417                 val |= BIT3;
4418         if (info->signals & SerialSignal_RTS)
4419                 val |= BIT2;
4420         if (info->if_mode & MGSL_INTERFACE_LL)
4421                 val |= BIT1;
4422         if (info->if_mode & MGSL_INTERFACE_RL)
4423                 val |= BIT0;
4424         wr_reg8(info, VCR, val);
4425 }
4426
4427 /*
4428  * set state of V24 control (output) signals
4429  */
4430 static void set_signals(struct slgt_info *info)
4431 {
4432         unsigned char val = rd_reg8(info, VCR);
4433         if (info->signals & SerialSignal_DTR)
4434                 val |= BIT3;
4435         else
4436                 val &= ~BIT3;
4437         if (info->signals & SerialSignal_RTS)
4438                 val |= BIT2;
4439         else
4440                 val &= ~BIT2;
4441         wr_reg8(info, VCR, val);
4442 }
4443
4444 /*
4445  * free range of receive DMA buffers (i to last)
4446  */
4447 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4448 {
4449         int done = 0;
4450
4451         while(!done) {
4452                 /* reset current buffer for reuse */
4453                 info->rbufs[i].status = 0;
4454                 switch(info->params.mode) {
4455                 case MGSL_MODE_RAW:
4456                 case MGSL_MODE_MONOSYNC:
4457                 case MGSL_MODE_BISYNC:
4458                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4459                         break;
4460                 default:
4461                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4462                 }
4463
4464                 if (i == last)
4465                         done = 1;
4466                 if (++i == info->rbuf_count)
4467                         i = 0;
4468         }
4469         info->rbuf_current = i;
4470 }
4471
4472 /*
4473  * mark all receive DMA buffers as free
4474  */
4475 static void reset_rbufs(struct slgt_info *info)
4476 {
4477         free_rbufs(info, 0, info->rbuf_count - 1);
4478 }
4479
4480 /*
4481  * pass receive HDLC frame to upper layer
4482  *
4483  * return true if frame available, otherwise false
4484  */
4485 static bool rx_get_frame(struct slgt_info *info)
4486 {
4487         unsigned int start, end;
4488         unsigned short status;
4489         unsigned int framesize = 0;
4490         unsigned long flags;
4491         struct tty_struct *tty = info->port.tty;
4492         unsigned char addr_field = 0xff;
4493         unsigned int crc_size = 0;
4494
4495         switch (info->params.crc_type & HDLC_CRC_MASK) {
4496         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4497         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4498         }
4499
4500 check_again:
4501
4502         framesize = 0;
4503         addr_field = 0xff;
4504         start = end = info->rbuf_current;
4505
4506         for (;;) {
4507                 if (!desc_complete(info->rbufs[end]))
4508                         goto cleanup;
4509
4510                 if (framesize == 0 && info->params.addr_filter != 0xff)
4511                         addr_field = info->rbufs[end].buf[0];
4512
4513                 framesize += desc_count(info->rbufs[end]);
4514
4515                 if (desc_eof(info->rbufs[end]))
4516                         break;
4517
4518                 if (++end == info->rbuf_count)
4519                         end = 0;
4520
4521                 if (end == info->rbuf_current) {
4522                         if (info->rx_enabled){
4523                                 spin_lock_irqsave(&info->lock,flags);
4524                                 rx_start(info);
4525                                 spin_unlock_irqrestore(&info->lock,flags);
4526                         }
4527                         goto cleanup;
4528                 }
4529         }
4530
4531         /* status
4532          *
4533          * 15      buffer complete
4534          * 14..06  reserved
4535          * 05..04  residue
4536          * 02      eof (end of frame)
4537          * 01      CRC error
4538          * 00      abort
4539          */
4540         status = desc_status(info->rbufs[end]);
4541
4542         /* ignore CRC bit if not using CRC (bit is undefined) */
4543         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4544                 status &= ~BIT1;
4545
4546         if (framesize == 0 ||
4547                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4548                 free_rbufs(info, start, end);
4549                 goto check_again;
4550         }
4551
4552         if (framesize < (2 + crc_size) || status & BIT0) {
4553                 info->icount.rxshort++;
4554                 framesize = 0;
4555         } else if (status & BIT1) {
4556                 info->icount.rxcrc++;
4557                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4558                         framesize = 0;
4559         }
4560
4561 #if SYNCLINK_GENERIC_HDLC
4562         if (framesize == 0) {
4563                 info->netdev->stats.rx_errors++;
4564                 info->netdev->stats.rx_frame_errors++;
4565         }
4566 #endif
4567
4568         DBGBH(("%s rx frame status=%04X size=%d\n",
4569                 info->device_name, status, framesize));
4570         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4571
4572         if (framesize) {
4573                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4574                         framesize -= crc_size;
4575                         crc_size = 0;
4576                 }
4577
4578                 if (framesize > info->max_frame_size + crc_size)
4579                         info->icount.rxlong++;
4580                 else {
4581                         /* copy dma buffer(s) to contiguous temp buffer */
4582                         int copy_count = framesize;
4583                         int i = start;
4584                         unsigned char *p = info->tmp_rbuf;
4585                         info->tmp_rbuf_count = framesize;
4586
4587                         info->icount.rxok++;
4588
4589                         while(copy_count) {
4590                                 int partial_count = min(copy_count, DMABUFSIZE);
4591                                 memcpy(p, info->rbufs[i].buf, partial_count);
4592                                 p += partial_count;
4593                                 copy_count -= partial_count;
4594                                 if (++i == info->rbuf_count)
4595                                         i = 0;
4596                         }
4597
4598                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4599                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4600                                 framesize++;
4601                         }
4602
4603 #if SYNCLINK_GENERIC_HDLC
4604                         if (info->netcount)
4605                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4606                         else
4607 #endif
4608                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4609                 }
4610         }
4611         free_rbufs(info, start, end);
4612         return true;
4613
4614 cleanup:
4615         return false;
4616 }
4617
4618 /*
4619  * pass receive buffer (RAW synchronous mode) to tty layer
4620  * return true if buffer available, otherwise false
4621  */
4622 static bool rx_get_buf(struct slgt_info *info)
4623 {
4624         unsigned int i = info->rbuf_current;
4625         unsigned int count;
4626
4627         if (!desc_complete(info->rbufs[i]))
4628                 return false;
4629         count = desc_count(info->rbufs[i]);
4630         switch(info->params.mode) {
4631         case MGSL_MODE_MONOSYNC:
4632         case MGSL_MODE_BISYNC:
4633                 /* ignore residue in byte synchronous modes */
4634                 if (desc_residue(info->rbufs[i]))
4635                         count--;
4636                 break;
4637         }
4638         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4639         DBGINFO(("rx_get_buf size=%d\n", count));
4640         if (count)
4641                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4642                                   info->flag_buf, count);
4643         free_rbufs(info, i, i);
4644         return true;
4645 }
4646
4647 static void reset_tbufs(struct slgt_info *info)
4648 {
4649         unsigned int i;
4650         info->tbuf_current = 0;
4651         for (i=0 ; i < info->tbuf_count ; i++) {
4652                 info->tbufs[i].status = 0;
4653                 info->tbufs[i].count  = 0;
4654         }
4655 }
4656
4657 /*
4658  * return number of free transmit DMA buffers
4659  */
4660 static unsigned int free_tbuf_count(struct slgt_info *info)
4661 {
4662         unsigned int count = 0;
4663         unsigned int i = info->tbuf_current;
4664
4665         do
4666         {
4667                 if (desc_count(info->tbufs[i]))
4668                         break; /* buffer in use */
4669                 ++count;
4670                 if (++i == info->tbuf_count)
4671                         i=0;
4672         } while (i != info->tbuf_current);
4673
4674         /* if tx DMA active, last zero count buffer is in use */
4675         if (count && (rd_reg32(info, TDCSR) & BIT0))
4676                 --count;
4677
4678         return count;
4679 }
4680
4681 /*
4682  * load transmit DMA buffer(s) with data
4683  */
4684 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4685 {
4686         unsigned short count;
4687         unsigned int i;
4688         struct slgt_desc *d;
4689
4690         if (size == 0)
4691                 return;
4692
4693         DBGDATA(info, buf, size, "tx");
4694
4695         info->tbuf_start = i = info->tbuf_current;
4696
4697         while (size) {
4698                 d = &info->tbufs[i];
4699                 if (++i == info->tbuf_count)
4700                         i = 0;
4701
4702                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4703                 memcpy(d->buf, buf, count);
4704
4705                 size -= count;
4706                 buf  += count;
4707
4708                 /*
4709                  * set EOF bit for last buffer of HDLC frame or
4710                  * for every buffer in raw mode
4711                  */
4712                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4713                     info->params.mode == MGSL_MODE_RAW)
4714                         set_desc_eof(*d, 1);
4715                 else
4716                         set_desc_eof(*d, 0);
4717
4718                 set_desc_count(*d, count);
4719         }
4720
4721         info->tbuf_current = i;
4722 }
4723
4724 static int register_test(struct slgt_info *info)
4725 {
4726         static unsigned short patterns[] =
4727                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4728         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4729         unsigned int i;
4730         int rc = 0;
4731
4732         for (i=0 ; i < count ; i++) {
4733                 wr_reg16(info, TIR, patterns[i]);
4734                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4735                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4736                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4737                         rc = -ENODEV;
4738                         break;
4739                 }
4740         }
4741         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4742         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4743         return rc;
4744 }
4745
4746 static int irq_test(struct slgt_info *info)
4747 {
4748         unsigned long timeout;
4749         unsigned long flags;
4750         struct tty_struct *oldtty = info->port.tty;
4751         u32 speed = info->params.data_rate;
4752
4753         info->params.data_rate = 921600;
4754         info->port.tty = NULL;
4755
4756         spin_lock_irqsave(&info->lock, flags);
4757         async_mode(info);
4758         slgt_irq_on(info, IRQ_TXIDLE);
4759
4760         /* enable transmitter */
4761         wr_reg16(info, TCR,
4762                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4763
4764         /* write one byte and wait for tx idle */
4765         wr_reg16(info, TDR, 0);
4766
4767         /* assume failure */
4768         info->init_error = DiagStatus_IrqFailure;
4769         info->irq_occurred = false;
4770
4771         spin_unlock_irqrestore(&info->lock, flags);
4772
4773         timeout=100;
4774         while(timeout-- && !info->irq_occurred)
4775                 msleep_interruptible(10);
4776
4777         spin_lock_irqsave(&info->lock,flags);
4778         reset_port(info);
4779         spin_unlock_irqrestore(&info->lock,flags);
4780
4781         info->params.data_rate = speed;
4782         info->port.tty = oldtty;
4783
4784         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4785         return info->irq_occurred ? 0 : -ENODEV;
4786 }
4787
4788 static int loopback_test_rx(struct slgt_info *info)
4789 {
4790         unsigned char *src, *dest;
4791         int count;
4792
4793         if (desc_complete(info->rbufs[0])) {
4794                 count = desc_count(info->rbufs[0]);
4795                 src   = info->rbufs[0].buf;
4796                 dest  = info->tmp_rbuf;
4797
4798                 for( ; count ; count-=2, src+=2) {
4799                         /* src=data byte (src+1)=status byte */
4800                         if (!(*(src+1) & (BIT9 + BIT8))) {
4801                                 *dest = *src;
4802                                 dest++;
4803                                 info->tmp_rbuf_count++;
4804                         }
4805                 }
4806                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4807                 return 1;
4808         }
4809         return 0;
4810 }
4811
4812 static int loopback_test(struct slgt_info *info)
4813 {
4814 #define TESTFRAMESIZE 20
4815
4816         unsigned long timeout;
4817         u16 count = TESTFRAMESIZE;
4818         unsigned char buf[TESTFRAMESIZE];
4819         int rc = -ENODEV;
4820         unsigned long flags;
4821
4822         struct tty_struct *oldtty = info->port.tty;
4823         MGSL_PARAMS params;
4824
4825         memcpy(&params, &info->params, sizeof(params));
4826
4827         info->params.mode = MGSL_MODE_ASYNC;
4828         info->params.data_rate = 921600;
4829         info->params.loopback = 1;
4830         info->port.tty = NULL;
4831
4832         /* build and send transmit frame */
4833         for (count = 0; count < TESTFRAMESIZE; ++count)
4834                 buf[count] = (unsigned char)count;
4835
4836         info->tmp_rbuf_count = 0;
4837         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4838
4839         /* program hardware for HDLC and enabled receiver */
4840         spin_lock_irqsave(&info->lock,flags);
4841         async_mode(info);
4842         rx_start(info);
4843         info->tx_count = count;
4844         tx_load(info, buf, count);
4845         tx_start(info);
4846         spin_unlock_irqrestore(&info->lock, flags);
4847
4848         /* wait for receive complete */
4849         for (timeout = 100; timeout; --timeout) {
4850                 msleep_interruptible(10);
4851                 if (loopback_test_rx(info)) {
4852                         rc = 0;
4853                         break;
4854                 }
4855         }
4856
4857         /* verify received frame length and contents */
4858         if (!rc && (info->tmp_rbuf_count != count ||
4859                   memcmp(buf, info->tmp_rbuf, count))) {
4860                 rc = -ENODEV;
4861         }
4862
4863         spin_lock_irqsave(&info->lock,flags);
4864         reset_adapter(info);
4865         spin_unlock_irqrestore(&info->lock,flags);
4866
4867         memcpy(&info->params, &params, sizeof(info->params));
4868         info->port.tty = oldtty;
4869
4870         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4871         return rc;
4872 }
4873
4874 static int adapter_test(struct slgt_info *info)
4875 {
4876         DBGINFO(("testing %s\n", info->device_name));
4877         if (register_test(info) < 0) {
4878                 printk("register test failure %s addr=%08X\n",
4879                         info->device_name, info->phys_reg_addr);
4880         } else if (irq_test(info) < 0) {
4881                 printk("IRQ test failure %s IRQ=%d\n",
4882                         info->device_name, info->irq_level);
4883         } else if (loopback_test(info) < 0) {
4884                 printk("loopback test failure %s\n", info->device_name);
4885         }
4886         return info->init_error;
4887 }
4888
4889 /*
4890  * transmit timeout handler
4891  */
4892 static void tx_timeout(unsigned long context)
4893 {
4894         struct slgt_info *info = (struct slgt_info*)context;
4895         unsigned long flags;
4896
4897         DBGINFO(("%s tx_timeout\n", info->device_name));
4898         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4899                 info->icount.txtimeout++;
4900         }
4901         spin_lock_irqsave(&info->lock,flags);
4902         info->tx_active = false;
4903         info->tx_count = 0;
4904         spin_unlock_irqrestore(&info->lock,flags);
4905
4906 #if SYNCLINK_GENERIC_HDLC
4907         if (info->netcount)
4908                 hdlcdev_tx_done(info);
4909         else
4910 #endif
4911                 bh_transmit(info);
4912 }
4913
4914 /*
4915  * receive buffer polling timer
4916  */
4917 static void rx_timeout(unsigned long context)
4918 {
4919         struct slgt_info *info = (struct slgt_info*)context;
4920         unsigned long flags;
4921
4922         DBGINFO(("%s rx_timeout\n", info->device_name));
4923         spin_lock_irqsave(&info->lock, flags);
4924         info->pending_bh |= BH_RECEIVE;
4925         spin_unlock_irqrestore(&info->lock, flags);
4926         bh_handler(&info->task);
4927 }
4928