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   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76 #include <linux/synclink.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  86 #define SYNCLINK_GENERIC_HDLC 1
  87 #else
  88 #define SYNCLINK_GENERIC_HDLC 0
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.50 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 32
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {0,}, /* terminate list */
 108 };
 109 MODULE_DEVICE_TABLE(pci, pci_table);
 110
 111 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 112 static void remove_one(struct pci_dev *dev);
 113 static struct pci_driver pci_driver = {
 114         .name           = "synclink_gt",
 115         .id_table       = pci_table,
 116         .probe          = init_one,
 117         .remove         = __devexit_p(remove_one),
 118 };
 119
 120 static bool pci_registered;
 121
 122 /*
 123  * module configuration and status
 124  */
 125 static struct slgt_info *slgt_device_list;
 126 static int slgt_device_count;
 127
 128 static int ttymajor;
 129 static int debug_level;
 130 static int maxframe[MAX_DEVICES];
 131 static int dosyncppp[MAX_DEVICES];
 132
 133 module_param(ttymajor, int, 0);
 134 module_param(debug_level, int, 0);
 135 module_param_array(maxframe, int, NULL, 0);
 136 module_param_array(dosyncppp, int, NULL, 0);
 137
 138 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 139 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 140 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 141 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 142
 143 /*
 144  * tty support and callbacks
 145  */
 146 static struct tty_driver *serial_driver;
 147
 148 static int  open(struct tty_struct *tty, struct file * filp);
 149 static void close(struct tty_struct *tty, struct file * filp);
 150 static void hangup(struct tty_struct *tty);
 151 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 152
 153 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 154 static int put_char(struct tty_struct *tty, unsigned char ch);
 155 static void send_xchar(struct tty_struct *tty, char ch);
 156 static void wait_until_sent(struct tty_struct *tty, int timeout);
 157 static int  write_room(struct tty_struct *tty);
 158 static void flush_chars(struct tty_struct *tty);
 159 static void flush_buffer(struct tty_struct *tty);
 160 static void tx_hold(struct tty_struct *tty);
 161 static void tx_release(struct tty_struct *tty);
 162
 163 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 164 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 165 static int  chars_in_buffer(struct tty_struct *tty);
 166 static void throttle(struct tty_struct * tty);
 167 static void unthrottle(struct tty_struct * tty);
 168 static void set_break(struct tty_struct *tty, int break_state);
 169
 170 /*
 171  * generic HDLC support and callbacks
 172  */
 173 #if SYNCLINK_GENERIC_HDLC
 174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 175 static void hdlcdev_tx_done(struct slgt_info *info);
 176 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 177 static int  hdlcdev_init(struct slgt_info *info);
 178 static void hdlcdev_exit(struct slgt_info *info);
 179 #endif
 180
 181
 182 /*
 183  * device specific structures, macros and functions
 184  */
 185
 186 #define SLGT_MAX_PORTS 4
 187 #define SLGT_REG_SIZE  256
 188
 189 /*
 190  * conditional wait facility
 191  */
 192 struct cond_wait {
 193         struct cond_wait *next;
 194         wait_queue_head_t q;
 195         wait_queue_t wait;
 196         unsigned int data;
 197 };
 198 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 199 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 200 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void flush_cond_wait(struct cond_wait **head);
 202
 203 /*
 204  * DMA buffer descriptor and access macros
 205  */
 206 struct slgt_desc
 207 {
 208         __le16 count;
 209         __le16 status;
 210         __le32 pbuf;  /* physical address of data buffer */
 211         __le32 next;  /* physical address of next descriptor */
 212
 213         /* driver book keeping */
 214         char *buf;          /* virtual  address of data buffer */
 215         unsigned int pdesc; /* physical address of this descriptor */
 216         dma_addr_t buf_dma_addr;
 217 };
 218
 219 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 220 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 222 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 223 #define desc_count(a)      (le16_to_cpu((a).count))
 224 #define desc_status(a)     (le16_to_cpu((a).status))
 225 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 226 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 227 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 228 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 229 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 230
 231 struct _input_signal_events {
 232         int ri_up;
 233         int ri_down;
 234         int dsr_up;
 235         int dsr_down;
 236         int dcd_up;
 237         int dcd_down;
 238         int cts_up;
 239         int cts_down;
 240 };
 241
 242 /*
 243  * device instance data structure
 244  */
 245 struct slgt_info {
 246         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 247
 248         struct slgt_info *next_device;  /* device list link */
 249
 250         int magic;
 251         int flags;
 252
 253         char device_name[25];
 254         struct pci_dev *pdev;
 255
 256         int port_count;  /* count of ports on adapter */
 257         int adapter_num; /* adapter instance number */
 258         int port_num;    /* port instance number */
 259
 260         /* array of pointers to port contexts on this adapter */
 261         struct slgt_info *port_array[SLGT_MAX_PORTS];
 262
 263         int                     count;          /* count of opens */
 264         int                     line;           /* tty line instance number */
 265         unsigned short          close_delay;
 266         unsigned short          closing_wait;   /* time to wait before closing */
 267
 268         struct mgsl_icount      icount;
 269
 270         struct tty_struct       *tty;
 271         int                     timeout;
 272         int                     x_char;         /* xon/xoff character */
 273         int                     blocked_open;   /* # of blocked opens */
 274         unsigned int            read_status_mask;
 275         unsigned int            ignore_status_mask;
 276
 277         wait_queue_head_t       open_wait;
 278         wait_queue_head_t       close_wait;
 279
 280         wait_queue_head_t       status_event_wait_q;
 281         wait_queue_head_t       event_wait_q;
 282         struct timer_list       tx_timer;
 283         struct timer_list       rx_timer;
 284
 285         unsigned int            gpio_present;
 286         struct cond_wait        *gpio_wait_q;
 287
 288         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 289
 290         struct work_struct task;
 291         u32 pending_bh;
 292         bool bh_requested;
 293         bool bh_running;
 294
 295         int isr_overflow;
 296         bool irq_requested;     /* true if IRQ requested */
 297         bool irq_occurred;      /* for diagnostics use */
 298
 299         /* device configuration */
 300
 301         unsigned int bus_type;
 302         unsigned int irq_level;
 303         unsigned long irq_flags;
 304
 305         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 306         u32 phys_reg_addr;
 307         bool reg_addr_requested;
 308
 309         MGSL_PARAMS params;       /* communications parameters */
 310         u32 idle_mode;
 311         u32 max_frame_size;       /* as set by device config */
 312
 313         unsigned int raw_rx_size;
 314         unsigned int if_mode;
 315
 316         /* device status */
 317
 318         bool rx_enabled;
 319         bool rx_restart;
 320
 321         bool tx_enabled;
 322         bool tx_active;
 323
 324         unsigned char signals;    /* serial signal states */
 325         int init_error;  /* initialization error */
 326
 327         unsigned char *tx_buf;
 328         int tx_count;
 329
 330         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 331         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 332         bool drop_rts_on_tx_done;
 333         struct  _input_signal_events    input_signal_events;
 334
 335         int dcd_chkcount;       /* check counts to prevent */
 336         int cts_chkcount;       /* too many IRQs if a signal */
 337         int dsr_chkcount;       /* is floating */
 338         int ri_chkcount;
 339
 340         char *bufs;             /* virtual address of DMA buffer lists */
 341         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 342
 343         unsigned int rbuf_count;
 344         struct slgt_desc *rbufs;
 345         unsigned int rbuf_current;
 346         unsigned int rbuf_index;
 347
 348         unsigned int tbuf_count;
 349         struct slgt_desc *tbufs;
 350         unsigned int tbuf_current;
 351         unsigned int tbuf_start;
 352
 353         unsigned char *tmp_rbuf;
 354         unsigned int tmp_rbuf_count;
 355
 356         /* SPPP/Cisco HDLC device parts */
 357
 358         int netcount;
 359         int dosyncppp;
 360         spinlock_t netlock;
 361 #if SYNCLINK_GENERIC_HDLC
 362         struct net_device *netdev;
 363 #endif
 364
 365 };
 366
 367 static MGSL_PARAMS default_params = {
 368         .mode            = MGSL_MODE_HDLC,
 369         .loopback        = 0,
 370         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 371         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 372         .clock_speed     = 0,
 373         .addr_filter     = 0xff,
 374         .crc_type        = HDLC_CRC_16_CCITT,
 375         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 376         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 377         .data_rate       = 9600,
 378         .data_bits       = 8,
 379         .stop_bits       = 1,
 380         .parity          = ASYNC_PARITY_NONE
 381 };
 382
 383
 384 #define BH_RECEIVE  1
 385 #define BH_TRANSMIT 2
 386 #define BH_STATUS   4
 387 #define IO_PIN_SHUTDOWN_LIMIT 100
 388
 389 #define DMABUFSIZE 256
 390 #define DESC_LIST_SIZE 4096
 391
 392 #define MASK_PARITY  BIT1
 393 #define MASK_FRAMING BIT0
 394 #define MASK_BREAK   BIT14
 395 #define MASK_OVERRUN BIT4
 396
 397 #define GSR   0x00 /* global status */
 398 #define JCR   0x04 /* JTAG control */
 399 #define IODR  0x08 /* GPIO direction */
 400 #define IOER  0x0c /* GPIO interrupt enable */
 401 #define IOVR  0x10 /* GPIO value */
 402 #define IOSR  0x14 /* GPIO interrupt status */
 403 #define TDR   0x80 /* tx data */
 404 #define RDR   0x80 /* rx data */
 405 #define TCR   0x82 /* tx control */
 406 #define TIR   0x84 /* tx idle */
 407 #define TPR   0x85 /* tx preamble */
 408 #define RCR   0x86 /* rx control */
 409 #define VCR   0x88 /* V.24 control */
 410 #define CCR   0x89 /* clock control */
 411 #define BDR   0x8a /* baud divisor */
 412 #define SCR   0x8c /* serial control */
 413 #define SSR   0x8e /* serial status */
 414 #define RDCSR 0x90 /* rx DMA control/status */
 415 #define TDCSR 0x94 /* tx DMA control/status */
 416 #define RDDAR 0x98 /* rx DMA descriptor address */
 417 #define TDDAR 0x9c /* tx DMA descriptor address */
 418
 419 #define RXIDLE      BIT14
 420 #define RXBREAK     BIT14
 421 #define IRQ_TXDATA  BIT13
 422 #define IRQ_TXIDLE  BIT12
 423 #define IRQ_TXUNDER BIT11 /* HDLC */
 424 #define IRQ_RXDATA  BIT10
 425 #define IRQ_RXIDLE  BIT9  /* HDLC */
 426 #define IRQ_RXBREAK BIT9  /* async */
 427 #define IRQ_RXOVER  BIT8
 428 #define IRQ_DSR     BIT7
 429 #define IRQ_CTS     BIT6
 430 #define IRQ_DCD     BIT5
 431 #define IRQ_RI      BIT4
 432 #define IRQ_ALL     0x3ff0
 433 #define IRQ_MASTER  BIT0
 434
 435 #define slgt_irq_on(info, mask) \
 436         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 437 #define slgt_irq_off(info, mask) \
 438         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 439
 440 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 441 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 442 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 443 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 444 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 445 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 446
 447 static void  msc_set_vcr(struct slgt_info *info);
 448
 449 static int  startup(struct slgt_info *info);
 450 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 451 static void shutdown(struct slgt_info *info);
 452 static void program_hw(struct slgt_info *info);
 453 static void change_params(struct slgt_info *info);
 454
 455 static int  register_test(struct slgt_info *info);
 456 static int  irq_test(struct slgt_info *info);
 457 static int  loopback_test(struct slgt_info *info);
 458 static int  adapter_test(struct slgt_info *info);
 459
 460 static void reset_adapter(struct slgt_info *info);
 461 static void reset_port(struct slgt_info *info);
 462 static void async_mode(struct slgt_info *info);
 463 static void sync_mode(struct slgt_info *info);
 464
 465 static void rx_stop(struct slgt_info *info);
 466 static void rx_start(struct slgt_info *info);
 467 static void reset_rbufs(struct slgt_info *info);
 468 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 469 static void rdma_reset(struct slgt_info *info);
 470 static bool rx_get_frame(struct slgt_info *info);
 471 static bool rx_get_buf(struct slgt_info *info);
 472
 473 static void tx_start(struct slgt_info *info);
 474 static void tx_stop(struct slgt_info *info);
 475 static void tx_set_idle(struct slgt_info *info);
 476 static unsigned int free_tbuf_count(struct slgt_info *info);
 477 static void reset_tbufs(struct slgt_info *info);
 478 static void tdma_reset(struct slgt_info *info);
 479 static void tdma_start(struct slgt_info *info);
 480 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 481
 482 static void get_signals(struct slgt_info *info);
 483 static void set_signals(struct slgt_info *info);
 484 static void enable_loopback(struct slgt_info *info);
 485 static void set_rate(struct slgt_info *info, u32 data_rate);
 486
 487 static int  bh_action(struct slgt_info *info);
 488 static void bh_handler(struct work_struct *work);
 489 static void bh_transmit(struct slgt_info *info);
 490 static void isr_serial(struct slgt_info *info);
 491 static void isr_rdma(struct slgt_info *info);
 492 static void isr_txeom(struct slgt_info *info, unsigned short status);
 493 static void isr_tdma(struct slgt_info *info);
 494
 495 static int  alloc_dma_bufs(struct slgt_info *info);
 496 static void free_dma_bufs(struct slgt_info *info);
 497 static int  alloc_desc(struct slgt_info *info);
 498 static void free_desc(struct slgt_info *info);
 499 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 500 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 501
 502 static int  alloc_tmp_rbuf(struct slgt_info *info);
 503 static void free_tmp_rbuf(struct slgt_info *info);
 504
 505 static void tx_timeout(unsigned long context);
 506 static void rx_timeout(unsigned long context);
 507
 508 /*
 509  * ioctl handlers
 510  */
 511 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 512 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 513 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 514 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 515 static int  set_txidle(struct slgt_info *info, int idle_mode);
 516 static int  tx_enable(struct slgt_info *info, int enable);
 517 static int  tx_abort(struct slgt_info *info);
 518 static int  rx_enable(struct slgt_info *info, int enable);
 519 static int  modem_input_wait(struct slgt_info *info,int arg);
 520 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 521 static int  tiocmget(struct tty_struct *tty, struct file *file);
 522 static int  tiocmset(struct tty_struct *tty, struct file *file,
 523                      unsigned int set, unsigned int clear);
 524 static void set_break(struct tty_struct *tty, int break_state);
 525 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 526 static int  set_interface(struct slgt_info *info, int if_mode);
 527 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 528 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 529 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 530
 531 /*
 532  * driver functions
 533  */
 534 static void add_device(struct slgt_info *info);
 535 static void device_init(int adapter_num, struct pci_dev *pdev);
 536 static int  claim_resources(struct slgt_info *info);
 537 static void release_resources(struct slgt_info *info);
 538
 539 /*
 540  * DEBUG OUTPUT CODE
 541  */
 542 #ifndef DBGINFO
 543 #define DBGINFO(fmt)
 544 #endif
 545 #ifndef DBGERR
 546 #define DBGERR(fmt)
 547 #endif
 548 #ifndef DBGBH
 549 #define DBGBH(fmt)
 550 #endif
 551 #ifndef DBGISR
 552 #define DBGISR(fmt)
 553 #endif
 554
 555 #ifdef DBGDATA
 556 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 557 {
 558         int i;
 559         int linecount;
 560         printk("%s %s data:\n",info->device_name, label);
 561         while(count) {
 562                 linecount = (count > 16) ? 16 : count;
 563                 for(i=0; i < linecount; i++)
 564                         printk("%02X ",(unsigned char)data[i]);
 565                 for(;i<17;i++)
 566                         printk("   ");
 567                 for(i=0;i<linecount;i++) {
 568                         if (data[i]>=040 && data[i]<=0176)
 569                                 printk("%c",data[i]);
 570                         else
 571                                 printk(".");
 572                 }
 573                 printk("\n");
 574                 data  += linecount;
 575                 count -= linecount;
 576         }
 577 }
 578 #else
 579 #define DBGDATA(info, buf, size, label)
 580 #endif
 581
 582 #ifdef DBGTBUF
 583 static void dump_tbufs(struct slgt_info *info)
 584 {
 585         int i;
 586         printk("tbuf_current=%d\n", info->tbuf_current);
 587         for (i=0 ; i < info->tbuf_count ; i++) {
 588                 printk("%d: count=%04X status=%04X\n",
 589                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 590         }
 591 }
 592 #else
 593 #define DBGTBUF(info)
 594 #endif
 595
 596 #ifdef DBGRBUF
 597 static void dump_rbufs(struct slgt_info *info)
 598 {
 599         int i;
 600         printk("rbuf_current=%d\n", info->rbuf_current);
 601         for (i=0 ; i < info->rbuf_count ; i++) {
 602                 printk("%d: count=%04X status=%04X\n",
 603                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 604         }
 605 }
 606 #else
 607 #define DBGRBUF(info)
 608 #endif
 609
 610 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 611 {
 612 #ifdef SANITY_CHECK
 613         if (!info) {
 614                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 615                 return 1;
 616         }
 617         if (info->magic != MGSL_MAGIC) {
 618                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 619                 return 1;
 620         }
 621 #else
 622         if (!info)
 623                 return 1;
 624 #endif
 625         return 0;
 626 }
 627
 628 /**
 629  * line discipline callback wrappers
 630  *
 631  * The wrappers maintain line discipline references
 632  * while calling into the line discipline.
 633  *
 634  * ldisc_receive_buf  - pass receive data to line discipline
 635  */
 636 static void ldisc_receive_buf(struct tty_struct *tty,
 637                               const __u8 *data, char *flags, int count)
 638 {
 639         struct tty_ldisc *ld;
 640         if (!tty)
 641                 return;
 642         ld = tty_ldisc_ref(tty);
 643         if (ld) {
 644                 if (ld->receive_buf)
 645                         ld->receive_buf(tty, data, flags, count);
 646                 tty_ldisc_deref(ld);
 647         }
 648 }
 649
 650 /* tty callbacks */
 651
 652 static int open(struct tty_struct *tty, struct file *filp)
 653 {
 654         struct slgt_info *info;
 655         int retval, line;
 656         unsigned long flags;
 657
 658         line = tty->index;
 659         if ((line < 0) || (line >= slgt_device_count)) {
 660                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 661                 return -ENODEV;
 662         }
 663
 664         info = slgt_device_list;
 665         while(info && info->line != line)
 666                 info = info->next_device;
 667         if (sanity_check(info, tty->name, "open"))
 668                 return -ENODEV;
 669         if (info->init_error) {
 670                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 671                 return -ENODEV;
 672         }
 673
 674         tty->driver_data = info;
 675         info->tty = tty;
 676
 677         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
 678
 679         /* If port is closing, signal caller to try again */
 680         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 681                 if (info->flags & ASYNC_CLOSING)
 682                         interruptible_sleep_on(&info->close_wait);
 683                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 684                         -EAGAIN : -ERESTARTSYS);
 685                 goto cleanup;
 686         }
 687
 688         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 689
 690         spin_lock_irqsave(&info->netlock, flags);
 691         if (info->netcount) {
 692                 retval = -EBUSY;
 693                 spin_unlock_irqrestore(&info->netlock, flags);
 694                 goto cleanup;
 695         }
 696         info->count++;
 697         spin_unlock_irqrestore(&info->netlock, flags);
 698
 699         if (info->count == 1) {
 700                 /* 1st open on this device, init hardware */
 701                 retval = startup(info);
 702                 if (retval < 0)
 703                         goto cleanup;
 704         }
 705
 706         retval = block_til_ready(tty, filp, info);
 707         if (retval) {
 708                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 709                 goto cleanup;
 710         }
 711
 712         retval = 0;
 713
 714 cleanup:
 715         if (retval) {
 716                 if (tty->count == 1)
 717                         info->tty = NULL; /* tty layer will release tty struct */
 718                 if(info->count)
 719                         info->count--;
 720         }
 721
 722         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 723         return retval;
 724 }
 725
 726 static void close(struct tty_struct *tty, struct file *filp)
 727 {
 728         struct slgt_info *info = tty->driver_data;
 729
 730         if (sanity_check(info, tty->name, "close"))
 731                 return;
 732         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
 733
 734         if (!info->count)
 735                 return;
 736
 737         if (tty_hung_up_p(filp))
 738                 goto cleanup;
 739
 740         if ((tty->count == 1) && (info->count != 1)) {
 741                 /*
 742                  * tty->count is 1 and the tty structure will be freed.
 743                  * info->count should be one in this case.
 744                  * if it's not, correct it so that the port is shutdown.
 745                  */
 746                 DBGERR(("%s close: bad refcount; tty->count=1, "
 747                        "info->count=%d\n", info->device_name, info->count));
 748                 info->count = 1;
 749         }
 750
 751         info->count--;
 752
 753         /* if at least one open remaining, leave hardware active */
 754         if (info->count)
 755                 goto cleanup;
 756
 757         info->flags |= ASYNC_CLOSING;
 758
 759         /* set tty->closing to notify line discipline to
 760          * only process XON/XOFF characters. Only the N_TTY
 761          * discipline appears to use this (ppp does not).
 762          */
 763         tty->closing = 1;
 764
 765         /* wait for transmit data to clear all layers */
 766
 767         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 768                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 769                 tty_wait_until_sent(tty, info->closing_wait);
 770         }
 771
 772         if (info->flags & ASYNC_INITIALIZED)
 773                 wait_until_sent(tty, info->timeout);
 774         flush_buffer(tty);
 775         tty_ldisc_flush(tty);
 776
 777         shutdown(info);
 778
 779         tty->closing = 0;
 780         info->tty = NULL;
 781
 782         if (info->blocked_open) {
 783                 if (info->close_delay) {
 784                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 785                 }
 786                 wake_up_interruptible(&info->open_wait);
 787         }
 788
 789         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 790
 791         wake_up_interruptible(&info->close_wait);
 792
 793 cleanup:
 794         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
 795 }
 796
 797 static void hangup(struct tty_struct *tty)
 798 {
 799         struct slgt_info *info = tty->driver_data;
 800
 801         if (sanity_check(info, tty->name, "hangup"))
 802                 return;
 803         DBGINFO(("%s hangup\n", info->device_name));
 804
 805         flush_buffer(tty);
 806         shutdown(info);
 807
 808         info->count = 0;
 809         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 810         info->tty = NULL;
 811
 812         wake_up_interruptible(&info->open_wait);
 813 }
 814
 815 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 816 {
 817         struct slgt_info *info = tty->driver_data;
 818         unsigned long flags;
 819
 820         DBGINFO(("%s set_termios\n", tty->driver->name));
 821
 822         change_params(info);
 823
 824         /* Handle transition to B0 status */
 825         if (old_termios->c_cflag & CBAUD &&
 826             !(tty->termios->c_cflag & CBAUD)) {
 827                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 828                 spin_lock_irqsave(&info->lock,flags);
 829                 set_signals(info);
 830                 spin_unlock_irqrestore(&info->lock,flags);
 831         }
 832
 833         /* Handle transition away from B0 status */
 834         if (!(old_termios->c_cflag & CBAUD) &&
 835             tty->termios->c_cflag & CBAUD) {
 836                 info->signals |= SerialSignal_DTR;
 837                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 838                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 839                         info->signals |= SerialSignal_RTS;
 840                 }
 841                 spin_lock_irqsave(&info->lock,flags);
 842                 set_signals(info);
 843                 spin_unlock_irqrestore(&info->lock,flags);
 844         }
 845
 846         /* Handle turning off CRTSCTS */
 847         if (old_termios->c_cflag & CRTSCTS &&
 848             !(tty->termios->c_cflag & CRTSCTS)) {
 849                 tty->hw_stopped = 0;
 850                 tx_release(tty);
 851         }
 852 }
 853
 854 static int write(struct tty_struct *tty,
 855                  const unsigned char *buf, int count)
 856 {
 857         int ret = 0;
 858         struct slgt_info *info = tty->driver_data;
 859         unsigned long flags;
 860
 861         if (sanity_check(info, tty->name, "write"))
 862                 goto cleanup;
 863         DBGINFO(("%s write count=%d\n", info->device_name, count));
 864
 865         if (!info->tx_buf)
 866                 goto cleanup;
 867
 868         if (count > info->max_frame_size) {
 869                 ret = -EIO;
 870                 goto cleanup;
 871         }
 872
 873         if (!count)
 874                 goto cleanup;
 875
 876         if (info->params.mode == MGSL_MODE_RAW ||
 877             info->params.mode == MGSL_MODE_MONOSYNC ||
 878             info->params.mode == MGSL_MODE_BISYNC) {
 879                 unsigned int bufs_needed = (count/DMABUFSIZE);
 880                 unsigned int bufs_free = free_tbuf_count(info);
 881                 if (count % DMABUFSIZE)
 882                         ++bufs_needed;
 883                 if (bufs_needed > bufs_free)
 884                         goto cleanup;
 885         } else {
 886                 if (info->tx_active)
 887                         goto cleanup;
 888                 if (info->tx_count) {
 889                         /* send accumulated data from send_char() calls */
 890                         /* as frame and wait before accepting more data. */
 891                         tx_load(info, info->tx_buf, info->tx_count);
 892                         goto start;
 893                 }
 894         }
 895
 896         ret = info->tx_count = count;
 897         tx_load(info, buf, count);
 898         goto start;
 899
 900 start:
 901         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 902                 spin_lock_irqsave(&info->lock,flags);
 903                 if (!info->tx_active)
 904                         tx_start(info);
 905                 else
 906                         tdma_start(info);
 907                 spin_unlock_irqrestore(&info->lock,flags);
 908         }
 909
 910 cleanup:
 911         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 912         return ret;
 913 }
 914
 915 static int put_char(struct tty_struct *tty, unsigned char ch)
 916 {
 917         struct slgt_info *info = tty->driver_data;
 918         unsigned long flags;
 919         int ret = 0;
 920
 921         if (sanity_check(info, tty->name, "put_char"))
 922                 return 0;
 923         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 924         if (!info->tx_buf)
 925                 return 0;
 926         spin_lock_irqsave(&info->lock,flags);
 927         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 928                 info->tx_buf[info->tx_count++] = ch;
 929                 ret = 1;
 930         }
 931         spin_unlock_irqrestore(&info->lock,flags);
 932         return ret;
 933 }
 934
 935 static void send_xchar(struct tty_struct *tty, char ch)
 936 {
 937         struct slgt_info *info = tty->driver_data;
 938         unsigned long flags;
 939
 940         if (sanity_check(info, tty->name, "send_xchar"))
 941                 return;
 942         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 943         info->x_char = ch;
 944         if (ch) {
 945                 spin_lock_irqsave(&info->lock,flags);
 946                 if (!info->tx_enabled)
 947                         tx_start(info);
 948                 spin_unlock_irqrestore(&info->lock,flags);
 949         }
 950 }
 951
 952 static void wait_until_sent(struct tty_struct *tty, int timeout)
 953 {
 954         struct slgt_info *info = tty->driver_data;
 955         unsigned long orig_jiffies, char_time;
 956
 957         if (!info )
 958                 return;
 959         if (sanity_check(info, tty->name, "wait_until_sent"))
 960                 return;
 961         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 962         if (!(info->flags & ASYNC_INITIALIZED))
 963                 goto exit;
 964
 965         orig_jiffies = jiffies;
 966
 967         /* Set check interval to 1/5 of estimated time to
 968          * send a character, and make it at least 1. The check
 969          * interval should also be less than the timeout.
 970          * Note: use tight timings here to satisfy the NIST-PCTS.
 971          */
 972
 973         lock_kernel();
 974
 975         if (info->params.data_rate) {
 976                 char_time = info->timeout/(32 * 5);
 977                 if (!char_time)
 978                         char_time++;
 979         } else
 980                 char_time = 1;
 981
 982         if (timeout)
 983                 char_time = min_t(unsigned long, char_time, timeout);
 984
 985         while (info->tx_active) {
 986                 msleep_interruptible(jiffies_to_msecs(char_time));
 987                 if (signal_pending(current))
 988                         break;
 989                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 990                         break;
 991         }
 992         unlock_kernel();
 993
 994 exit:
 995         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 996 }
 997
 998 static int write_room(struct tty_struct *tty)
 999 {
1000         struct slgt_info *info = tty->driver_data;
1001         int ret;
1002
1003         if (sanity_check(info, tty->name, "write_room"))
1004                 return 0;
1005         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1006         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1007         return ret;
1008 }
1009
1010 static void flush_chars(struct tty_struct *tty)
1011 {
1012         struct slgt_info *info = tty->driver_data;
1013         unsigned long flags;
1014
1015         if (sanity_check(info, tty->name, "flush_chars"))
1016                 return;
1017         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1018
1019         if (info->tx_count <= 0 || tty->stopped ||
1020             tty->hw_stopped || !info->tx_buf)
1021                 return;
1022
1023         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1024
1025         spin_lock_irqsave(&info->lock,flags);
1026         if (!info->tx_active && info->tx_count) {
1027                 tx_load(info, info->tx_buf,info->tx_count);
1028                 tx_start(info);
1029         }
1030         spin_unlock_irqrestore(&info->lock,flags);
1031 }
1032
1033 static void flush_buffer(struct tty_struct *tty)
1034 {
1035         struct slgt_info *info = tty->driver_data;
1036         unsigned long flags;
1037
1038         if (sanity_check(info, tty->name, "flush_buffer"))
1039                 return;
1040         DBGINFO(("%s flush_buffer\n", info->device_name));
1041
1042         spin_lock_irqsave(&info->lock,flags);
1043         if (!info->tx_active)
1044                 info->tx_count = 0;
1045         spin_unlock_irqrestore(&info->lock,flags);
1046
1047         tty_wakeup(tty);
1048 }
1049
1050 /*
1051  * throttle (stop) transmitter
1052  */
1053 static void tx_hold(struct tty_struct *tty)
1054 {
1055         struct slgt_info *info = tty->driver_data;
1056         unsigned long flags;
1057
1058         if (sanity_check(info, tty->name, "tx_hold"))
1059                 return;
1060         DBGINFO(("%s tx_hold\n", info->device_name));
1061         spin_lock_irqsave(&info->lock,flags);
1062         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1063                 tx_stop(info);
1064         spin_unlock_irqrestore(&info->lock,flags);
1065 }
1066
1067 /*
1068  * release (start) transmitter
1069  */
1070 static void tx_release(struct tty_struct *tty)
1071 {
1072         struct slgt_info *info = tty->driver_data;
1073         unsigned long flags;
1074
1075         if (sanity_check(info, tty->name, "tx_release"))
1076                 return;
1077         DBGINFO(("%s tx_release\n", info->device_name));
1078         spin_lock_irqsave(&info->lock,flags);
1079         if (!info->tx_active && info->tx_count) {
1080                 tx_load(info, info->tx_buf, info->tx_count);
1081                 tx_start(info);
1082         }
1083         spin_unlock_irqrestore(&info->lock,flags);
1084 }
1085
1086 /*
1087  * Service an IOCTL request
1088  *
1089  * Arguments
1090  *
1091  *      tty     pointer to tty instance data
1092  *      file    pointer to associated file object for device
1093  *      cmd     IOCTL command code
1094  *      arg     command argument/context
1095  *
1096  * Return 0 if success, otherwise error code
1097  */
1098 static int ioctl(struct tty_struct *tty, struct file *file,
1099                  unsigned int cmd, unsigned long arg)
1100 {
1101         struct slgt_info *info = tty->driver_data;
1102         struct mgsl_icount cnow;        /* kernel counter temps */
1103         struct serial_icounter_struct __user *p_cuser;  /* user space */
1104         unsigned long flags;
1105         void __user *argp = (void __user *)arg;
1106         int ret;
1107
1108         if (sanity_check(info, tty->name, "ioctl"))
1109                 return -ENODEV;
1110         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1111
1112         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1113             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1114                 if (tty->flags & (1 << TTY_IO_ERROR))
1115                     return -EIO;
1116         }
1117
1118         lock_kernel();
1119
1120         switch (cmd) {
1121         case MGSL_IOCGPARAMS:
1122                 ret = get_params(info, argp);
1123                 break;
1124         case MGSL_IOCSPARAMS:
1125                 ret = set_params(info, argp);
1126                 break;
1127         case MGSL_IOCGTXIDLE:
1128                 ret = get_txidle(info, argp);
1129                 break;
1130         case MGSL_IOCSTXIDLE:
1131                 ret = set_txidle(info, (int)arg);
1132                 break;
1133         case MGSL_IOCTXENABLE:
1134                 ret = tx_enable(info, (int)arg);
1135                 break;
1136         case MGSL_IOCRXENABLE:
1137                 ret = rx_enable(info, (int)arg);
1138                 break;
1139         case MGSL_IOCTXABORT:
1140                 ret = tx_abort(info);
1141                 break;
1142         case MGSL_IOCGSTATS:
1143                 ret = get_stats(info, argp);
1144                 break;
1145         case MGSL_IOCWAITEVENT:
1146                 ret = wait_mgsl_event(info, argp);
1147                 break;
1148         case TIOCMIWAIT:
1149                 ret = modem_input_wait(info,(int)arg);
1150                 break;
1151         case MGSL_IOCGIF:
1152                 ret = get_interface(info, argp);
1153                 break;
1154         case MGSL_IOCSIF:
1155                 ret = set_interface(info,(int)arg);
1156                 break;
1157         case MGSL_IOCSGPIO:
1158                 ret = set_gpio(info, argp);
1159                 break;
1160         case MGSL_IOCGGPIO:
1161                 ret = get_gpio(info, argp);
1162                 break;
1163         case MGSL_IOCWAITGPIO:
1164                 ret = wait_gpio(info, argp);
1165                 break;
1166         case TIOCGICOUNT:
1167                 spin_lock_irqsave(&info->lock,flags);
1168                 cnow = info->icount;
1169                 spin_unlock_irqrestore(&info->lock,flags);
1170                 p_cuser = argp;
1171                 if (put_user(cnow.cts, &p_cuser->cts) ||
1172                     put_user(cnow.dsr, &p_cuser->dsr) ||
1173                     put_user(cnow.rng, &p_cuser->rng) ||
1174                     put_user(cnow.dcd, &p_cuser->dcd) ||
1175                     put_user(cnow.rx, &p_cuser->rx) ||
1176                     put_user(cnow.tx, &p_cuser->tx) ||
1177                     put_user(cnow.frame, &p_cuser->frame) ||
1178                     put_user(cnow.overrun, &p_cuser->overrun) ||
1179                     put_user(cnow.parity, &p_cuser->parity) ||
1180                     put_user(cnow.brk, &p_cuser->brk) ||
1181                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1182                         ret = -EFAULT;
1183                 ret = 0;
1184                 break;
1185         default:
1186                 ret = -ENOIOCTLCMD;
1187         }
1188         unlock_kernel();
1189         return ret;
1190 }
1191
1192 /*
1193  * support for 32 bit ioctl calls on 64 bit systems
1194  */
1195 #ifdef CONFIG_COMPAT
1196 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1197 {
1198         struct MGSL_PARAMS32 tmp_params;
1199
1200         DBGINFO(("%s get_params32\n", info->device_name));
1201         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1202         tmp_params.loopback        = info->params.loopback;
1203         tmp_params.flags           = info->params.flags;
1204         tmp_params.encoding        = info->params.encoding;
1205         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1206         tmp_params.addr_filter     = info->params.addr_filter;
1207         tmp_params.crc_type        = info->params.crc_type;
1208         tmp_params.preamble_length = info->params.preamble_length;
1209         tmp_params.preamble        = info->params.preamble;
1210         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1211         tmp_params.data_bits       = info->params.data_bits;
1212         tmp_params.stop_bits       = info->params.stop_bits;
1213         tmp_params.parity          = info->params.parity;
1214         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1215                 return -EFAULT;
1216         return 0;
1217 }
1218
1219 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1220 {
1221         struct MGSL_PARAMS32 tmp_params;
1222
1223         DBGINFO(("%s set_params32\n", info->device_name));
1224         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1225                 return -EFAULT;
1226
1227         spin_lock(&info->lock);
1228         info->params.mode            = tmp_params.mode;
1229         info->params.loopback        = tmp_params.loopback;
1230         info->params.flags           = tmp_params.flags;
1231         info->params.encoding        = tmp_params.encoding;
1232         info->params.clock_speed     = tmp_params.clock_speed;
1233         info->params.addr_filter     = tmp_params.addr_filter;
1234         info->params.crc_type        = tmp_params.crc_type;
1235         info->params.preamble_length = tmp_params.preamble_length;
1236         info->params.preamble        = tmp_params.preamble;
1237         info->params.data_rate       = tmp_params.data_rate;
1238         info->params.data_bits       = tmp_params.data_bits;
1239         info->params.stop_bits       = tmp_params.stop_bits;
1240         info->params.parity          = tmp_params.parity;
1241         spin_unlock(&info->lock);
1242
1243         change_params(info);
1244
1245         return 0;
1246 }
1247
1248 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1249                          unsigned int cmd, unsigned long arg)
1250 {
1251         struct slgt_info *info = tty->driver_data;
1252         int rc = -ENOIOCTLCMD;
1253
1254         if (sanity_check(info, tty->name, "compat_ioctl"))
1255                 return -ENODEV;
1256         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1257
1258         switch (cmd) {
1259
1260         case MGSL_IOCSPARAMS32:
1261                 rc = set_params32(info, compat_ptr(arg));
1262                 break;
1263
1264         case MGSL_IOCGPARAMS32:
1265                 rc = get_params32(info, compat_ptr(arg));
1266                 break;
1267
1268         case MGSL_IOCGPARAMS:
1269         case MGSL_IOCSPARAMS:
1270         case MGSL_IOCGTXIDLE:
1271         case MGSL_IOCGSTATS:
1272         case MGSL_IOCWAITEVENT:
1273         case MGSL_IOCGIF:
1274         case MGSL_IOCSGPIO:
1275         case MGSL_IOCGGPIO:
1276         case MGSL_IOCWAITGPIO:
1277         case TIOCGICOUNT:
1278                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1279                 break;
1280
1281         case MGSL_IOCSTXIDLE:
1282         case MGSL_IOCTXENABLE:
1283         case MGSL_IOCRXENABLE:
1284         case MGSL_IOCTXABORT:
1285         case TIOCMIWAIT:
1286         case MGSL_IOCSIF:
1287                 rc = ioctl(tty, file, cmd, arg);
1288                 break;
1289         }
1290
1291         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1292         return rc;
1293 }
1294 #else
1295 #define slgt_compat_ioctl NULL
1296 #endif /* ifdef CONFIG_COMPAT */
1297
1298 /*
1299  * proc fs support
1300  */
1301 static inline int line_info(char *buf, struct slgt_info *info)
1302 {
1303         char stat_buf[30];
1304         int ret;
1305         unsigned long flags;
1306
1307         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1308                       info->device_name, info->phys_reg_addr,
1309                       info->irq_level, info->max_frame_size);
1310
1311         /* output current serial signal states */
1312         spin_lock_irqsave(&info->lock,flags);
1313         get_signals(info);
1314         spin_unlock_irqrestore(&info->lock,flags);
1315
1316         stat_buf[0] = 0;
1317         stat_buf[1] = 0;
1318         if (info->signals & SerialSignal_RTS)
1319                 strcat(stat_buf, "|RTS");
1320         if (info->signals & SerialSignal_CTS)
1321                 strcat(stat_buf, "|CTS");
1322         if (info->signals & SerialSignal_DTR)
1323                 strcat(stat_buf, "|DTR");
1324         if (info->signals & SerialSignal_DSR)
1325                 strcat(stat_buf, "|DSR");
1326         if (info->signals & SerialSignal_DCD)
1327                 strcat(stat_buf, "|CD");
1328         if (info->signals & SerialSignal_RI)
1329                 strcat(stat_buf, "|RI");
1330
1331         if (info->params.mode != MGSL_MODE_ASYNC) {
1332                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1333                                info->icount.txok, info->icount.rxok);
1334                 if (info->icount.txunder)
1335                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1336                 if (info->icount.txabort)
1337                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1338                 if (info->icount.rxshort)
1339                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1340                 if (info->icount.rxlong)
1341                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1342                 if (info->icount.rxover)
1343                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1344                 if (info->icount.rxcrc)
1345                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1346         } else {
1347                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1348                                info->icount.tx, info->icount.rx);
1349                 if (info->icount.frame)
1350                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1351                 if (info->icount.parity)
1352                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1353                 if (info->icount.brk)
1354                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1355                 if (info->icount.overrun)
1356                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1357         }
1358
1359         /* Append serial signal status to end */
1360         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1361
1362         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1363                        info->tx_active,info->bh_requested,info->bh_running,
1364                        info->pending_bh);
1365
1366         return ret;
1367 }
1368
1369 /* Called to print information about devices
1370  */
1371 static int read_proc(char *page, char **start, off_t off, int count,
1372                      int *eof, void *data)
1373 {
1374         int len = 0, l;
1375         off_t   begin = 0;
1376         struct slgt_info *info;
1377
1378         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1379
1380         info = slgt_device_list;
1381         while( info ) {
1382                 l = line_info(page + len, info);
1383                 len += l;
1384                 if (len+begin > off+count)
1385                         goto done;
1386                 if (len+begin < off) {
1387                         begin += len;
1388                         len = 0;
1389                 }
1390                 info = info->next_device;
1391         }
1392
1393         *eof = 1;
1394 done:
1395         if (off >= len+begin)
1396                 return 0;
1397         *start = page + (off-begin);
1398         return ((count < begin+len-off) ? count : begin+len-off);
1399 }
1400
1401 /*
1402  * return count of bytes in transmit buffer
1403  */
1404 static int chars_in_buffer(struct tty_struct *tty)
1405 {
1406         struct slgt_info *info = tty->driver_data;
1407         if (sanity_check(info, tty->name, "chars_in_buffer"))
1408                 return 0;
1409         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1410         return info->tx_count;
1411 }
1412
1413 /*
1414  * signal remote device to throttle send data (our receive data)
1415  */
1416 static void throttle(struct tty_struct * tty)
1417 {
1418         struct slgt_info *info = tty->driver_data;
1419         unsigned long flags;
1420
1421         if (sanity_check(info, tty->name, "throttle"))
1422                 return;
1423         DBGINFO(("%s throttle\n", info->device_name));
1424         if (I_IXOFF(tty))
1425                 send_xchar(tty, STOP_CHAR(tty));
1426         if (tty->termios->c_cflag & CRTSCTS) {
1427                 spin_lock_irqsave(&info->lock,flags);
1428                 info->signals &= ~SerialSignal_RTS;
1429                 set_signals(info);
1430                 spin_unlock_irqrestore(&info->lock,flags);
1431         }
1432 }
1433
1434 /*
1435  * signal remote device to stop throttling send data (our receive data)
1436  */
1437 static void unthrottle(struct tty_struct * tty)
1438 {
1439         struct slgt_info *info = tty->driver_data;
1440         unsigned long flags;
1441
1442         if (sanity_check(info, tty->name, "unthrottle"))
1443                 return;
1444         DBGINFO(("%s unthrottle\n", info->device_name));
1445         if (I_IXOFF(tty)) {
1446                 if (info->x_char)
1447                         info->x_char = 0;
1448                 else
1449                         send_xchar(tty, START_CHAR(tty));
1450         }
1451         if (tty->termios->c_cflag & CRTSCTS) {
1452                 spin_lock_irqsave(&info->lock,flags);
1453                 info->signals |= SerialSignal_RTS;
1454                 set_signals(info);
1455                 spin_unlock_irqrestore(&info->lock,flags);
1456         }
1457 }
1458
1459 /*
1460  * set or clear transmit break condition
1461  * break_state  -1=set break condition, 0=clear
1462  */
1463 static void set_break(struct tty_struct *tty, int break_state)
1464 {
1465         struct slgt_info *info = tty->driver_data;
1466         unsigned short value;
1467         unsigned long flags;
1468
1469         if (sanity_check(info, tty->name, "set_break"))
1470                 return;
1471         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1472
1473         spin_lock_irqsave(&info->lock,flags);
1474         value = rd_reg16(info, TCR);
1475         if (break_state == -1)
1476                 value |= BIT6;
1477         else
1478                 value &= ~BIT6;
1479         wr_reg16(info, TCR, value);
1480         spin_unlock_irqrestore(&info->lock,flags);
1481 }
1482
1483 #if SYNCLINK_GENERIC_HDLC
1484
1485 /**
1486  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1487  * set encoding and frame check sequence (FCS) options
1488  *
1489  * dev       pointer to network device structure
1490  * encoding  serial encoding setting
1491  * parity    FCS setting
1492  *
1493  * returns 0 if success, otherwise error code
1494  */
1495 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1496                           unsigned short parity)
1497 {
1498         struct slgt_info *info = dev_to_port(dev);
1499         unsigned char  new_encoding;
1500         unsigned short new_crctype;
1501
1502         /* return error if TTY interface open */
1503         if (info->count)
1504                 return -EBUSY;
1505
1506         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1507
1508         switch (encoding)
1509         {
1510         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1511         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1512         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1513         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1514         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1515         default: return -EINVAL;
1516         }
1517
1518         switch (parity)
1519         {
1520         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1521         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1522         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1523         default: return -EINVAL;
1524         }
1525
1526         info->params.encoding = new_encoding;
1527         info->params.crc_type = new_crctype;
1528
1529         /* if network interface up, reprogram hardware */
1530         if (info->netcount)
1531                 program_hw(info);
1532
1533         return 0;
1534 }
1535
1536 /**
1537  * called by generic HDLC layer to send frame
1538  *
1539  * skb  socket buffer containing HDLC frame
1540  * dev  pointer to network device structure
1541  *
1542  * returns 0 if success, otherwise error code
1543  */
1544 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1545 {
1546         struct slgt_info *info = dev_to_port(dev);
1547         unsigned long flags;
1548
1549         DBGINFO(("%s hdlc_xmit\n", dev->name));
1550
1551         /* stop sending until this frame completes */
1552         netif_stop_queue(dev);
1553
1554         /* copy data to device buffers */
1555         info->tx_count = skb->len;
1556         tx_load(info, skb->data, skb->len);
1557
1558         /* update network statistics */
1559         dev->stats.tx_packets++;
1560         dev->stats.tx_bytes += skb->len;
1561
1562         /* done with socket buffer, so free it */
1563         dev_kfree_skb(skb);
1564
1565         /* save start time for transmit timeout detection */
1566         dev->trans_start = jiffies;
1567
1568         /* start hardware transmitter if necessary */
1569         spin_lock_irqsave(&info->lock,flags);
1570         if (!info->tx_active)
1571                 tx_start(info);
1572         spin_unlock_irqrestore(&info->lock,flags);
1573
1574         return 0;
1575 }
1576
1577 /**
1578  * called by network layer when interface enabled
1579  * claim resources and initialize hardware
1580  *
1581  * dev  pointer to network device structure
1582  *
1583  * returns 0 if success, otherwise error code
1584  */
1585 static int hdlcdev_open(struct net_device *dev)
1586 {
1587         struct slgt_info *info = dev_to_port(dev);
1588         int rc;
1589         unsigned long flags;
1590
1591         if (!try_module_get(THIS_MODULE))
1592                 return -EBUSY;
1593
1594         DBGINFO(("%s hdlcdev_open\n", dev->name));
1595
1596         /* generic HDLC layer open processing */
1597         if ((rc = hdlc_open(dev)))
1598                 return rc;
1599
1600         /* arbitrate between network and tty opens */
1601         spin_lock_irqsave(&info->netlock, flags);
1602         if (info->count != 0 || info->netcount != 0) {
1603                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1604                 spin_unlock_irqrestore(&info->netlock, flags);
1605                 return -EBUSY;
1606         }
1607         info->netcount=1;
1608         spin_unlock_irqrestore(&info->netlock, flags);
1609
1610         /* claim resources and init adapter */
1611         if ((rc = startup(info)) != 0) {
1612                 spin_lock_irqsave(&info->netlock, flags);
1613                 info->netcount=0;
1614                 spin_unlock_irqrestore(&info->netlock, flags);
1615                 return rc;
1616         }
1617
1618         /* assert DTR and RTS, apply hardware settings */
1619         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1620         program_hw(info);
1621
1622         /* enable network layer transmit */
1623         dev->trans_start = jiffies;
1624         netif_start_queue(dev);
1625
1626         /* inform generic HDLC layer of current DCD status */
1627         spin_lock_irqsave(&info->lock, flags);
1628         get_signals(info);
1629         spin_unlock_irqrestore(&info->lock, flags);
1630         if (info->signals & SerialSignal_DCD)
1631                 netif_carrier_on(dev);
1632         else
1633                 netif_carrier_off(dev);
1634         return 0;
1635 }
1636
1637 /**
1638  * called by network layer when interface is disabled
1639  * shutdown hardware and release resources
1640  *
1641  * dev  pointer to network device structure
1642  *
1643  * returns 0 if success, otherwise error code
1644  */
1645 static int hdlcdev_close(struct net_device *dev)
1646 {
1647         struct slgt_info *info = dev_to_port(dev);
1648         unsigned long flags;
1649
1650         DBGINFO(("%s hdlcdev_close\n", dev->name));
1651
1652         netif_stop_queue(dev);
1653
1654         /* shutdown adapter and release resources */
1655         shutdown(info);
1656
1657         hdlc_close(dev);
1658
1659         spin_lock_irqsave(&info->netlock, flags);
1660         info->netcount=0;
1661         spin_unlock_irqrestore(&info->netlock, flags);
1662
1663         module_put(THIS_MODULE);
1664         return 0;
1665 }
1666
1667 /**
1668  * called by network layer to process IOCTL call to network device
1669  *
1670  * dev  pointer to network device structure
1671  * ifr  pointer to network interface request structure
1672  * cmd  IOCTL command code
1673  *
1674  * returns 0 if success, otherwise error code
1675  */
1676 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1677 {
1678         const size_t size = sizeof(sync_serial_settings);
1679         sync_serial_settings new_line;
1680         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1681         struct slgt_info *info = dev_to_port(dev);
1682         unsigned int flags;
1683
1684         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1685
1686         /* return error if TTY interface open */
1687         if (info->count)
1688                 return -EBUSY;
1689
1690         if (cmd != SIOCWANDEV)
1691                 return hdlc_ioctl(dev, ifr, cmd);
1692
1693         switch(ifr->ifr_settings.type) {
1694         case IF_GET_IFACE: /* return current sync_serial_settings */
1695
1696                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1697                 if (ifr->ifr_settings.size < size) {
1698                         ifr->ifr_settings.size = size; /* data size wanted */
1699                         return -ENOBUFS;
1700                 }
1701
1702                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1703                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1704                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1705                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1706
1707                 switch (flags){
1708                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1709                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1710                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1711                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1712                 default: new_line.clock_type = CLOCK_DEFAULT;
1713                 }
1714
1715                 new_line.clock_rate = info->params.clock_speed;
1716                 new_line.loopback   = info->params.loopback ? 1:0;
1717
1718                 if (copy_to_user(line, &new_line, size))
1719                         return -EFAULT;
1720                 return 0;
1721
1722         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1723
1724                 if(!capable(CAP_NET_ADMIN))
1725                         return -EPERM;
1726                 if (copy_from_user(&new_line, line, size))
1727                         return -EFAULT;
1728
1729                 switch (new_line.clock_type)
1730                 {
1731                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1732                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1733                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1734                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1735                 case CLOCK_DEFAULT:  flags = info->params.flags &
1736                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1737                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1738                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1739                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1740                 default: return -EINVAL;
1741                 }
1742
1743                 if (new_line.loopback != 0 && new_line.loopback != 1)
1744                         return -EINVAL;
1745
1746                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1747                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1748                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1749                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1750                 info->params.flags |= flags;
1751
1752                 info->params.loopback = new_line.loopback;
1753
1754                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1755                         info->params.clock_speed = new_line.clock_rate;
1756                 else
1757                         info->params.clock_speed = 0;
1758
1759                 /* if network interface up, reprogram hardware */
1760                 if (info->netcount)
1761                         program_hw(info);
1762                 return 0;
1763
1764         default:
1765                 return hdlc_ioctl(dev, ifr, cmd);
1766         }
1767 }
1768
1769 /**
1770  * called by network layer when transmit timeout is detected
1771  *
1772  * dev  pointer to network device structure
1773  */
1774 static void hdlcdev_tx_timeout(struct net_device *dev)
1775 {
1776         struct slgt_info *info = dev_to_port(dev);
1777         unsigned long flags;
1778
1779         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1780
1781         dev->stats.tx_errors++;
1782         dev->stats.tx_aborted_errors++;
1783
1784         spin_lock_irqsave(&info->lock,flags);
1785         tx_stop(info);
1786         spin_unlock_irqrestore(&info->lock,flags);
1787
1788         netif_wake_queue(dev);
1789 }
1790
1791 /**
1792  * called by device driver when transmit completes
1793  * reenable network layer transmit if stopped
1794  *
1795  * info  pointer to device instance information
1796  */
1797 static void hdlcdev_tx_done(struct slgt_info *info)
1798 {
1799         if (netif_queue_stopped(info->netdev))
1800                 netif_wake_queue(info->netdev);
1801 }
1802
1803 /**
1804  * called by device driver when frame received
1805  * pass frame to network layer
1806  *
1807  * info  pointer to device instance information
1808  * buf   pointer to buffer contianing frame data
1809  * size  count of data bytes in buf
1810  */
1811 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1812 {
1813         struct sk_buff *skb = dev_alloc_skb(size);
1814         struct net_device *dev = info->netdev;
1815
1816         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1817
1818         if (skb == NULL) {
1819                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1820                 dev->stats.rx_dropped++;
1821                 return;
1822         }
1823
1824         memcpy(skb_put(skb, size), buf, size);
1825
1826         skb->protocol = hdlc_type_trans(skb, dev);
1827
1828         dev->stats.rx_packets++;
1829         dev->stats.rx_bytes += size;
1830
1831         netif_rx(skb);
1832
1833         dev->last_rx = jiffies;
1834 }
1835
1836 /**
1837  * called by device driver when adding device instance
1838  * do generic HDLC initialization
1839  *
1840  * info  pointer to device instance information
1841  *
1842  * returns 0 if success, otherwise error code
1843  */
1844 static int hdlcdev_init(struct slgt_info *info)
1845 {
1846         int rc;
1847         struct net_device *dev;
1848         hdlc_device *hdlc;
1849
1850         /* allocate and initialize network and HDLC layer objects */
1851
1852         if (!(dev = alloc_hdlcdev(info))) {
1853                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1854                 return -ENOMEM;
1855         }
1856
1857         /* for network layer reporting purposes only */
1858         dev->mem_start = info->phys_reg_addr;
1859         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1860         dev->irq       = info->irq_level;
1861
1862         /* network layer callbacks and settings */
1863         dev->do_ioctl       = hdlcdev_ioctl;
1864         dev->open           = hdlcdev_open;
1865         dev->stop           = hdlcdev_close;
1866         dev->tx_timeout     = hdlcdev_tx_timeout;
1867         dev->watchdog_timeo = 10*HZ;
1868         dev->tx_queue_len   = 50;
1869
1870         /* generic HDLC layer callbacks and settings */
1871         hdlc         = dev_to_hdlc(dev);
1872         hdlc->attach = hdlcdev_attach;
1873         hdlc->xmit   = hdlcdev_xmit;
1874
1875         /* register objects with HDLC layer */
1876         if ((rc = register_hdlc_device(dev))) {
1877                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1878                 free_netdev(dev);
1879                 return rc;
1880         }
1881
1882         info->netdev = dev;
1883         return 0;
1884 }
1885
1886 /**
1887  * called by device driver when removing device instance
1888  * do generic HDLC cleanup
1889  *
1890  * info  pointer to device instance information
1891  */
1892 static void hdlcdev_exit(struct slgt_info *info)
1893 {
1894         unregister_hdlc_device(info->netdev);
1895         free_netdev(info->netdev);
1896         info->netdev = NULL;
1897 }
1898
1899 #endif /* ifdef CONFIG_HDLC */
1900
1901 /*
1902  * get async data from rx DMA buffers
1903  */
1904 static void rx_async(struct slgt_info *info)
1905 {
1906         struct tty_struct *tty = info->tty;
1907         struct mgsl_icount *icount = &info->icount;
1908         unsigned int start, end;
1909         unsigned char *p;
1910         unsigned char status;
1911         struct slgt_desc *bufs = info->rbufs;
1912         int i, count;
1913         int chars = 0;
1914         int stat;
1915         unsigned char ch;
1916
1917         start = end = info->rbuf_current;
1918
1919         while(desc_complete(bufs[end])) {
1920                 count = desc_count(bufs[end]) - info->rbuf_index;
1921                 p     = bufs[end].buf + info->rbuf_index;
1922
1923                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1924                 DBGDATA(info, p, count, "rx");
1925
1926                 for(i=0 ; i < count; i+=2, p+=2) {
1927                         ch = *p;
1928                         icount->rx++;
1929
1930                         stat = 0;
1931
1932                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1933                                 if (status & BIT1)
1934                                         icount->parity++;
1935                                 else if (status & BIT0)
1936                                         icount->frame++;
1937                                 /* discard char if tty control flags say so */
1938                                 if (status & info->ignore_status_mask)
1939                                         continue;
1940                                 if (status & BIT1)
1941                                         stat = TTY_PARITY;
1942                                 else if (status & BIT0)
1943                                         stat = TTY_FRAME;
1944                         }
1945                         if (tty) {
1946                                 tty_insert_flip_char(tty, ch, stat);
1947                                 chars++;
1948                         }
1949                 }
1950
1951                 if (i < count) {
1952                         /* receive buffer not completed */
1953                         info->rbuf_index += i;
1954                         mod_timer(&info->rx_timer, jiffies + 1);
1955                         break;
1956                 }
1957
1958                 info->rbuf_index = 0;
1959                 free_rbufs(info, end, end);
1960
1961                 if (++end == info->rbuf_count)
1962                         end = 0;
1963
1964                 /* if entire list searched then no frame available */
1965                 if (end == start)
1966                         break;
1967         }
1968
1969         if (tty && chars)
1970                 tty_flip_buffer_push(tty);
1971 }
1972
1973 /*
1974  * return next bottom half action to perform
1975  */
1976 static int bh_action(struct slgt_info *info)
1977 {
1978         unsigned long flags;
1979         int rc;
1980
1981         spin_lock_irqsave(&info->lock,flags);
1982
1983         if (info->pending_bh & BH_RECEIVE) {
1984                 info->pending_bh &= ~BH_RECEIVE;
1985                 rc = BH_RECEIVE;
1986         } else if (info->pending_bh & BH_TRANSMIT) {
1987                 info->pending_bh &= ~BH_TRANSMIT;
1988                 rc = BH_TRANSMIT;
1989         } else if (info->pending_bh & BH_STATUS) {
1990                 info->pending_bh &= ~BH_STATUS;
1991                 rc = BH_STATUS;
1992         } else {
1993                 /* Mark BH routine as complete */
1994                 info->bh_running = false;
1995                 info->bh_requested = false;
1996                 rc = 0;
1997         }
1998
1999         spin_unlock_irqrestore(&info->lock,flags);
2000
2001         return rc;
2002 }
2003
2004 /*
2005  * perform bottom half processing
2006  */
2007 static void bh_handler(struct work_struct *work)
2008 {
2009         struct slgt_info *info = container_of(work, struct slgt_info, task);
2010         int action;
2011
2012         if (!info)
2013                 return;
2014         info->bh_running = true;
2015
2016         while((action = bh_action(info))) {
2017                 switch (action) {
2018                 case BH_RECEIVE:
2019                         DBGBH(("%s bh receive\n", info->device_name));
2020                         switch(info->params.mode) {
2021                         case MGSL_MODE_ASYNC:
2022                                 rx_async(info);
2023                                 break;
2024                         case MGSL_MODE_HDLC:
2025                                 while(rx_get_frame(info));
2026                                 break;
2027                         case MGSL_MODE_RAW:
2028                         case MGSL_MODE_MONOSYNC:
2029                         case MGSL_MODE_BISYNC:
2030                                 while(rx_get_buf(info));
2031                                 break;
2032                         }
2033                         /* restart receiver if rx DMA buffers exhausted */
2034                         if (info->rx_restart)
2035                                 rx_start(info);
2036                         break;
2037                 case BH_TRANSMIT:
2038                         bh_transmit(info);
2039                         break;
2040                 case BH_STATUS:
2041                         DBGBH(("%s bh status\n", info->device_name));
2042                         info->ri_chkcount = 0;
2043                         info->dsr_chkcount = 0;
2044                         info->dcd_chkcount = 0;
2045                         info->cts_chkcount = 0;
2046                         break;
2047                 default:
2048                         DBGBH(("%s unknown action\n", info->device_name));
2049                         break;
2050                 }
2051         }
2052         DBGBH(("%s bh_handler exit\n", info->device_name));
2053 }
2054
2055 static void bh_transmit(struct slgt_info *info)
2056 {
2057         struct tty_struct *tty = info->tty;
2058
2059         DBGBH(("%s bh_transmit\n", info->device_name));
2060         if (tty)
2061                 tty_wakeup(tty);
2062 }
2063
2064 static void dsr_change(struct slgt_info *info, unsigned short status)
2065 {
2066         if (status & BIT3) {
2067                 info->signals |= SerialSignal_DSR;
2068                 info->input_signal_events.dsr_up++;
2069         } else {
2070                 info->signals &= ~SerialSignal_DSR;
2071                 info->input_signal_events.dsr_down++;
2072         }
2073         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2074         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2075                 slgt_irq_off(info, IRQ_DSR);
2076                 return;
2077         }
2078         info->icount.dsr++;
2079         wake_up_interruptible(&info->status_event_wait_q);
2080         wake_up_interruptible(&info->event_wait_q);
2081         info->pending_bh |= BH_STATUS;
2082 }
2083
2084 static void cts_change(struct slgt_info *info, unsigned short status)
2085 {
2086         if (status & BIT2) {
2087                 info->signals |= SerialSignal_CTS;
2088                 info->input_signal_events.cts_up++;
2089         } else {
2090                 info->signals &= ~SerialSignal_CTS;
2091                 info->input_signal_events.cts_down++;
2092         }
2093         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2094         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2095                 slgt_irq_off(info, IRQ_CTS);
2096                 return;
2097         }
2098         info->icount.cts++;
2099         wake_up_interruptible(&info->status_event_wait_q);
2100         wake_up_interruptible(&info->event_wait_q);
2101         info->pending_bh |= BH_STATUS;
2102
2103         if (info->flags & ASYNC_CTS_FLOW) {
2104                 if (info->tty) {
2105                         if (info->tty->hw_stopped) {
2106                                 if (info->signals & SerialSignal_CTS) {
2107                                         info->tty->hw_stopped = 0;
2108                                         info->pending_bh |= BH_TRANSMIT;
2109                                         return;
2110                                 }
2111                         } else {
2112                                 if (!(info->signals & SerialSignal_CTS))
2113                                         info->tty->hw_stopped = 1;
2114                         }
2115                 }
2116         }
2117 }
2118
2119 static void dcd_change(struct slgt_info *info, unsigned short status)
2120 {
2121         if (status & BIT1) {
2122                 info->signals |= SerialSignal_DCD;
2123                 info->input_signal_events.dcd_up++;
2124         } else {
2125                 info->signals &= ~SerialSignal_DCD;
2126                 info->input_signal_events.dcd_down++;
2127         }
2128         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2129         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2130                 slgt_irq_off(info, IRQ_DCD);
2131                 return;
2132         }
2133         info->icount.dcd++;
2134 #if SYNCLINK_GENERIC_HDLC
2135         if (info->netcount) {
2136                 if (info->signals & SerialSignal_DCD)
2137                         netif_carrier_on(info->netdev);
2138                 else
2139                         netif_carrier_off(info->netdev);
2140         }
2141 #endif
2142         wake_up_interruptible(&info->status_event_wait_q);
2143         wake_up_interruptible(&info->event_wait_q);
2144         info->pending_bh |= BH_STATUS;
2145
2146         if (info->flags & ASYNC_CHECK_CD) {
2147                 if (info->signals & SerialSignal_DCD)
2148                         wake_up_interruptible(&info->open_wait);
2149                 else {
2150                         if (info->tty)
2151                                 tty_hangup(info->tty);
2152                 }
2153         }
2154 }
2155
2156 static void ri_change(struct slgt_info *info, unsigned short status)
2157 {
2158         if (status & BIT0) {
2159                 info->signals |= SerialSignal_RI;
2160                 info->input_signal_events.ri_up++;
2161         } else {
2162                 info->signals &= ~SerialSignal_RI;
2163                 info->input_signal_events.ri_down++;
2164         }
2165         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2166         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2167                 slgt_irq_off(info, IRQ_RI);
2168                 return;
2169         }
2170         info->icount.rng++;
2171         wake_up_interruptible(&info->status_event_wait_q);
2172         wake_up_interruptible(&info->event_wait_q);
2173         info->pending_bh |= BH_STATUS;
2174 }
2175
2176 static void isr_serial(struct slgt_info *info)
2177 {
2178         unsigned short status = rd_reg16(info, SSR);
2179
2180         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2181
2182         wr_reg16(info, SSR, status); /* clear pending */
2183
2184         info->irq_occurred = true;
2185
2186         if (info->params.mode == MGSL_MODE_ASYNC) {
2187                 if (status & IRQ_TXIDLE) {
2188                         if (info->tx_count)
2189                                 isr_txeom(info, status);
2190                 }
2191                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2192                         info->icount.brk++;
2193                         /* process break detection if tty control allows */
2194                         if (info->tty) {
2195                                 if (!(status & info->ignore_status_mask)) {
2196                                         if (info->read_status_mask & MASK_BREAK) {
2197                                                 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2198                                                 if (info->flags & ASYNC_SAK)
2199                                                         do_SAK(info->tty);
2200                                         }
2201                                 }
2202                         }
2203                 }
2204         } else {
2205                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2206                         isr_txeom(info, status);
2207
2208                 if (status & IRQ_RXIDLE) {
2209                         if (status & RXIDLE)
2210                                 info->icount.rxidle++;
2211                         else
2212                                 info->icount.exithunt++;
2213                         wake_up_interruptible(&info->event_wait_q);
2214                 }
2215
2216                 if (status & IRQ_RXOVER)
2217                         rx_start(info);
2218         }
2219
2220         if (status & IRQ_DSR)
2221                 dsr_change(info, status);
2222         if (status & IRQ_CTS)
2223                 cts_change(info, status);
2224         if (status & IRQ_DCD)
2225                 dcd_change(info, status);
2226         if (status & IRQ_RI)
2227                 ri_change(info, status);
2228 }
2229
2230 static void isr_rdma(struct slgt_info *info)
2231 {
2232         unsigned int status = rd_reg32(info, RDCSR);
2233
2234         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2235
2236         /* RDCSR (rx DMA control/status)
2237          *
2238          * 31..07  reserved
2239          * 06      save status byte to DMA buffer
2240          * 05      error
2241          * 04      eol (end of list)
2242          * 03      eob (end of buffer)
2243          * 02      IRQ enable
2244          * 01      reset
2245          * 00      enable
2246          */
2247         wr_reg32(info, RDCSR, status);  /* clear pending */
2248
2249         if (status & (BIT5 + BIT4)) {
2250                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2251                 info->rx_restart = true;
2252         }
2253         info->pending_bh |= BH_RECEIVE;
2254 }
2255
2256 static void isr_tdma(struct slgt_info *info)
2257 {
2258         unsigned int status = rd_reg32(info, TDCSR);
2259
2260         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2261
2262         /* TDCSR (tx DMA control/status)
2263          *
2264          * 31..06  reserved
2265          * 05      error
2266          * 04      eol (end of list)
2267          * 03      eob (end of buffer)
2268          * 02      IRQ enable
2269          * 01      reset
2270          * 00      enable
2271          */
2272         wr_reg32(info, TDCSR, status);  /* clear pending */
2273
2274         if (status & (BIT5 + BIT4 + BIT3)) {
2275                 // another transmit buffer has completed
2276                 // run bottom half to get more send data from user
2277                 info->pending_bh |= BH_TRANSMIT;
2278         }
2279 }
2280
2281 static void isr_txeom(struct slgt_info *info, unsigned short status)
2282 {
2283         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2284
2285         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2286         tdma_reset(info);
2287         reset_tbufs(info);
2288         if (status & IRQ_TXUNDER) {
2289                 unsigned short val = rd_reg16(info, TCR);
2290                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2291                 wr_reg16(info, TCR, val); /* clear reset bit */
2292         }
2293
2294         if (info->tx_active) {
2295                 if (info->params.mode != MGSL_MODE_ASYNC) {
2296                         if (status & IRQ_TXUNDER)
2297                                 info->icount.txunder++;
2298                         else if (status & IRQ_TXIDLE)
2299                                 info->icount.txok++;
2300                 }
2301
2302                 info->tx_active = false;
2303                 info->tx_count = 0;
2304
2305                 del_timer(&info->tx_timer);
2306
2307                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2308                         info->signals &= ~SerialSignal_RTS;
2309                         info->drop_rts_on_tx_done = false;
2310                         set_signals(info);
2311                 }
2312
2313 #if SYNCLINK_GENERIC_HDLC
2314                 if (info->netcount)
2315                         hdlcdev_tx_done(info);
2316                 else
2317 #endif
2318                 {
2319                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2320                                 tx_stop(info);
2321                                 return;
2322                         }
2323                         info->pending_bh |= BH_TRANSMIT;
2324                 }
2325         }
2326 }
2327
2328 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2329 {
2330         struct cond_wait *w, *prev;
2331
2332         /* wake processes waiting for specific transitions */
2333         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2334                 if (w->data & changed) {
2335                         w->data = state;
2336                         wake_up_interruptible(&w->q);
2337                         if (prev != NULL)
2338                                 prev->next = w->next;
2339                         else
2340                                 info->gpio_wait_q = w->next;
2341                 } else
2342                         prev = w;
2343         }
2344 }
2345
2346 /* interrupt service routine
2347  *
2348  *      irq     interrupt number
2349  *      dev_id  device ID supplied during interrupt registration
2350  */
2351 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2352 {
2353         struct slgt_info *info = dev_id;
2354         unsigned int gsr;
2355         unsigned int i;
2356
2357         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2358
2359         spin_lock(&info->lock);
2360
2361         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2362                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2363                 info->irq_occurred = true;
2364                 for(i=0; i < info->port_count ; i++) {
2365                         if (info->port_array[i] == NULL)
2366                                 continue;
2367                         if (gsr & (BIT8 << i))
2368                                 isr_serial(info->port_array[i]);
2369                         if (gsr & (BIT16 << (i*2)))
2370                                 isr_rdma(info->port_array[i]);
2371                         if (gsr & (BIT17 << (i*2)))
2372                                 isr_tdma(info->port_array[i]);
2373                 }
2374         }
2375
2376         if (info->gpio_present) {
2377                 unsigned int state;
2378                 unsigned int changed;
2379                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2380                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2381                         /* read latched state of GPIO signals */
2382                         state = rd_reg32(info, IOVR);
2383                         /* clear pending GPIO interrupt bits */
2384                         wr_reg32(info, IOSR, changed);
2385                         for (i=0 ; i < info->port_count ; i++) {
2386                                 if (info->port_array[i] != NULL)
2387                                         isr_gpio(info->port_array[i], changed, state);
2388                         }
2389                 }
2390         }
2391
2392         for(i=0; i < info->port_count ; i++) {
2393                 struct slgt_info *port = info->port_array[i];
2394
2395                 if (port && (port->count || port->netcount) &&
2396                     port->pending_bh && !port->bh_running &&
2397                     !port->bh_requested) {
2398                         DBGISR(("%s bh queued\n", port->device_name));
2399                         schedule_work(&port->task);
2400                         port->bh_requested = true;
2401                 }
2402         }
2403
2404         spin_unlock(&info->lock);
2405
2406         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2407         return IRQ_HANDLED;
2408 }
2409
2410 static int startup(struct slgt_info *info)
2411 {
2412         DBGINFO(("%s startup\n", info->device_name));
2413
2414         if (info->flags & ASYNC_INITIALIZED)
2415                 return 0;
2416
2417         if (!info->tx_buf) {
2418                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2419                 if (!info->tx_buf) {
2420                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2421                         return -ENOMEM;
2422                 }
2423         }
2424
2425         info->pending_bh = 0;
2426
2427         memset(&info->icount, 0, sizeof(info->icount));
2428
2429         /* program hardware for current parameters */
2430         change_params(info);
2431
2432         if (info->tty)
2433                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2434
2435         info->flags |= ASYNC_INITIALIZED;
2436
2437         return 0;
2438 }
2439
2440 /*
2441  *  called by close() and hangup() to shutdown hardware
2442  */
2443 static void shutdown(struct slgt_info *info)
2444 {
2445         unsigned long flags;
2446
2447         if (!(info->flags & ASYNC_INITIALIZED))
2448                 return;
2449
2450         DBGINFO(("%s shutdown\n", info->device_name));
2451
2452         /* clear status wait queue because status changes */
2453         /* can't happen after shutting down the hardware */
2454         wake_up_interruptible(&info->status_event_wait_q);
2455         wake_up_interruptible(&info->event_wait_q);
2456
2457         del_timer_sync(&info->tx_timer);
2458         del_timer_sync(&info->rx_timer);
2459
2460         kfree(info->tx_buf);
2461         info->tx_buf = NULL;
2462
2463         spin_lock_irqsave(&info->lock,flags);
2464
2465         tx_stop(info);
2466         rx_stop(info);
2467
2468         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2469
2470         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2471                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2472                 set_signals(info);
2473         }
2474
2475         flush_cond_wait(&info->gpio_wait_q);
2476
2477         spin_unlock_irqrestore(&info->lock,flags);
2478
2479         if (info->tty)
2480                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2481
2482         info->flags &= ~ASYNC_INITIALIZED;
2483 }
2484
2485 static void program_hw(struct slgt_info *info)
2486 {
2487         unsigned long flags;
2488
2489         spin_lock_irqsave(&info->lock,flags);
2490
2491         rx_stop(info);
2492         tx_stop(info);
2493
2494         if (info->params.mode != MGSL_MODE_ASYNC ||
2495             info->netcount)
2496                 sync_mode(info);
2497         else
2498                 async_mode(info);
2499
2500         set_signals(info);
2501
2502         info->dcd_chkcount = 0;
2503         info->cts_chkcount = 0;
2504         info->ri_chkcount = 0;
2505         info->dsr_chkcount = 0;
2506
2507         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2508         get_signals(info);
2509
2510         if (info->netcount ||
2511             (info->tty && info->tty->termios->c_cflag & CREAD))
2512                 rx_start(info);
2513
2514         spin_unlock_irqrestore(&info->lock,flags);
2515 }
2516
2517 /*
2518  * reconfigure adapter based on new parameters
2519  */
2520 static void change_params(struct slgt_info *info)
2521 {
2522         unsigned cflag;
2523         int bits_per_char;
2524
2525         if (!info->tty || !info->tty->termios)
2526                 return;
2527         DBGINFO(("%s change_params\n", info->device_name));
2528
2529         cflag = info->tty->termios->c_cflag;
2530
2531         /* if B0 rate (hangup) specified then negate DTR and RTS */
2532         /* otherwise assert DTR and RTS */
2533         if (cflag & CBAUD)
2534                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2535         else
2536                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2537
2538         /* byte size and parity */
2539
2540         switch (cflag & CSIZE) {
2541         case CS5: info->params.data_bits = 5; break;
2542         case CS6: info->params.data_bits = 6; break;
2543         case CS7: info->params.data_bits = 7; break;
2544         case CS8: info->params.data_bits = 8; break;
2545         default:  info->params.data_bits = 7; break;
2546         }
2547
2548         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2549
2550         if (cflag & PARENB)
2551                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2552         else
2553                 info->params.parity = ASYNC_PARITY_NONE;
2554
2555         /* calculate number of jiffies to transmit a full
2556          * FIFO (32 bytes) at specified data rate
2557          */
2558         bits_per_char = info->params.data_bits +
2559                         info->params.stop_bits + 1;
2560
2561         info->params.data_rate = tty_get_baud_rate(info->tty);
2562
2563         if (info->params.data_rate) {
2564                 info->timeout = (32*HZ*bits_per_char) /
2565                                 info->params.data_rate;
2566         }
2567         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2568
2569         if (cflag & CRTSCTS)
2570                 info->flags |= ASYNC_CTS_FLOW;
2571         else
2572                 info->flags &= ~ASYNC_CTS_FLOW;
2573
2574         if (cflag & CLOCAL)
2575                 info->flags &= ~ASYNC_CHECK_CD;
2576         else
2577                 info->flags |= ASYNC_CHECK_CD;
2578
2579         /* process tty input control flags */
2580
2581         info->read_status_mask = IRQ_RXOVER;
2582         if (I_INPCK(info->tty))
2583                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2584         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2585                 info->read_status_mask |= MASK_BREAK;
2586         if (I_IGNPAR(info->tty))
2587                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2588         if (I_IGNBRK(info->tty)) {
2589                 info->ignore_status_mask |= MASK_BREAK;
2590                 /* If ignoring parity and break indicators, ignore
2591                  * overruns too.  (For real raw support).
2592                  */
2593                 if (I_IGNPAR(info->tty))
2594                         info->ignore_status_mask |= MASK_OVERRUN;
2595         }
2596
2597         program_hw(info);
2598 }
2599
2600 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2601 {
2602         DBGINFO(("%s get_stats\n",  info->device_name));
2603         if (!user_icount) {
2604                 memset(&info->icount, 0, sizeof(info->icount));
2605         } else {
2606                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2607                         return -EFAULT;
2608         }
2609         return 0;
2610 }
2611
2612 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2613 {
2614         DBGINFO(("%s get_params\n", info->device_name));
2615         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2616                 return -EFAULT;
2617         return 0;
2618 }
2619
2620 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2621 {
2622         unsigned long flags;
2623         MGSL_PARAMS tmp_params;
2624
2625         DBGINFO(("%s set_params\n", info->device_name));
2626         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2627                 return -EFAULT;
2628
2629         spin_lock_irqsave(&info->lock, flags);
2630         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2631         spin_unlock_irqrestore(&info->lock, flags);
2632
2633         change_params(info);
2634
2635         return 0;
2636 }
2637
2638 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2639 {
2640         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2641         if (put_user(info->idle_mode, idle_mode))
2642                 return -EFAULT;
2643         return 0;
2644 }
2645
2646 static int set_txidle(struct slgt_info *info, int idle_mode)
2647 {
2648         unsigned long flags;
2649         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2650         spin_lock_irqsave(&info->lock,flags);
2651         info->idle_mode = idle_mode;
2652         if (info->params.mode != MGSL_MODE_ASYNC)
2653                 tx_set_idle(info);
2654         spin_unlock_irqrestore(&info->lock,flags);
2655         return 0;
2656 }
2657
2658 static int tx_enable(struct slgt_info *info, int enable)
2659 {
2660         unsigned long flags;
2661         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2662         spin_lock_irqsave(&info->lock,flags);
2663         if (enable) {
2664                 if (!info->tx_enabled)
2665                         tx_start(info);
2666         } else {
2667                 if (info->tx_enabled)
2668                         tx_stop(info);
2669         }
2670         spin_unlock_irqrestore(&info->lock,flags);
2671         return 0;
2672 }
2673
2674 /*
2675  * abort transmit HDLC frame
2676  */
2677 static int tx_abort(struct slgt_info *info)
2678 {
2679         unsigned long flags;
2680         DBGINFO(("%s tx_abort\n", info->device_name));
2681         spin_lock_irqsave(&info->lock,flags);
2682         tdma_reset(info);
2683         spin_unlock_irqrestore(&info->lock,flags);
2684         return 0;
2685 }
2686
2687 static int rx_enable(struct slgt_info *info, int enable)
2688 {
2689         unsigned long flags;
2690         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2691         spin_lock_irqsave(&info->lock,flags);
2692         if (enable) {
2693                 if (!info->rx_enabled)
2694                         rx_start(info);
2695                 else if (enable == 2) {
2696                         /* force hunt mode (write 1 to RCR[3]) */
2697                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2698                 }
2699         } else {
2700                 if (info->rx_enabled)
2701                         rx_stop(info);
2702         }
2703         spin_unlock_irqrestore(&info->lock,flags);
2704         return 0;
2705 }
2706
2707 /*
2708  *  wait for specified event to occur
2709  */
2710 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2711 {
2712         unsigned long flags;
2713         int s;
2714         int rc=0;
2715         struct mgsl_icount cprev, cnow;
2716         int events;
2717         int mask;
2718         struct  _input_signal_events oldsigs, newsigs;
2719         DECLARE_WAITQUEUE(wait, current);
2720
2721         if (get_user(mask, mask_ptr))
2722                 return -EFAULT;
2723
2724         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2725
2726         spin_lock_irqsave(&info->lock,flags);
2727
2728         /* return immediately if state matches requested events */
2729         get_signals(info);
2730         s = info->signals;
2731
2732         events = mask &
2733                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2734                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2735                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2736                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2737         if (events) {
2738                 spin_unlock_irqrestore(&info->lock,flags);
2739                 goto exit;
2740         }
2741
2742         /* save current irq counts */
2743         cprev = info->icount;
2744         oldsigs = info->input_signal_events;
2745
2746         /* enable hunt and idle irqs if needed */
2747         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2748                 unsigned short val = rd_reg16(info, SCR);
2749                 if (!(val & IRQ_RXIDLE))
2750                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2751         }
2752
2753         set_current_state(TASK_INTERRUPTIBLE);
2754         add_wait_queue(&info->event_wait_q, &wait);
2755
2756         spin_unlock_irqrestore(&info->lock,flags);
2757
2758         for(;;) {
2759                 schedule();
2760                 if (signal_pending(current)) {
2761                         rc = -ERESTARTSYS;
2762                         break;
2763                 }
2764
2765                 /* get current irq counts */
2766                 spin_lock_irqsave(&info->lock,flags);
2767                 cnow = info->icount;
2768                 newsigs = info->input_signal_events;
2769                 set_current_state(TASK_INTERRUPTIBLE);
2770                 spin_unlock_irqrestore(&info->lock,flags);
2771
2772                 /* if no change, wait aborted for some reason */
2773                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2774                     newsigs.dsr_down == oldsigs.dsr_down &&
2775                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2776                     newsigs.dcd_down == oldsigs.dcd_down &&
2777                     newsigs.cts_up   == oldsigs.cts_up   &&
2778                     newsigs.cts_down == oldsigs.cts_down &&
2779                     newsigs.ri_up    == oldsigs.ri_up    &&
2780                     newsigs.ri_down  == oldsigs.ri_down  &&
2781                     cnow.exithunt    == cprev.exithunt   &&
2782                     cnow.rxidle      == cprev.rxidle) {
2783                         rc = -EIO;
2784                         break;
2785                 }
2786
2787                 events = mask &
2788                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2789                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2790                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2791                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2792                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2793                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2794                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2795                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2796                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2797                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2798                 if (events)
2799                         break;
2800
2801                 cprev = cnow;
2802                 oldsigs = newsigs;
2803         }
2804
2805         remove_wait_queue(&info->event_wait_q, &wait);
2806         set_current_state(TASK_RUNNING);
2807
2808
2809         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2810                 spin_lock_irqsave(&info->lock,flags);
2811                 if (!waitqueue_active(&info->event_wait_q)) {
2812                         /* disable enable exit hunt mode/idle rcvd IRQs */
2813                         wr_reg16(info, SCR,
2814                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2815                 }
2816                 spin_unlock_irqrestore(&info->lock,flags);
2817         }
2818 exit:
2819         if (rc == 0)
2820                 rc = put_user(events, mask_ptr);
2821         return rc;
2822 }
2823
2824 static int get_interface(struct slgt_info *info, int __user *if_mode)
2825 {
2826         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2827         if (put_user(info->if_mode, if_mode))
2828                 return -EFAULT;
2829         return 0;
2830 }
2831
2832 static int set_interface(struct slgt_info *info, int if_mode)
2833 {
2834         unsigned long flags;
2835         unsigned short val;
2836
2837         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2838         spin_lock_irqsave(&info->lock,flags);
2839         info->if_mode = if_mode;
2840
2841         msc_set_vcr(info);
2842
2843         /* TCR (tx control) 07  1=RTS driver control */
2844         val = rd_reg16(info, TCR);
2845         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2846                 val |= BIT7;
2847         else
2848                 val &= ~BIT7;
2849         wr_reg16(info, TCR, val);
2850
2851         spin_unlock_irqrestore(&info->lock,flags);
2852         return 0;
2853 }
2854
2855 /*
2856  * set general purpose IO pin state and direction
2857  *
2858  * user_gpio fields:
2859  * state   each bit indicates a pin state
2860  * smask   set bit indicates pin state to set
2861  * dir     each bit indicates a pin direction (0=input, 1=output)
2862  * dmask   set bit indicates pin direction to set
2863  */
2864 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2865 {
2866         unsigned long flags;
2867         struct gpio_desc gpio;
2868         __u32 data;
2869
2870         if (!info->gpio_present)
2871                 return -EINVAL;
2872         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2873                 return -EFAULT;
2874         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2875                  info->device_name, gpio.state, gpio.smask,
2876                  gpio.dir, gpio.dmask));
2877
2878         spin_lock_irqsave(&info->lock,flags);
2879         if (gpio.dmask) {
2880                 data = rd_reg32(info, IODR);
2881                 data |= gpio.dmask & gpio.dir;
2882                 data &= ~(gpio.dmask & ~gpio.dir);
2883                 wr_reg32(info, IODR, data);
2884         }
2885         if (gpio.smask) {
2886                 data = rd_reg32(info, IOVR);
2887                 data |= gpio.smask & gpio.state;
2888                 data &= ~(gpio.smask & ~gpio.state);
2889                 wr_reg32(info, IOVR, data);
2890         }
2891         spin_unlock_irqrestore(&info->lock,flags);
2892
2893         return 0;
2894 }
2895
2896 /*
2897  * get general purpose IO pin state and direction
2898  */
2899 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2900 {
2901         struct gpio_desc gpio;
2902         if (!info->gpio_present)
2903                 return -EINVAL;
2904         gpio.state = rd_reg32(info, IOVR);
2905         gpio.smask = 0xffffffff;
2906         gpio.dir   = rd_reg32(info, IODR);
2907         gpio.dmask = 0xffffffff;
2908         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2909                 return -EFAULT;
2910         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2911                  info->device_name, gpio.state, gpio.dir));
2912         return 0;
2913 }
2914
2915 /*
2916  * conditional wait facility
2917  */
2918 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2919 {
2920         init_waitqueue_head(&w->q);
2921         init_waitqueue_entry(&w->wait, current);
2922         w->data = data;
2923 }
2924
2925 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2926 {
2927         set_current_state(TASK_INTERRUPTIBLE);
2928         add_wait_queue(&w->q, &w->wait);
2929         w->next = *head;
2930         *head = w;
2931 }
2932
2933 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2934 {
2935         struct cond_wait *w, *prev;
2936         remove_wait_queue(&cw->q, &cw->wait);
2937         set_current_state(TASK_RUNNING);
2938         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2939                 if (w == cw) {
2940                         if (prev != NULL)
2941                                 prev->next = w->next;
2942                         else
2943                                 *head = w->next;
2944                         break;
2945                 }
2946         }
2947 }
2948
2949 static void flush_cond_wait(struct cond_wait **head)
2950 {
2951         while (*head != NULL) {
2952                 wake_up_interruptible(&(*head)->q);
2953                 *head = (*head)->next;
2954         }
2955 }
2956
2957 /*
2958  * wait for general purpose I/O pin(s) to enter specified state
2959  *
2960  * user_gpio fields:
2961  * state - bit indicates target pin state
2962  * smask - set bit indicates watched pin
2963  *
2964  * The wait ends when at least one watched pin enters the specified
2965  * state. When 0 (no error) is returned, user_gpio->state is set to the
2966  * state of all GPIO pins when the wait ends.
2967  *
2968  * Note: Each pin may be a dedicated input, dedicated output, or
2969  * configurable input/output. The number and configuration of pins
2970  * varies with the specific adapter model. Only input pins (dedicated
2971  * or configured) can be monitored with this function.
2972  */
2973 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2974 {
2975         unsigned long flags;
2976         int rc = 0;
2977         struct gpio_desc gpio;
2978         struct cond_wait wait;
2979         u32 state;
2980
2981         if (!info->gpio_present)
2982                 return -EINVAL;
2983         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2984                 return -EFAULT;
2985         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2986                  info->device_name, gpio.state, gpio.smask));
2987         /* ignore output pins identified by set IODR bit */
2988         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2989                 return -EINVAL;
2990         init_cond_wait(&wait, gpio.smask);
2991
2992         spin_lock_irqsave(&info->lock, flags);
2993         /* enable interrupts for watched pins */
2994         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2995         /* get current pin states */
2996         state = rd_reg32(info, IOVR);
2997
2998         if (gpio.smask & ~(state ^ gpio.state)) {
2999                 /* already in target state */
3000                 gpio.state = state;
3001         } else {
3002                 /* wait for target state */
3003                 add_cond_wait(&info->gpio_wait_q, &wait);
3004                 spin_unlock_irqrestore(&info->lock, flags);
3005                 schedule();
3006                 if (signal_pending(current))
3007                         rc = -ERESTARTSYS;
3008                 else
3009                         gpio.state = wait.data;
3010                 spin_lock_irqsave(&info->lock, flags);
3011                 remove_cond_wait(&info->gpio_wait_q, &wait);
3012         }
3013
3014         /* disable all GPIO interrupts if no waiting processes */
3015         if (info->gpio_wait_q == NULL)
3016                 wr_reg32(info, IOER, 0);
3017         spin_unlock_irqrestore(&info->lock,flags);
3018
3019         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3020                 rc = -EFAULT;
3021         return rc;
3022 }
3023
3024 static int modem_input_wait(struct slgt_info *info,int arg)
3025 {
3026         unsigned long flags;
3027         int rc;
3028         struct mgsl_icount cprev, cnow;
3029         DECLARE_WAITQUEUE(wait, current);
3030
3031         /* save current irq counts */
3032         spin_lock_irqsave(&info->lock,flags);
3033         cprev = info->icount;
3034         add_wait_queue(&info->status_event_wait_q, &wait);
3035         set_current_state(TASK_INTERRUPTIBLE);
3036         spin_unlock_irqrestore(&info->lock,flags);
3037
3038         for(;;) {
3039                 schedule();
3040                 if (signal_pending(current)) {
3041                         rc = -ERESTARTSYS;
3042                         break;
3043                 }
3044
3045                 /* get new irq counts */
3046                 spin_lock_irqsave(&info->lock,flags);
3047                 cnow = info->icount;
3048                 set_current_state(TASK_INTERRUPTIBLE);
3049                 spin_unlock_irqrestore(&info->lock,flags);
3050
3051                 /* if no change, wait aborted for some reason */
3052                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3053                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3054                         rc = -EIO;
3055                         break;
3056                 }
3057
3058                 /* check for change in caller specified modem input */
3059                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3060                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3061                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3062                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3063                         rc = 0;
3064                         break;
3065                 }
3066
3067                 cprev = cnow;
3068         }
3069         remove_wait_queue(&info->status_event_wait_q, &wait);
3070         set_current_state(TASK_RUNNING);
3071         return rc;
3072 }
3073
3074 /*
3075  *  return state of serial control and status signals
3076  */
3077 static int tiocmget(struct tty_struct *tty, struct file *file)
3078 {
3079         struct slgt_info *info = tty->driver_data;
3080         unsigned int result;
3081         unsigned long flags;
3082
3083         spin_lock_irqsave(&info->lock,flags);
3084         get_signals(info);
3085         spin_unlock_irqrestore(&info->lock,flags);
3086
3087         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3088                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3089                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3090                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3091                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3092                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3093
3094         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3095         return result;
3096 }
3097
3098 /*
3099  * set modem control signals (DTR/RTS)
3100  *
3101  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3102  *              TIOCMSET = set/clear signal values
3103  *      value   bit mask for command
3104  */
3105 static int tiocmset(struct tty_struct *tty, struct file *file,
3106                     unsigned int set, unsigned int clear)
3107 {
3108         struct slgt_info *info = tty->driver_data;
3109         unsigned long flags;
3110
3111         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3112
3113         if (set & TIOCM_RTS)
3114                 info->signals |= SerialSignal_RTS;
3115         if (set & TIOCM_DTR)
3116                 info->signals |= SerialSignal_DTR;
3117         if (clear & TIOCM_RTS)
3118                 info->signals &= ~SerialSignal_RTS;
3119         if (clear & TIOCM_DTR)
3120                 info->signals &= ~SerialSignal_DTR;
3121
3122         spin_lock_irqsave(&info->lock,flags);
3123         set_signals(info);
3124         spin_unlock_irqrestore(&info->lock,flags);
3125         return 0;
3126 }
3127
3128 /*
3129  *  block current process until the device is ready to open
3130  */
3131 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3132                            struct slgt_info *info)
3133 {
3134         DECLARE_WAITQUEUE(wait, current);
3135         int             retval;
3136         bool            do_clocal = false;
3137         bool            extra_count = false;
3138         unsigned long   flags;
3139
3140         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3141
3142         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3143                 /* nonblock mode is set or port is not enabled */
3144                 info->flags |= ASYNC_NORMAL_ACTIVE;
3145                 return 0;
3146         }
3147
3148         if (tty->termios->c_cflag & CLOCAL)
3149                 do_clocal = true;
3150
3151         /* Wait for carrier detect and the line to become
3152          * free (i.e., not in use by the callout).  While we are in
3153          * this loop, info->count is dropped by one, so that
3154          * close() knows when to free things.  We restore it upon
3155          * exit, either normal or abnormal.
3156          */
3157
3158         retval = 0;
3159         add_wait_queue(&info->open_wait, &wait);
3160
3161         spin_lock_irqsave(&info->lock, flags);
3162         if (!tty_hung_up_p(filp)) {
3163                 extra_count = true;
3164                 info->count--;
3165         }
3166         spin_unlock_irqrestore(&info->lock, flags);
3167         info->blocked_open++;
3168
3169         while (1) {
3170                 if ((tty->termios->c_cflag & CBAUD)) {
3171                         spin_lock_irqsave(&info->lock,flags);
3172                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3173                         set_signals(info);
3174                         spin_unlock_irqrestore(&info->lock,flags);
3175                 }
3176
3177                 set_current_state(TASK_INTERRUPTIBLE);
3178
3179                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3180                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3181                                         -EAGAIN : -ERESTARTSYS;
3182                         break;
3183                 }
3184
3185                 spin_lock_irqsave(&info->lock,flags);
3186                 get_signals(info);
3187                 spin_unlock_irqrestore(&info->lock,flags);
3188
3189                 if (!(info->flags & ASYNC_CLOSING) &&
3190                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3191                         break;
3192                 }
3193
3194                 if (signal_pending(current)) {
3195                         retval = -ERESTARTSYS;
3196                         break;
3197                 }
3198
3199                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3200                 schedule();
3201         }
3202
3203         set_current_state(TASK_RUNNING);
3204         remove_wait_queue(&info->open_wait, &wait);
3205
3206         if (extra_count)
3207                 info->count++;
3208         info->blocked_open--;
3209
3210         if (!retval)
3211                 info->flags |= ASYNC_NORMAL_ACTIVE;
3212
3213         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3214         return retval;
3215 }
3216
3217 static int alloc_tmp_rbuf(struct slgt_info *info)
3218 {
3219         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3220         if (info->tmp_rbuf == NULL)
3221                 return -ENOMEM;
3222         return 0;
3223 }
3224
3225 static void free_tmp_rbuf(struct slgt_info *info)
3226 {
3227         kfree(info->tmp_rbuf);
3228         info->tmp_rbuf = NULL;
3229 }
3230
3231 /*
3232  * allocate DMA descriptor lists.
3233  */
3234 static int alloc_desc(struct slgt_info *info)
3235 {
3236         unsigned int i;
3237         unsigned int pbufs;
3238
3239         /* allocate memory to hold descriptor lists */
3240         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3241         if (info->bufs == NULL)
3242                 return -ENOMEM;
3243
3244         memset(info->bufs, 0, DESC_LIST_SIZE);
3245
3246         info->rbufs = (struct slgt_desc*)info->bufs;
3247         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3248
3249         pbufs = (unsigned int)info->bufs_dma_addr;
3250
3251         /*
3252          * Build circular lists of descriptors
3253          */
3254
3255         for (i=0; i < info->rbuf_count; i++) {
3256                 /* physical address of this descriptor */
3257                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3258
3259                 /* physical address of next descriptor */
3260                 if (i == info->rbuf_count - 1)
3261                         info->rbufs[i].next = cpu_to_le32(pbufs);
3262                 else
3263                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3264                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3265         }
3266
3267         for (i=0; i < info->tbuf_count; i++) {
3268                 /* physical address of this descriptor */
3269                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3270
3271                 /* physical address of next descriptor */
3272                 if (i == info->tbuf_count - 1)
3273                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3274                 else
3275                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3276         }
3277
3278         return 0;
3279 }
3280
3281 static void free_desc(struct slgt_info *info)
3282 {
3283         if (info->bufs != NULL) {
3284                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3285                 info->bufs  = NULL;
3286                 info->rbufs = NULL;
3287                 info->tbufs = NULL;
3288         }
3289 }
3290
3291 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3292 {
3293         int i;
3294         for (i=0; i < count; i++) {
3295                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3296                         return -ENOMEM;
3297                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3298         }
3299         return 0;
3300 }
3301
3302 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3303 {
3304         int i;
3305         for (i=0; i < count; i++) {
3306                 if (bufs[i].buf == NULL)
3307                         continue;
3308                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3309                 bufs[i].buf = NULL;
3310         }
3311 }
3312
3313 static int alloc_dma_bufs(struct slgt_info *info)
3314 {
3315         info->rbuf_count = 32;
3316         info->tbuf_count = 32;
3317
3318         if (alloc_desc(info) < 0 ||
3319             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3320             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3321             alloc_tmp_rbuf(info) < 0) {
3322                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3323                 return -ENOMEM;
3324         }
3325         reset_rbufs(info);
3326         return 0;
3327 }
3328
3329 static void free_dma_bufs(struct slgt_info *info)
3330 {
3331         if (info->bufs) {
3332                 free_bufs(info, info->rbufs, info->rbuf_count);
3333                 free_bufs(info, info->tbufs, info->tbuf_count);
3334                 free_desc(info);
3335         }
3336         free_tmp_rbuf(info);
3337 }
3338
3339 static int claim_resources(struct slgt_info *info)
3340 {
3341         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3342                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3343                         info->device_name, info->phys_reg_addr));
3344                 info->init_error = DiagStatus_AddressConflict;
3345                 goto errout;
3346         }
3347         else
3348                 info->reg_addr_requested = true;
3349
3350         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3351         if (!info->reg_addr) {
3352                 DBGERR(("%s cant map device registers, addr=%08X\n",
3353                         info->device_name, info->phys_reg_addr));
3354                 info->init_error = DiagStatus_CantAssignPciResources;
3355                 goto errout;
3356         }
3357         return 0;
3358
3359 errout:
3360         release_resources(info);
3361         return -ENODEV;
3362 }
3363
3364 static void release_resources(struct slgt_info *info)
3365 {
3366         if (info->irq_requested) {
3367                 free_irq(info->irq_level, info);
3368                 info->irq_requested = false;
3369         }
3370
3371         if (info->reg_addr_requested) {
3372                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3373                 info->reg_addr_requested = false;
3374         }
3375
3376         if (info->reg_addr) {
3377                 iounmap(info->reg_addr);
3378                 info->reg_addr = NULL;
3379         }
3380 }
3381
3382 /* Add the specified device instance data structure to the
3383  * global linked list of devices and increment the device count.
3384  */
3385 static void add_device(struct slgt_info *info)
3386 {
3387         char *devstr;
3388
3389         info->next_device = NULL;
3390         info->line = slgt_device_count;
3391         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3392
3393         if (info->line < MAX_DEVICES) {
3394                 if (maxframe[info->line])
3395                         info->max_frame_size = maxframe[info->line];
3396                 info->dosyncppp = dosyncppp[info->line];
3397         }
3398
3399         slgt_device_count++;
3400
3401         if (!slgt_device_list)
3402                 slgt_device_list = info;
3403         else {
3404                 struct slgt_info *current_dev = slgt_device_list;
3405                 while(current_dev->next_device)
3406                         current_dev = current_dev->next_device;
3407                 current_dev->next_device = info;
3408         }
3409
3410         if (info->max_frame_size < 4096)
3411                 info->max_frame_size = 4096;
3412         else if (info->max_frame_size > 65535)
3413                 info->max_frame_size = 65535;
3414
3415         switch(info->pdev->device) {
3416         case SYNCLINK_GT_DEVICE_ID:
3417                 devstr = "GT";
3418                 break;
3419         case SYNCLINK_GT2_DEVICE_ID:
3420                 devstr = "GT2";
3421                 break;
3422         case SYNCLINK_GT4_DEVICE_ID:
3423                 devstr = "GT4";
3424                 break;
3425         case SYNCLINK_AC_DEVICE_ID:
3426                 devstr = "AC";
3427                 info->params.mode = MGSL_MODE_ASYNC;
3428                 break;
3429         default:
3430                 devstr = "(unknown model)";
3431         }
3432         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3433                 devstr, info->device_name, info->phys_reg_addr,
3434                 info->irq_level, info->max_frame_size);
3435
3436 #if SYNCLINK_GENERIC_HDLC
3437         hdlcdev_init(info);
3438 #endif
3439 }
3440
3441 /*
3442  *  allocate device instance structure, return NULL on failure
3443  */
3444 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3445 {
3446         struct slgt_info *info;
3447
3448         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3449
3450         if (!info) {
3451                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3452                         driver_name, adapter_num, port_num));
3453         } else {
3454                 info->magic = MGSL_MAGIC;
3455                 INIT_WORK(&info->task, bh_handler);
3456                 info->max_frame_size = 4096;
3457                 info->raw_rx_size = DMABUFSIZE;
3458                 info->close_delay = 5*HZ/10;
3459                 info->closing_wait = 30*HZ;
3460                 init_waitqueue_head(&info->open_wait);
3461                 init_waitqueue_head(&info->close_wait);
3462                 init_waitqueue_head(&info->status_event_wait_q);
3463                 init_waitqueue_head(&info->event_wait_q);
3464                 spin_lock_init(&info->netlock);
3465                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3466                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3467                 info->adapter_num = adapter_num;
3468                 info->port_num = port_num;
3469
3470                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3471                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3472
3473                 /* Copy configuration info to device instance data */
3474                 info->pdev = pdev;
3475                 info->irq_level = pdev->irq;
3476                 info->phys_reg_addr = pci_resource_start(pdev,0);
3477
3478                 info->bus_type = MGSL_BUS_TYPE_PCI;
3479                 info->irq_flags = IRQF_SHARED;
3480
3481                 info->init_error = -1; /* assume error, set to 0 on successful init */
3482         }
3483
3484         return info;
3485 }
3486
3487 static void device_init(int adapter_num, struct pci_dev *pdev)
3488 {
3489         struct slgt_info *port_array[SLGT_MAX_PORTS];
3490         int i;
3491         int port_count = 1;
3492
3493         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3494                 port_count = 2;
3495         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3496                 port_count = 4;
3497
3498         /* allocate device instances for all ports */
3499         for (i=0; i < port_count; ++i) {
3500                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3501                 if (port_array[i] == NULL) {
3502                         for (--i; i >= 0; --i)
3503                                 kfree(port_array[i]);
3504                         return;
3505                 }
3506         }
3507
3508         /* give copy of port_array to all ports and add to device list  */
3509         for (i=0; i < port_count; ++i) {
3510                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3511                 add_device(port_array[i]);
3512                 port_array[i]->port_count = port_count;
3513                 spin_lock_init(&port_array[i]->lock);
3514         }
3515
3516         /* Allocate and claim adapter resources */
3517         if (!claim_resources(port_array[0])) {
3518
3519                 alloc_dma_bufs(port_array[0]);
3520
3521                 /* copy resource information from first port to others */
3522                 for (i = 1; i < port_count; ++i) {
3523                         port_array[i]->lock      = port_array[0]->lock;
3524                         port_array[i]->irq_level = port_array[0]->irq_level;
3525                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3526                         alloc_dma_bufs(port_array[i]);
3527                 }
3528
3529                 if (request_irq(port_array[0]->irq_level,
3530                                         slgt_interrupt,
3531                                         port_array[0]->irq_flags,
3532                                         port_array[0]->device_name,
3533                                         port_array[0]) < 0) {
3534                         DBGERR(("%s request_irq failed IRQ=%d\n",
3535                                 port_array[0]->device_name,
3536                                 port_array[0]->irq_level));
3537                 } else {
3538                         port_array[0]->irq_requested = true;
3539                         adapter_test(port_array[0]);
3540                         for (i=1 ; i < port_count ; i++) {
3541                                 port_array[i]->init_error = port_array[0]->init_error;
3542                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3543                         }
3544                 }
3545         }
3546
3547         for (i=0; i < port_count; ++i)
3548                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3549 }
3550
3551 static int __devinit init_one(struct pci_dev *dev,
3552                               const struct pci_device_id *ent)
3553 {
3554         if (pci_enable_device(dev)) {
3555                 printk("error enabling pci device %p\n", dev);
3556                 return -EIO;
3557         }
3558         pci_set_master(dev);
3559         device_init(slgt_device_count, dev);
3560         return 0;
3561 }
3562
3563 static void __devexit remove_one(struct pci_dev *dev)
3564 {
3565 }
3566
3567 static const struct tty_operations ops = {
3568         .open = open,
3569         .close = close,
3570         .write = write,
3571         .put_char = put_char,
3572         .flush_chars = flush_chars,
3573         .write_room = write_room,
3574         .chars_in_buffer = chars_in_buffer,
3575         .flush_buffer = flush_buffer,
3576         .ioctl = ioctl,
3577         .compat_ioctl = slgt_compat_ioctl,
3578         .throttle = throttle,
3579         .unthrottle = unthrottle,
3580         .send_xchar = send_xchar,
3581         .break_ctl = set_break,
3582         .wait_until_sent = wait_until_sent,
3583         .read_proc = read_proc,
3584         .set_termios = set_termios,
3585         .stop = tx_hold,
3586         .start = tx_release,
3587         .hangup = hangup,
3588         .tiocmget = tiocmget,
3589         .tiocmset = tiocmset,
3590 };
3591
3592 static void slgt_cleanup(void)
3593 {
3594         int rc;
3595         struct slgt_info *info;
3596         struct slgt_info *tmp;
3597
3598         printk("unload %s %s\n", driver_name, driver_version);
3599
3600         if (serial_driver) {
3601                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3602                         tty_unregister_device(serial_driver, info->line);
3603                 if ((rc = tty_unregister_driver(serial_driver)))
3604                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3605                 put_tty_driver(serial_driver);
3606         }
3607
3608         /* reset devices */
3609         info = slgt_device_list;
3610         while(info) {
3611                 reset_port(info);
3612                 info = info->next_device;
3613         }
3614
3615         /* release devices */
3616         info = slgt_device_list;
3617         while(info) {
3618 #if SYNCLINK_GENERIC_HDLC
3619                 hdlcdev_exit(info);
3620 #endif
3621                 free_dma_bufs(info);
3622                 free_tmp_rbuf(info);
3623                 if (info->port_num == 0)
3624                         release_resources(info);
3625                 tmp = info;
3626                 info = info->next_device;
3627                 kfree(tmp);
3628         }
3629
3630         if (pci_registered)
3631                 pci_unregister_driver(&pci_driver);
3632 }
3633
3634 /*
3635  *  Driver initialization entry point.
3636  */
3637 static int __init slgt_init(void)
3638 {
3639         int rc;
3640
3641         printk("%s %s\n", driver_name, driver_version);
3642
3643         serial_driver = alloc_tty_driver(MAX_DEVICES);
3644         if (!serial_driver) {
3645                 printk("%s can't allocate tty driver\n", driver_name);
3646                 return -ENOMEM;
3647         }
3648
3649         /* Initialize the tty_driver structure */
3650
3651         serial_driver->owner = THIS_MODULE;
3652         serial_driver->driver_name = tty_driver_name;
3653         serial_driver->name = tty_dev_prefix;
3654         serial_driver->major = ttymajor;
3655         serial_driver->minor_start = 64;
3656         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3657         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3658         serial_driver->init_termios = tty_std_termios;
3659         serial_driver->init_termios.c_cflag =
3660                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3661         serial_driver->init_termios.c_ispeed = 9600;
3662         serial_driver->init_termios.c_ospeed = 9600;
3663         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3664         tty_set_operations(serial_driver, &ops);
3665         if ((rc = tty_register_driver(serial_driver)) < 0) {
3666                 DBGERR(("%s can't register serial driver\n", driver_name));
3667                 put_tty_driver(serial_driver);
3668                 serial_driver = NULL;
3669                 goto error;
3670         }
3671
3672         printk("%s %s, tty major#%d\n",
3673                 driver_name, driver_version,
3674                 serial_driver->major);
3675
3676         slgt_device_count = 0;
3677         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3678                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3679                 goto error;
3680         }
3681         pci_registered = true;
3682
3683         if (!slgt_device_list)
3684                 printk("%s no devices found\n",driver_name);
3685
3686         return 0;
3687
3688 error:
3689         slgt_cleanup();
3690         return rc;
3691 }
3692
3693 static void __exit slgt_exit(void)
3694 {
3695         slgt_cleanup();
3696 }
3697
3698 module_init(slgt_init);
3699 module_exit(slgt_exit);
3700
3701 /*
3702  * register access routines
3703  */
3704
3705 #define CALC_REGADDR() \
3706         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3707         if (addr >= 0x80) \
3708                 reg_addr += (info->port_num) * 32;
3709
3710 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3711 {
3712         CALC_REGADDR();
3713         return readb((void __iomem *)reg_addr);
3714 }
3715
3716 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3717 {
3718         CALC_REGADDR();
3719         writeb(value, (void __iomem *)reg_addr);
3720 }
3721
3722 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3723 {
3724         CALC_REGADDR();
3725         return readw((void __iomem *)reg_addr);
3726 }
3727
3728 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3729 {
3730         CALC_REGADDR();
3731         writew(value, (void __iomem *)reg_addr);
3732 }
3733
3734 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3735 {
3736         CALC_REGADDR();
3737         return readl((void __iomem *)reg_addr);
3738 }
3739
3740 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3741 {
3742         CALC_REGADDR();
3743         writel(value, (void __iomem *)reg_addr);
3744 }
3745
3746 static void rdma_reset(struct slgt_info *info)
3747 {
3748         unsigned int i;
3749
3750         /* set reset bit */
3751         wr_reg32(info, RDCSR, BIT1);
3752
3753         /* wait for enable bit cleared */
3754         for(i=0 ; i < 1000 ; i++)
3755                 if (!(rd_reg32(info, RDCSR) & BIT0))
3756                         break;
3757 }
3758
3759 static void tdma_reset(struct slgt_info *info)
3760 {
3761         unsigned int i;
3762
3763         /* set reset bit */
3764         wr_reg32(info, TDCSR, BIT1);
3765
3766         /* wait for enable bit cleared */
3767         for(i=0 ; i < 1000 ; i++)
3768                 if (!(rd_reg32(info, TDCSR) & BIT0))
3769                         break;
3770 }
3771
3772 /*
3773  * enable internal loopback
3774  * TxCLK and RxCLK are generated from BRG
3775  * and TxD is looped back to RxD internally.
3776  */
3777 static void enable_loopback(struct slgt_info *info)
3778 {
3779         /* SCR (serial control) BIT2=looopback enable */
3780         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3781
3782         if (info->params.mode != MGSL_MODE_ASYNC) {
3783                 /* CCR (clock control)
3784                  * 07..05  tx clock source (010 = BRG)
3785                  * 04..02  rx clock source (010 = BRG)
3786                  * 01      auxclk enable   (0 = disable)
3787                  * 00      BRG enable      (1 = enable)
3788                  *
3789                  * 0100 1001
3790                  */
3791                 wr_reg8(info, CCR, 0x49);
3792
3793                 /* set speed if available, otherwise use default */
3794                 if (info->params.clock_speed)
3795                         set_rate(info, info->params.clock_speed);
3796                 else
3797                         set_rate(info, 3686400);
3798         }
3799 }
3800
3801 /*
3802  *  set baud rate generator to specified rate
3803  */
3804 static void set_rate(struct slgt_info *info, u32 rate)
3805 {
3806         unsigned int div;
3807         static unsigned int osc = 14745600;
3808
3809         /* div = osc/rate - 1
3810          *
3811          * Round div up if osc/rate is not integer to
3812          * force to next slowest rate.
3813          */
3814
3815         if (rate) {
3816                 div = osc/rate;
3817                 if (!(osc % rate) && div)
3818                         div--;
3819                 wr_reg16(info, BDR, (unsigned short)div);
3820         }
3821 }
3822
3823 static void rx_stop(struct slgt_info *info)
3824 {
3825         unsigned short val;
3826
3827         /* disable and reset receiver */
3828         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3829         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3830         wr_reg16(info, RCR, val);                  /* clear reset bit */
3831
3832         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3833
3834         /* clear pending rx interrupts */
3835         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3836
3837         rdma_reset(info);
3838
3839         info->rx_enabled = false;
3840         info->rx_restart = false;
3841 }
3842
3843 static void rx_start(struct slgt_info *info)
3844 {
3845         unsigned short val;
3846
3847         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3848
3849         /* clear pending rx overrun IRQ */
3850         wr_reg16(info, SSR, IRQ_RXOVER);
3851
3852         /* reset and disable receiver */
3853         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3854         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3855         wr_reg16(info, RCR, val);                  /* clear reset bit */
3856
3857         rdma_reset(info);
3858         reset_rbufs(info);
3859
3860         /* set 1st descriptor address */
3861         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3862
3863         if (info->params.mode != MGSL_MODE_ASYNC) {
3864                 /* enable rx DMA and DMA interrupt */
3865                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3866         } else {
3867                 /* enable saving of rx status, rx DMA and DMA interrupt */
3868                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3869         }
3870
3871         slgt_irq_on(info, IRQ_RXOVER);
3872
3873         /* enable receiver */
3874         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3875
3876         info->rx_restart = false;
3877         info->rx_enabled = true;
3878 }
3879
3880 static void tx_start(struct slgt_info *info)
3881 {
3882         if (!info->tx_enabled) {
3883                 wr_reg16(info, TCR,
3884                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3885                 info->tx_enabled = true;
3886         }
3887
3888         if (info->tx_count) {
3889                 info->drop_rts_on_tx_done = false;
3890
3891                 if (info->params.mode != MGSL_MODE_ASYNC) {
3892                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3893                                 get_signals(info);
3894                                 if (!(info->signals & SerialSignal_RTS)) {
3895                                         info->signals |= SerialSignal_RTS;
3896                                         set_signals(info);
3897                                         info->drop_rts_on_tx_done = true;
3898                                 }
3899                         }
3900
3901                         slgt_irq_off(info, IRQ_TXDATA);
3902                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3903                         /* clear tx idle and underrun status bits */
3904                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3905                         if (info->params.mode == MGSL_MODE_HDLC)
3906                                 mod_timer(&info->tx_timer, jiffies +
3907                                                 msecs_to_jiffies(5000));
3908                 } else {
3909                         slgt_irq_off(info, IRQ_TXDATA);
3910                         slgt_irq_on(info, IRQ_TXIDLE);
3911                         /* clear tx idle status bit */
3912                         wr_reg16(info, SSR, IRQ_TXIDLE);
3913                 }
3914                 tdma_start(info);
3915                 info->tx_active = true;
3916         }
3917 }
3918
3919 /*
3920  * start transmit DMA if inactive and there are unsent buffers
3921  */
3922 static void tdma_start(struct slgt_info *info)
3923 {
3924         unsigned int i;
3925
3926         if (rd_reg32(info, TDCSR) & BIT0)
3927                 return;
3928
3929         /* transmit DMA inactive, check for unsent buffers */
3930         i = info->tbuf_start;
3931         while (!desc_count(info->tbufs[i])) {
3932                 if (++i == info->tbuf_count)
3933                         i = 0;
3934                 if (i == info->tbuf_current)
3935                         return;
3936         }
3937         info->tbuf_start = i;
3938
3939         /* there are unsent buffers, start transmit DMA */
3940
3941         /* reset needed if previous error condition */
3942         tdma_reset(info);
3943
3944         /* set 1st descriptor address */
3945         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3946         switch(info->params.mode) {
3947         case MGSL_MODE_RAW:
3948         case MGSL_MODE_MONOSYNC:
3949         case MGSL_MODE_BISYNC:
3950                 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3951                 break;
3952         default:
3953                 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3954         }
3955 }
3956
3957 static void tx_stop(struct slgt_info *info)
3958 {
3959         unsigned short val;
3960
3961         del_timer(&info->tx_timer);
3962
3963         tdma_reset(info);
3964
3965         /* reset and disable transmitter */
3966         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3967         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3968
3969         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3970
3971         /* clear tx idle and underrun status bit */
3972         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3973
3974         reset_tbufs(info);
3975
3976         info->tx_enabled = false;
3977         info->tx_active = false;
3978 }
3979
3980 static void reset_port(struct slgt_info *info)
3981 {
3982         if (!info->reg_addr)
3983                 return;
3984
3985         tx_stop(info);
3986         rx_stop(info);
3987
3988         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3989         set_signals(info);
3990
3991         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3992 }
3993
3994 static void reset_adapter(struct slgt_info *info)
3995 {
3996         int i;
3997         for (i=0; i < info->port_count; ++i) {
3998                 if (info->port_array[i])
3999                         reset_port(info->port_array[i]);
4000         }
4001 }
4002
4003 static void async_mode(struct slgt_info *info)
4004 {
4005         unsigned short val;
4006
4007         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4008         tx_stop(info);
4009         rx_stop(info);
4010
4011         /* TCR (tx control)
4012          *
4013          * 15..13  mode, 010=async
4014          * 12..10  encoding, 000=NRZ
4015          * 09      parity enable
4016          * 08      1=odd parity, 0=even parity
4017          * 07      1=RTS driver control
4018          * 06      1=break enable
4019          * 05..04  character length
4020          *         00=5 bits
4021          *         01=6 bits
4022          *         10=7 bits
4023          *         11=8 bits
4024          * 03      0=1 stop bit, 1=2 stop bits
4025          * 02      reset
4026          * 01      enable
4027          * 00      auto-CTS enable
4028          */
4029         val = 0x4000;
4030
4031         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4032                 val |= BIT7;
4033
4034         if (info->params.parity != ASYNC_PARITY_NONE) {
4035                 val |= BIT9;
4036                 if (info->params.parity == ASYNC_PARITY_ODD)
4037                         val |= BIT8;
4038         }
4039
4040         switch (info->params.data_bits)
4041         {
4042         case 6: val |= BIT4; break;
4043         case 7: val |= BIT5; break;
4044         case 8: val |= BIT5 + BIT4; break;
4045         }
4046
4047         if (info->params.stop_bits != 1)
4048                 val |= BIT3;
4049
4050         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4051                 val |= BIT0;
4052
4053         wr_reg16(info, TCR, val);
4054
4055         /* RCR (rx control)
4056          *
4057          * 15..13  mode, 010=async
4058          * 12..10  encoding, 000=NRZ
4059          * 09      parity enable
4060          * 08      1=odd parity, 0=even parity
4061          * 07..06  reserved, must be 0
4062          * 05..04  character length
4063          *         00=5 bits
4064          *         01=6 bits
4065          *         10=7 bits
4066          *         11=8 bits
4067          * 03      reserved, must be zero
4068          * 02      reset
4069          * 01      enable
4070          * 00      auto-DCD enable
4071          */
4072         val = 0x4000;
4073
4074         if (info->params.parity != ASYNC_PARITY_NONE) {
4075                 val |= BIT9;
4076                 if (info->params.parity == ASYNC_PARITY_ODD)
4077                         val |= BIT8;
4078         }
4079
4080         switch (info->params.data_bits)
4081         {
4082         case 6: val |= BIT4; break;
4083         case 7: val |= BIT5; break;
4084         case 8: val |= BIT5 + BIT4; break;
4085         }
4086
4087         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4088                 val |= BIT0;
4089
4090         wr_reg16(info, RCR, val);
4091
4092         /* CCR (clock control)
4093          *
4094          * 07..05  011 = tx clock source is BRG/16
4095          * 04..02  010 = rx clock source is BRG
4096          * 01      0 = auxclk disabled
4097          * 00      1 = BRG enabled
4098          *
4099          * 0110 1001
4100          */
4101         wr_reg8(info, CCR, 0x69);
4102
4103         msc_set_vcr(info);
4104
4105         /* SCR (serial control)
4106          *
4107          * 15  1=tx req on FIFO half empty
4108          * 14  1=rx req on FIFO half full
4109          * 13  tx data  IRQ enable
4110          * 12  tx idle  IRQ enable
4111          * 11  rx break on IRQ enable
4112          * 10  rx data  IRQ enable
4113          * 09  rx break off IRQ enable
4114          * 08  overrun  IRQ enable
4115          * 07  DSR      IRQ enable
4116          * 06  CTS      IRQ enable
4117          * 05  DCD      IRQ enable
4118          * 04  RI       IRQ enable
4119          * 03  reserved, must be zero
4120          * 02  1=txd->rxd internal loopback enable
4121          * 01  reserved, must be zero
4122          * 00  1=master IRQ enable
4123          */
4124         val = BIT15 + BIT14 + BIT0;
4125         wr_reg16(info, SCR, val);
4126
4127         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4128
4129         set_rate(info, info->params.data_rate * 16);
4130
4131         if (info->params.loopback)
4132                 enable_loopback(info);
4133 }
4134
4135 static void sync_mode(struct slgt_info *info)
4136 {
4137         unsigned short val;
4138
4139         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4140         tx_stop(info);
4141         rx_stop(info);
4142
4143         /* TCR (tx control)
4144          *
4145          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4146          * 12..10  encoding
4147          * 09      CRC enable
4148          * 08      CRC32
4149          * 07      1=RTS driver control
4150          * 06      preamble enable
4151          * 05..04  preamble length
4152          * 03      share open/close flag
4153          * 02      reset
4154          * 01      enable
4155          * 00      auto-CTS enable
4156          */
4157         val = 0;
4158
4159         switch(info->params.mode) {
4160         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4161         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4162         case MGSL_MODE_RAW:      val |= BIT13; break;
4163         }
4164         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4165                 val |= BIT7;
4166
4167         switch(info->params.encoding)
4168         {
4169         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4170         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4171         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4172         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4173         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4174         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4175         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4176         }
4177
4178         switch (info->params.crc_type & HDLC_CRC_MASK)
4179         {
4180         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4181         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4182         }
4183
4184         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4185                 val |= BIT6;
4186
4187         switch (info->params.preamble_length)
4188         {
4189         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4190         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4191         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4192         }
4193
4194         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4195                 val |= BIT0;
4196
4197         wr_reg16(info, TCR, val);
4198
4199         /* TPR (transmit preamble) */
4200
4201         switch (info->params.preamble)
4202         {
4203         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4204         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4205         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4206         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4207         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4208         default:                          val = 0x7e; break;
4209         }
4210         wr_reg8(info, TPR, (unsigned char)val);
4211
4212         /* RCR (rx control)
4213          *
4214          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4215          * 12..10  encoding
4216          * 09      CRC enable
4217          * 08      CRC32
4218          * 07..03  reserved, must be 0
4219          * 02      reset
4220          * 01      enable
4221          * 00      auto-DCD enable
4222          */
4223         val = 0;
4224
4225         switch(info->params.mode) {
4226         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4227         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4228         case MGSL_MODE_RAW:      val |= BIT13; break;
4229         }
4230
4231         switch(info->params.encoding)
4232         {
4233         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4234         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4235         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4236         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4237         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4238         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4239         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4240         }
4241
4242         switch (info->params.crc_type & HDLC_CRC_MASK)
4243         {
4244         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4245         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4246         }
4247
4248         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4249                 val |= BIT0;
4250
4251         wr_reg16(info, RCR, val);
4252
4253         /* CCR (clock control)
4254          *
4255          * 07..05  tx clock source
4256          * 04..02  rx clock source
4257          * 01      auxclk enable
4258          * 00      BRG enable
4259          */
4260         val = 0;
4261
4262         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4263         {
4264                 // when RxC source is DPLL, BRG generates 16X DPLL
4265                 // reference clock, so take TxC from BRG/16 to get
4266                 // transmit clock at actual data rate
4267                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4268                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4269                 else
4270                         val |= BIT6;    /* 010, txclk = BRG */
4271         }
4272         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4273                 val |= BIT7;    /* 100, txclk = DPLL Input */
4274         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4275                 val |= BIT5;    /* 001, txclk = RXC Input */
4276
4277         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4278                 val |= BIT3;    /* 010, rxclk = BRG */
4279         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4280                 val |= BIT4;    /* 100, rxclk = DPLL */
4281         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4282                 val |= BIT2;    /* 001, rxclk = TXC Input */
4283
4284         if (info->params.clock_speed)
4285                 val |= BIT1 + BIT0;
4286
4287         wr_reg8(info, CCR, (unsigned char)val);
4288
4289         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4290         {
4291                 // program DPLL mode
4292                 switch(info->params.encoding)
4293                 {
4294                 case HDLC_ENCODING_BIPHASE_MARK:
4295                 case HDLC_ENCODING_BIPHASE_SPACE:
4296                         val = BIT7; break;
4297                 case HDLC_ENCODING_BIPHASE_LEVEL:
4298                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4299                         val = BIT7 + BIT6; break;
4300                 default: val = BIT6;    // NRZ encodings
4301                 }
4302                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4303
4304                 // DPLL requires a 16X reference clock from BRG
4305                 set_rate(info, info->params.clock_speed * 16);
4306         }
4307         else
4308                 set_rate(info, info->params.clock_speed);
4309
4310         tx_set_idle(info);
4311
4312         msc_set_vcr(info);
4313
4314         /* SCR (serial control)
4315          *
4316          * 15  1=tx req on FIFO half empty
4317          * 14  1=rx req on FIFO half full
4318          * 13  tx data  IRQ enable
4319          * 12  tx idle  IRQ enable
4320          * 11  underrun IRQ enable
4321          * 10  rx data  IRQ enable
4322          * 09  rx idle  IRQ enable
4323          * 08  overrun  IRQ enable
4324          * 07  DSR      IRQ enable
4325          * 06  CTS      IRQ enable
4326          * 05  DCD      IRQ enable
4327          * 04  RI       IRQ enable
4328          * 03  reserved, must be zero
4329          * 02  1=txd->rxd internal loopback enable
4330          * 01  reserved, must be zero
4331          * 00  1=master IRQ enable
4332          */
4333         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4334
4335         if (info->params.loopback)
4336                 enable_loopback(info);
4337 }
4338
4339 /*
4340  *  set transmit idle mode
4341  */
4342 static void tx_set_idle(struct slgt_info *info)
4343 {
4344         unsigned char val;
4345         unsigned short tcr;
4346
4347         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4348          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4349          */
4350         tcr = rd_reg16(info, TCR);
4351         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4352                 /* disable preamble, set idle size to 16 bits */
4353                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4354                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4355                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4356         } else if (!(tcr & BIT6)) {
4357                 /* preamble is disabled, set idle size to 8 bits */
4358                 tcr &= ~(BIT5 + BIT4);
4359         }
4360         wr_reg16(info, TCR, tcr);
4361
4362         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4363                 /* LSB of custom tx idle specified in tx idle register */
4364                 val = (unsigned char)(info->idle_mode & 0xff);
4365         } else {
4366                 /* standard 8 bit idle patterns */
4367                 switch(info->idle_mode)
4368                 {
4369                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4370                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4371                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4372                 case HDLC_TXIDLE_ZEROS:
4373                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4374                 default:                         val = 0xff;
4375                 }
4376         }
4377
4378         wr_reg8(info, TIR, val);
4379 }
4380
4381 /*
4382  * get state of V24 status (input) signals
4383  */
4384 static void get_signals(struct slgt_info *info)
4385 {
4386         unsigned short status = rd_reg16(info, SSR);
4387
4388         /* clear all serial signals except DTR and RTS */
4389         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4390
4391         if (status & BIT3)
4392                 info->signals |= SerialSignal_DSR;
4393         if (status & BIT2)
4394                 info->signals |= SerialSignal_CTS;
4395         if (status & BIT1)
4396                 info->signals |= SerialSignal_DCD;
4397         if (status & BIT0)
4398                 info->signals |= SerialSignal_RI;
4399 }
4400
4401 /*
4402  * set V.24 Control Register based on current configuration
4403  */
4404 static void msc_set_vcr(struct slgt_info *info)
4405 {
4406         unsigned char val = 0;
4407
4408         /* VCR (V.24 control)
4409          *
4410          * 07..04  serial IF select
4411          * 03      DTR
4412          * 02      RTS
4413          * 01      LL
4414          * 00      RL
4415          */
4416
4417         switch(info->if_mode & MGSL_INTERFACE_MASK)
4418         {
4419         case MGSL_INTERFACE_RS232:
4420                 val |= BIT5; /* 0010 */
4421                 break;
4422         case MGSL_INTERFACE_V35:
4423                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4424                 break;
4425         case MGSL_INTERFACE_RS422:
4426                 val |= BIT6; /* 0100 */
4427                 break;
4428         }
4429
4430         if (info->signals & SerialSignal_DTR)
4431                 val |= BIT3;
4432         if (info->signals & SerialSignal_RTS)
4433                 val |= BIT2;
4434         if (info->if_mode & MGSL_INTERFACE_LL)
4435                 val |= BIT1;
4436         if (info->if_mode & MGSL_INTERFACE_RL)
4437                 val |= BIT0;
4438         wr_reg8(info, VCR, val);
4439 }
4440
4441 /*
4442  * set state of V24 control (output) signals
4443  */
4444 static void set_signals(struct slgt_info *info)
4445 {
4446         unsigned char val = rd_reg8(info, VCR);
4447         if (info->signals & SerialSignal_DTR)
4448                 val |= BIT3;
4449         else
4450                 val &= ~BIT3;
4451         if (info->signals & SerialSignal_RTS)
4452                 val |= BIT2;
4453         else
4454                 val &= ~BIT2;
4455         wr_reg8(info, VCR, val);
4456 }
4457
4458 /*
4459  * free range of receive DMA buffers (i to last)
4460  */
4461 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4462 {
4463         int done = 0;
4464
4465         while(!done) {
4466                 /* reset current buffer for reuse */
4467                 info->rbufs[i].status = 0;
4468                 switch(info->params.mode) {
4469                 case MGSL_MODE_RAW:
4470                 case MGSL_MODE_MONOSYNC:
4471                 case MGSL_MODE_BISYNC:
4472                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4473                         break;
4474                 default:
4475                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4476                 }
4477
4478                 if (i == last)
4479                         done = 1;
4480                 if (++i == info->rbuf_count)
4481                         i = 0;
4482         }
4483         info->rbuf_current = i;
4484 }
4485
4486 /*
4487  * mark all receive DMA buffers as free
4488  */
4489 static void reset_rbufs(struct slgt_info *info)
4490 {
4491         free_rbufs(info, 0, info->rbuf_count - 1);
4492 }
4493
4494 /*
4495  * pass receive HDLC frame to upper layer
4496  *
4497  * return true if frame available, otherwise false
4498  */
4499 static bool rx_get_frame(struct slgt_info *info)
4500 {
4501         unsigned int start, end;
4502         unsigned short status;
4503         unsigned int framesize = 0;
4504         unsigned long flags;
4505         struct tty_struct *tty = info->tty;
4506         unsigned char addr_field = 0xff;
4507         unsigned int crc_size = 0;
4508
4509         switch (info->params.crc_type & HDLC_CRC_MASK) {
4510         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4511         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4512         }
4513
4514 check_again:
4515
4516         framesize = 0;
4517         addr_field = 0xff;
4518         start = end = info->rbuf_current;
4519
4520         for (;;) {
4521                 if (!desc_complete(info->rbufs[end]))
4522                         goto cleanup;
4523
4524                 if (framesize == 0 && info->params.addr_filter != 0xff)
4525                         addr_field = info->rbufs[end].buf[0];
4526
4527                 framesize += desc_count(info->rbufs[end]);
4528
4529                 if (desc_eof(info->rbufs[end]))
4530                         break;
4531
4532                 if (++end == info->rbuf_count)
4533                         end = 0;
4534
4535                 if (end == info->rbuf_current) {
4536                         if (info->rx_enabled){
4537                                 spin_lock_irqsave(&info->lock,flags);
4538                                 rx_start(info);
4539                                 spin_unlock_irqrestore(&info->lock,flags);
4540                         }
4541                         goto cleanup;
4542                 }
4543         }
4544
4545         /* status
4546          *
4547          * 15      buffer complete
4548          * 14..06  reserved
4549          * 05..04  residue
4550          * 02      eof (end of frame)
4551          * 01      CRC error
4552          * 00      abort
4553          */
4554         status = desc_status(info->rbufs[end]);
4555
4556         /* ignore CRC bit if not using CRC (bit is undefined) */
4557         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4558                 status &= ~BIT1;
4559
4560         if (framesize == 0 ||
4561                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4562                 free_rbufs(info, start, end);
4563                 goto check_again;
4564         }
4565
4566         if (framesize < (2 + crc_size) || status & BIT0) {
4567                 info->icount.rxshort++;
4568                 framesize = 0;
4569         } else if (status & BIT1) {
4570                 info->icount.rxcrc++;
4571                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4572                         framesize = 0;
4573         }
4574
4575 #if SYNCLINK_GENERIC_HDLC
4576         if (framesize == 0) {
4577                 info->netdev->stats.rx_errors++;
4578                 info->netdev->stats.rx_frame_errors++;
4579         }
4580 #endif
4581
4582         DBGBH(("%s rx frame status=%04X size=%d\n",
4583                 info->device_name, status, framesize));
4584         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4585
4586         if (framesize) {
4587                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4588                         framesize -= crc_size;
4589                         crc_size = 0;
4590                 }
4591
4592                 if (framesize > info->max_frame_size + crc_size)
4593                         info->icount.rxlong++;
4594                 else {
4595                         /* copy dma buffer(s) to contiguous temp buffer */
4596                         int copy_count = framesize;
4597                         int i = start;
4598                         unsigned char *p = info->tmp_rbuf;
4599                         info->tmp_rbuf_count = framesize;
4600
4601                         info->icount.rxok++;
4602
4603                         while(copy_count) {
4604                                 int partial_count = min(copy_count, DMABUFSIZE);
4605                                 memcpy(p, info->rbufs[i].buf, partial_count);
4606                                 p += partial_count;
4607                                 copy_count -= partial_count;
4608                                 if (++i == info->rbuf_count)
4609                                         i = 0;
4610                         }
4611
4612                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4613                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4614                                 framesize++;
4615                         }
4616
4617 #if SYNCLINK_GENERIC_HDLC
4618                         if (info->netcount)
4619                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4620                         else
4621 #endif
4622                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4623                 }
4624         }
4625         free_rbufs(info, start, end);
4626         return true;
4627
4628 cleanup:
4629         return false;
4630 }
4631
4632 /*
4633  * pass receive buffer (RAW synchronous mode) to tty layer
4634  * return true if buffer available, otherwise false
4635  */
4636 static bool rx_get_buf(struct slgt_info *info)
4637 {
4638         unsigned int i = info->rbuf_current;
4639         unsigned int count;
4640
4641         if (!desc_complete(info->rbufs[i]))
4642                 return false;
4643         count = desc_count(info->rbufs[i]);
4644         switch(info->params.mode) {
4645         case MGSL_MODE_MONOSYNC:
4646         case MGSL_MODE_BISYNC:
4647                 /* ignore residue in byte synchronous modes */
4648                 if (desc_residue(info->rbufs[i]))
4649                         count--;
4650                 break;
4651         }
4652         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4653         DBGINFO(("rx_get_buf size=%d\n", count));
4654         if (count)
4655                 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4656                                   info->flag_buf, count);
4657         free_rbufs(info, i, i);
4658         return true;
4659 }
4660
4661 static void reset_tbufs(struct slgt_info *info)
4662 {
4663         unsigned int i;
4664         info->tbuf_current = 0;
4665         for (i=0 ; i < info->tbuf_count ; i++) {
4666                 info->tbufs[i].status = 0;
4667                 info->tbufs[i].count  = 0;
4668         }
4669 }
4670
4671 /*
4672  * return number of free transmit DMA buffers
4673  */
4674 static unsigned int free_tbuf_count(struct slgt_info *info)
4675 {
4676         unsigned int count = 0;
4677         unsigned int i = info->tbuf_current;
4678
4679         do
4680         {
4681                 if (desc_count(info->tbufs[i]))
4682                         break; /* buffer in use */
4683                 ++count;
4684                 if (++i == info->tbuf_count)
4685                         i=0;
4686         } while (i != info->tbuf_current);
4687
4688         /* if tx DMA active, last zero count buffer is in use */
4689         if (count && (rd_reg32(info, TDCSR) & BIT0))
4690                 --count;
4691
4692         return count;
4693 }
4694
4695 /*
4696  * load transmit DMA buffer(s) with data
4697  */
4698 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4699 {
4700         unsigned short count;
4701         unsigned int i;
4702         struct slgt_desc *d;
4703
4704         if (size == 0)
4705                 return;
4706
4707         DBGDATA(info, buf, size, "tx");
4708
4709         info->tbuf_start = i = info->tbuf_current;
4710
4711         while (size) {
4712                 d = &info->tbufs[i];
4713                 if (++i == info->tbuf_count)
4714                         i = 0;
4715
4716                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4717                 memcpy(d->buf, buf, count);
4718
4719                 size -= count;
4720                 buf  += count;
4721
4722                 /*
4723                  * set EOF bit for last buffer of HDLC frame or
4724                  * for every buffer in raw mode
4725                  */
4726                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4727                     info->params.mode == MGSL_MODE_RAW)
4728                         set_desc_eof(*d, 1);
4729                 else
4730                         set_desc_eof(*d, 0);
4731
4732                 set_desc_count(*d, count);
4733         }
4734
4735         info->tbuf_current = i;
4736 }
4737
4738 static int register_test(struct slgt_info *info)
4739 {
4740         static unsigned short patterns[] =
4741                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4742         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4743         unsigned int i;
4744         int rc = 0;
4745
4746         for (i=0 ; i < count ; i++) {
4747                 wr_reg16(info, TIR, patterns[i]);
4748                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4749                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4750                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4751                         rc = -ENODEV;
4752                         break;
4753                 }
4754         }
4755         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4756         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4757         return rc;
4758 }
4759
4760 static int irq_test(struct slgt_info *info)
4761 {
4762         unsigned long timeout;
4763         unsigned long flags;
4764         struct tty_struct *oldtty = info->tty;
4765         u32 speed = info->params.data_rate;
4766
4767         info->params.data_rate = 921600;
4768         info->tty = NULL;
4769
4770         spin_lock_irqsave(&info->lock, flags);
4771         async_mode(info);
4772         slgt_irq_on(info, IRQ_TXIDLE);
4773
4774         /* enable transmitter */
4775         wr_reg16(info, TCR,
4776                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4777
4778         /* write one byte and wait for tx idle */
4779         wr_reg16(info, TDR, 0);
4780
4781         /* assume failure */
4782         info->init_error = DiagStatus_IrqFailure;
4783         info->irq_occurred = false;
4784
4785         spin_unlock_irqrestore(&info->lock, flags);
4786
4787         timeout=100;
4788         while(timeout-- && !info->irq_occurred)
4789                 msleep_interruptible(10);
4790
4791         spin_lock_irqsave(&info->lock,flags);
4792         reset_port(info);
4793         spin_unlock_irqrestore(&info->lock,flags);
4794
4795         info->params.data_rate = speed;
4796         info->tty = oldtty;
4797
4798         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4799         return info->irq_occurred ? 0 : -ENODEV;
4800 }
4801
4802 static int loopback_test_rx(struct slgt_info *info)
4803 {
4804         unsigned char *src, *dest;
4805         int count;
4806
4807         if (desc_complete(info->rbufs[0])) {
4808                 count = desc_count(info->rbufs[0]);
4809                 src   = info->rbufs[0].buf;
4810                 dest  = info->tmp_rbuf;
4811
4812                 for( ; count ; count-=2, src+=2) {
4813                         /* src=data byte (src+1)=status byte */
4814                         if (!(*(src+1) & (BIT9 + BIT8))) {
4815                                 *dest = *src;
4816                                 dest++;
4817                                 info->tmp_rbuf_count++;
4818                         }
4819                 }
4820                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4821                 return 1;
4822         }
4823         return 0;
4824 }
4825
4826 static int loopback_test(struct slgt_info *info)
4827 {
4828 #define TESTFRAMESIZE 20
4829
4830         unsigned long timeout;
4831         u16 count = TESTFRAMESIZE;
4832         unsigned char buf[TESTFRAMESIZE];
4833         int rc = -ENODEV;
4834         unsigned long flags;
4835
4836         struct tty_struct *oldtty = info->tty;
4837         MGSL_PARAMS params;
4838
4839         memcpy(&params, &info->params, sizeof(params));
4840
4841         info->params.mode = MGSL_MODE_ASYNC;
4842         info->params.data_rate = 921600;
4843         info->params.loopback = 1;
4844         info->tty = NULL;
4845
4846         /* build and send transmit frame */
4847         for (count = 0; count < TESTFRAMESIZE; ++count)
4848                 buf[count] = (unsigned char)count;
4849
4850         info->tmp_rbuf_count = 0;
4851         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4852
4853         /* program hardware for HDLC and enabled receiver */
4854         spin_lock_irqsave(&info->lock,flags);
4855         async_mode(info);
4856         rx_start(info);
4857         info->tx_count = count;
4858         tx_load(info, buf, count);
4859         tx_start(info);
4860         spin_unlock_irqrestore(&info->lock, flags);
4861
4862         /* wait for receive complete */
4863         for (timeout = 100; timeout; --timeout) {
4864                 msleep_interruptible(10);
4865                 if (loopback_test_rx(info)) {
4866                         rc = 0;
4867                         break;
4868                 }
4869         }
4870
4871         /* verify received frame length and contents */
4872         if (!rc && (info->tmp_rbuf_count != count ||
4873                   memcmp(buf, info->tmp_rbuf, count))) {
4874                 rc = -ENODEV;
4875         }
4876
4877         spin_lock_irqsave(&info->lock,flags);
4878         reset_adapter(info);
4879         spin_unlock_irqrestore(&info->lock,flags);
4880
4881         memcpy(&info->params, &params, sizeof(info->params));
4882         info->tty = oldtty;
4883
4884         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4885         return rc;
4886 }
4887
4888 static int adapter_test(struct slgt_info *info)
4889 {
4890         DBGINFO(("testing %s\n", info->device_name));
4891         if (register_test(info) < 0) {
4892                 printk("register test failure %s addr=%08X\n",
4893                         info->device_name, info->phys_reg_addr);
4894         } else if (irq_test(info) < 0) {
4895                 printk("IRQ test failure %s IRQ=%d\n",
4896                         info->device_name, info->irq_level);
4897         } else if (loopback_test(info) < 0) {
4898                 printk("loopback test failure %s\n", info->device_name);
4899         }
4900         return info->init_error;
4901 }
4902
4903 /*
4904  * transmit timeout handler
4905  */
4906 static void tx_timeout(unsigned long context)
4907 {
4908         struct slgt_info *info = (struct slgt_info*)context;
4909         unsigned long flags;
4910
4911         DBGINFO(("%s tx_timeout\n", info->device_name));
4912         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4913                 info->icount.txtimeout++;
4914         }
4915         spin_lock_irqsave(&info->lock,flags);
4916         info->tx_active = false;
4917         info->tx_count = 0;
4918         spin_unlock_irqrestore(&info->lock,flags);
4919
4920 #if SYNCLINK_GENERIC_HDLC
4921         if (info->netcount)
4922                 hdlcdev_tx_done(info);
4923         else
4924 #endif
4925                 bh_transmit(info);
4926 }
4927
4928 /*
4929  * receive buffer polling timer
4930  */
4931 static void rx_timeout(unsigned long context)
4932 {
4933         struct slgt_info *info = (struct slgt_info*)context;
4934         unsigned long flags;
4935
4936         DBGINFO(("%s rx_timeout\n", info->device_name));
4937         spin_lock_irqsave(&info->lock, flags);
4938         info->pending_bh |= BH_RECEIVE;
4939         spin_unlock_irqrestore(&info->lock, flags);
4940         bh_handler(&info->task);
4941 }
4942