2 * linux/drivers/char/synclink.c
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
57 # define BREAKPOINT() asm(" int $3");
59 # define BREAKPOINT() { }
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
82 #include <linux/slab.h>
83 #include <linux/delay.h>
84 #include <linux/netdevice.h>
85 #include <linux/vmalloc.h>
86 #include <linux/init.h>
87 #include <linux/ioctl.h>
88 #include <linux/synclink.h>
90 #include <asm/system.h>
94 #include <linux/bitops.h>
95 #include <asm/types.h>
96 #include <linux/termios.h>
97 #include <linux/workqueue.h>
98 #include <linux/hdlc.h>
99 #include <linux/dma-mapping.h>
101 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
102 #define SYNCLINK_GENERIC_HDLC 1
104 #define SYNCLINK_GENERIC_HDLC 0
107 #define GET_USER(error,value,addr) error = get_user(value,addr)
108 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
109 #define PUT_USER(error,value,addr) error = put_user(value,addr)
110 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
112 #include <asm/uaccess.h>
114 #define RCLRVALUE 0xffff
116 static MGSL_PARAMS default_params = {
117 MGSL_MODE_HDLC, /* unsigned long mode */
118 0, /* unsigned char loopback; */
119 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
120 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
121 0, /* unsigned long clock_speed; */
122 0xff, /* unsigned char addr_filter; */
123 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
124 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
125 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
126 9600, /* unsigned long data_rate; */
127 8, /* unsigned char data_bits; */
128 1, /* unsigned char stop_bits; */
129 ASYNC_PARITY_NONE /* unsigned char parity; */
132 #define SHARED_MEM_ADDRESS_SIZE 0x40000
133 #define BUFFERLISTSIZE 4096
134 #define DMABUFFERSIZE 4096
135 #define MAXRXFRAMES 7
137 typedef struct _DMABUFFERENTRY
139 u32 phys_addr; /* 32-bit flat physical address of data buffer */
140 volatile u16 count; /* buffer size/data count */
141 volatile u16 status; /* Control/status field */
142 volatile u16 rcc; /* character count field */
143 u16 reserved; /* padding required by 16C32 */
144 u32 link; /* 32-bit flat link to next buffer entry */
145 char *virt_addr; /* virtual address of data buffer */
146 u32 phys_entry; /* physical address of this buffer entry */
148 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
150 /* The queue of BH actions to be performed */
153 #define BH_TRANSMIT 2
156 #define IO_PIN_SHUTDOWN_LIMIT 100
158 struct _input_signal_events {
169 /* transmit holding buffer definitions*/
170 #define MAX_TX_HOLDING_BUFFERS 5
171 struct tx_holding_buffer {
173 unsigned char * buffer;
178 * Device instance data structure
183 struct tty_port port;
187 struct mgsl_icount icount;
190 int x_char; /* xon/xoff character */
191 u16 read_status_mask;
192 u16 ignore_status_mask;
193 unsigned char *xmit_buf;
198 wait_queue_head_t status_event_wait_q;
199 wait_queue_head_t event_wait_q;
200 struct timer_list tx_timer; /* HDLC transmit timeout timer */
201 struct mgsl_struct *next_device; /* device list link */
203 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
204 struct work_struct task; /* task structure for scheduling bh */
206 u32 EventMask; /* event trigger mask */
207 u32 RecordedEvents; /* pending events */
209 u32 max_frame_size; /* as set by device config */
213 bool bh_running; /* Protection from multiple */
217 int dcd_chkcount; /* check counts to prevent */
218 int cts_chkcount; /* too many IRQs if a signal */
219 int dsr_chkcount; /* is floating */
222 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
223 u32 buffer_list_phys;
224 dma_addr_t buffer_list_dma_addr;
226 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
227 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
228 unsigned int current_rx_buffer;
230 int num_tx_dma_buffers; /* number of tx dma frames required */
231 int tx_dma_buffers_used;
232 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
233 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
234 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
235 int current_tx_buffer; /* next tx dma buffer to be loaded */
237 unsigned char *intermediate_rxbuffer;
239 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
240 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
241 int put_tx_holding_index; /* next tx holding buffer to store user request */
242 int tx_holding_count; /* number of tx holding buffers waiting */
243 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
247 bool rx_rcc_underrun;
256 char device_name[25]; /* device instance name */
258 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
259 unsigned char bus; /* expansion bus number (zero based) */
260 unsigned char function; /* PCI device number */
262 unsigned int io_base; /* base I/O address of adapter */
263 unsigned int io_addr_size; /* size of the I/O address range */
264 bool io_addr_requested; /* true if I/O address requested */
266 unsigned int irq_level; /* interrupt level */
267 unsigned long irq_flags;
268 bool irq_requested; /* true if IRQ requested */
270 unsigned int dma_level; /* DMA channel */
271 bool dma_requested; /* true if dma channel requested */
277 MGSL_PARAMS params; /* communications parameters */
279 unsigned char serial_signals; /* current serial signal states */
281 bool irq_occurred; /* for diagnostics use */
282 unsigned int init_error; /* Initialization startup error (DIAGS) */
283 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
286 unsigned char* memory_base; /* shared memory address (PCI only) */
287 u32 phys_memory_base;
288 bool shared_mem_requested;
290 unsigned char* lcr_base; /* local config registers (PCI only) */
293 bool lcr_mem_requested;
296 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
297 char char_buf[MAX_ASYNC_BUFFER_SIZE];
298 bool drop_rts_on_tx_done;
300 bool loopmode_insert_requested;
301 bool loopmode_send_done_requested;
303 struct _input_signal_events input_signal_events;
305 /* generic HDLC device parts */
309 #if SYNCLINK_GENERIC_HDLC
310 struct net_device *netdev;
314 #define MGSL_MAGIC 0x5401
317 * The size of the serial xmit buffer is 1 page, or 4096 bytes
319 #ifndef SERIAL_XMIT_SIZE
320 #define SERIAL_XMIT_SIZE 4096
324 * These macros define the offsets used in calculating the
325 * I/O address of the specified USC registers.
329 #define DCPIN 2 /* Bit 1 of I/O address */
330 #define SDPIN 4 /* Bit 2 of I/O address */
332 #define DCAR 0 /* DMA command/address register */
333 #define CCAR SDPIN /* channel command/address register */
334 #define DATAREG DCPIN + SDPIN /* serial data register */
339 * These macros define the register address (ordinal number)
340 * used for writing address/value pairs to the USC.
343 #define CMR 0x02 /* Channel mode Register */
344 #define CCSR 0x04 /* Channel Command/status Register */
345 #define CCR 0x06 /* Channel Control Register */
346 #define PSR 0x08 /* Port status Register */
347 #define PCR 0x0a /* Port Control Register */
348 #define TMDR 0x0c /* Test mode Data Register */
349 #define TMCR 0x0e /* Test mode Control Register */
350 #define CMCR 0x10 /* Clock mode Control Register */
351 #define HCR 0x12 /* Hardware Configuration Register */
352 #define IVR 0x14 /* Interrupt Vector Register */
353 #define IOCR 0x16 /* Input/Output Control Register */
354 #define ICR 0x18 /* Interrupt Control Register */
355 #define DCCR 0x1a /* Daisy Chain Control Register */
356 #define MISR 0x1c /* Misc Interrupt status Register */
357 #define SICR 0x1e /* status Interrupt Control Register */
358 #define RDR 0x20 /* Receive Data Register */
359 #define RMR 0x22 /* Receive mode Register */
360 #define RCSR 0x24 /* Receive Command/status Register */
361 #define RICR 0x26 /* Receive Interrupt Control Register */
362 #define RSR 0x28 /* Receive Sync Register */
363 #define RCLR 0x2a /* Receive count Limit Register */
364 #define RCCR 0x2c /* Receive Character count Register */
365 #define TC0R 0x2e /* Time Constant 0 Register */
366 #define TDR 0x30 /* Transmit Data Register */
367 #define TMR 0x32 /* Transmit mode Register */
368 #define TCSR 0x34 /* Transmit Command/status Register */
369 #define TICR 0x36 /* Transmit Interrupt Control Register */
370 #define TSR 0x38 /* Transmit Sync Register */
371 #define TCLR 0x3a /* Transmit count Limit Register */
372 #define TCCR 0x3c /* Transmit Character count Register */
373 #define TC1R 0x3e /* Time Constant 1 Register */
377 * MACRO DEFINITIONS FOR DMA REGISTERS
380 #define DCR 0x06 /* DMA Control Register (shared) */
381 #define DACR 0x08 /* DMA Array count Register (shared) */
382 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
383 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
384 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
385 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
386 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
388 #define TDMR 0x02 /* Transmit DMA mode Register */
389 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
390 #define TBCR 0x2a /* Transmit Byte count Register */
391 #define TARL 0x2c /* Transmit Address Register (low) */
392 #define TARU 0x2e /* Transmit Address Register (high) */
393 #define NTBCR 0x3a /* Next Transmit Byte count Register */
394 #define NTARL 0x3c /* Next Transmit Address Register (low) */
395 #define NTARU 0x3e /* Next Transmit Address Register (high) */
397 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
398 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
399 #define RBCR 0xaa /* Receive Byte count Register */
400 #define RARL 0xac /* Receive Address Register (low) */
401 #define RARU 0xae /* Receive Address Register (high) */
402 #define NRBCR 0xba /* Next Receive Byte count Register */
403 #define NRARL 0xbc /* Next Receive Address Register (low) */
404 #define NRARU 0xbe /* Next Receive Address Register (high) */
408 * MACRO DEFINITIONS FOR MODEM STATUS BITS
411 #define MODEMSTATUS_DTR 0x80
412 #define MODEMSTATUS_DSR 0x40
413 #define MODEMSTATUS_RTS 0x20
414 #define MODEMSTATUS_CTS 0x10
415 #define MODEMSTATUS_RI 0x04
416 #define MODEMSTATUS_DCD 0x01
420 * Channel Command/Address Register (CCAR) Command Codes
423 #define RTCmd_Null 0x0000
424 #define RTCmd_ResetHighestIus 0x1000
425 #define RTCmd_TriggerChannelLoadDma 0x2000
426 #define RTCmd_TriggerRxDma 0x2800
427 #define RTCmd_TriggerTxDma 0x3000
428 #define RTCmd_TriggerRxAndTxDma 0x3800
429 #define RTCmd_PurgeRxFifo 0x4800
430 #define RTCmd_PurgeTxFifo 0x5000
431 #define RTCmd_PurgeRxAndTxFifo 0x5800
432 #define RTCmd_LoadRcc 0x6800
433 #define RTCmd_LoadTcc 0x7000
434 #define RTCmd_LoadRccAndTcc 0x7800
435 #define RTCmd_LoadTC0 0x8800
436 #define RTCmd_LoadTC1 0x9000
437 #define RTCmd_LoadTC0AndTC1 0x9800
438 #define RTCmd_SerialDataLSBFirst 0xa000
439 #define RTCmd_SerialDataMSBFirst 0xa800
440 #define RTCmd_SelectBigEndian 0xb000
441 #define RTCmd_SelectLittleEndian 0xb800
445 * DMA Command/Address Register (DCAR) Command Codes
448 #define DmaCmd_Null 0x0000
449 #define DmaCmd_ResetTxChannel 0x1000
450 #define DmaCmd_ResetRxChannel 0x1200
451 #define DmaCmd_StartTxChannel 0x2000
452 #define DmaCmd_StartRxChannel 0x2200
453 #define DmaCmd_ContinueTxChannel 0x3000
454 #define DmaCmd_ContinueRxChannel 0x3200
455 #define DmaCmd_PauseTxChannel 0x4000
456 #define DmaCmd_PauseRxChannel 0x4200
457 #define DmaCmd_AbortTxChannel 0x5000
458 #define DmaCmd_AbortRxChannel 0x5200
459 #define DmaCmd_InitTxChannel 0x7000
460 #define DmaCmd_InitRxChannel 0x7200
461 #define DmaCmd_ResetHighestDmaIus 0x8000
462 #define DmaCmd_ResetAllChannels 0x9000
463 #define DmaCmd_StartAllChannels 0xa000
464 #define DmaCmd_ContinueAllChannels 0xb000
465 #define DmaCmd_PauseAllChannels 0xc000
466 #define DmaCmd_AbortAllChannels 0xd000
467 #define DmaCmd_InitAllChannels 0xf000
469 #define TCmd_Null 0x0000
470 #define TCmd_ClearTxCRC 0x2000
471 #define TCmd_SelectTicrTtsaData 0x4000
472 #define TCmd_SelectTicrTxFifostatus 0x5000
473 #define TCmd_SelectTicrIntLevel 0x6000
474 #define TCmd_SelectTicrdma_level 0x7000
475 #define TCmd_SendFrame 0x8000
476 #define TCmd_SendAbort 0x9000
477 #define TCmd_EnableDleInsertion 0xc000
478 #define TCmd_DisableDleInsertion 0xd000
479 #define TCmd_ClearEofEom 0xe000
480 #define TCmd_SetEofEom 0xf000
482 #define RCmd_Null 0x0000
483 #define RCmd_ClearRxCRC 0x2000
484 #define RCmd_EnterHuntmode 0x3000
485 #define RCmd_SelectRicrRtsaData 0x4000
486 #define RCmd_SelectRicrRxFifostatus 0x5000
487 #define RCmd_SelectRicrIntLevel 0x6000
488 #define RCmd_SelectRicrdma_level 0x7000
491 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
494 #define RECEIVE_STATUS BIT5
495 #define RECEIVE_DATA BIT4
496 #define TRANSMIT_STATUS BIT3
497 #define TRANSMIT_DATA BIT2
503 * Receive status Bits in Receive Command/status Register RCSR
506 #define RXSTATUS_SHORT_FRAME BIT8
507 #define RXSTATUS_CODE_VIOLATION BIT8
508 #define RXSTATUS_EXITED_HUNT BIT7
509 #define RXSTATUS_IDLE_RECEIVED BIT6
510 #define RXSTATUS_BREAK_RECEIVED BIT5
511 #define RXSTATUS_ABORT_RECEIVED BIT5
512 #define RXSTATUS_RXBOUND BIT4
513 #define RXSTATUS_CRC_ERROR BIT3
514 #define RXSTATUS_FRAMING_ERROR BIT3
515 #define RXSTATUS_ABORT BIT2
516 #define RXSTATUS_PARITY_ERROR BIT2
517 #define RXSTATUS_OVERRUN BIT1
518 #define RXSTATUS_DATA_AVAILABLE BIT0
519 #define RXSTATUS_ALL 0x01f6
520 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
523 * Values for setting transmit idle mode in
524 * Transmit Control/status Register (TCSR)
526 #define IDLEMODE_FLAGS 0x0000
527 #define IDLEMODE_ALT_ONE_ZERO 0x0100
528 #define IDLEMODE_ZERO 0x0200
529 #define IDLEMODE_ONE 0x0300
530 #define IDLEMODE_ALT_MARK_SPACE 0x0500
531 #define IDLEMODE_SPACE 0x0600
532 #define IDLEMODE_MARK 0x0700
533 #define IDLEMODE_MASK 0x0700
536 * IUSC revision identifiers
538 #define IUSC_SL1660 0x4d44
539 #define IUSC_PRE_SL1660 0x4553
542 * Transmit status Bits in Transmit Command/status Register (TCSR)
545 #define TCSR_PRESERVE 0x0F00
547 #define TCSR_UNDERWAIT BIT11
548 #define TXSTATUS_PREAMBLE_SENT BIT7
549 #define TXSTATUS_IDLE_SENT BIT6
550 #define TXSTATUS_ABORT_SENT BIT5
551 #define TXSTATUS_EOF_SENT BIT4
552 #define TXSTATUS_EOM_SENT BIT4
553 #define TXSTATUS_CRC_SENT BIT3
554 #define TXSTATUS_ALL_SENT BIT2
555 #define TXSTATUS_UNDERRUN BIT1
556 #define TXSTATUS_FIFO_EMPTY BIT0
557 #define TXSTATUS_ALL 0x00fa
558 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
561 #define MISCSTATUS_RXC_LATCHED BIT15
562 #define MISCSTATUS_RXC BIT14
563 #define MISCSTATUS_TXC_LATCHED BIT13
564 #define MISCSTATUS_TXC BIT12
565 #define MISCSTATUS_RI_LATCHED BIT11
566 #define MISCSTATUS_RI BIT10
567 #define MISCSTATUS_DSR_LATCHED BIT9
568 #define MISCSTATUS_DSR BIT8
569 #define MISCSTATUS_DCD_LATCHED BIT7
570 #define MISCSTATUS_DCD BIT6
571 #define MISCSTATUS_CTS_LATCHED BIT5
572 #define MISCSTATUS_CTS BIT4
573 #define MISCSTATUS_RCC_UNDERRUN BIT3
574 #define MISCSTATUS_DPLL_NO_SYNC BIT2
575 #define MISCSTATUS_BRG1_ZERO BIT1
576 #define MISCSTATUS_BRG0_ZERO BIT0
578 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
579 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
581 #define SICR_RXC_ACTIVE BIT15
582 #define SICR_RXC_INACTIVE BIT14
583 #define SICR_RXC (BIT15+BIT14)
584 #define SICR_TXC_ACTIVE BIT13
585 #define SICR_TXC_INACTIVE BIT12
586 #define SICR_TXC (BIT13+BIT12)
587 #define SICR_RI_ACTIVE BIT11
588 #define SICR_RI_INACTIVE BIT10
589 #define SICR_RI (BIT11+BIT10)
590 #define SICR_DSR_ACTIVE BIT9
591 #define SICR_DSR_INACTIVE BIT8
592 #define SICR_DSR (BIT9+BIT8)
593 #define SICR_DCD_ACTIVE BIT7
594 #define SICR_DCD_INACTIVE BIT6
595 #define SICR_DCD (BIT7+BIT6)
596 #define SICR_CTS_ACTIVE BIT5
597 #define SICR_CTS_INACTIVE BIT4
598 #define SICR_CTS (BIT5+BIT4)
599 #define SICR_RCC_UNDERFLOW BIT3
600 #define SICR_DPLL_NO_SYNC BIT2
601 #define SICR_BRG1_ZERO BIT1
602 #define SICR_BRG0_ZERO BIT0
604 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
605 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
606 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
607 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
608 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
610 #define usc_EnableInterrupts( a, b ) \
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
613 #define usc_DisableInterrupts( a, b ) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
616 #define usc_EnableMasterIrqBit(a) \
617 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
619 #define usc_DisableMasterIrqBit(a) \
620 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
622 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
625 * Transmit status Bits in Transmit Control status Register (TCSR)
626 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
629 #define TXSTATUS_PREAMBLE_SENT BIT7
630 #define TXSTATUS_IDLE_SENT BIT6
631 #define TXSTATUS_ABORT_SENT BIT5
632 #define TXSTATUS_EOF BIT4
633 #define TXSTATUS_CRC_SENT BIT3
634 #define TXSTATUS_ALL_SENT BIT2
635 #define TXSTATUS_UNDERRUN BIT1
636 #define TXSTATUS_FIFO_EMPTY BIT0
638 #define DICR_MASTER BIT15
639 #define DICR_TRANSMIT BIT0
640 #define DICR_RECEIVE BIT1
642 #define usc_EnableDmaInterrupts(a,b) \
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
645 #define usc_DisableDmaInterrupts(a,b) \
646 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
648 #define usc_EnableStatusIrqs(a,b) \
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
651 #define usc_DisablestatusIrqs(a,b) \
652 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
654 /* Transmit status Bits in Transmit Control status Register (TCSR) */
655 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
658 #define DISABLE_UNCONDITIONAL 0
659 #define DISABLE_END_OF_FRAME 1
660 #define ENABLE_UNCONDITIONAL 2
661 #define ENABLE_AUTO_CTS 3
662 #define ENABLE_AUTO_DCD 3
663 #define usc_EnableTransmitter(a,b) \
664 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
665 #define usc_EnableReceiver(a,b) \
666 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
668 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
669 static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
670 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
672 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
673 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
674 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
675 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
676 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
678 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
679 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
681 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
683 static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
684 static void usc_start_receiver( struct mgsl_struct *info );
685 static void usc_stop_receiver( struct mgsl_struct *info );
687 static void usc_start_transmitter( struct mgsl_struct *info );
688 static void usc_stop_transmitter( struct mgsl_struct *info );
689 static void usc_set_txidle( struct mgsl_struct *info );
690 static void usc_load_txfifo( struct mgsl_struct *info );
692 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
693 static void usc_enable_loopback( struct mgsl_struct *info, int enable );
695 static void usc_get_serial_signals( struct mgsl_struct *info );
696 static void usc_set_serial_signals( struct mgsl_struct *info );
698 static void usc_reset( struct mgsl_struct *info );
700 static void usc_set_sync_mode( struct mgsl_struct *info );
701 static void usc_set_sdlc_mode( struct mgsl_struct *info );
702 static void usc_set_async_mode( struct mgsl_struct *info );
703 static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
705 static void usc_loopback_frame( struct mgsl_struct *info );
707 static void mgsl_tx_timeout(unsigned long context);
710 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
711 static void usc_loopmode_insert_request( struct mgsl_struct * info );
712 static int usc_loopmode_active( struct mgsl_struct * info);
713 static void usc_loopmode_send_done( struct mgsl_struct * info );
715 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
717 #if SYNCLINK_GENERIC_HDLC
718 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
719 static void hdlcdev_tx_done(struct mgsl_struct *info);
720 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
721 static int hdlcdev_init(struct mgsl_struct *info);
722 static void hdlcdev_exit(struct mgsl_struct *info);
726 * Defines a BUS descriptor value for the PCI adapter
727 * local bus address ranges.
730 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
741 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
744 * Adapter diagnostic routines
746 static bool mgsl_register_test( struct mgsl_struct *info );
747 static bool mgsl_irq_test( struct mgsl_struct *info );
748 static bool mgsl_dma_test( struct mgsl_struct *info );
749 static bool mgsl_memory_test( struct mgsl_struct *info );
750 static int mgsl_adapter_test( struct mgsl_struct *info );
753 * device and resource management routines
755 static int mgsl_claim_resources(struct mgsl_struct *info);
756 static void mgsl_release_resources(struct mgsl_struct *info);
757 static void mgsl_add_device(struct mgsl_struct *info);
758 static struct mgsl_struct* mgsl_allocate_device(void);
761 * DMA buffer manupulation functions.
763 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
764 static bool mgsl_get_rx_frame( struct mgsl_struct *info );
765 static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
766 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
767 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
768 static int num_free_tx_dma_buffers(struct mgsl_struct *info);
769 static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
770 static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
773 * DMA and Shared Memory buffer allocation and formatting
775 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
776 static void mgsl_free_dma_buffers(struct mgsl_struct *info);
777 static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
778 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
779 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
780 static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
781 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
782 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
783 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
784 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
785 static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
786 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
789 * Bottom half interrupt handlers
791 static void mgsl_bh_handler(struct work_struct *work);
792 static void mgsl_bh_receive(struct mgsl_struct *info);
793 static void mgsl_bh_transmit(struct mgsl_struct *info);
794 static void mgsl_bh_status(struct mgsl_struct *info);
797 * Interrupt handler routines and dispatch table.
799 static void mgsl_isr_null( struct mgsl_struct *info );
800 static void mgsl_isr_transmit_data( struct mgsl_struct *info );
801 static void mgsl_isr_receive_data( struct mgsl_struct *info );
802 static void mgsl_isr_receive_status( struct mgsl_struct *info );
803 static void mgsl_isr_transmit_status( struct mgsl_struct *info );
804 static void mgsl_isr_io_pin( struct mgsl_struct *info );
805 static void mgsl_isr_misc( struct mgsl_struct *info );
806 static void mgsl_isr_receive_dma( struct mgsl_struct *info );
807 static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
809 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
811 static isr_dispatch_func UscIsrTable[7] =
816 mgsl_isr_transmit_data,
817 mgsl_isr_transmit_status,
818 mgsl_isr_receive_data,
819 mgsl_isr_receive_status
823 * ioctl call handlers
825 static int tiocmget(struct tty_struct *tty, struct file *file);
826 static int tiocmset(struct tty_struct *tty, struct file *file,
827 unsigned int set, unsigned int clear);
828 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
829 __user *user_icount);
830 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
831 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
832 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
833 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
834 static int mgsl_txenable(struct mgsl_struct * info, int enable);
835 static int mgsl_txabort(struct mgsl_struct * info);
836 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
837 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
838 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
840 /* set non-zero on successful registration with PCI subsystem */
841 static bool pci_registered;
844 * Global linked list of SyncLink devices
846 static struct mgsl_struct *mgsl_device_list;
847 static int mgsl_device_count;
850 * Set this param to non-zero to load eax with the
851 * .text section address and breakpoint on module load.
852 * This is useful for use with gdb and add-symbol-file command.
854 static int break_on_load;
857 * Driver major number, defaults to zero to get auto
858 * assigned major number. May be forced as module parameter.
863 * Array of user specified options for ISA adapters.
865 static int io[MAX_ISA_DEVICES];
866 static int irq[MAX_ISA_DEVICES];
867 static int dma[MAX_ISA_DEVICES];
868 static int debug_level;
869 static int maxframe[MAX_TOTAL_DEVICES];
870 static int txdmabufs[MAX_TOTAL_DEVICES];
871 static int txholdbufs[MAX_TOTAL_DEVICES];
873 module_param(break_on_load, bool, 0);
874 module_param(ttymajor, int, 0);
875 module_param_array(io, int, NULL, 0);
876 module_param_array(irq, int, NULL, 0);
877 module_param_array(dma, int, NULL, 0);
878 module_param(debug_level, int, 0);
879 module_param_array(maxframe, int, NULL, 0);
880 module_param_array(txdmabufs, int, NULL, 0);
881 module_param_array(txholdbufs, int, NULL, 0);
883 static char *driver_name = "SyncLink serial driver";
884 static char *driver_version = "$Revision: 4.38 $";
886 static int synclink_init_one (struct pci_dev *dev,
887 const struct pci_device_id *ent);
888 static void synclink_remove_one (struct pci_dev *dev);
890 static struct pci_device_id synclink_pci_tbl[] = {
891 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
892 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
893 { 0, }, /* terminate list */
895 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
897 MODULE_LICENSE("GPL");
899 static struct pci_driver synclink_pci_driver = {
901 .id_table = synclink_pci_tbl,
902 .probe = synclink_init_one,
903 .remove = __devexit_p(synclink_remove_one),
906 static struct tty_driver *serial_driver;
908 /* number of characters left in xmit buffer before we ask for more */
909 #define WAKEUP_CHARS 256
912 static void mgsl_change_params(struct mgsl_struct *info);
913 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
916 * 1st function defined in .text section. Calling this function in
917 * init_module() followed by a breakpoint allows a remote debugger
918 * (gdb) to get the .text address for the add-symbol-file command.
919 * This allows remote debugging of dynamically loadable modules.
921 static void* mgsl_get_text_ptr(void)
923 return mgsl_get_text_ptr;
926 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
927 char *name, const char *routine)
929 #ifdef MGSL_PARANOIA_CHECK
930 static const char *badmagic =
931 "Warning: bad magic number for mgsl struct (%s) in %s\n";
932 static const char *badinfo =
933 "Warning: null mgsl_struct for (%s) in %s\n";
936 printk(badinfo, name, routine);
939 if (info->magic != MGSL_MAGIC) {
940 printk(badmagic, name, routine);
951 * line discipline callback wrappers
953 * The wrappers maintain line discipline references
954 * while calling into the line discipline.
956 * ldisc_receive_buf - pass receive data to line discipline
959 static void ldisc_receive_buf(struct tty_struct *tty,
960 const __u8 *data, char *flags, int count)
962 struct tty_ldisc *ld;
965 ld = tty_ldisc_ref(tty);
967 if (ld->ops->receive_buf)
968 ld->ops->receive_buf(tty, data, flags, count);
973 /* mgsl_stop() throttle (stop) transmitter
975 * Arguments: tty pointer to tty info structure
978 static void mgsl_stop(struct tty_struct *tty)
980 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
983 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
986 if ( debug_level >= DEBUG_LEVEL_INFO )
987 printk("mgsl_stop(%s)\n",info->device_name);
989 spin_lock_irqsave(&info->irq_spinlock,flags);
990 if (info->tx_enabled)
991 usc_stop_transmitter(info);
992 spin_unlock_irqrestore(&info->irq_spinlock,flags);
994 } /* end of mgsl_stop() */
996 /* mgsl_start() release (start) transmitter
998 * Arguments: tty pointer to tty info structure
1001 static void mgsl_start(struct tty_struct *tty)
1003 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1004 unsigned long flags;
1006 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1009 if ( debug_level >= DEBUG_LEVEL_INFO )
1010 printk("mgsl_start(%s)\n",info->device_name);
1012 spin_lock_irqsave(&info->irq_spinlock,flags);
1013 if (!info->tx_enabled)
1014 usc_start_transmitter(info);
1015 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1017 } /* end of mgsl_start() */
1020 * Bottom half work queue access functions
1023 /* mgsl_bh_action() Return next bottom half action to perform.
1024 * Return Value: BH action code or 0 if nothing to do.
1026 static int mgsl_bh_action(struct mgsl_struct *info)
1028 unsigned long flags;
1031 spin_lock_irqsave(&info->irq_spinlock,flags);
1033 if (info->pending_bh & BH_RECEIVE) {
1034 info->pending_bh &= ~BH_RECEIVE;
1036 } else if (info->pending_bh & BH_TRANSMIT) {
1037 info->pending_bh &= ~BH_TRANSMIT;
1039 } else if (info->pending_bh & BH_STATUS) {
1040 info->pending_bh &= ~BH_STATUS;
1045 /* Mark BH routine as complete */
1046 info->bh_running = false;
1047 info->bh_requested = false;
1050 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1056 * Perform bottom half processing of work items queued by ISR.
1058 static void mgsl_bh_handler(struct work_struct *work)
1060 struct mgsl_struct *info =
1061 container_of(work, struct mgsl_struct, task);
1067 if ( debug_level >= DEBUG_LEVEL_BH )
1068 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1069 __FILE__,__LINE__,info->device_name);
1071 info->bh_running = true;
1073 while((action = mgsl_bh_action(info)) != 0) {
1075 /* Process work item */
1076 if ( debug_level >= DEBUG_LEVEL_BH )
1077 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1078 __FILE__,__LINE__,action);
1083 mgsl_bh_receive(info);
1086 mgsl_bh_transmit(info);
1089 mgsl_bh_status(info);
1092 /* unknown work item ID */
1093 printk("Unknown work item ID=%08X!\n", action);
1098 if ( debug_level >= DEBUG_LEVEL_BH )
1099 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1100 __FILE__,__LINE__,info->device_name);
1103 static void mgsl_bh_receive(struct mgsl_struct *info)
1105 bool (*get_rx_frame)(struct mgsl_struct *info) =
1106 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1108 if ( debug_level >= DEBUG_LEVEL_BH )
1109 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1110 __FILE__,__LINE__,info->device_name);
1114 if (info->rx_rcc_underrun) {
1115 unsigned long flags;
1116 spin_lock_irqsave(&info->irq_spinlock,flags);
1117 usc_start_receiver(info);
1118 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1121 } while(get_rx_frame(info));
1124 static void mgsl_bh_transmit(struct mgsl_struct *info)
1126 struct tty_struct *tty = info->port.tty;
1127 unsigned long flags;
1129 if ( debug_level >= DEBUG_LEVEL_BH )
1130 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1131 __FILE__,__LINE__,info->device_name);
1136 /* if transmitter idle and loopmode_send_done_requested
1137 * then start echoing RxD to TxD
1139 spin_lock_irqsave(&info->irq_spinlock,flags);
1140 if ( !info->tx_active && info->loopmode_send_done_requested )
1141 usc_loopmode_send_done( info );
1142 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1145 static void mgsl_bh_status(struct mgsl_struct *info)
1147 if ( debug_level >= DEBUG_LEVEL_BH )
1148 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1149 __FILE__,__LINE__,info->device_name);
1151 info->ri_chkcount = 0;
1152 info->dsr_chkcount = 0;
1153 info->dcd_chkcount = 0;
1154 info->cts_chkcount = 0;
1157 /* mgsl_isr_receive_status()
1159 * Service a receive status interrupt. The type of status
1160 * interrupt is indicated by the state of the RCSR.
1161 * This is only used for HDLC mode.
1163 * Arguments: info pointer to device instance data
1164 * Return Value: None
1166 static void mgsl_isr_receive_status( struct mgsl_struct *info )
1168 u16 status = usc_InReg( info, RCSR );
1170 if ( debug_level >= DEBUG_LEVEL_ISR )
1171 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1172 __FILE__,__LINE__,status);
1174 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1175 info->loopmode_insert_requested &&
1176 usc_loopmode_active(info) )
1178 ++info->icount.rxabort;
1179 info->loopmode_insert_requested = false;
1181 /* clear CMR:13 to start echoing RxD to TxD */
1182 info->cmr_value &= ~BIT13;
1183 usc_OutReg(info, CMR, info->cmr_value);
1185 /* disable received abort irq (no longer required) */
1186 usc_OutReg(info, RICR,
1187 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1190 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1191 if (status & RXSTATUS_EXITED_HUNT)
1192 info->icount.exithunt++;
1193 if (status & RXSTATUS_IDLE_RECEIVED)
1194 info->icount.rxidle++;
1195 wake_up_interruptible(&info->event_wait_q);
1198 if (status & RXSTATUS_OVERRUN){
1199 info->icount.rxover++;
1200 usc_process_rxoverrun_sync( info );
1203 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1204 usc_UnlatchRxstatusBits( info, status );
1206 } /* end of mgsl_isr_receive_status() */
1208 /* mgsl_isr_transmit_status()
1210 * Service a transmit status interrupt
1211 * HDLC mode :end of transmit frame
1212 * Async mode:all data is sent
1213 * transmit status is indicated by bits in the TCSR.
1215 * Arguments: info pointer to device instance data
1216 * Return Value: None
1218 static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1220 u16 status = usc_InReg( info, TCSR );
1222 if ( debug_level >= DEBUG_LEVEL_ISR )
1223 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1224 __FILE__,__LINE__,status);
1226 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1227 usc_UnlatchTxstatusBits( info, status );
1229 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1231 /* finished sending HDLC abort. This may leave */
1232 /* the TxFifo with data from the aborted frame */
1233 /* so purge the TxFifo. Also shutdown the DMA */
1234 /* channel in case there is data remaining in */
1235 /* the DMA buffer */
1236 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1237 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1240 if ( status & TXSTATUS_EOF_SENT )
1241 info->icount.txok++;
1242 else if ( status & TXSTATUS_UNDERRUN )
1243 info->icount.txunder++;
1244 else if ( status & TXSTATUS_ABORT_SENT )
1245 info->icount.txabort++;
1247 info->icount.txunder++;
1249 info->tx_active = false;
1250 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1251 del_timer(&info->tx_timer);
1253 if ( info->drop_rts_on_tx_done ) {
1254 usc_get_serial_signals( info );
1255 if ( info->serial_signals & SerialSignal_RTS ) {
1256 info->serial_signals &= ~SerialSignal_RTS;
1257 usc_set_serial_signals( info );
1259 info->drop_rts_on_tx_done = false;
1262 #if SYNCLINK_GENERIC_HDLC
1264 hdlcdev_tx_done(info);
1268 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1269 usc_stop_transmitter(info);
1272 info->pending_bh |= BH_TRANSMIT;
1275 } /* end of mgsl_isr_transmit_status() */
1277 /* mgsl_isr_io_pin()
1279 * Service an Input/Output pin interrupt. The type of
1280 * interrupt is indicated by bits in the MISR
1282 * Arguments: info pointer to device instance data
1283 * Return Value: None
1285 static void mgsl_isr_io_pin( struct mgsl_struct *info )
1287 struct mgsl_icount *icount;
1288 u16 status = usc_InReg( info, MISR );
1290 if ( debug_level >= DEBUG_LEVEL_ISR )
1291 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1292 __FILE__,__LINE__,status);
1294 usc_ClearIrqPendingBits( info, IO_PIN );
1295 usc_UnlatchIostatusBits( info, status );
1297 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1298 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1299 icount = &info->icount;
1300 /* update input line counters */
1301 if (status & MISCSTATUS_RI_LATCHED) {
1302 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1303 usc_DisablestatusIrqs(info,SICR_RI);
1305 if ( status & MISCSTATUS_RI )
1306 info->input_signal_events.ri_up++;
1308 info->input_signal_events.ri_down++;
1310 if (status & MISCSTATUS_DSR_LATCHED) {
1311 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1312 usc_DisablestatusIrqs(info,SICR_DSR);
1314 if ( status & MISCSTATUS_DSR )
1315 info->input_signal_events.dsr_up++;
1317 info->input_signal_events.dsr_down++;
1319 if (status & MISCSTATUS_DCD_LATCHED) {
1320 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1321 usc_DisablestatusIrqs(info,SICR_DCD);
1323 if (status & MISCSTATUS_DCD) {
1324 info->input_signal_events.dcd_up++;
1326 info->input_signal_events.dcd_down++;
1327 #if SYNCLINK_GENERIC_HDLC
1328 if (info->netcount) {
1329 if (status & MISCSTATUS_DCD)
1330 netif_carrier_on(info->netdev);
1332 netif_carrier_off(info->netdev);
1336 if (status & MISCSTATUS_CTS_LATCHED)
1338 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1339 usc_DisablestatusIrqs(info,SICR_CTS);
1341 if ( status & MISCSTATUS_CTS )
1342 info->input_signal_events.cts_up++;
1344 info->input_signal_events.cts_down++;
1346 wake_up_interruptible(&info->status_event_wait_q);
1347 wake_up_interruptible(&info->event_wait_q);
1349 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1350 (status & MISCSTATUS_DCD_LATCHED) ) {
1351 if ( debug_level >= DEBUG_LEVEL_ISR )
1352 printk("%s CD now %s...", info->device_name,
1353 (status & MISCSTATUS_DCD) ? "on" : "off");
1354 if (status & MISCSTATUS_DCD)
1355 wake_up_interruptible(&info->port.open_wait);
1357 if ( debug_level >= DEBUG_LEVEL_ISR )
1358 printk("doing serial hangup...");
1360 tty_hangup(info->port.tty);
1364 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
1365 (status & MISCSTATUS_CTS_LATCHED) ) {
1366 if (info->port.tty->hw_stopped) {
1367 if (status & MISCSTATUS_CTS) {
1368 if ( debug_level >= DEBUG_LEVEL_ISR )
1369 printk("CTS tx start...");
1371 info->port.tty->hw_stopped = 0;
1372 usc_start_transmitter(info);
1373 info->pending_bh |= BH_TRANSMIT;
1377 if (!(status & MISCSTATUS_CTS)) {
1378 if ( debug_level >= DEBUG_LEVEL_ISR )
1379 printk("CTS tx stop...");
1381 info->port.tty->hw_stopped = 1;
1382 usc_stop_transmitter(info);
1388 info->pending_bh |= BH_STATUS;
1390 /* for diagnostics set IRQ flag */
1391 if ( status & MISCSTATUS_TXC_LATCHED ){
1392 usc_OutReg( info, SICR,
1393 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1394 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1395 info->irq_occurred = true;
1398 } /* end of mgsl_isr_io_pin() */
1400 /* mgsl_isr_transmit_data()
1402 * Service a transmit data interrupt (async mode only).
1404 * Arguments: info pointer to device instance data
1405 * Return Value: None
1407 static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1409 if ( debug_level >= DEBUG_LEVEL_ISR )
1410 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1411 __FILE__,__LINE__,info->xmit_cnt);
1413 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1415 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1416 usc_stop_transmitter(info);
1420 if ( info->xmit_cnt )
1421 usc_load_txfifo( info );
1423 info->tx_active = false;
1425 if (info->xmit_cnt < WAKEUP_CHARS)
1426 info->pending_bh |= BH_TRANSMIT;
1428 } /* end of mgsl_isr_transmit_data() */
1430 /* mgsl_isr_receive_data()
1432 * Service a receive data interrupt. This occurs
1433 * when operating in asynchronous interrupt transfer mode.
1434 * The receive data FIFO is flushed to the receive data buffers.
1436 * Arguments: info pointer to device instance data
1437 * Return Value: None
1439 static void mgsl_isr_receive_data( struct mgsl_struct *info )
1444 unsigned char DataByte;
1445 struct tty_struct *tty = info->port.tty;
1446 struct mgsl_icount *icount = &info->icount;
1448 if ( debug_level >= DEBUG_LEVEL_ISR )
1449 printk("%s(%d):mgsl_isr_receive_data\n",
1452 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1454 /* select FIFO status for RICR readback */
1455 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1457 /* clear the Wordstatus bit so that status readback */
1458 /* only reflects the status of this byte */
1459 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1461 /* flush the receive FIFO */
1463 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1466 /* read one byte from RxFIFO */
1467 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1468 info->io_base + CCAR );
1469 DataByte = inb( info->io_base + CCAR );
1471 /* get the status of the received byte */
1472 status = usc_InReg(info, RCSR);
1473 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1474 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1475 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1480 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1481 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1482 printk("rxerr=%04X\n",status);
1483 /* update error statistics */
1484 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1485 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1487 } else if (status & RXSTATUS_PARITY_ERROR)
1489 else if (status & RXSTATUS_FRAMING_ERROR)
1491 else if (status & RXSTATUS_OVERRUN) {
1492 /* must issue purge fifo cmd before */
1493 /* 16C32 accepts more receive chars */
1494 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1498 /* discard char if tty control flags say so */
1499 if (status & info->ignore_status_mask)
1502 status &= info->read_status_mask;
1504 if (status & RXSTATUS_BREAK_RECEIVED) {
1506 if (info->port.flags & ASYNC_SAK)
1508 } else if (status & RXSTATUS_PARITY_ERROR)
1510 else if (status & RXSTATUS_FRAMING_ERROR)
1512 } /* end of if (error) */
1513 tty_insert_flip_char(tty, DataByte, flag);
1514 if (status & RXSTATUS_OVERRUN) {
1515 /* Overrun is special, since it's
1516 * reported immediately, and doesn't
1517 * affect the current character
1519 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1523 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1524 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1525 __FILE__,__LINE__,icount->rx,icount->brk,
1526 icount->parity,icount->frame,icount->overrun);
1530 tty_flip_buffer_push(tty);
1535 * Service a miscellaneous interrupt source.
1537 * Arguments: info pointer to device extension (instance data)
1538 * Return Value: None
1540 static void mgsl_isr_misc( struct mgsl_struct *info )
1542 u16 status = usc_InReg( info, MISR );
1544 if ( debug_level >= DEBUG_LEVEL_ISR )
1545 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1546 __FILE__,__LINE__,status);
1548 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1549 (info->params.mode == MGSL_MODE_HDLC)) {
1551 /* turn off receiver and rx DMA */
1552 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1553 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1554 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1555 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1556 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1558 /* schedule BH handler to restart receiver */
1559 info->pending_bh |= BH_RECEIVE;
1560 info->rx_rcc_underrun = true;
1563 usc_ClearIrqPendingBits( info, MISC );
1564 usc_UnlatchMiscstatusBits( info, status );
1566 } /* end of mgsl_isr_misc() */
1570 * Services undefined interrupt vectors from the
1571 * USC. (hence this function SHOULD never be called)
1573 * Arguments: info pointer to device extension (instance data)
1574 * Return Value: None
1576 static void mgsl_isr_null( struct mgsl_struct *info )
1579 } /* end of mgsl_isr_null() */
1581 /* mgsl_isr_receive_dma()
1583 * Service a receive DMA channel interrupt.
1584 * For this driver there are two sources of receive DMA interrupts
1585 * as identified in the Receive DMA mode Register (RDMR):
1587 * BIT3 EOA/EOL End of List, all receive buffers in receive
1588 * buffer list have been filled (no more free buffers
1589 * available). The DMA controller has shut down.
1591 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1592 * DMA buffer is terminated in response to completion
1593 * of a good frame or a frame with errors. The status
1594 * of the frame is stored in the buffer entry in the
1595 * list of receive buffer entries.
1597 * Arguments: info pointer to device instance data
1598 * Return Value: None
1600 static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1604 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1605 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1607 /* Read the receive DMA status to identify interrupt type. */
1608 /* This also clears the status bits. */
1609 status = usc_InDmaReg( info, RDMR );
1611 if ( debug_level >= DEBUG_LEVEL_ISR )
1612 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1613 __FILE__,__LINE__,info->device_name,status);
1615 info->pending_bh |= BH_RECEIVE;
1617 if ( status & BIT3 ) {
1618 info->rx_overflow = true;
1619 info->icount.buf_overrun++;
1622 } /* end of mgsl_isr_receive_dma() */
1624 /* mgsl_isr_transmit_dma()
1626 * This function services a transmit DMA channel interrupt.
1628 * For this driver there is one source of transmit DMA interrupts
1629 * as identified in the Transmit DMA Mode Register (TDMR):
1631 * BIT2 EOB End of Buffer. This interrupt occurs when a
1632 * transmit DMA buffer has been emptied.
1634 * The driver maintains enough transmit DMA buffers to hold at least
1635 * one max frame size transmit frame. When operating in a buffered
1636 * transmit mode, there may be enough transmit DMA buffers to hold at
1637 * least two or more max frame size frames. On an EOB condition,
1638 * determine if there are any queued transmit buffers and copy into
1639 * transmit DMA buffers if we have room.
1641 * Arguments: info pointer to device instance data
1642 * Return Value: None
1644 static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1648 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1649 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1651 /* Read the transmit DMA status to identify interrupt type. */
1652 /* This also clears the status bits. */
1654 status = usc_InDmaReg( info, TDMR );
1656 if ( debug_level >= DEBUG_LEVEL_ISR )
1657 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1658 __FILE__,__LINE__,info->device_name,status);
1660 if ( status & BIT2 ) {
1661 --info->tx_dma_buffers_used;
1663 /* if there are transmit frames queued,
1664 * try to load the next one
1666 if ( load_next_tx_holding_buffer(info) ) {
1667 /* if call returns non-zero value, we have
1668 * at least one free tx holding buffer
1670 info->pending_bh |= BH_TRANSMIT;
1674 } /* end of mgsl_isr_transmit_dma() */
1678 * Interrupt service routine entry point.
1682 * irq interrupt number that caused interrupt
1683 * dev_id device ID supplied during interrupt registration
1685 * Return Value: None
1687 static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1689 struct mgsl_struct *info = dev_id;
1693 if ( debug_level >= DEBUG_LEVEL_ISR )
1694 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1695 __FILE__, __LINE__, info->irq_level);
1697 spin_lock(&info->irq_spinlock);
1700 /* Read the interrupt vectors from hardware. */
1701 UscVector = usc_InReg(info, IVR) >> 9;
1702 DmaVector = usc_InDmaReg(info, DIVR);
1704 if ( debug_level >= DEBUG_LEVEL_ISR )
1705 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1706 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1708 if ( !UscVector && !DmaVector )
1711 /* Dispatch interrupt vector */
1713 (*UscIsrTable[UscVector])(info);
1714 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1715 mgsl_isr_transmit_dma(info);
1717 mgsl_isr_receive_dma(info);
1719 if ( info->isr_overflow ) {
1720 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1721 __FILE__, __LINE__, info->device_name, info->irq_level);
1722 usc_DisableMasterIrqBit(info);
1723 usc_DisableDmaInterrupts(info,DICR_MASTER);
1728 /* Request bottom half processing if there's something
1729 * for it to do and the bh is not already running
1732 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1733 if ( debug_level >= DEBUG_LEVEL_ISR )
1734 printk("%s(%d):%s queueing bh task.\n",
1735 __FILE__,__LINE__,info->device_name);
1736 schedule_work(&info->task);
1737 info->bh_requested = true;
1740 spin_unlock(&info->irq_spinlock);
1742 if ( debug_level >= DEBUG_LEVEL_ISR )
1743 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1744 __FILE__, __LINE__, info->irq_level);
1747 } /* end of mgsl_interrupt() */
1751 * Initialize and start device.
1753 * Arguments: info pointer to device instance data
1754 * Return Value: 0 if success, otherwise error code
1756 static int startup(struct mgsl_struct * info)
1760 if ( debug_level >= DEBUG_LEVEL_INFO )
1761 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1763 if (info->port.flags & ASYNC_INITIALIZED)
1766 if (!info->xmit_buf) {
1767 /* allocate a page of memory for a transmit buffer */
1768 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1769 if (!info->xmit_buf) {
1770 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1771 __FILE__,__LINE__,info->device_name);
1776 info->pending_bh = 0;
1778 memset(&info->icount, 0, sizeof(info->icount));
1780 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1782 /* Allocate and claim adapter resources */
1783 retval = mgsl_claim_resources(info);
1785 /* perform existence check and diagnostics */
1787 retval = mgsl_adapter_test(info);
1790 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1791 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1792 mgsl_release_resources(info);
1796 /* program hardware for current parameters */
1797 mgsl_change_params(info);
1800 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1802 info->port.flags |= ASYNC_INITIALIZED;
1806 } /* end of startup() */
1810 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1812 * Arguments: info pointer to device instance data
1813 * Return Value: None
1815 static void shutdown(struct mgsl_struct * info)
1817 unsigned long flags;
1819 if (!(info->port.flags & ASYNC_INITIALIZED))
1822 if (debug_level >= DEBUG_LEVEL_INFO)
1823 printk("%s(%d):mgsl_shutdown(%s)\n",
1824 __FILE__,__LINE__, info->device_name );
1826 /* clear status wait queue because status changes */
1827 /* can't happen after shutting down the hardware */
1828 wake_up_interruptible(&info->status_event_wait_q);
1829 wake_up_interruptible(&info->event_wait_q);
1831 del_timer_sync(&info->tx_timer);
1833 if (info->xmit_buf) {
1834 free_page((unsigned long) info->xmit_buf);
1835 info->xmit_buf = NULL;
1838 spin_lock_irqsave(&info->irq_spinlock,flags);
1839 usc_DisableMasterIrqBit(info);
1840 usc_stop_receiver(info);
1841 usc_stop_transmitter(info);
1842 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1843 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1844 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1846 /* Disable DMAEN (Port 7, Bit 14) */
1847 /* This disconnects the DMA request signal from the ISA bus */
1848 /* on the ISA adapter. This has no effect for the PCI adapter */
1849 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1851 /* Disable INTEN (Port 6, Bit12) */
1852 /* This disconnects the IRQ request signal to the ISA bus */
1853 /* on the ISA adapter. This has no effect for the PCI adapter */
1854 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1856 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1857 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1858 usc_set_serial_signals(info);
1861 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1863 mgsl_release_resources(info);
1866 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1868 info->port.flags &= ~ASYNC_INITIALIZED;
1870 } /* end of shutdown() */
1872 static void mgsl_program_hw(struct mgsl_struct *info)
1874 unsigned long flags;
1876 spin_lock_irqsave(&info->irq_spinlock,flags);
1878 usc_stop_receiver(info);
1879 usc_stop_transmitter(info);
1880 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1882 if (info->params.mode == MGSL_MODE_HDLC ||
1883 info->params.mode == MGSL_MODE_RAW ||
1885 usc_set_sync_mode(info);
1887 usc_set_async_mode(info);
1889 usc_set_serial_signals(info);
1891 info->dcd_chkcount = 0;
1892 info->cts_chkcount = 0;
1893 info->ri_chkcount = 0;
1894 info->dsr_chkcount = 0;
1896 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1897 usc_EnableInterrupts(info, IO_PIN);
1898 usc_get_serial_signals(info);
1900 if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
1901 usc_start_receiver(info);
1903 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1906 /* Reconfigure adapter based on new parameters
1908 static void mgsl_change_params(struct mgsl_struct *info)
1913 if (!info->port.tty || !info->port.tty->termios)
1916 if (debug_level >= DEBUG_LEVEL_INFO)
1917 printk("%s(%d):mgsl_change_params(%s)\n",
1918 __FILE__,__LINE__, info->device_name );
1920 cflag = info->port.tty->termios->c_cflag;
1922 /* if B0 rate (hangup) specified then negate DTR and RTS */
1923 /* otherwise assert DTR and RTS */
1925 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1927 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1929 /* byte size and parity */
1931 switch (cflag & CSIZE) {
1932 case CS5: info->params.data_bits = 5; break;
1933 case CS6: info->params.data_bits = 6; break;
1934 case CS7: info->params.data_bits = 7; break;
1935 case CS8: info->params.data_bits = 8; break;
1936 /* Never happens, but GCC is too dumb to figure it out */
1937 default: info->params.data_bits = 7; break;
1941 info->params.stop_bits = 2;
1943 info->params.stop_bits = 1;
1945 info->params.parity = ASYNC_PARITY_NONE;
1946 if (cflag & PARENB) {
1948 info->params.parity = ASYNC_PARITY_ODD;
1950 info->params.parity = ASYNC_PARITY_EVEN;
1953 info->params.parity = ASYNC_PARITY_SPACE;
1957 /* calculate number of jiffies to transmit a full
1958 * FIFO (32 bytes) at specified data rate
1960 bits_per_char = info->params.data_bits +
1961 info->params.stop_bits + 1;
1963 /* if port data rate is set to 460800 or less then
1964 * allow tty settings to override, otherwise keep the
1965 * current data rate.
1967 if (info->params.data_rate <= 460800)
1968 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1970 if ( info->params.data_rate ) {
1971 info->timeout = (32*HZ*bits_per_char) /
1972 info->params.data_rate;
1974 info->timeout += HZ/50; /* Add .02 seconds of slop */
1976 if (cflag & CRTSCTS)
1977 info->port.flags |= ASYNC_CTS_FLOW;
1979 info->port.flags &= ~ASYNC_CTS_FLOW;
1982 info->port.flags &= ~ASYNC_CHECK_CD;
1984 info->port.flags |= ASYNC_CHECK_CD;
1986 /* process tty input control flags */
1988 info->read_status_mask = RXSTATUS_OVERRUN;
1989 if (I_INPCK(info->port.tty))
1990 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1991 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1992 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1994 if (I_IGNPAR(info->port.tty))
1995 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1996 if (I_IGNBRK(info->port.tty)) {
1997 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1998 /* If ignoring parity and break indicators, ignore
1999 * overruns too. (For real raw support).
2001 if (I_IGNPAR(info->port.tty))
2002 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2005 mgsl_program_hw(info);
2007 } /* end of mgsl_change_params() */
2011 * Add a character to the transmit buffer.
2013 * Arguments: tty pointer to tty information structure
2014 * ch character to add to transmit buffer
2016 * Return Value: None
2018 static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2020 struct mgsl_struct *info = tty->driver_data;
2021 unsigned long flags;
2024 if (debug_level >= DEBUG_LEVEL_INFO) {
2025 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2026 __FILE__, __LINE__, ch, info->device_name);
2029 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2032 if (!tty || !info->xmit_buf)
2035 spin_lock_irqsave(&info->irq_spinlock, flags);
2037 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2038 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2039 info->xmit_buf[info->xmit_head++] = ch;
2040 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2045 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2048 } /* end of mgsl_put_char() */
2050 /* mgsl_flush_chars()
2052 * Enable transmitter so remaining characters in the
2053 * transmit buffer are sent.
2055 * Arguments: tty pointer to tty information structure
2056 * Return Value: None
2058 static void mgsl_flush_chars(struct tty_struct *tty)
2060 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2061 unsigned long flags;
2063 if ( debug_level >= DEBUG_LEVEL_INFO )
2064 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2065 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2067 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2070 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2074 if ( debug_level >= DEBUG_LEVEL_INFO )
2075 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2076 __FILE__,__LINE__,info->device_name );
2078 spin_lock_irqsave(&info->irq_spinlock,flags);
2080 if (!info->tx_active) {
2081 if ( (info->params.mode == MGSL_MODE_HDLC ||
2082 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2083 /* operating in synchronous (frame oriented) mode */
2084 /* copy data from circular xmit_buf to */
2085 /* transmit DMA buffer. */
2086 mgsl_load_tx_dma_buffer(info,
2087 info->xmit_buf,info->xmit_cnt);
2089 usc_start_transmitter(info);
2092 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2094 } /* end of mgsl_flush_chars() */
2098 * Send a block of data
2102 * tty pointer to tty information structure
2103 * buf pointer to buffer containing send data
2104 * count size of send data in bytes
2106 * Return Value: number of characters written
2108 static int mgsl_write(struct tty_struct * tty,
2109 const unsigned char *buf, int count)
2112 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2113 unsigned long flags;
2115 if ( debug_level >= DEBUG_LEVEL_INFO )
2116 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2117 __FILE__,__LINE__,info->device_name,count);
2119 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2122 if (!tty || !info->xmit_buf)
2125 if ( info->params.mode == MGSL_MODE_HDLC ||
2126 info->params.mode == MGSL_MODE_RAW ) {
2127 /* operating in synchronous (frame oriented) mode */
2128 /* operating in synchronous (frame oriented) mode */
2129 if (info->tx_active) {
2131 if ( info->params.mode == MGSL_MODE_HDLC ) {
2135 /* transmitter is actively sending data -
2136 * if we have multiple transmit dma and
2137 * holding buffers, attempt to queue this
2138 * frame for transmission at a later time.
2140 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2141 /* no tx holding buffers available */
2146 /* queue transmit frame request */
2148 save_tx_buffer_request(info,buf,count);
2150 /* if we have sufficient tx dma buffers,
2151 * load the next buffered tx request
2153 spin_lock_irqsave(&info->irq_spinlock,flags);
2154 load_next_tx_holding_buffer(info);
2155 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2159 /* if operating in HDLC LoopMode and the adapter */
2160 /* has yet to be inserted into the loop, we can't */
2163 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2164 !usc_loopmode_active(info) )
2170 if ( info->xmit_cnt ) {
2171 /* Send accumulated from send_char() calls */
2172 /* as frame and wait before accepting more data. */
2175 /* copy data from circular xmit_buf to */
2176 /* transmit DMA buffer. */
2177 mgsl_load_tx_dma_buffer(info,
2178 info->xmit_buf,info->xmit_cnt);
2179 if ( debug_level >= DEBUG_LEVEL_INFO )
2180 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2181 __FILE__,__LINE__,info->device_name);
2183 if ( debug_level >= DEBUG_LEVEL_INFO )
2184 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2185 __FILE__,__LINE__,info->device_name);
2187 info->xmit_cnt = count;
2188 mgsl_load_tx_dma_buffer(info,buf,count);
2192 spin_lock_irqsave(&info->irq_spinlock,flags);
2193 c = min_t(int, count,
2194 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2195 SERIAL_XMIT_SIZE - info->xmit_head));
2197 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2200 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2201 info->xmit_head = ((info->xmit_head + c) &
2202 (SERIAL_XMIT_SIZE-1));
2203 info->xmit_cnt += c;
2204 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2211 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2212 spin_lock_irqsave(&info->irq_spinlock,flags);
2213 if (!info->tx_active)
2214 usc_start_transmitter(info);
2215 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2218 if ( debug_level >= DEBUG_LEVEL_INFO )
2219 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2220 __FILE__,__LINE__,info->device_name,ret);
2224 } /* end of mgsl_write() */
2226 /* mgsl_write_room()
2228 * Return the count of free bytes in transmit buffer
2230 * Arguments: tty pointer to tty info structure
2231 * Return Value: None
2233 static int mgsl_write_room(struct tty_struct *tty)
2235 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2238 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2240 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2244 if (debug_level >= DEBUG_LEVEL_INFO)
2245 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2246 __FILE__,__LINE__, info->device_name,ret );
2248 if ( info->params.mode == MGSL_MODE_HDLC ||
2249 info->params.mode == MGSL_MODE_RAW ) {
2250 /* operating in synchronous (frame oriented) mode */
2251 if ( info->tx_active )
2254 return HDLC_MAX_FRAME_SIZE;
2259 } /* end of mgsl_write_room() */
2261 /* mgsl_chars_in_buffer()
2263 * Return the count of bytes in transmit buffer
2265 * Arguments: tty pointer to tty info structure
2266 * Return Value: None
2268 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2270 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2272 if (debug_level >= DEBUG_LEVEL_INFO)
2273 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2274 __FILE__,__LINE__, info->device_name );
2276 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2279 if (debug_level >= DEBUG_LEVEL_INFO)
2280 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2281 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2283 if ( info->params.mode == MGSL_MODE_HDLC ||
2284 info->params.mode == MGSL_MODE_RAW ) {
2285 /* operating in synchronous (frame oriented) mode */
2286 if ( info->tx_active )
2287 return info->max_frame_size;
2292 return info->xmit_cnt;
2293 } /* end of mgsl_chars_in_buffer() */
2295 /* mgsl_flush_buffer()
2297 * Discard all data in the send buffer
2299 * Arguments: tty pointer to tty info structure
2300 * Return Value: None
2302 static void mgsl_flush_buffer(struct tty_struct *tty)
2304 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2305 unsigned long flags;
2307 if (debug_level >= DEBUG_LEVEL_INFO)
2308 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2309 __FILE__,__LINE__, info->device_name );
2311 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2314 spin_lock_irqsave(&info->irq_spinlock,flags);
2315 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2316 del_timer(&info->tx_timer);
2317 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2322 /* mgsl_send_xchar()
2324 * Send a high-priority XON/XOFF character
2326 * Arguments: tty pointer to tty info structure
2327 * ch character to send
2328 * Return Value: None
2330 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2332 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2333 unsigned long flags;
2335 if (debug_level >= DEBUG_LEVEL_INFO)
2336 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2337 __FILE__,__LINE__, info->device_name, ch );
2339 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2344 /* Make sure transmit interrupts are on */
2345 spin_lock_irqsave(&info->irq_spinlock,flags);
2346 if (!info->tx_enabled)
2347 usc_start_transmitter(info);
2348 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2350 } /* end of mgsl_send_xchar() */
2354 * Signal remote device to throttle send data (our receive data)
2356 * Arguments: tty pointer to tty info structure
2357 * Return Value: None
2359 static void mgsl_throttle(struct tty_struct * tty)
2361 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2362 unsigned long flags;
2364 if (debug_level >= DEBUG_LEVEL_INFO)
2365 printk("%s(%d):mgsl_throttle(%s) entry\n",
2366 __FILE__,__LINE__, info->device_name );
2368 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2372 mgsl_send_xchar(tty, STOP_CHAR(tty));
2374 if (tty->termios->c_cflag & CRTSCTS) {
2375 spin_lock_irqsave(&info->irq_spinlock,flags);
2376 info->serial_signals &= ~SerialSignal_RTS;
2377 usc_set_serial_signals(info);
2378 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2380 } /* end of mgsl_throttle() */
2382 /* mgsl_unthrottle()
2384 * Signal remote device to stop throttling send data (our receive data)
2386 * Arguments: tty pointer to tty info structure
2387 * Return Value: None
2389 static void mgsl_unthrottle(struct tty_struct * tty)
2391 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2392 unsigned long flags;
2394 if (debug_level >= DEBUG_LEVEL_INFO)
2395 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2396 __FILE__,__LINE__, info->device_name );
2398 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2405 mgsl_send_xchar(tty, START_CHAR(tty));
2408 if (tty->termios->c_cflag & CRTSCTS) {
2409 spin_lock_irqsave(&info->irq_spinlock,flags);
2410 info->serial_signals |= SerialSignal_RTS;
2411 usc_set_serial_signals(info);
2412 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2415 } /* end of mgsl_unthrottle() */
2419 * get the current serial parameters information
2421 * Arguments: info pointer to device instance data
2422 * user_icount pointer to buffer to hold returned stats
2424 * Return Value: 0 if success, otherwise error code
2426 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2430 if (debug_level >= DEBUG_LEVEL_INFO)
2431 printk("%s(%d):mgsl_get_params(%s)\n",
2432 __FILE__,__LINE__, info->device_name);
2435 memset(&info->icount, 0, sizeof(info->icount));
2437 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2444 } /* end of mgsl_get_stats() */
2446 /* mgsl_get_params()
2448 * get the current serial parameters information
2450 * Arguments: info pointer to device instance data
2451 * user_params pointer to buffer to hold returned params
2453 * Return Value: 0 if success, otherwise error code
2455 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2458 if (debug_level >= DEBUG_LEVEL_INFO)
2459 printk("%s(%d):mgsl_get_params(%s)\n",
2460 __FILE__,__LINE__, info->device_name);
2462 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2464 if ( debug_level >= DEBUG_LEVEL_INFO )
2465 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2466 __FILE__,__LINE__,info->device_name);
2472 } /* end of mgsl_get_params() */
2474 /* mgsl_set_params()
2476 * set the serial parameters
2480 * info pointer to device instance data
2481 * new_params user buffer containing new serial params
2483 * Return Value: 0 if success, otherwise error code
2485 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2487 unsigned long flags;
2488 MGSL_PARAMS tmp_params;
2491 if (debug_level >= DEBUG_LEVEL_INFO)
2492 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2493 info->device_name );
2494 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2496 if ( debug_level >= DEBUG_LEVEL_INFO )
2497 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2498 __FILE__,__LINE__,info->device_name);
2502 spin_lock_irqsave(&info->irq_spinlock,flags);
2503 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2504 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2506 mgsl_change_params(info);
2510 } /* end of mgsl_set_params() */
2512 /* mgsl_get_txidle()
2514 * get the current transmit idle mode
2516 * Arguments: info pointer to device instance data
2517 * idle_mode pointer to buffer to hold returned idle mode
2519 * Return Value: 0 if success, otherwise error code
2521 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2525 if (debug_level >= DEBUG_LEVEL_INFO)
2526 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2527 __FILE__,__LINE__, info->device_name, info->idle_mode);
2529 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2531 if ( debug_level >= DEBUG_LEVEL_INFO )
2532 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2533 __FILE__,__LINE__,info->device_name);
2539 } /* end of mgsl_get_txidle() */
2541 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2543 * Arguments: info pointer to device instance data
2544 * idle_mode new idle mode
2546 * Return Value: 0 if success, otherwise error code
2548 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2550 unsigned long flags;
2552 if (debug_level >= DEBUG_LEVEL_INFO)
2553 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2554 info->device_name, idle_mode );
2556 spin_lock_irqsave(&info->irq_spinlock,flags);
2557 info->idle_mode = idle_mode;
2558 usc_set_txidle( info );
2559 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2562 } /* end of mgsl_set_txidle() */
2566 * enable or disable the transmitter
2570 * info pointer to device instance data
2571 * enable 1 = enable, 0 = disable
2573 * Return Value: 0 if success, otherwise error code
2575 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2577 unsigned long flags;
2579 if (debug_level >= DEBUG_LEVEL_INFO)
2580 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2581 info->device_name, enable);
2583 spin_lock_irqsave(&info->irq_spinlock,flags);
2585 if ( !info->tx_enabled ) {
2587 usc_start_transmitter(info);
2588 /*--------------------------------------------------
2589 * if HDLC/SDLC Loop mode, attempt to insert the
2590 * station in the 'loop' by setting CMR:13. Upon
2591 * receipt of the next GoAhead (RxAbort) sequence,
2592 * the OnLoop indicator (CCSR:7) should go active
2593 * to indicate that we are on the loop
2594 *--------------------------------------------------*/
2595 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2596 usc_loopmode_insert_request( info );
2599 if ( info->tx_enabled )
2600 usc_stop_transmitter(info);
2602 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2605 } /* end of mgsl_txenable() */
2607 /* mgsl_txabort() abort send HDLC frame
2609 * Arguments: info pointer to device instance data
2610 * Return Value: 0 if success, otherwise error code
2612 static int mgsl_txabort(struct mgsl_struct * info)
2614 unsigned long flags;
2616 if (debug_level >= DEBUG_LEVEL_INFO)
2617 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2620 spin_lock_irqsave(&info->irq_spinlock,flags);
2621 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2623 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2624 usc_loopmode_cancel_transmit( info );
2626 usc_TCmd(info,TCmd_SendAbort);
2628 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2631 } /* end of mgsl_txabort() */
2633 /* mgsl_rxenable() enable or disable the receiver
2635 * Arguments: info pointer to device instance data
2636 * enable 1 = enable, 0 = disable
2637 * Return Value: 0 if success, otherwise error code
2639 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2641 unsigned long flags;
2643 if (debug_level >= DEBUG_LEVEL_INFO)
2644 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2645 info->device_name, enable);
2647 spin_lock_irqsave(&info->irq_spinlock,flags);
2649 if ( !info->rx_enabled )
2650 usc_start_receiver(info);
2652 if ( info->rx_enabled )
2653 usc_stop_receiver(info);
2655 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2658 } /* end of mgsl_rxenable() */
2660 /* mgsl_wait_event() wait for specified event to occur
2662 * Arguments: info pointer to device instance data
2663 * mask pointer to bitmask of events to wait for
2664 * Return Value: 0 if successful and bit mask updated with
2665 * of events triggerred,
2666 * otherwise error code
2668 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2670 unsigned long flags;
2673 struct mgsl_icount cprev, cnow;
2676 struct _input_signal_events oldsigs, newsigs;
2677 DECLARE_WAITQUEUE(wait, current);
2679 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2684 if (debug_level >= DEBUG_LEVEL_INFO)
2685 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2686 info->device_name, mask);
2688 spin_lock_irqsave(&info->irq_spinlock,flags);
2690 /* return immediately if state matches requested events */
2691 usc_get_serial_signals(info);
2692 s = info->serial_signals;
2694 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2695 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2696 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2697 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2699 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2703 /* save current irq counts */
2704 cprev = info->icount;
2705 oldsigs = info->input_signal_events;
2707 /* enable hunt and idle irqs if needed */
2708 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2709 u16 oldreg = usc_InReg(info,RICR);
2710 u16 newreg = oldreg +
2711 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2712 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2713 if (oldreg != newreg)
2714 usc_OutReg(info, RICR, newreg);
2717 set_current_state(TASK_INTERRUPTIBLE);
2718 add_wait_queue(&info->event_wait_q, &wait);
2720 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2725 if (signal_pending(current)) {
2730 /* get current irq counts */
2731 spin_lock_irqsave(&info->irq_spinlock,flags);
2732 cnow = info->icount;
2733 newsigs = info->input_signal_events;
2734 set_current_state(TASK_INTERRUPTIBLE);
2735 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2737 /* if no change, wait aborted for some reason */
2738 if (newsigs.dsr_up == oldsigs.dsr_up &&
2739 newsigs.dsr_down == oldsigs.dsr_down &&
2740 newsigs.dcd_up == oldsigs.dcd_up &&
2741 newsigs.dcd_down == oldsigs.dcd_down &&
2742 newsigs.cts_up == oldsigs.cts_up &&
2743 newsigs.cts_down == oldsigs.cts_down &&
2744 newsigs.ri_up == oldsigs.ri_up &&
2745 newsigs.ri_down == oldsigs.ri_down &&
2746 cnow.exithunt == cprev.exithunt &&
2747 cnow.rxidle == cprev.rxidle) {
2753 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2754 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2755 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2756 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2757 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2758 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2759 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2760 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2761 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2762 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2770 remove_wait_queue(&info->event_wait_q, &wait);
2771 set_current_state(TASK_RUNNING);
2773 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2774 spin_lock_irqsave(&info->irq_spinlock,flags);
2775 if (!waitqueue_active(&info->event_wait_q)) {
2776 /* disable enable exit hunt mode/idle rcvd IRQs */
2777 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2778 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2780 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2784 PUT_USER(rc, events, mask_ptr);
2788 } /* end of mgsl_wait_event() */
2790 static int modem_input_wait(struct mgsl_struct *info,int arg)
2792 unsigned long flags;
2794 struct mgsl_icount cprev, cnow;
2795 DECLARE_WAITQUEUE(wait, current);
2797 /* save current irq counts */
2798 spin_lock_irqsave(&info->irq_spinlock,flags);
2799 cprev = info->icount;
2800 add_wait_queue(&info->status_event_wait_q, &wait);
2801 set_current_state(TASK_INTERRUPTIBLE);
2802 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2806 if (signal_pending(current)) {
2811 /* get new irq counts */
2812 spin_lock_irqsave(&info->irq_spinlock,flags);
2813 cnow = info->icount;
2814 set_current_state(TASK_INTERRUPTIBLE);
2815 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2817 /* if no change, wait aborted for some reason */
2818 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2819 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2824 /* check for change in caller specified modem input */
2825 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2826 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2827 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2828 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2835 remove_wait_queue(&info->status_event_wait_q, &wait);
2836 set_current_state(TASK_RUNNING);
2840 /* return the state of the serial control and status signals
2842 static int tiocmget(struct tty_struct *tty, struct file *file)
2844 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2845 unsigned int result;
2846 unsigned long flags;
2848 spin_lock_irqsave(&info->irq_spinlock,flags);
2849 usc_get_serial_signals(info);
2850 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2852 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2853 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2854 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2855 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2856 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2857 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2859 if (debug_level >= DEBUG_LEVEL_INFO)
2860 printk("%s(%d):%s tiocmget() value=%08X\n",
2861 __FILE__,__LINE__, info->device_name, result );
2865 /* set modem control signals (DTR/RTS)
2867 static int tiocmset(struct tty_struct *tty, struct file *file,
2868 unsigned int set, unsigned int clear)
2870 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2871 unsigned long flags;
2873 if (debug_level >= DEBUG_LEVEL_INFO)
2874 printk("%s(%d):%s tiocmset(%x,%x)\n",
2875 __FILE__,__LINE__,info->device_name, set, clear);
2877 if (set & TIOCM_RTS)
2878 info->serial_signals |= SerialSignal_RTS;
2879 if (set & TIOCM_DTR)
2880 info->serial_signals |= SerialSignal_DTR;
2881 if (clear & TIOCM_RTS)
2882 info->serial_signals &= ~SerialSignal_RTS;
2883 if (clear & TIOCM_DTR)
2884 info->serial_signals &= ~SerialSignal_DTR;
2886 spin_lock_irqsave(&info->irq_spinlock,flags);
2887 usc_set_serial_signals(info);
2888 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2893 /* mgsl_break() Set or clear transmit break condition
2895 * Arguments: tty pointer to tty instance data
2896 * break_state -1=set break condition, 0=clear
2897 * Return Value: None
2899 static void mgsl_break(struct tty_struct *tty, int break_state)
2901 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2902 unsigned long flags;
2904 if (debug_level >= DEBUG_LEVEL_INFO)
2905 printk("%s(%d):mgsl_break(%s,%d)\n",
2906 __FILE__,__LINE__, info->device_name, break_state);
2908 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2911 spin_lock_irqsave(&info->irq_spinlock,flags);
2912 if (break_state == -1)
2913 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2915 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2916 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2918 } /* end of mgsl_break() */
2920 /* mgsl_ioctl() Service an IOCTL request
2924 * tty pointer to tty instance data
2925 * file pointer to associated file object for device
2926 * cmd IOCTL command code
2927 * arg command argument/context
2929 * Return Value: 0 if success, otherwise error code
2931 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2932 unsigned int cmd, unsigned long arg)
2934 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2937 if (debug_level >= DEBUG_LEVEL_INFO)
2938 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2939 info->device_name, cmd );
2941 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2944 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2945 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2946 if (tty->flags & (1 << TTY_IO_ERROR))
2951 ret = mgsl_ioctl_common(info, cmd, arg);
2956 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2959 struct mgsl_icount cnow; /* kernel counter temps */
2960 void __user *argp = (void __user *)arg;
2961 struct serial_icounter_struct __user *p_cuser; /* user space */
2962 unsigned long flags;
2965 case MGSL_IOCGPARAMS:
2966 return mgsl_get_params(info, argp);
2967 case MGSL_IOCSPARAMS:
2968 return mgsl_set_params(info, argp);
2969 case MGSL_IOCGTXIDLE:
2970 return mgsl_get_txidle(info, argp);
2971 case MGSL_IOCSTXIDLE:
2972 return mgsl_set_txidle(info,(int)arg);
2973 case MGSL_IOCTXENABLE:
2974 return mgsl_txenable(info,(int)arg);
2975 case MGSL_IOCRXENABLE:
2976 return mgsl_rxenable(info,(int)arg);
2977 case MGSL_IOCTXABORT:
2978 return mgsl_txabort(info);
2979 case MGSL_IOCGSTATS:
2980 return mgsl_get_stats(info, argp);
2981 case MGSL_IOCWAITEVENT:
2982 return mgsl_wait_event(info, argp);
2983 case MGSL_IOCLOOPTXDONE:
2984 return mgsl_loopmode_send_done(info);
2985 /* Wait for modem input (DCD,RI,DSR,CTS) change
2986 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2989 return modem_input_wait(info,(int)arg);
2992 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2993 * Return: write counters to the user passed counter struct
2994 * NB: both 1->0 and 0->1 transitions are counted except for
2995 * RI where only 0->1 is counted.
2998 spin_lock_irqsave(&info->irq_spinlock,flags);
2999 cnow = info->icount;
3000 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3002 PUT_USER(error,cnow.cts, &p_cuser->cts);
3003 if (error) return error;
3004 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3005 if (error) return error;
3006 PUT_USER(error,cnow.rng, &p_cuser->rng);
3007 if (error) return error;
3008 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3009 if (error) return error;
3010 PUT_USER(error,cnow.rx, &p_cuser->rx);
3011 if (error) return error;
3012 PUT_USER(error,cnow.tx, &p_cuser->tx);
3013 if (error) return error;
3014 PUT_USER(error,cnow.frame, &p_cuser->frame);
3015 if (error) return error;
3016 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3017 if (error) return error;
3018 PUT_USER(error,cnow.parity, &p_cuser->parity);
3019 if (error) return error;
3020 PUT_USER(error,cnow.brk, &p_cuser->brk);
3021 if (error) return error;
3022 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3023 if (error) return error;
3026 return -ENOIOCTLCMD;
3031 /* mgsl_set_termios()
3033 * Set new termios settings
3037 * tty pointer to tty structure
3038 * termios pointer to buffer to hold returned old termios
3040 * Return Value: None
3042 static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3044 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3045 unsigned long flags;
3047 if (debug_level >= DEBUG_LEVEL_INFO)
3048 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3049 tty->driver->name );
3051 mgsl_change_params(info);
3053 /* Handle transition to B0 status */
3054 if (old_termios->c_cflag & CBAUD &&
3055 !(tty->termios->c_cflag & CBAUD)) {
3056 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3057 spin_lock_irqsave(&info->irq_spinlock,flags);
3058 usc_set_serial_signals(info);
3059 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3062 /* Handle transition away from B0 status */
3063 if (!(old_termios->c_cflag & CBAUD) &&
3064 tty->termios->c_cflag & CBAUD) {
3065 info->serial_signals |= SerialSignal_DTR;
3066 if (!(tty->termios->c_cflag & CRTSCTS) ||
3067 !test_bit(TTY_THROTTLED, &tty->flags)) {
3068 info->serial_signals |= SerialSignal_RTS;
3070 spin_lock_irqsave(&info->irq_spinlock,flags);
3071 usc_set_serial_signals(info);
3072 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3075 /* Handle turning off CRTSCTS */
3076 if (old_termios->c_cflag & CRTSCTS &&
3077 !(tty->termios->c_cflag & CRTSCTS)) {
3078 tty->hw_stopped = 0;
3082 } /* end of mgsl_set_termios() */
3086 * Called when port is closed. Wait for remaining data to be
3087 * sent. Disable port and free resources.
3091 * tty pointer to open tty structure
3092 * filp pointer to open file object
3094 * Return Value: None
3096 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3098 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3100 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3103 if (debug_level >= DEBUG_LEVEL_INFO)
3104 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3105 __FILE__,__LINE__, info->device_name, info->port.count);
3107 if (!info->port.count)
3110 if (tty_hung_up_p(filp))
3113 if ((tty->count == 1) && (info->port.count != 1)) {
3115 * tty->count is 1 and the tty structure will be freed.
3116 * info->port.count should be one in this case.
3117 * if it's not, correct it so that the port is shutdown.
3119 printk("mgsl_close: bad refcount; tty->count is 1, "
3120 "info->port.count is %d\n", info->port.count);
3121 info->port.count = 1;
3126 /* if at least one open remaining, leave hardware active */
3127 if (info->port.count)
3130 info->port.flags |= ASYNC_CLOSING;
3132 /* set tty->closing to notify line discipline to
3133 * only process XON/XOFF characters. Only the N_TTY
3134 * discipline appears to use this (ppp does not).
3138 /* wait for transmit data to clear all layers */
3140 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3141 if (debug_level >= DEBUG_LEVEL_INFO)
3142 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3143 __FILE__,__LINE__, info->device_name );
3144 tty_wait_until_sent(tty, info->port.closing_wait);
3147 if (info->port.flags & ASYNC_INITIALIZED)
3148 mgsl_wait_until_sent(tty, info->timeout);
3150 mgsl_flush_buffer(tty);
3152 tty_ldisc_flush(tty);
3157 info->port.tty = NULL;
3159 if (info->port.blocked_open) {
3160 if (info->port.close_delay) {
3161 msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
3163 wake_up_interruptible(&info->port.open_wait);
3166 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3168 wake_up_interruptible(&info->port.close_wait);
3171 if (debug_level >= DEBUG_LEVEL_INFO)
3172 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3173 tty->driver->name, info->port.count);
3175 } /* end of mgsl_close() */
3177 /* mgsl_wait_until_sent()
3179 * Wait until the transmitter is empty.
3183 * tty pointer to tty info structure
3184 * timeout time to wait for send completion
3186 * Return Value: None
3188 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3190 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3191 unsigned long orig_jiffies, char_time;
3196 if (debug_level >= DEBUG_LEVEL_INFO)
3197 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3198 __FILE__,__LINE__, info->device_name );
3200 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3203 if (!(info->port.flags & ASYNC_INITIALIZED))
3206 orig_jiffies = jiffies;
3208 /* Set check interval to 1/5 of estimated time to
3209 * send a character, and make it at least 1. The check
3210 * interval should also be less than the timeout.
3211 * Note: use tight timings here to satisfy the NIST-PCTS.
3215 if ( info->params.data_rate ) {
3216 char_time = info->timeout/(32 * 5);
3223 char_time = min_t(unsigned long, char_time, timeout);
3225 if ( info->params.mode == MGSL_MODE_HDLC ||
3226 info->params.mode == MGSL_MODE_RAW ) {
3227 while (info->tx_active) {
3228 msleep_interruptible(jiffies_to_msecs(char_time));
3229 if (signal_pending(current))
3231 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3235 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3237 msleep_interruptible(jiffies_to_msecs(char_time));
3238 if (signal_pending(current))
3240 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3247 if (debug_level >= DEBUG_LEVEL_INFO)
3248 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3249 __FILE__,__LINE__, info->device_name );
3251 } /* end of mgsl_wait_until_sent() */
3255 * Called by tty_hangup() when a hangup is signaled.
3256 * This is the same as to closing all open files for the port.
3258 * Arguments: tty pointer to associated tty object
3259 * Return Value: None
3261 static void mgsl_hangup(struct tty_struct *tty)
3263 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3265 if (debug_level >= DEBUG_LEVEL_INFO)
3266 printk("%s(%d):mgsl_hangup(%s)\n",
3267 __FILE__,__LINE__, info->device_name );
3269 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3272 mgsl_flush_buffer(tty);
3275 info->port.count = 0;
3276 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3277 info->port.tty = NULL;
3279 wake_up_interruptible(&info->port.open_wait);
3281 } /* end of mgsl_hangup() */
3283 /* block_til_ready()
3285 * Block the current process until the specified port
3286 * is ready to be opened.
3290 * tty pointer to tty info structure
3291 * filp pointer to open file object
3292 * info pointer to device instance data
3294 * Return Value: 0 if success, otherwise error code
3296 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3297 struct mgsl_struct *info)
3299 DECLARE_WAITQUEUE(wait, current);
3301 bool do_clocal = false;
3302 bool extra_count = false;
3303 unsigned long flags;
3305 if (debug_level >= DEBUG_LEVEL_INFO)
3306 printk("%s(%d):block_til_ready on %s\n",
3307 __FILE__,__LINE__, tty->driver->name );
3309 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3310 /* nonblock mode is set or port is not enabled */
3311 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3315 if (tty->termios->c_cflag & CLOCAL)
3318 /* Wait for carrier detect and the line to become
3319 * free (i.e., not in use by the callout). While we are in
3320 * this loop, info->port.count is dropped by one, so that
3321 * mgsl_close() knows when to free things. We restore it upon
3322 * exit, either normal or abnormal.
3326 add_wait_queue(&info->port.open_wait, &wait);
3328 if (debug_level >= DEBUG_LEVEL_INFO)
3329 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3330 __FILE__,__LINE__, tty->driver->name, info->port.count );
3332 spin_lock_irqsave(&info->irq_spinlock, flags);
3333 if (!tty_hung_up_p(filp)) {
3337 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3338 info->port.blocked_open++;
3341 if (tty->termios->c_cflag & CBAUD) {
3342 spin_lock_irqsave(&info->irq_spinlock,flags);
3343 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3344 usc_set_serial_signals(info);
3345 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3348 set_current_state(TASK_INTERRUPTIBLE);
3350 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3351 retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3352 -EAGAIN : -ERESTARTSYS;
3356 spin_lock_irqsave(&info->irq_spinlock,flags);
3357 usc_get_serial_signals(info);
3358 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3360 if (!(info->port.flags & ASYNC_CLOSING) &&
3361 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3365 if (signal_pending(current)) {
3366 retval = -ERESTARTSYS;
3370 if (debug_level >= DEBUG_LEVEL_INFO)
3371 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3372 __FILE__,__LINE__, tty->driver->name, info->port.count );
3377 set_current_state(TASK_RUNNING);
3378 remove_wait_queue(&info->port.open_wait, &wait);
3382 info->port.blocked_open--;
3384 if (debug_level >= DEBUG_LEVEL_INFO)
3385 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3386 __FILE__,__LINE__, tty->driver->name, info->port.count );
3389 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3393 } /* end of block_til_ready() */
3397 * Called when a port is opened. Init and enable port.
3398 * Perform serial-specific initialization for the tty structure.
3400 * Arguments: tty pointer to tty info structure
3401 * filp associated file pointer
3403 * Return Value: 0 if success, otherwise error code
3405 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3407 struct mgsl_struct *info;
3409 unsigned long flags;
3411 /* verify range of specified line number */
3413 if ((line < 0) || (line >= mgsl_device_count)) {
3414 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3415 __FILE__,__LINE__,line);
3419 /* find the info structure for the specified line */
3420 info = mgsl_device_list;
3421 while(info && info->line != line)
3422 info = info->next_device;
3423 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3426 tty->driver_data = info;
3427 info->port.tty = tty;
3429 if (debug_level >= DEBUG_LEVEL_INFO)
3430 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3431 __FILE__,__LINE__,tty->driver->name, info->port.count);
3433 /* If port is closing, signal caller to try again */
3434 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3435 if (info->port.flags & ASYNC_CLOSING)
3436 interruptible_sleep_on(&info->port.close_wait);
3437 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3438 -EAGAIN : -ERESTARTSYS);
3442 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3444 spin_lock_irqsave(&info->netlock, flags);
3445 if (info->netcount) {
3447 spin_unlock_irqrestore(&info->netlock, flags);
3451 spin_unlock_irqrestore(&info->netlock, flags);
3453 if (info->port.count == 1) {
3454 /* 1st open on this device, init hardware */
3455 retval = startup(info);
3460 retval = block_til_ready(tty, filp, info);
3462 if (debug_level >= DEBUG_LEVEL_INFO)
3463 printk("%s(%d):block_til_ready(%s) returned %d\n",
3464 __FILE__,__LINE__, info->device_name, retval);
3468 if (debug_level >= DEBUG_LEVEL_INFO)
3469 printk("%s(%d):mgsl_open(%s) success\n",
3470 __FILE__,__LINE__, info->device_name);
3475 if (tty->count == 1)
3476 info->port.tty = NULL; /* tty layer will release tty struct */
3477 if(info->port.count)
3483 } /* end of mgsl_open() */
3486 * /proc fs routines....
3489 static inline int line_info(char *buf, struct mgsl_struct *info)
3493 unsigned long flags;
3495 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3496 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3497 info->device_name, info->io_base, info->irq_level,
3498 info->phys_memory_base, info->phys_lcr_base);
3500 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3501 info->device_name, info->io_base,
3502 info->irq_level, info->dma_level);
3505 /* output current serial signal states */
3506 spin_lock_irqsave(&info->irq_spinlock,flags);
3507 usc_get_serial_signals(info);
3508 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3512 if (info->serial_signals & SerialSignal_RTS)
3513 strcat(stat_buf, "|RTS");
3514 if (info->serial_signals & SerialSignal_CTS)
3515 strcat(stat_buf, "|CTS");
3516 if (info->serial_signals & SerialSignal_DTR)
3517 strcat(stat_buf, "|DTR");
3518 if (info->serial_signals & SerialSignal_DSR)
3519 strcat(stat_buf, "|DSR");
3520 if (info->serial_signals & SerialSignal_DCD)
3521 strcat(stat_buf, "|CD");
3522 if (info->serial_signals & SerialSignal_RI)
3523 strcat(stat_buf, "|RI");
3525 if (info->params.mode == MGSL_MODE_HDLC ||
3526 info->params.mode == MGSL_MODE_RAW ) {
3527 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3528 info->icount.txok, info->icount.rxok);
3529 if (info->icount.txunder)
3530 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3531 if (info->icount.txabort)
3532 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3533 if (info->icount.rxshort)
3534 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3535 if (info->icount.rxlong)
3536 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3537 if (info->icount.rxover)
3538 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3539 if (info->icount.rxcrc)
3540 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
3542 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3543 info->icount.tx, info->icount.rx);
3544 if (info->icount.frame)
3545 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3546 if (info->icount.parity)
3547 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3548 if (info->icount.brk)
3549 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3550 if (info->icount.overrun)
3551 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3554 /* Append serial signal status to end */
3555 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3557 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3558 info->tx_active,info->bh_requested,info->bh_running,
3561 spin_lock_irqsave(&info->irq_spinlock,flags);
3563 u16 Tcsr = usc_InReg( info, TCSR );
3564 u16 Tdmr = usc_InDmaReg( info, TDMR );
3565 u16 Ticr = usc_InReg( info, TICR );
3566 u16 Rscr = usc_InReg( info, RCSR );
3567 u16 Rdmr = usc_InDmaReg( info, RDMR );
3568 u16 Ricr = usc_InReg( info, RICR );
3569 u16 Icr = usc_InReg( info, ICR );
3570 u16 Dccr = usc_InReg( info, DCCR );
3571 u16 Tmr = usc_InReg( info, TMR );
3572 u16 Tccr = usc_InReg( info, TCCR );
3573 u16 Ccar = inw( info->io_base + CCAR );
3574 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3575 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3576 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3578 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3582 } /* end of line_info() */
3586 * Called to print information about devices
3589 * page page of memory to hold returned info
3598 static int mgsl_read_proc(char *page, char **start, off_t off, int count,
3599 int *eof, void *data)
3603 struct mgsl_struct *info;
3605 len += sprintf(page, "synclink driver:%s\n", driver_version);
3607 info = mgsl_device_list;
3609 l = line_info(page + len, info);
3611 if (len+begin > off+count)
3613 if (len+begin < off) {
3617 info = info->next_device;
3622 if (off >= len+begin)
3624 *start = page + (off-begin);
3625 return ((count < begin+len-off) ? count : begin+len-off);
3627 } /* end of mgsl_read_proc() */
3629 /* mgsl_allocate_dma_buffers()
3631 * Allocate and format DMA buffers (ISA adapter)
3632 * or format shared memory buffers (PCI adapter).
3634 * Arguments: info pointer to device instance data
3635 * Return Value: 0 if success, otherwise error
3637 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3639 unsigned short BuffersPerFrame;
3641 info->last_mem_alloc = 0;
3643 /* Calculate the number of DMA buffers necessary to hold the */
3644 /* largest allowable frame size. Note: If the max frame size is */
3645 /* not an even multiple of the DMA buffer size then we need to */
3646 /* round the buffer count per frame up one. */
3648 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3649 if ( info->max_frame_size % DMABUFFERSIZE )
3652 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3654 * The PCI adapter has 256KBytes of shared memory to use.
3655 * This is 64 PAGE_SIZE buffers.
3657 * The first page is used for padding at this time so the
3658 * buffer list does not begin at offset 0 of the PCI
3659 * adapter's shared memory.
3661 * The 2nd page is used for the buffer list. A 4K buffer
3662 * list can hold 128 DMA_BUFFER structures at 32 bytes
3665 * This leaves 62 4K pages.
3667 * The next N pages are used for transmit frame(s). We
3668 * reserve enough 4K page blocks to hold the required
3669 * number of transmit dma buffers (num_tx_dma_buffers),
3670 * each of MaxFrameSize size.
3672 * Of the remaining pages (62-N), determine how many can
3673 * be used to receive full MaxFrameSize inbound frames
3675 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3676 info->rx_buffer_count = 62 - info->tx_buffer_count;
3678 /* Calculate the number of PAGE_SIZE buffers needed for */
3679 /* receive and transmit DMA buffers. */
3682 /* Calculate the number of DMA buffers necessary to */
3683 /* hold 7 max size receive frames and one max size transmit frame. */
3684 /* The receive buffer count is bumped by one so we avoid an */
3685 /* End of List condition if all receive buffers are used when */
3686 /* using linked list DMA buffers. */
3688 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3689 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3692 * limit total TxBuffers & RxBuffers to 62 4K total
3693 * (ala PCI Allocation)
3696 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3697 info->rx_buffer_count = 62 - info->tx_buffer_count;
3701 if ( debug_level >= DEBUG_LEVEL_INFO )
3702 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3703 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3705 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3706 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3707 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3708 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3709 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3710 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3714 mgsl_reset_rx_dma_buffers( info );
3715 mgsl_reset_tx_dma_buffers( info );
3719 } /* end of mgsl_allocate_dma_buffers() */
3722 * mgsl_alloc_buffer_list_memory()
3724 * Allocate a common DMA buffer for use as the
3725 * receive and transmit buffer lists.
3727 * A buffer list is a set of buffer entries where each entry contains
3728 * a pointer to an actual buffer and a pointer to the next buffer entry
3729 * (plus some other info about the buffer).
3731 * The buffer entries for a list are built to form a circular list so
3732 * that when the entire list has been traversed you start back at the
3735 * This function allocates memory for just the buffer entries.
3736 * The links (pointer to next entry) are filled in with the physical
3737 * address of the next entry so the adapter can navigate the list
3738 * using bus master DMA. The pointers to the actual buffers are filled
3739 * out later when the actual buffers are allocated.
3741 * Arguments: info pointer to device instance data
3742 * Return Value: 0 if success, otherwise error
3744 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3748 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3749 /* PCI adapter uses shared memory. */
3750 info->buffer_list = info->memory_base + info->last_mem_alloc;
3751 info->buffer_list_phys = info->last_mem_alloc;
3752 info->last_mem_alloc += BUFFERLISTSIZE;
3754 /* ISA adapter uses system memory. */
3755 /* The buffer lists are allocated as a common buffer that both */
3756 /* the processor and adapter can access. This allows the driver to */
3757 /* inspect portions of the buffer while other portions are being */
3758 /* updated by the adapter using Bus Master DMA. */
3760 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3761 if (info->buffer_list == NULL)
3763 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3766 /* We got the memory for the buffer entry lists. */
3767 /* Initialize the memory block to all zeros. */
3768 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3770 /* Save virtual address pointers to the receive and */
3771 /* transmit buffer lists. (Receive 1st). These pointers will */
3772 /* be used by the processor to access the lists. */
3773 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3774 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3775 info->tx_buffer_list += info->rx_buffer_count;
3778 * Build the links for the buffer entry lists such that
3779 * two circular lists are built. (Transmit and Receive).
3781 * Note: the links are physical addresses
3782 * which are read by the adapter to determine the next
3783 * buffer entry to use.
3786 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3787 /* calculate and store physical address of this buffer entry */
3788 info->rx_buffer_list[i].phys_entry =
3789 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3791 /* calculate and store physical address of */
3792 /* next entry in cirular list of entries */
3794 info->rx_buffer_list[i].link = info->buffer_list_phys;
3796 if ( i < info->rx_buffer_count - 1 )
3797 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3800 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3801 /* calculate and store physical address of this buffer entry */
3802 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3803 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3805 /* calculate and store physical address of */
3806 /* next entry in cirular list of entries */
3808 info->tx_buffer_list[i].link = info->buffer_list_phys +
3809 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3811 if ( i < info->tx_buffer_count - 1 )
3812 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3817 } /* end of mgsl_alloc_buffer_list_memory() */
3819 /* Free DMA buffers allocated for use as the
3820 * receive and transmit buffer lists.
3823 * The data transfer buffers associated with the buffer list
3824 * MUST be freed before freeing the buffer list itself because
3825 * the buffer list contains the information necessary to free
3826 * the individual buffers!
3828 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3830 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3831 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3833 info->buffer_list = NULL;
3834 info->rx_buffer_list = NULL;
3835 info->tx_buffer_list = NULL;
3837 } /* end of mgsl_free_buffer_list_memory() */
3840 * mgsl_alloc_frame_memory()
3842 * Allocate the frame DMA buffers used by the specified buffer list.
3843 * Each DMA buffer will be one memory page in size. This is necessary
3844 * because memory can fragment enough that it may be impossible
3849 * info pointer to device instance data
3850 * BufferList pointer to list of buffer entries
3851 * Buffercount count of buffer entries in buffer list
3853 * Return Value: 0 if success, otherwise -ENOMEM
3855 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3860 /* Allocate page sized buffers for the receive buffer list */
3862 for ( i = 0; i < Buffercount; i++ ) {
3863 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3864 /* PCI adapter uses shared memory buffers. */
3865 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3866 phys_addr = info->last_mem_alloc;
3867 info->last_mem_alloc += DMABUFFERSIZE;
3869 /* ISA adapter uses system memory. */
3870 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3871 if (BufferList[i].virt_addr == NULL)
3873 phys_addr = (u32)(BufferList[i].dma_addr);
3875 BufferList[i].phys_addr = phys_addr;
3880 } /* end of mgsl_alloc_frame_memory() */
3883 * mgsl_free_frame_memory()
3885 * Free the buffers associated with
3886 * each buffer entry of a buffer list.
3890 * info pointer to device instance data
3891 * BufferList pointer to list of buffer entries
3892 * Buffercount count of buffer entries in buffer list
3894 * Return Value: None
3896 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3901 for ( i = 0 ; i < Buffercount ; i++ ) {
3902 if ( BufferList[i].virt_addr ) {
3903 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3904 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3905 BufferList[i].virt_addr = NULL;
3910 } /* end of mgsl_free_frame_memory() */
3912 /* mgsl_free_dma_buffers()
3916 * Arguments: info pointer to device instance data
3917 * Return Value: None
3919 static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3921 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3922 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3923 mgsl_free_buffer_list_memory( info );
3925 } /* end of mgsl_free_dma_buffers() */
3929 * mgsl_alloc_intermediate_rxbuffer_memory()
3931 * Allocate a buffer large enough to hold max_frame_size. This buffer
3932 * is used to pass an assembled frame to the line discipline.
3936 * info pointer to device instance data
3938 * Return Value: 0 if success, otherwise -ENOMEM
3940 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3942 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3943 if ( info->intermediate_rxbuffer == NULL )
3948 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3951 * mgsl_free_intermediate_rxbuffer_memory()
3956 * info pointer to device instance data
3958 * Return Value: None
3960 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3962 kfree(info->intermediate_rxbuffer);
3963 info->intermediate_rxbuffer = NULL;
3965 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3968 * mgsl_alloc_intermediate_txbuffer_memory()
3970 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3971 * This buffer is used to load transmit frames into the adapter's dma transfer
3972 * buffers when there is sufficient space.
3976 * info pointer to device instance data
3978 * Return Value: 0 if success, otherwise -ENOMEM
3980 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3984 if ( debug_level >= DEBUG_LEVEL_INFO )
3985 printk("%s %s(%d) allocating %d tx holding buffers\n",
3986 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3988 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3990 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3991 info->tx_holding_buffers[i].buffer =
3992 kmalloc(info->max_frame_size, GFP_KERNEL);
3993 if (info->tx_holding_buffers[i].buffer == NULL) {
3994 for (--i; i >= 0; i--) {
3995 kfree(info->tx_holding_buffers[i].buffer);
3996 info->tx_holding_buffers[i].buffer = NULL;
4004 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4007 * mgsl_free_intermediate_txbuffer_memory()
4012 * info pointer to device instance data
4014 * Return Value: None
4016 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
4020 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
4021 kfree(info->tx_holding_buffers[i].buffer);
4022 info->tx_holding_buffers[i].buffer = NULL;
4025 info->get_tx_holding_index = 0;
4026 info->put_tx_holding_index = 0;
4027 info->tx_holding_count = 0;
4029 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4033 * load_next_tx_holding_buffer()
4035 * attempts to load the next buffered tx request into the
4040 * info pointer to device instance data
4042 * Return Value: true if next buffered tx request loaded
4043 * into adapter's tx dma buffer,
4046 static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4050 if ( info->tx_holding_count ) {
4051 /* determine if we have enough tx dma buffers
4052 * to accommodate the next tx frame
4054 struct tx_holding_buffer *ptx =
4055 &info->tx_holding_buffers[info->get_tx_holding_index];
4056 int num_free = num_free_tx_dma_buffers(info);
4057 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4058 if ( ptx->buffer_size % DMABUFFERSIZE )
4061 if (num_needed <= num_free) {
4062 info->xmit_cnt = ptx->buffer_size;
4063 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4065 --info->tx_holding_count;
4066 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4067 info->get_tx_holding_index=0;
4069 /* restart transmit timer */
4070 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4080 * save_tx_buffer_request()
4082 * attempt to store transmit frame request for later transmission
4086 * info pointer to device instance data
4087 * Buffer pointer to buffer containing frame to load
4088 * BufferSize size in bytes of frame in Buffer
4090 * Return Value: 1 if able to store, 0 otherwise
4092 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4094 struct tx_holding_buffer *ptx;
4096 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4097 return 0; /* all buffers in use */
4100 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4101 ptx->buffer_size = BufferSize;
4102 memcpy( ptx->buffer, Buffer, BufferSize);
4104 ++info->tx_holding_count;
4105 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4106 info->put_tx_holding_index=0;
4111 static int mgsl_claim_resources(struct mgsl_struct *info)
4113 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4114 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4115 __FILE__,__LINE__,info->device_name, info->io_base);
4118 info->io_addr_requested = true;
4120 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4121 info->device_name, info ) < 0 ) {
4122 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4123 __FILE__,__LINE__,info->device_name, info->irq_level );
4126 info->irq_requested = true;
4128 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4129 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4130 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4131 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4134 info->shared_mem_requested = true;
4135 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4136 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4137 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4140 info->lcr_mem_requested = true;
4142 info->memory_base = ioremap_nocache(info->phys_memory_base,
4144 if (!info->memory_base) {
4145 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4146 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4150 if ( !mgsl_memory_test(info) ) {
4151 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4152 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4156 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4158 if (!info->lcr_base) {
4159 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4160 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4163 info->lcr_base += info->lcr_offset;
4166 /* claim DMA channel */
4168 if (request_dma(info->dma_level,info->device_name) < 0){
4169 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4170 __FILE__,__LINE__,info->device_name, info->dma_level );
4171 mgsl_release_resources( info );
4174 info->dma_requested = true;
4176 /* ISA adapter uses bus master DMA */
4177 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4178 enable_dma(info->dma_level);
4181 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4182 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4183 __FILE__,__LINE__,info->device_name, info->dma_level );
4189 mgsl_release_resources(info);
4192 } /* end of mgsl_claim_resources() */
4194 static void mgsl_release_resources(struct mgsl_struct *info)
4196 if ( debug_level >= DEBUG_LEVEL_INFO )
4197 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4198 __FILE__,__LINE__,info->device_name );
4200 if ( info->irq_requested ) {
4201 free_irq(info->irq_level, info);
4202 info->irq_requested = false;
4204 if ( info->dma_requested ) {
4205 disable_dma(info->dma_level);
4206 free_dma(info->dma_level);
4207 info->dma_requested = false;
4209 mgsl_free_dma_buffers(info);
4210 mgsl_free_intermediate_rxbuffer_memory(info);
4211 mgsl_free_intermediate_txbuffer_memory(info);
4213 if ( info->io_addr_requested ) {
4214 release_region(info->io_base,info->io_addr_size);
4215 info->io_addr_requested = false;
4217 if ( info->shared_mem_requested ) {
4218 release_mem_region(info->phys_memory_base,0x40000);
4219 info->shared_mem_requested = false;
4221 if ( info->lcr_mem_requested ) {
4222 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4223 info->lcr_mem_requested = false;
4225 if (info->memory_base){
4226 iounmap(info->memory_base);
4227 info->memory_base = NULL;
4229 if (info->lcr_base){
4230 iounmap(info->lcr_base - info->lcr_offset);
4231 info->lcr_base = NULL;
4234 if ( debug_level >= DEBUG_LEVEL_INFO )
4235 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4236 __FILE__,__LINE__,info->device_name );
4238 } /* end of mgsl_release_resources() */
4240 /* mgsl_add_device()
4242 * Add the specified device instance data structure to the
4243 * global linked list of devices and increment the device count.
4245 * Arguments: info pointer to device instance data
4246 * Return Value: None
4248 static void mgsl_add_device( struct mgsl_struct *info )
4250 info->next_device = NULL;
4251 info->line = mgsl_device_count;
4252 sprintf(info->device_name,"ttySL%d",info->line);
4254 if (info->line < MAX_TOTAL_DEVICES) {
4255 if (maxframe[info->line])
4256 info->max_frame_size = maxframe[info->line];
4258 if (txdmabufs[info->line]) {
4259 info->num_tx_dma_buffers = txdmabufs[info->line];
4260 if (info->num_tx_dma_buffers < 1)
4261 info->num_tx_dma_buffers = 1;
4264 if (txholdbufs[info->line]) {
4265 info->num_tx_holding_buffers = txholdbufs[info->line];
4266 if (info->num_tx_holding_buffers < 1)
4267 info->num_tx_holding_buffers = 1;
4268 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4269 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4273 mgsl_device_count++;
4275 if ( !mgsl_device_list )
4276 mgsl_device_list = info;
4278 struct mgsl_struct *current_dev = mgsl_device_list;
4279 while( current_dev->next_device )
4280 current_dev = current_dev->next_device;
4281 current_dev->next_device = info;
4284 if ( info->max_frame_size < 4096 )
4285 info->max_frame_size = 4096;
4286 else if ( info->max_frame_size > 65535 )
4287 info->max_frame_size = 65535;
4289 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4290 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4291 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4292 info->phys_memory_base, info->phys_lcr_base,
4293 info->max_frame_size );
4295 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4296 info->device_name, info->io_base, info->irq_level, info->dma_level,
4297 info->max_frame_size );
4300 #if SYNCLINK_GENERIC_HDLC
4304 } /* end of mgsl_add_device() */
4306 /* mgsl_allocate_device()
4308 * Allocate and initialize a device instance structure
4311 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4313 static struct mgsl_struct* mgsl_allocate_device(void)
4315 struct mgsl_struct *info;
4317 info = kzalloc(sizeof(struct mgsl_struct),
4321 printk("Error can't allocate device instance data\n");
4323 tty_port_init(&info->port);
4324 info->magic = MGSL_MAGIC;
4325 INIT_WORK(&info->task, mgsl_bh_handler);
4326 info->max_frame_size = 4096;
4327 info->port.close_delay = 5*HZ/10;
4328 info->port.closing_wait = 30*HZ;
4329 init_waitqueue_head(&info->status_event_wait_q);
4330 init_waitqueue_head(&info->event_wait_q);
4331 spin_lock_init(&info->irq_spinlock);
4332 spin_lock_init(&info->netlock);
4333 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4334 info->idle_mode = HDLC_TXIDLE_FLAGS;
4335 info->num_tx_dma_buffers = 1;
4336 info->num_tx_holding_buffers = 0;
4341 } /* end of mgsl_allocate_device()*/
4343 static const struct tty_operations mgsl_ops = {
4345 .close = mgsl_close,
4346 .write = mgsl_write,
4347 .put_char = mgsl_put_char,
4348 .flush_chars = mgsl_flush_chars,
4349 .write_room = mgsl_write_room,
4350 .chars_in_buffer = mgsl_chars_in_buffer,
4351 .flush_buffer = mgsl_flush_buffer,
4352 .ioctl = mgsl_ioctl,
4353 .throttle = mgsl_throttle,
4354 .unthrottle = mgsl_unthrottle,
4355 .send_xchar = mgsl_send_xchar,
4356 .break_ctl = mgsl_break,
4357 .wait_until_sent = mgsl_wait_until_sent,
4358 .read_proc = mgsl_read_proc,
4359 .set_termios = mgsl_set_termios,
4361 .start = mgsl_start,
4362 .hangup = mgsl_hangup,
4363 .tiocmget = tiocmget,
4364 .tiocmset = tiocmset,
4368 * perform tty device initialization
4370 static int mgsl_init_tty(void)
4374 serial_driver = alloc_tty_driver(128);
4378 serial_driver->owner = THIS_MODULE;
4379 serial_driver->driver_name = "synclink";
4380 serial_driver->name = "ttySL";
4381 serial_driver->major = ttymajor;
4382 serial_driver->minor_start = 64;
4383 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4384 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4385 serial_driver->init_termios = tty_std_termios;
4386 serial_driver->init_termios.c_cflag =
4387 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4388 serial_driver->init_termios.c_ispeed = 9600;
4389 serial_driver->init_termios.c_ospeed = 9600;
4390 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4391 tty_set_operations(serial_driver, &mgsl_ops);
4392 if ((rc = tty_register_driver(serial_driver)) < 0) {
4393 printk("%s(%d):Couldn't register serial driver\n",
4395 put_tty_driver(serial_driver);
4396 serial_driver = NULL;
4400 printk("%s %s, tty major#%d\n",
4401 driver_name, driver_version,
4402 serial_driver->major);
4406 /* enumerate user specified ISA adapters
4408 static void mgsl_enum_isa_devices(void)
4410 struct mgsl_struct *info;
4413 /* Check for user specified ISA devices */
4415 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4416 if ( debug_level >= DEBUG_LEVEL_INFO )
4417 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4418 io[i], irq[i], dma[i] );
4420 info = mgsl_allocate_device();
4422 /* error allocating device instance data */
4423 if ( debug_level >= DEBUG_LEVEL_ERROR )
4424 printk( "can't allocate device instance data.\n");
4428 /* Copy user configuration info to device instance data */
4429 info->io_base = (unsigned int)io[i];
4430 info->irq_level = (unsigned int)irq[i];
4431 info->irq_level = irq_canonicalize(info->irq_level);
4432 info->dma_level = (unsigned int)dma[i];
4433 info->bus_type = MGSL_BUS_TYPE_ISA;
4434 info->io_addr_size = 16;
4435 info->irq_flags = 0;
4437 mgsl_add_device( info );
4441 static void synclink_cleanup(void)
4444 struct mgsl_struct *info;
4445 struct mgsl_struct *tmp;
4447 printk("Unloading %s: %s\n", driver_name, driver_version);
4449 if (serial_driver) {
4450 if ((rc = tty_unregister_driver(serial_driver)))
4451 printk("%s(%d) failed to unregister tty driver err=%d\n",
4452 __FILE__,__LINE__,rc);
4453 put_tty_driver(serial_driver);
4456 info = mgsl_device_list;
4458 #if SYNCLINK_GENERIC_HDLC
4461 mgsl_release_resources(info);
4463 info = info->next_device;
4468 pci_unregister_driver(&synclink_pci_driver);
4471 static int __init synclink_init(void)
4475 if (break_on_load) {
4476 mgsl_get_text_ptr();
4480 printk("%s %s\n", driver_name, driver_version);
4482 mgsl_enum_isa_devices();
4483 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4484 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4486 pci_registered = true;
4488 if ((rc = mgsl_init_tty()) < 0)
4498 static void __exit synclink_exit(void)
4503 module_init(synclink_init);
4504 module_exit(synclink_exit);
4509 * Issue a USC Receive/Transmit command to the
4510 * Channel Command/Address Register (CCAR).
4514 * The command is encoded in the most significant 5 bits <15..11>
4515 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4516 * and Bits <6..0> must be written as zeros.
4520 * info pointer to device information structure
4521 * Cmd command mask (use symbolic macros)
4527 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4529 /* output command to CCAR in bits <15..11> */
4530 /* preserve bits <10..7>, bits <6..0> must be zero */
4532 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4534 /* Read to flush write to CCAR */
4535 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4536 inw( info->io_base + CCAR );
4538 } /* end of usc_RTCmd() */
4543 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4547 * info pointer to device information structure
4548 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4554 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4556 /* write command mask to DCAR */
4557 outw( Cmd + info->mbre_bit, info->io_base );
4559 /* Read to flush write to DCAR */
4560 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4561 inw( info->io_base );
4563 } /* end of usc_DmaCmd() */
4568 * Write a 16-bit value to a USC DMA register
4572 * info pointer to device info structure
4573 * RegAddr register address (number) for write
4574 * RegValue 16-bit value to write to register
4581 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4583 /* Note: The DCAR is located at the adapter base address */
4584 /* Note: must preserve state of BIT8 in DCAR */
4586 outw( RegAddr + info->mbre_bit, info->io_base );
4587 outw( RegValue, info->io_base );
4589 /* Read to flush write to DCAR */
4590 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4591 inw( info->io_base );
4593 } /* end of usc_OutDmaReg() */
4598 * Read a 16-bit value from a DMA register
4602 * info pointer to device info structure
4603 * RegAddr register address (number) to read from
4607 * The 16-bit value read from register
4610 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4612 /* Note: The DCAR is located at the adapter base address */
4613 /* Note: must preserve state of BIT8 in DCAR */
4615 outw( RegAddr + info->mbre_bit, info->io_base );
4616 return inw( info->io_base );
4618 } /* end of usc_InDmaReg() */
4624 * Write a 16-bit value to a USC serial channel register
4628 * info pointer to device info structure
4629 * RegAddr register address (number) to write to
4630 * RegValue 16-bit value to write to register
4637 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4639 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4640 outw( RegValue, info->io_base + CCAR );
4642 /* Read to flush write to CCAR */
4643 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4644 inw( info->io_base + CCAR );
4646 } /* end of usc_OutReg() */
4651 * Reads a 16-bit value from a USC serial channel register
4655 * info pointer to device extension
4656 * RegAddr register address (number) to read from
4660 * 16-bit value read from register
4662 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4664 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4665 return inw( info->io_base + CCAR );
4667 } /* end of usc_InReg() */
4669 /* usc_set_sdlc_mode()
4671 * Set up the adapter for SDLC DMA communications.
4673 * Arguments: info pointer to device instance data
4674 * Return Value: NONE
4676 static void usc_set_sdlc_mode( struct mgsl_struct *info )
4682 * determine if the IUSC on the adapter is pre-SL1660. If
4683 * not, take advantage of the UnderWait feature of more
4684 * modern chips. If an underrun occurs and this bit is set,
4685 * the transmitter will idle the programmed idle pattern
4686 * until the driver has time to service the underrun. Otherwise,
4687 * the dma controller may get the cycles previously requested
4688 * and begin transmitting queued tx data.
4690 usc_OutReg(info,TMCR,0x1f);
4691 RegValue=usc_InReg(info,TMDR);
4692 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4694 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4697 ** Channel Mode Register (CMR)
4699 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4700 ** <13> 0 0 = Transmit Disabled (initially)
4701 ** <12> 0 1 = Consecutive Idles share common 0
4702 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4703 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4704 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4706 ** 1000 1110 0000 0110 = 0x8e06
4710 /*--------------------------------------------------
4711 * ignore user options for UnderRun Actions and
4713 *--------------------------------------------------*/
4717 /* Channel mode Register (CMR)
4719 * <15..14> 00 Tx Sub modes, Underrun Action
4720 * <13> 0 1 = Send Preamble before opening flag
4721 * <12> 0 1 = Consecutive Idles share common 0
4722 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4723 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4724 * <3..0> 0110 Receiver mode = HDLC/SDLC
4726 * 0000 0110 0000 0110 = 0x0606
4728 if (info->params.mode == MGSL_MODE_RAW) {
4729 RegValue = 0x0001; /* Set Receive mode = external sync */
4731 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4732 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4736 * CMR <15> 0 Don't send CRC on Tx Underrun
4737 * CMR <14> x undefined
4738 * CMR <13> 0 Send preamble before openning sync
4739 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4742 * CMR <11-8) 0100 MonoSync
4744 * 0x00 0100 xxxx xxxx 04xx
4752 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4754 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4756 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4757 RegValue |= BIT15 + BIT14;
4760 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4764 if ( info->params.mode == MGSL_MODE_HDLC &&
4765 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4768 if ( info->params.addr_filter != 0xff )
4770 /* set up receive address filtering */
4771 usc_OutReg( info, RSR, info->params.addr_filter );
4775 usc_OutReg( info, CMR, RegValue );
4776 info->cmr_value = RegValue;
4778 /* Receiver mode Register (RMR)
4780 * <15..13> 000 encoding
4781 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4782 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4783 * <9> 0 1 = Include Receive chars in CRC
4784 * <8> 1 1 = Use Abort/PE bit as abort indicator
4785 * <7..6> 00 Even parity
4786 * <5> 0 parity disabled
4787 * <4..2> 000 Receive Char Length = 8 bits
4788 * <1..0> 00 Disable Receiver
4790 * 0000 0101 0000 0000 = 0x0500
4795 switch ( info->params.encoding ) {
4796 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4797 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4798 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4799 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4800 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4801 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4802 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4805 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4807 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4808 RegValue |= ( BIT12 | BIT10 | BIT9 );
4810 usc_OutReg( info, RMR, RegValue );
4812 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4813 /* When an opening flag of an SDLC frame is recognized the */
4814 /* Receive Character count (RCC) is loaded with the value in */
4815 /* RCLR. The RCC is decremented for each received byte. The */
4816 /* value of RCC is stored after the closing flag of the frame */
4817 /* allowing the frame size to be computed. */
4819 usc_OutReg( info, RCLR, RCLRVALUE );
4821 usc_RCmd( info, RCmd_SelectRicrdma_level );
4823 /* Receive Interrupt Control Register (RICR)
4825 * <15..8> ? RxFIFO DMA Request Level
4826 * <7> 0 Exited Hunt IA (Interrupt Arm)
4827 * <6> 0 Idle Received IA
4828 * <5> 0 Break/Abort IA
4830 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4832 * <1> 1 Rx Overrun IA
4833 * <0> 0 Select TC0 value for readback
4835 * 0000 0000 0000 1000 = 0x000a
4838 /* Carry over the Exit Hunt and Idle Received bits */
4839 /* in case they have been armed by usc_ArmEvents. */
4841 RegValue = usc_InReg( info, RICR ) & 0xc0;
4843 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4844 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4846 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4848 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4850 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4851 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4853 /* Transmit mode Register (TMR)
4855 * <15..13> 000 encoding
4856 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4857 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4858 * <9> 0 1 = Tx CRC Enabled
4859 * <8> 0 1 = Append CRC to end of transmit frame
4860 * <7..6> 00 Transmit parity Even
4861 * <5> 0 Transmit parity Disabled
4862 * <4..2> 000 Tx Char Length = 8 bits
4863 * <1..0> 00 Disable Transmitter
4865 * 0000 0100 0000 0000 = 0x0400
4870 switch ( info->params.encoding ) {
4871 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4872 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4873 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4874 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4875 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4876 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4877 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4880 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4881 RegValue |= BIT9 + BIT8;
4882 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4883 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4885 usc_OutReg( info, TMR, RegValue );
4887 usc_set_txidle( info );
4890 usc_TCmd( info, TCmd_SelectTicrdma_level );
4892 /* Transmit Interrupt Control Register (TICR)
4894 * <15..8> ? Transmit FIFO DMA Level
4895 * <7> 0 Present IA (Interrupt Arm)
4896 * <6> 0 Idle Sent IA
4897 * <5> 1 Abort Sent IA
4898 * <4> 1 EOF/EOM Sent IA
4900 * <2> 1 1 = Wait for SW Trigger to Start Frame
4901 * <1> 1 Tx Underrun IA
4902 * <0> 0 TC0 constant on read back
4904 * 0000 0000 0011 0110 = 0x0036
4907 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4908 usc_OutReg( info, TICR, 0x0736 );
4910 usc_OutReg( info, TICR, 0x1436 );
4912 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4913 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4916 ** Transmit Command/Status Register (TCSR)
4918 ** <15..12> 0000 TCmd
4919 ** <11> 0/1 UnderWait
4920 ** <10..08> 000 TxIdle
4924 ** <4> x EOF/EOM Sent
4930 ** 0000 0000 0000 0000 = 0x0000
4932 info->tcsr_value = 0;
4935 info->tcsr_value |= TCSR_UNDERWAIT;
4937 usc_OutReg( info, TCSR, info->tcsr_value );
4939 /* Clock mode Control Register (CMCR)
4941 * <15..14> 00 counter 1 Source = Disabled
4942 * <13..12> 00 counter 0 Source = Disabled
4943 * <11..10> 11 BRG1 Input is TxC Pin
4944 * <9..8> 11 BRG0 Input is TxC Pin
4945 * <7..6> 01 DPLL Input is BRG1 Output
4946 * <5..3> XXX TxCLK comes from Port 0
4947 * <2..0> XXX RxCLK comes from Port 1
4949 * 0000 1111 0111 0111 = 0x0f77
4954 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4955 RegValue |= 0x0003; /* RxCLK from DPLL */
4956 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4957 RegValue |= 0x0004; /* RxCLK from BRG0 */
4958 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4959 RegValue |= 0x0006; /* RxCLK from TXC Input */
4961 RegValue |= 0x0007; /* RxCLK from Port1 */
4963 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4964 RegValue |= 0x0018; /* TxCLK from DPLL */
4965 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4966 RegValue |= 0x0020; /* TxCLK from BRG0 */
4967 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4968 RegValue |= 0x0038; /* RxCLK from TXC Input */
4970 RegValue |= 0x0030; /* TxCLK from Port0 */
4972 usc_OutReg( info, CMCR, RegValue );
4975 /* Hardware Configuration Register (HCR)
4977 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4978 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4979 * <12> 0 CVOK:0=report code violation in biphase
4980 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4981 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4982 * <7..6> 00 reserved
4983 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4985 * <3..2> 00 reserved
4986 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4992 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4997 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4998 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5000 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5001 XtalSpeed = 11059200;
5003 XtalSpeed = 14745600;
5005 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5009 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5016 /* Tc = (Xtal/Speed) - 1 */
5017 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5018 /* then rounding up gives a more precise time constant. Instead */
5019 /* of rounding up and then subtracting 1 we just don't subtract */
5020 /* the one in this case. */
5022 /*--------------------------------------------------
5023 * ejz: for DPLL mode, application should use the
5024 * same clock speed as the partner system, even
5025 * though clocking is derived from the input RxData.
5026 * In case the user uses a 0 for the clock speed,
5027 * default to 0xffffffff and don't try to divide by
5029 *--------------------------------------------------*/
5030 if ( info->params.clock_speed )
5032 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5033 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5034 / info->params.clock_speed) )
5041 /* Write 16-bit Time Constant for BRG1 */
5042 usc_OutReg( info, TC1R, Tc );
5044 RegValue |= BIT4; /* enable BRG1 */
5046 switch ( info->params.encoding ) {
5047 case HDLC_ENCODING_NRZ:
5048 case HDLC_ENCODING_NRZB:
5049 case HDLC_ENCODING_NRZI_MARK:
5050 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5051 case HDLC_ENCODING_BIPHASE_MARK:
5052 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5053 case HDLC_ENCODING_BIPHASE_LEVEL:
5054 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5058 usc_OutReg( info, HCR, RegValue );
5061 /* Channel Control/status Register (CCSR)
5063 * <15> X RCC FIFO Overflow status (RO)
5064 * <14> X RCC FIFO Not Empty status (RO)
5065 * <13> 0 1 = Clear RCC FIFO (WO)
5066 * <12> X DPLL Sync (RW)
5067 * <11> X DPLL 2 Missed Clocks status (RO)
5068 * <10> X DPLL 1 Missed Clock status (RO)
5069 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5070 * <7> X SDLC Loop On status (RO)
5071 * <6> X SDLC Loop Send status (RO)
5072 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5073 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5074 * <1..0> 00 reserved
5076 * 0000 0000 0010 0000 = 0x0020
5079 usc_OutReg( info, CCSR, 0x1020 );
5082 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5083 usc_OutReg( info, SICR,
5084 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5088 /* enable Master Interrupt Enable bit (MIE) */
5089 usc_EnableMasterIrqBit( info );
5091 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5092 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5094 /* arm RCC underflow interrupt */
5095 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5096 usc_EnableInterrupts(info, MISC);
5099 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5100 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5101 info->mbre_bit = BIT8;
5102 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5104 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5105 /* Enable DMAEN (Port 7, Bit 14) */
5106 /* This connects the DMA request signal to the ISA bus */
5107 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5110 /* DMA Control Register (DCR)
5112 * <15..14> 10 Priority mode = Alternating Tx/Rx
5113 * 01 Rx has priority
5114 * 00 Tx has priority
5116 * <13> 1 Enable Priority Preempt per DCR<15..14>
5117 * (WARNING DCR<11..10> must be 00 when this is 1)
5118 * 0 Choose activate channel per DCR<11..10>
5120 * <12> 0 Little Endian for Array/List
5121 * <11..10> 00 Both Channels can use each bus grant
5122 * <9..6> 0000 reserved
5123 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5124 * <4> 0 1 = drive D/C and S/D pins
5125 * <3> 1 1 = Add one wait state to all DMA cycles.
5126 * <2> 0 1 = Strobe /UAS on every transfer.
5127 * <1..0> 11 Addr incrementing only affects LS24 bits
5129 * 0110 0000 0000 1011 = 0x600b
5132 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5133 /* PCI adapter does not need DMA wait state */
5134 usc_OutDmaReg( info, DCR, 0xa00b );
5137 usc_OutDmaReg( info, DCR, 0x800b );
5140 /* Receive DMA mode Register (RDMR)
5142 * <15..14> 11 DMA mode = Linked List Buffer mode
5143 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5144 * <12> 1 Clear count of List Entry after fetching
5145 * <11..10> 00 Address mode = Increment
5146 * <9> 1 Terminate Buffer on RxBound
5147 * <8> 0 Bus Width = 16bits
5148 * <7..0> ? status Bits (write as 0s)
5150 * 1111 0010 0000 0000 = 0xf200
5153 usc_OutDmaReg( info, RDMR, 0xf200 );
5156 /* Transmit DMA mode Register (TDMR)
5158 * <15..14> 11 DMA mode = Linked List Buffer mode
5159 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5160 * <12> 1 Clear count of List Entry after fetching
5161 * <11..10> 00 Address mode = Increment
5162 * <9> 1 Terminate Buffer on end of frame
5163 * <8> 0 Bus Width = 16bits
5164 * <7..0> ? status Bits (Read Only so write as 0)
5166 * 1111 0010 0000 0000 = 0xf200
5169 usc_OutDmaReg( info, TDMR, 0xf200 );
5172 /* DMA Interrupt Control Register (DICR)
5174 * <15> 1 DMA Interrupt Enable
5175 * <14> 0 1 = Disable IEO from USC
5176 * <13> 0 1 = Don't provide vector during IntAck
5177 * <12> 1 1 = Include status in Vector
5178 * <10..2> 0 reserved, Must be 0s
5179 * <1> 0 1 = Rx DMA Interrupt Enabled
5180 * <0> 0 1 = Tx DMA Interrupt Enabled
5182 * 1001 0000 0000 0000 = 0x9000
5185 usc_OutDmaReg( info, DICR, 0x9000 );
5187 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5188 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5189 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5191 /* Channel Control Register (CCR)
5193 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5194 * <13> 0 Trigger Tx on SW Command Disabled
5195 * <12> 0 Flag Preamble Disabled
5196 * <11..10> 00 Preamble Length
5197 * <9..8> 00 Preamble Pattern
5198 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5199 * <5> 0 Trigger Rx on SW Command Disabled
5202 * 1000 0000 1000 0000 = 0x8080
5207 switch ( info->params.preamble_length ) {
5208 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5209 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5210 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5213 switch ( info->params.preamble ) {
5214 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5215 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5216 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5217 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5220 usc_OutReg( info, CCR, RegValue );
5224 * Burst/Dwell Control Register
5226 * <15..8> 0x20 Maximum number of transfers per bus grant
5227 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5230 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5231 /* don't limit bus occupancy on PCI adapter */
5232 usc_OutDmaReg( info, BDCR, 0x0000 );
5235 usc_OutDmaReg( info, BDCR, 0x2000 );
5237 usc_stop_transmitter(info);
5238 usc_stop_receiver(info);
5240 } /* end of usc_set_sdlc_mode() */
5242 /* usc_enable_loopback()
5244 * Set the 16C32 for internal loopback mode.
5245 * The TxCLK and RxCLK signals are generated from the BRG0 and
5246 * the TxD is looped back to the RxD internally.
5248 * Arguments: info pointer to device instance data
5249 * enable 1 = enable loopback, 0 = disable
5250 * Return Value: None
5252 static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5255 /* blank external TXD output */
5256 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5258 /* Clock mode Control Register (CMCR)
5260 * <15..14> 00 counter 1 Disabled
5261 * <13..12> 00 counter 0 Disabled
5262 * <11..10> 11 BRG1 Input is TxC Pin
5263 * <9..8> 11 BRG0 Input is TxC Pin
5264 * <7..6> 01 DPLL Input is BRG1 Output
5265 * <5..3> 100 TxCLK comes from BRG0
5266 * <2..0> 100 RxCLK comes from BRG0
5268 * 0000 1111 0110 0100 = 0x0f64
5271 usc_OutReg( info, CMCR, 0x0f64 );
5273 /* Write 16-bit Time Constant for BRG0 */
5274 /* use clock speed if available, otherwise use 8 for diagnostics */
5275 if (info->params.clock_speed) {
5276 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5277 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5279 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5281 usc_OutReg(info, TC0R, (u16)8);
5283 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5284 mode = Continuous Set Bit 0 to enable BRG0. */
5285 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5287 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5288 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5290 /* set Internal Data loopback mode */
5291 info->loopback_bits = 0x300;
5292 outw( 0x0300, info->io_base + CCAR );
5294 /* enable external TXD output */
5295 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5297 /* clear Internal Data loopback mode */
5298 info->loopback_bits = 0;
5299 outw( 0,info->io_base + CCAR );
5302 } /* end of usc_enable_loopback() */
5304 /* usc_enable_aux_clock()
5306 * Enabled the AUX clock output at the specified frequency.
5310 * info pointer to device extension
5311 * data_rate data rate of clock in bits per second
5312 * A data rate of 0 disables the AUX clock.
5314 * Return Value: None
5316 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5322 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5323 XtalSpeed = 11059200;
5325 XtalSpeed = 14745600;
5328 /* Tc = (Xtal/Speed) - 1 */
5329 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5330 /* then rounding up gives a more precise time constant. Instead */
5331 /* of rounding up and then subtracting 1 we just don't subtract */
5332 /* the one in this case. */
5335 Tc = (u16)(XtalSpeed/data_rate);
5336 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5339 /* Write 16-bit Time Constant for BRG0 */
5340 usc_OutReg( info, TC0R, Tc );
5343 * Hardware Configuration Register (HCR)
5344 * Clear Bit 1, BRG0 mode = Continuous
5345 * Set Bit 0 to enable BRG0.
5348 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5350 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5351 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5353 /* data rate == 0 so turn off BRG0 */
5354 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5357 } /* end of usc_enable_aux_clock() */
5361 * usc_process_rxoverrun_sync()
5363 * This function processes a receive overrun by resetting the
5364 * receive DMA buffers and issuing a Purge Rx FIFO command
5365 * to allow the receiver to continue receiving.
5369 * info pointer to device extension
5371 * Return Value: None
5373 static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5377 int frame_start_index;
5378 bool start_of_frame_found = false;
5379 bool end_of_frame_found = false;
5380 bool reprogram_dma = false;
5382 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5385 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5386 usc_RCmd( info, RCmd_EnterHuntmode );
5387 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5389 /* CurrentRxBuffer points to the 1st buffer of the next */
5390 /* possibly available receive frame. */
5392 frame_start_index = start_index = end_index = info->current_rx_buffer;
5394 /* Search for an unfinished string of buffers. This means */
5395 /* that a receive frame started (at least one buffer with */
5396 /* count set to zero) but there is no terminiting buffer */
5397 /* (status set to non-zero). */
5399 while( !buffer_list[end_index].count )
5401 /* Count field has been reset to zero by 16C32. */
5402 /* This buffer is currently in use. */
5404 if ( !start_of_frame_found )
5406 start_of_frame_found = true;
5407 frame_start_index = end_index;
5408 end_of_frame_found = false;
5411 if ( buffer_list[end_index].status )
5413 /* Status field has been set by 16C32. */
5414 /* This is the last buffer of a received frame. */
5416 /* We want to leave the buffers for this frame intact. */
5417 /* Move on to next possible frame. */
5419 start_of_frame_found = false;
5420 end_of_frame_found = true;
5423 /* advance to next buffer entry in linked list */
5425 if ( end_index == info->rx_buffer_count )
5428 if ( start_index == end_index )
5430 /* The entire list has been searched with all Counts == 0 and */
5431 /* all Status == 0. The receive buffers are */
5432 /* completely screwed, reset all receive buffers! */
5433 mgsl_reset_rx_dma_buffers( info );
5434 frame_start_index = 0;
5435 start_of_frame_found = false;
5436 reprogram_dma = true;
5441 if ( start_of_frame_found && !end_of_frame_found )
5443 /* There is an unfinished string of receive DMA buffers */
5444 /* as a result of the receiver overrun. */
5446 /* Reset the buffers for the unfinished frame */
5447 /* and reprogram the receive DMA controller to start */
5448 /* at the 1st buffer of unfinished frame. */
5450 start_index = frame_start_index;
5454 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5456 /* Adjust index for wrap around. */
5457 if ( start_index == info->rx_buffer_count )
5460 } while( start_index != end_index );
5462 reprogram_dma = true;
5465 if ( reprogram_dma )
5467 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5468 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5469 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5471 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5473 /* This empties the receive FIFO and loads the RCC with RCLR */
5474 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5476 /* program 16C32 with physical address of 1st DMA buffer entry */
5477 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5478 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5479 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5481 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5482 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5483 usc_EnableInterrupts( info, RECEIVE_STATUS );
5485 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5486 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5488 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5489 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5490 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5491 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5492 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5494 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5498 /* This empties the receive FIFO and loads the RCC with RCLR */
5499 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5500 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5503 } /* end of usc_process_rxoverrun_sync() */
5505 /* usc_stop_receiver()
5507 * Disable USC receiver
5509 * Arguments: info pointer to device instance data
5510 * Return Value: None
5512 static void usc_stop_receiver( struct mgsl_struct *info )
5514 if (debug_level >= DEBUG_LEVEL_ISR)
5515 printk("%s(%d):usc_stop_receiver(%s)\n",
5516 __FILE__,__LINE__, info->device_name );
5518 /* Disable receive DMA channel. */
5519 /* This also disables receive DMA channel interrupts */
5520 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5522 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5523 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5524 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5526 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5528 /* This empties the receive FIFO and loads the RCC with RCLR */
5529 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5530 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5532 info->rx_enabled = false;
5533 info->rx_overflow = false;
5534 info->rx_rcc_underrun = false;
5536 } /* end of stop_receiver() */
5538 /* usc_start_receiver()
5540 * Enable the USC receiver
5542 * Arguments: info pointer to device instance data
5543 * Return Value: None
5545 static void usc_start_receiver( struct mgsl_struct *info )
5549 if (debug_level >= DEBUG_LEVEL_ISR)
5550 printk("%s(%d):usc_start_receiver(%s)\n",
5551 __FILE__,__LINE__, info->device_name );
5553 mgsl_reset_rx_dma_buffers( info );
5554 usc_stop_receiver( info );
5556 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5557 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5559 if ( info->params.mode == MGSL_MODE_HDLC ||
5560 info->params.mode == MGSL_MODE_RAW ) {
5561 /* DMA mode Transfers */
5562 /* Program the DMA controller. */
5563 /* Enable the DMA controller end of buffer interrupt. */
5565 /* program 16C32 with physical address of 1st DMA buffer entry */
5566 phys_addr = info->rx_buffer_list[0].phys_entry;
5567 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5568 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5570 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5571 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5572 usc_EnableInterrupts( info, RECEIVE_STATUS );
5574 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5575 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5577 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5578 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5579 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5580 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5581 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5583 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5585 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5586 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5587 usc_EnableInterrupts(info, RECEIVE_DATA);
5589 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5590 usc_RCmd( info, RCmd_EnterHuntmode );
5592 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5595 usc_OutReg( info, CCSR, 0x1020 );
5597 info->rx_enabled = true;
5599 } /* end of usc_start_receiver() */
5601 /* usc_start_transmitter()
5603 * Enable the USC transmitter and send a transmit frame if
5604 * one is loaded in the DMA buffers.
5606 * Arguments: info pointer to device instance data
5607 * Return Value: None
5609 static void usc_start_transmitter( struct mgsl_struct *info )
5612 unsigned int FrameSize;
5614 if (debug_level >= DEBUG_LEVEL_ISR)
5615 printk("%s(%d):usc_start_transmitter(%s)\n",
5616 __FILE__,__LINE__, info->device_name );
5618 if ( info->xmit_cnt ) {
5620 /* If auto RTS enabled and RTS is inactive, then assert */
5621 /* RTS and set a flag indicating that the driver should */
5622 /* negate RTS when the transmission completes. */
5624 info->drop_rts_on_tx_done = false;
5626 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5627 usc_get_serial_signals( info );
5628 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5629 info->serial_signals |= SerialSignal_RTS;
5630 usc_set_serial_signals( info );
5631 info->drop_rts_on_tx_done = true;
5636 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5637 if ( !info->tx_active ) {
5638 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5639 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5640 usc_EnableInterrupts(info, TRANSMIT_DATA);
5641 usc_load_txfifo(info);
5644 /* Disable transmit DMA controller while programming. */
5645 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5647 /* Transmit DMA buffer is loaded, so program USC */
5648 /* to send the frame contained in the buffers. */
5650 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5652 /* if operating in Raw sync mode, reset the rcc component
5653 * of the tx dma buffer entry, otherwise, the serial controller
5654 * will send a closing sync char after this count.
5656 if ( info->params.mode == MGSL_MODE_RAW )
5657 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5659 /* Program the Transmit Character Length Register (TCLR) */
5660 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5661 usc_OutReg( info, TCLR, (u16)FrameSize );
5663 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5665 /* Program the address of the 1st DMA Buffer Entry in linked list */
5666 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5667 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5668 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5670 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5671 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5672 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5674 if ( info->params.mode == MGSL_MODE_RAW &&
5675 info->num_tx_dma_buffers > 1 ) {
5676 /* When running external sync mode, attempt to 'stream' transmit */
5677 /* by filling tx dma buffers as they become available. To do this */
5678 /* we need to enable Tx DMA EOB Status interrupts : */
5680 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5681 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5683 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5684 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5687 /* Initialize Transmit DMA Channel */
5688 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5690 usc_TCmd( info, TCmd_SendFrame );
5692 mod_timer(&info->tx_timer, jiffies +
5693 msecs_to_jiffies(5000));
5695 info->tx_active = true;
5698 if ( !info->tx_enabled ) {
5699 info->tx_enabled = true;
5700 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5701 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5703 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5706 } /* end of usc_start_transmitter() */
5708 /* usc_stop_transmitter()
5710 * Stops the transmitter and DMA
5712 * Arguments: info pointer to device isntance data
5713 * Return Value: None
5715 static void usc_stop_transmitter( struct mgsl_struct *info )
5717 if (debug_level >= DEBUG_LEVEL_ISR)
5718 printk("%s(%d):usc_stop_transmitter(%s)\n",
5719 __FILE__,__LINE__, info->device_name );
5721 del_timer(&info->tx_timer);
5723 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5724 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5725 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5727 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5728 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5729 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5731 info->tx_enabled = false;
5732 info->tx_active = false;
5734 } /* end of usc_stop_transmitter() */
5736 /* usc_load_txfifo()
5738 * Fill the transmit FIFO until the FIFO is full or
5739 * there is no more data to load.
5741 * Arguments: info pointer to device extension (instance data)
5742 * Return Value: None
5744 static void usc_load_txfifo( struct mgsl_struct *info )
5749 if ( !info->xmit_cnt && !info->x_char )
5752 /* Select transmit FIFO status readback in TICR */
5753 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5755 /* load the Transmit FIFO until FIFOs full or all data sent */
5757 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5758 /* there is more space in the transmit FIFO and */
5759 /* there is more data in transmit buffer */
5761 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5762 /* write a 16-bit word from transmit buffer to 16C32 */
5764 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5765 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5766 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5767 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5769 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5771 info->xmit_cnt -= 2;
5772 info->icount.tx += 2;
5774 /* only 1 byte left to transmit or 1 FIFO slot left */
5776 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5777 info->io_base + CCAR );
5780 /* transmit pending high priority char */
5781 outw( info->x_char,info->io_base + CCAR );
5784 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5785 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5792 } /* end of usc_load_txfifo() */
5796 * Reset the adapter to a known state and prepare it for further use.
5798 * Arguments: info pointer to device instance data
5799 * Return Value: None
5801 static void usc_reset( struct mgsl_struct *info )
5803 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5807 /* Set BIT30 of Misc Control Register */
5808 /* (Local Control Register 0x50) to force reset of USC. */
5810 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5811 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5813 info->misc_ctrl_value |= BIT30;
5814 *MiscCtrl = info->misc_ctrl_value;
5817 * Force at least 170ns delay before clearing
5818 * reset bit. Each read from LCR takes at least
5819 * 30ns so 10 times for 300ns to be safe.
5822 readval = *MiscCtrl;
5824 info->misc_ctrl_value &= ~BIT30;
5825 *MiscCtrl = info->misc_ctrl_value;
5827 *LCR0BRDR = BUS_DESCRIPTOR(
5828 1, // Write Strobe Hold (0-3)
5829 2, // Write Strobe Delay (0-3)
5830 2, // Read Strobe Delay (0-3)
5831 0, // NWDD (Write data-data) (0-3)
5832 4, // NWAD (Write Addr-data) (0-31)
5833 0, // NXDA (Read/Write Data-Addr) (0-3)
5834 0, // NRDD (Read Data-Data) (0-3)
5835 5 // NRAD (Read Addr-Data) (0-31)
5839 outb( 0,info->io_base + 8 );
5843 info->loopback_bits = 0;
5844 info->usc_idle_mode = 0;
5847 * Program the Bus Configuration Register (BCR)
5849 * <15> 0 Don't use separate address
5850 * <14..6> 0 reserved
5851 * <5..4> 00 IAckmode = Default, don't care
5852 * <3> 1 Bus Request Totem Pole output
5853 * <2> 1 Use 16 Bit data bus
5854 * <1> 0 IRQ Totem Pole output
5855 * <0> 0 Don't Shift Right Addr
5857 * 0000 0000 0000 1100 = 0x000c
5859 * By writing to io_base + SDPIN the Wait/Ack pin is
5860 * programmed to work as a Wait pin.
5863 outw( 0x000c,info->io_base + SDPIN );
5866 outw( 0,info->io_base );
5867 outw( 0,info->io_base + CCAR );
5869 /* select little endian byte ordering */
5870 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5873 /* Port Control Register (PCR)
5875 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5876 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5877 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5878 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5879 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5880 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5881 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5882 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5884 * 1111 0000 1111 0101 = 0xf0f5
5887 usc_OutReg( info, PCR, 0xf0f5 );
5891 * Input/Output Control Register
5893 * <15..14> 00 CTS is active low input
5894 * <13..12> 00 DCD is active low input
5895 * <11..10> 00 TxREQ pin is input (DSR)
5896 * <9..8> 00 RxREQ pin is input (RI)
5897 * <7..6> 00 TxD is output (Transmit Data)
5898 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5899 * <2..0> 100 RxC is Output (drive with BRG0)
5901 * 0000 0000 0000 0100 = 0x0004
5904 usc_OutReg( info, IOCR, 0x0004 );
5906 } /* end of usc_reset() */
5908 /* usc_set_async_mode()
5910 * Program adapter for asynchronous communications.
5912 * Arguments: info pointer to device instance data
5913 * Return Value: None
5915 static void usc_set_async_mode( struct mgsl_struct *info )
5919 /* disable interrupts while programming USC */
5920 usc_DisableMasterIrqBit( info );
5922 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5923 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5925 usc_loopback_frame( info );
5927 /* Channel mode Register (CMR)
5929 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5930 * <13..12> 00 00 = 16X Clock
5931 * <11..8> 0000 Transmitter mode = Asynchronous
5932 * <7..6> 00 reserved?
5933 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5934 * <3..0> 0000 Receiver mode = Asynchronous
5936 * 0000 0000 0000 0000 = 0x0
5940 if ( info->params.stop_bits != 1 )
5942 usc_OutReg( info, CMR, RegValue );
5945 /* Receiver mode Register (RMR)
5947 * <15..13> 000 encoding = None
5948 * <12..08> 00000 reserved (Sync Only)
5949 * <7..6> 00 Even parity
5950 * <5> 0 parity disabled
5951 * <4..2> 000 Receive Char Length = 8 bits
5952 * <1..0> 00 Disable Receiver
5954 * 0000 0000 0000 0000 = 0x0
5959 if ( info->params.data_bits != 8 )
5960 RegValue |= BIT4+BIT3+BIT2;
5962 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5964 if ( info->params.parity != ASYNC_PARITY_ODD )
5968 usc_OutReg( info, RMR, RegValue );
5971 /* Set IRQ trigger level */
5973 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5976 /* Receive Interrupt Control Register (RICR)
5978 * <15..8> ? RxFIFO IRQ Request Level
5980 * Note: For async mode the receive FIFO level must be set
5981 * to 0 to avoid the situation where the FIFO contains fewer bytes
5982 * than the trigger level and no more data is expected.
5984 * <7> 0 Exited Hunt IA (Interrupt Arm)
5985 * <6> 0 Idle Received IA
5986 * <5> 0 Break/Abort IA
5988 * <3> 0 Queued status reflects oldest byte in FIFO
5990 * <1> 0 Rx Overrun IA
5991 * <0> 0 Select TC0 value for readback
5993 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5996 usc_OutReg( info, RICR, 0x0000 );
5998 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5999 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
6002 /* Transmit mode Register (TMR)
6004 * <15..13> 000 encoding = None
6005 * <12..08> 00000 reserved (Sync Only)
6006 * <7..6> 00 Transmit parity Even
6007 * <5> 0 Transmit parity Disabled
6008 * <4..2> 000 Tx Char Length = 8 bits
6009 * <1..0> 00 Disable Transmitter
6011 * 0000 0000 0000 0000 = 0x0
6016 if ( info->params.data_bits != 8 )
6017 RegValue |= BIT4+BIT3+BIT2;
6019 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6021 if ( info->params.parity != ASYNC_PARITY_ODD )
6025 usc_OutReg( info, TMR, RegValue );
6027 usc_set_txidle( info );
6030 /* Set IRQ trigger level */
6032 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6035 /* Transmit Interrupt Control Register (TICR)
6037 * <15..8> ? Transmit FIFO IRQ Level
6038 * <7> 0 Present IA (Interrupt Arm)
6039 * <6> 1 Idle Sent IA
6040 * <5> 0 Abort Sent IA
6041 * <4> 0 EOF/EOM Sent IA
6043 * <2> 0 1 = Wait for SW Trigger to Start Frame
6044 * <1> 0 Tx Underrun IA
6045 * <0> 0 TC0 constant on read back
6047 * 0000 0000 0100 0000 = 0x0040
6050 usc_OutReg( info, TICR, 0x1f40 );
6052 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6053 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6055 usc_enable_async_clock( info, info->params.data_rate );
6058 /* Channel Control/status Register (CCSR)
6060 * <15> X RCC FIFO Overflow status (RO)
6061 * <14> X RCC FIFO Not Empty status (RO)
6062 * <13> 0 1 = Clear RCC FIFO (WO)
6063 * <12> X DPLL in Sync status (RO)
6064 * <11> X DPLL 2 Missed Clocks status (RO)
6065 * <10> X DPLL 1 Missed Clock status (RO)
6066 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6067 * <7> X SDLC Loop On status (RO)
6068 * <6> X SDLC Loop Send status (RO)
6069 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6070 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6071 * <1..0> 00 reserved
6073 * 0000 0000 0010 0000 = 0x0020
6076 usc_OutReg( info, CCSR, 0x0020 );
6078 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6079 RECEIVE_DATA + RECEIVE_STATUS );
6081 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6082 RECEIVE_DATA + RECEIVE_STATUS );
6084 usc_EnableMasterIrqBit( info );
6086 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6087 /* Enable INTEN (Port 6, Bit12) */
6088 /* This connects the IRQ request signal to the ISA bus */
6089 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6092 if (info->params.loopback) {
6093 info->loopback_bits = 0x300;
6094 outw(0x0300, info->io_base + CCAR);
6097 } /* end of usc_set_async_mode() */
6099 /* usc_loopback_frame()
6101 * Loop back a small (2 byte) dummy SDLC frame.
6102 * Interrupts and DMA are NOT used. The purpose of this is to
6103 * clear any 'stale' status info left over from running in async mode.
6105 * The 16C32 shows the strange behaviour of marking the 1st
6106 * received SDLC frame with a CRC error even when there is no
6107 * CRC error. To get around this a small dummy from of 2 bytes
6108 * is looped back when switching from async to sync mode.
6110 * Arguments: info pointer to device instance data
6111 * Return Value: None
6113 static void usc_loopback_frame( struct mgsl_struct *info )
6116 unsigned long oldmode = info->params.mode;
6118 info->params.mode = MGSL_MODE_HDLC;
6120 usc_DisableMasterIrqBit( info );
6122 usc_set_sdlc_mode( info );
6123 usc_enable_loopback( info, 1 );
6125 /* Write 16-bit Time Constant for BRG0 */
6126 usc_OutReg( info, TC0R, 0 );
6128 /* Channel Control Register (CCR)
6130 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6131 * <13> 0 Trigger Tx on SW Command Disabled
6132 * <12> 0 Flag Preamble Disabled
6133 * <11..10> 00 Preamble Length = 8-Bits
6134 * <9..8> 01 Preamble Pattern = flags
6135 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6136 * <5> 0 Trigger Rx on SW Command Disabled
6139 * 0000 0001 0000 0000 = 0x0100
6142 usc_OutReg( info, CCR, 0x0100 );
6144 /* SETUP RECEIVER */
6145 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6146 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6148 /* SETUP TRANSMITTER */
6149 /* Program the Transmit Character Length Register (TCLR) */
6150 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6151 usc_OutReg( info, TCLR, 2 );
6152 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6154 /* unlatch Tx status bits, and start transmit channel. */
6155 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6156 outw(0,info->io_base + DATAREG);
6158 /* ENABLE TRANSMITTER */
6159 usc_TCmd( info, TCmd_SendFrame );
6160 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6162 /* WAIT FOR RECEIVE COMPLETE */
6163 for (i=0 ; i<1000 ; i++)
6164 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6167 /* clear Internal Data loopback mode */
6168 usc_enable_loopback(info, 0);
6170 usc_EnableMasterIrqBit(info);
6172 info->params.mode = oldmode;
6174 } /* end of usc_loopback_frame() */
6176 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6178 * Arguments: info pointer to adapter info structure
6179 * Return Value: None
6181 static void usc_set_sync_mode( struct mgsl_struct *info )
6183 usc_loopback_frame( info );
6184 usc_set_sdlc_mode( info );
6186 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6187 /* Enable INTEN (Port 6, Bit12) */
6188 /* This connects the IRQ request signal to the ISA bus */
6189 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6192 usc_enable_aux_clock(info, info->params.clock_speed);
6194 if (info->params.loopback)
6195 usc_enable_loopback(info,1);
6197 } /* end of mgsl_set_sync_mode() */
6199 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6201 * Arguments: info pointer to device instance data
6202 * Return Value: None
6204 static void usc_set_txidle( struct mgsl_struct *info )
6206 u16 usc_idle_mode = IDLEMODE_FLAGS;
6208 /* Map API idle mode to USC register bits */
6210 switch( info->idle_mode ){
6211 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6212 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6213 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6214 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6215 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6216 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6217 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6220 info->usc_idle_mode = usc_idle_mode;
6221 //usc_OutReg(info, TCSR, usc_idle_mode);
6222 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6223 info->tcsr_value += usc_idle_mode;
6224 usc_OutReg(info, TCSR, info->tcsr_value);
6227 * if SyncLink WAN adapter is running in external sync mode, the
6228 * transmitter has been set to Monosync in order to try to mimic
6229 * a true raw outbound bit stream. Monosync still sends an open/close
6230 * sync char at the start/end of a frame. Try to match those sync
6231 * patterns to the idle mode set here
6233 if ( info->params.mode == MGSL_MODE_RAW ) {
6234 unsigned char syncpat = 0;
6235 switch( info->idle_mode ) {
6236 case HDLC_TXIDLE_FLAGS:
6239 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6242 case HDLC_TXIDLE_ZEROS:
6243 case HDLC_TXIDLE_SPACE:
6246 case HDLC_TXIDLE_ONES:
6247 case HDLC_TXIDLE_MARK:
6250 case HDLC_TXIDLE_ALT_MARK_SPACE:
6255 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6258 } /* end of usc_set_txidle() */
6260 /* usc_get_serial_signals()
6262 * Query the adapter for the state of the V24 status (input) signals.
6264 * Arguments: info pointer to device instance data
6265 * Return Value: None
6267 static void usc_get_serial_signals( struct mgsl_struct *info )
6271 /* clear all serial signals except DTR and RTS */
6272 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6274 /* Read the Misc Interrupt status Register (MISR) to get */
6275 /* the V24 status signals. */
6277 status = usc_InReg( info, MISR );
6279 /* set serial signal bits to reflect MISR */
6281 if ( status & MISCSTATUS_CTS )
6282 info->serial_signals |= SerialSignal_CTS;
6284 if ( status & MISCSTATUS_DCD )
6285 info->serial_signals |= SerialSignal_DCD;
6287 if ( status & MISCSTATUS_RI )
6288 info->serial_signals |= SerialSignal_RI;
6290 if ( status & MISCSTATUS_DSR )
6291 info->serial_signals |= SerialSignal_DSR;
6293 } /* end of usc_get_serial_signals() */
6295 /* usc_set_serial_signals()
6297 * Set the state of DTR and RTS based on contents of
6298 * serial_signals member of device extension.
6300 * Arguments: info pointer to device instance data
6301 * Return Value: None
6303 static void usc_set_serial_signals( struct mgsl_struct *info )
6306 unsigned char V24Out = info->serial_signals;
6308 /* get the current value of the Port Control Register (PCR) */
6310 Control = usc_InReg( info, PCR );
6312 if ( V24Out & SerialSignal_RTS )
6317 if ( V24Out & SerialSignal_DTR )
6322 usc_OutReg( info, PCR, Control );
6324 } /* end of usc_set_serial_signals() */
6326 /* usc_enable_async_clock()
6328 * Enable the async clock at the specified frequency.
6330 * Arguments: info pointer to device instance data
6331 * data_rate data rate of clock in bps
6332 * 0 disables the AUX clock.
6333 * Return Value: None
6335 static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6339 * Clock mode Control Register (CMCR)
6341 * <15..14> 00 counter 1 Disabled
6342 * <13..12> 00 counter 0 Disabled
6343 * <11..10> 11 BRG1 Input is TxC Pin
6344 * <9..8> 11 BRG0 Input is TxC Pin
6345 * <7..6> 01 DPLL Input is BRG1 Output
6346 * <5..3> 100 TxCLK comes from BRG0
6347 * <2..0> 100 RxCLK comes from BRG0
6349 * 0000 1111 0110 0100 = 0x0f64
6352 usc_OutReg( info, CMCR, 0x0f64 );
6356 * Write 16-bit Time Constant for BRG0
6357 * Time Constant = (ClkSpeed / data_rate) - 1
6358 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6361 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6362 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6364 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6368 * Hardware Configuration Register (HCR)
6369 * Clear Bit 1, BRG0 mode = Continuous
6370 * Set Bit 0 to enable BRG0.
6373 usc_OutReg( info, HCR,
6374 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6377 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6379 usc_OutReg( info, IOCR,
6380 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6382 /* data rate == 0 so turn off BRG0 */
6383 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6386 } /* end of usc_enable_async_clock() */
6389 * Buffer Structures:
6391 * Normal memory access uses virtual addresses that can make discontiguous
6392 * physical memory pages appear to be contiguous in the virtual address
6393 * space (the processors memory mapping handles the conversions).
6395 * DMA transfers require physically contiguous memory. This is because
6396 * the DMA system controller and DMA bus masters deal with memory using
6397 * only physical addresses.
6399 * This causes a problem under Windows NT when large DMA buffers are
6400 * needed. Fragmentation of the nonpaged pool prevents allocations of
6401 * physically contiguous buffers larger than the PAGE_SIZE.
6403 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6404 * allows DMA transfers to physically discontiguous buffers. Information
6405 * about each data transfer buffer is contained in a memory structure
6406 * called a 'buffer entry'. A list of buffer entries is maintained
6407 * to track and control the use of the data transfer buffers.
6409 * To support this strategy we will allocate sufficient PAGE_SIZE
6410 * contiguous memory buffers to allow for the total required buffer
6413 * The 16C32 accesses the list of buffer entries using Bus Master
6414 * DMA. Control information is read from the buffer entries by the
6415 * 16C32 to control data transfers. status information is written to
6416 * the buffer entries by the 16C32 to indicate the status of completed
6419 * The CPU writes control information to the buffer entries to control
6420 * the 16C32 and reads status information from the buffer entries to
6421 * determine information about received and transmitted frames.
6423 * Because the CPU and 16C32 (adapter) both need simultaneous access
6424 * to the buffer entries, the buffer entry memory is allocated with
6425 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6426 * entry list to PAGE_SIZE.
6428 * The actual data buffers on the other hand will only be accessed
6429 * by the CPU or the adapter but not by both simultaneously. This allows
6430 * Scatter/Gather packet based DMA procedures for using physically
6431 * discontiguous pages.
6435 * mgsl_reset_tx_dma_buffers()
6437 * Set the count for all transmit buffers to 0 to indicate the
6438 * buffer is available for use and set the current buffer to the
6439 * first buffer. This effectively makes all buffers free and
6440 * discards any data in buffers.
6442 * Arguments: info pointer to device instance data
6443 * Return Value: None
6445 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6449 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6450 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6453 info->current_tx_buffer = 0;
6454 info->start_tx_dma_buffer = 0;
6455 info->tx_dma_buffers_used = 0;
6457 info->get_tx_holding_index = 0;
6458 info->put_tx_holding_index = 0;
6459 info->tx_holding_count = 0;
6461 } /* end of mgsl_reset_tx_dma_buffers() */
6464 * num_free_tx_dma_buffers()
6466 * returns the number of free tx dma buffers available
6468 * Arguments: info pointer to device instance data
6469 * Return Value: number of free tx dma buffers
6471 static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6473 return info->tx_buffer_count - info->tx_dma_buffers_used;
6477 * mgsl_reset_rx_dma_buffers()
6479 * Set the count for all receive buffers to DMABUFFERSIZE
6480 * and set the current buffer to the first buffer. This effectively
6481 * makes all buffers free and discards any data in buffers.
6483 * Arguments: info pointer to device instance data
6484 * Return Value: None
6486 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6490 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6491 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6492 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6493 // info->rx_buffer_list[i].status = 0;
6496 info->current_rx_buffer = 0;
6498 } /* end of mgsl_reset_rx_dma_buffers() */
6501 * mgsl_free_rx_frame_buffers()
6503 * Free the receive buffers used by a received SDLC
6504 * frame such that the buffers can be reused.
6508 * info pointer to device instance data
6509 * StartIndex index of 1st receive buffer of frame
6510 * EndIndex index of last receive buffer of frame
6512 * Return Value: None
6514 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6517 DMABUFFERENTRY *pBufEntry;
6520 /* Starting with 1st buffer entry of the frame clear the status */
6521 /* field and set the count field to DMA Buffer Size. */
6526 pBufEntry = &(info->rx_buffer_list[Index]);
6528 if ( Index == EndIndex ) {
6529 /* This is the last buffer of the frame! */
6533 /* reset current buffer for reuse */
6534 // pBufEntry->status = 0;
6535 // pBufEntry->count = DMABUFFERSIZE;
6536 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6538 /* advance to next buffer entry in linked list */
6540 if ( Index == info->rx_buffer_count )
6544 /* set current buffer to next buffer after last buffer of frame */
6545 info->current_rx_buffer = Index;
6547 } /* end of free_rx_frame_buffers() */
6549 /* mgsl_get_rx_frame()
6551 * This function attempts to return a received SDLC frame from the
6552 * receive DMA buffers. Only frames received without errors are returned.
6554 * Arguments: info pointer to device extension
6555 * Return Value: true if frame returned, otherwise false
6557 static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6559 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6560 unsigned short status;
6561 DMABUFFERENTRY *pBufEntry;
6562 unsigned int framesize = 0;
6563 bool ReturnCode = false;
6564 unsigned long flags;
6565 struct tty_struct *tty = info->port.tty;
6566 bool return_frame = false;
6569 * current_rx_buffer points to the 1st buffer of the next available
6570 * receive frame. To find the last buffer of the frame look for
6571 * a non-zero status field in the buffer entries. (The status
6572 * field is set by the 16C32 after completing a receive frame.
6575 StartIndex = EndIndex = info->current_rx_buffer;
6577 while( !info->rx_buffer_list[EndIndex].status ) {
6579 * If the count field of the buffer entry is non-zero then
6580 * this buffer has not been used. (The 16C32 clears the count
6581 * field when it starts using the buffer.) If an unused buffer
6582 * is encountered then there are no frames available.
6585 if ( info->rx_buffer_list[EndIndex].count )
6588 /* advance to next buffer entry in linked list */
6590 if ( EndIndex == info->rx_buffer_count )
6593 /* if entire list searched then no frame available */
6594 if ( EndIndex == StartIndex ) {
6595 /* If this occurs then something bad happened,
6596 * all buffers have been 'used' but none mark
6597 * the end of a frame. Reset buffers and receiver.
6600 if ( info->rx_enabled ){
6601 spin_lock_irqsave(&info->irq_spinlock,flags);
6602 usc_start_receiver(info);
6603 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6610 /* check status of receive frame */
6612 status = info->rx_buffer_list[EndIndex].status;
6614 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6615 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6616 if ( status & RXSTATUS_SHORT_FRAME )
6617 info->icount.rxshort++;
6618 else if ( status & RXSTATUS_ABORT )
6619 info->icount.rxabort++;
6620 else if ( status & RXSTATUS_OVERRUN )
6621 info->icount.rxover++;
6623 info->icount.rxcrc++;
6624 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6625 return_frame = true;
6628 #if SYNCLINK_GENERIC_HDLC
6630 info->netdev->stats.rx_errors++;
6631 info->netdev->stats.rx_frame_errors++;
6635 return_frame = true;
6637 if ( return_frame ) {
6638 /* receive frame has no errors, get frame size.
6639 * The frame size is the starting value of the RCC (which was
6640 * set to 0xffff) minus the ending value of the RCC (decremented
6641 * once for each receive character) minus 2 for the 16-bit CRC.
6644 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6646 /* adjust frame size for CRC if any */
6647 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6649 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6653 if ( debug_level >= DEBUG_LEVEL_BH )
6654 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6655 __FILE__,__LINE__,info->device_name,status,framesize);
6657 if ( debug_level >= DEBUG_LEVEL_DATA )
6658 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6659 min_t(int, framesize, DMABUFFERSIZE),0);
6662 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6663 ((framesize+1) > info->max_frame_size) ) ||
6664 (framesize > info->max_frame_size) )
6665 info->icount.rxlong++;
6667 /* copy dma buffer(s) to contiguous intermediate buffer */
6668 int copy_count = framesize;
6669 int index = StartIndex;
6670 unsigned char *ptmp = info->intermediate_rxbuffer;
6672 if ( !(status & RXSTATUS_CRC_ERROR))
6673 info->icount.rxok++;
6677 if ( copy_count > DMABUFFERSIZE )
6678 partial_count = DMABUFFERSIZE;
6680 partial_count = copy_count;
6682 pBufEntry = &(info->rx_buffer_list[index]);
6683 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6684 ptmp += partial_count;
6685 copy_count -= partial_count;
6687 if ( ++index == info->rx_buffer_count )
6691 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6693 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6697 if ( debug_level >= DEBUG_LEVEL_DATA )
6698 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6699 __FILE__,__LINE__,info->device_name,
6703 #if SYNCLINK_GENERIC_HDLC
6705 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6708 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6711 /* Free the buffers used by this frame. */
6712 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6718 if ( info->rx_enabled && info->rx_overflow ) {
6719 /* The receiver needs to restarted because of
6720 * a receive overflow (buffer or FIFO). If the
6721 * receive buffers are now empty, then restart receiver.
6724 if ( !info->rx_buffer_list[EndIndex].status &&
6725 info->rx_buffer_list[EndIndex].count ) {
6726 spin_lock_irqsave(&info->irq_spinlock,flags);
6727 usc_start_receiver(info);
6728 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6734 } /* end of mgsl_get_rx_frame() */
6736 /* mgsl_get_raw_rx_frame()
6738 * This function attempts to return a received frame from the
6739 * receive DMA buffers when running in external loop mode. In this mode,
6740 * we will return at most one DMABUFFERSIZE frame to the application.
6741 * The USC receiver is triggering off of DCD going active to start a new
6742 * frame, and DCD going inactive to terminate the frame (similar to
6743 * processing a closing flag character).
6745 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6746 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6747 * status field and the RCC field will indicate the length of the
6748 * entire received frame. We take this RCC field and get the modulus
6749 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6750 * last Rx DMA buffer and return that last portion of the frame.
6752 * Arguments: info pointer to device extension
6753 * Return Value: true if frame returned, otherwise false
6755 static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6757 unsigned int CurrentIndex, NextIndex;
6758 unsigned short status;
6759 DMABUFFERENTRY *pBufEntry;
6760 unsigned int framesize = 0;
6761 bool ReturnCode = false;
6762 unsigned long flags;
6763 struct tty_struct *tty = info->port.tty;
6766 * current_rx_buffer points to the 1st buffer of the next available
6767 * receive frame. The status field is set by the 16C32 after
6768 * completing a receive frame. If the status field of this buffer
6769 * is zero, either the USC is still filling this buffer or this
6770 * is one of a series of buffers making up a received frame.
6772 * If the count field of this buffer is zero, the USC is either
6773 * using this buffer or has used this buffer. Look at the count
6774 * field of the next buffer. If that next buffer's count is
6775 * non-zero, the USC is still actively using the current buffer.
6776 * Otherwise, if the next buffer's count field is zero, the
6777 * current buffer is complete and the USC is using the next
6780 CurrentIndex = NextIndex = info->current_rx_buffer;
6782 if ( NextIndex == info->rx_buffer_count )
6785 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6786 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6787 info->rx_buffer_list[NextIndex].count == 0)) {
6789 * Either the status field of this dma buffer is non-zero
6790 * (indicating the last buffer of a receive frame) or the next
6791 * buffer is marked as in use -- implying this buffer is complete
6792 * and an intermediate buffer for this received frame.
6795 status = info->rx_buffer_list[CurrentIndex].status;
6797 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6798 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6799 if ( status & RXSTATUS_SHORT_FRAME )
6800 info->icount.rxshort++;
6801 else if ( status & RXSTATUS_ABORT )
6802 info->icount.rxabort++;
6803 else if ( status & RXSTATUS_OVERRUN )
6804 info->icount.rxover++;
6806 info->icount.rxcrc++;
6810 * A receive frame is available, get frame size and status.
6812 * The frame size is the starting value of the RCC (which was
6813 * set to 0xffff) minus the ending value of the RCC (decremented
6814 * once for each receive character) minus 2 or 4 for the 16-bit
6817 * If the status field is zero, this is an intermediate buffer.
6820 * If the DMA Buffer Entry's Status field is non-zero, the
6821 * receive operation completed normally (ie: DCD dropped). The
6822 * RCC field is valid and holds the received frame size.
6823 * It is possible that the RCC field will be zero on a DMA buffer
6824 * entry with a non-zero status. This can occur if the total
6825 * frame size (number of bytes between the time DCD goes active
6826 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6827 * case the 16C32 has underrun on the RCC count and appears to
6828 * stop updating this counter to let us know the actual received
6829 * frame size. If this happens (non-zero status and zero RCC),
6830 * simply return the entire RxDMA Buffer
6834 * In the event that the final RxDMA Buffer is
6835 * terminated with a non-zero status and the RCC
6836 * field is zero, we interpret this as the RCC
6837 * having underflowed (received frame > 65535 bytes).
6839 * Signal the event to the user by passing back
6840 * a status of RxStatus_CrcError returning the full
6841 * buffer and let the app figure out what data is
6844 if ( info->rx_buffer_list[CurrentIndex].rcc )
6845 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6847 framesize = DMABUFFERSIZE;
6850 framesize = DMABUFFERSIZE;
6853 if ( framesize > DMABUFFERSIZE ) {
6855 * if running in raw sync mode, ISR handler for
6856 * End Of Buffer events terminates all buffers at 4K.
6857 * If this frame size is said to be >4K, get the
6858 * actual number of bytes of the frame in this buffer.
6860 framesize = framesize % DMABUFFERSIZE;
6864 if ( debug_level >= DEBUG_LEVEL_BH )
6865 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6866 __FILE__,__LINE__,info->device_name,status,framesize);
6868 if ( debug_level >= DEBUG_LEVEL_DATA )
6869 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6870 min_t(int, framesize, DMABUFFERSIZE),0);
6873 /* copy dma buffer(s) to contiguous intermediate buffer */
6874 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6876 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6877 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6878 info->icount.rxok++;
6880 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6883 /* Free the buffers used by this frame. */
6884 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6890 if ( info->rx_enabled && info->rx_overflow ) {
6891 /* The receiver needs to restarted because of
6892 * a receive overflow (buffer or FIFO). If the
6893 * receive buffers are now empty, then restart receiver.
6896 if ( !info->rx_buffer_list[CurrentIndex].status &&
6897 info->rx_buffer_list[CurrentIndex].count ) {
6898 spin_lock_irqsave(&info->irq_spinlock,flags);
6899 usc_start_receiver(info);
6900 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6906 } /* end of mgsl_get_raw_rx_frame() */
6908 /* mgsl_load_tx_dma_buffer()
6910 * Load the transmit DMA buffer with the specified data.
6914 * info pointer to device extension
6915 * Buffer pointer to buffer containing frame to load
6916 * BufferSize size in bytes of frame in Buffer
6918 * Return Value: None
6920 static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6921 const char *Buffer, unsigned int BufferSize)
6923 unsigned short Copycount;
6925 DMABUFFERENTRY *pBufEntry;
6927 if ( debug_level >= DEBUG_LEVEL_DATA )
6928 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6930 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6931 /* set CMR:13 to start transmit when
6932 * next GoAhead (abort) is received
6934 info->cmr_value |= BIT13;
6937 /* begin loading the frame in the next available tx dma
6938 * buffer, remember it's starting location for setting
6939 * up tx dma operation
6941 i = info->current_tx_buffer;
6942 info->start_tx_dma_buffer = i;
6944 /* Setup the status and RCC (Frame Size) fields of the 1st */
6945 /* buffer entry in the transmit DMA buffer list. */
6947 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6948 info->tx_buffer_list[i].rcc = BufferSize;
6949 info->tx_buffer_list[i].count = BufferSize;
6951 /* Copy frame data from 1st source buffer to the DMA buffers. */
6952 /* The frame data may span multiple DMA buffers. */
6954 while( BufferSize ){
6955 /* Get a pointer to next DMA buffer entry. */
6956 pBufEntry = &info->tx_buffer_list[i++];
6958 if ( i == info->tx_buffer_count )
6961 /* Calculate the number of bytes that can be copied from */
6962 /* the source buffer to this DMA buffer. */
6963 if ( BufferSize > DMABUFFERSIZE )
6964 Copycount = DMABUFFERSIZE;
6966 Copycount = BufferSize;
6968 /* Actually copy data from source buffer to DMA buffer. */
6969 /* Also set the data count for this individual DMA buffer. */
6970 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6971 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6973 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6975 pBufEntry->count = Copycount;
6977 /* Advance source pointer and reduce remaining data count. */
6978 Buffer += Copycount;
6979 BufferSize -= Copycount;
6981 ++info->tx_dma_buffers_used;
6984 /* remember next available tx dma buffer */
6985 info->current_tx_buffer = i;
6987 } /* end of mgsl_load_tx_dma_buffer() */
6990 * mgsl_register_test()
6992 * Performs a register test of the 16C32.
6994 * Arguments: info pointer to device instance data
6995 * Return Value: true if test passed, otherwise false
6997 static bool mgsl_register_test( struct mgsl_struct *info )
6999 static unsigned short BitPatterns[] =
7000 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7001 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
7004 unsigned long flags;
7006 spin_lock_irqsave(&info->irq_spinlock,flags);
7009 /* Verify the reset state of some registers. */
7011 if ( (usc_InReg( info, SICR ) != 0) ||
7012 (usc_InReg( info, IVR ) != 0) ||
7013 (usc_InDmaReg( info, DIVR ) != 0) ){
7018 /* Write bit patterns to various registers but do it out of */
7019 /* sync, then read back and verify values. */
7021 for ( i = 0 ; i < Patterncount ; i++ ) {
7022 usc_OutReg( info, TC0R, BitPatterns[i] );
7023 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
7024 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
7025 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
7026 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
7027 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7029 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7030 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7031 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7032 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7033 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7034 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7042 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7046 } /* end of mgsl_register_test() */
7048 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7050 * Arguments: info pointer to device instance data
7051 * Return Value: true if test passed, otherwise false
7053 static bool mgsl_irq_test( struct mgsl_struct *info )
7055 unsigned long EndTime;
7056 unsigned long flags;
7058 spin_lock_irqsave(&info->irq_spinlock,flags);
7062 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7063 * The ISR sets irq_occurred to true.
7066 info->irq_occurred = false;
7068 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7069 /* Enable INTEN (Port 6, Bit12) */
7070 /* This connects the IRQ request signal to the ISA bus */
7071 /* on the ISA adapter. This has no effect for the PCI adapter */
7072 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7074 usc_EnableMasterIrqBit(info);
7075 usc_EnableInterrupts(info, IO_PIN);
7076 usc_ClearIrqPendingBits(info, IO_PIN);
7078 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7079 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7081 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7084 while( EndTime-- && !info->irq_occurred ) {
7085 msleep_interruptible(10);
7088 spin_lock_irqsave(&info->irq_spinlock,flags);
7090 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7092 return info->irq_occurred;
7094 } /* end of mgsl_irq_test() */
7098 * Perform a DMA test of the 16C32. A small frame is
7099 * transmitted via DMA from a transmit buffer to a receive buffer
7100 * using single buffer DMA mode.
7102 * Arguments: info pointer to device instance data
7103 * Return Value: true if test passed, otherwise false
7105 static bool mgsl_dma_test( struct mgsl_struct *info )
7107 unsigned short FifoLevel;
7108 unsigned long phys_addr;
7109 unsigned int FrameSize;
7113 unsigned short status=0;
7114 unsigned long EndTime;
7115 unsigned long flags;
7116 MGSL_PARAMS tmp_params;
7118 /* save current port options */
7119 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7120 /* load default port options */
7121 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7123 #define TESTFRAMESIZE 40
7125 spin_lock_irqsave(&info->irq_spinlock,flags);
7127 /* setup 16C32 for SDLC DMA transfer mode */
7130 usc_set_sdlc_mode(info);
7131 usc_enable_loopback(info,1);
7133 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7134 * field of the buffer entry after fetching buffer address. This
7135 * way we can detect a DMA failure for a DMA read (which should be
7136 * non-destructive to system memory) before we try and write to
7137 * memory (where a failure could corrupt system memory).
7140 /* Receive DMA mode Register (RDMR)
7142 * <15..14> 11 DMA mode = Linked List Buffer mode
7143 * <13> 1 RSBinA/L = store Rx status Block in List entry
7144 * <12> 0 1 = Clear count of List Entry after fetching
7145 * <11..10> 00 Address mode = Increment
7146 * <9> 1 Terminate Buffer on RxBound
7147 * <8> 0 Bus Width = 16bits
7148 * <7..0> ? status Bits (write as 0s)
7150 * 1110 0010 0000 0000 = 0xe200
7153 usc_OutDmaReg( info, RDMR, 0xe200 );
7155 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7158 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7160 FrameSize = TESTFRAMESIZE;
7162 /* setup 1st transmit buffer entry: */
7163 /* with frame size and transmit control word */
7165 info->tx_buffer_list[0].count = FrameSize;
7166 info->tx_buffer_list[0].rcc = FrameSize;
7167 info->tx_buffer_list[0].status = 0x4000;
7169 /* build a transmit frame in 1st transmit DMA buffer */
7171 TmpPtr = info->tx_buffer_list[0].virt_addr;
7172 for (i = 0; i < FrameSize; i++ )
7175 /* setup 1st receive buffer entry: */
7176 /* clear status, set max receive buffer size */
7178 info->rx_buffer_list[0].status = 0;
7179 info->rx_buffer_list[0].count = FrameSize + 4;
7181 /* zero out the 1st receive buffer */
7183 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7185 /* Set count field of next buffer entries to prevent */
7186 /* 16C32 from using buffers after the 1st one. */
7188 info->tx_buffer_list[1].count = 0;
7189 info->rx_buffer_list[1].count = 0;
7192 /***************************/
7193 /* Program 16C32 receiver. */
7194 /***************************/
7196 spin_lock_irqsave(&info->irq_spinlock,flags);
7198 /* setup DMA transfers */
7199 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7201 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7202 phys_addr = info->rx_buffer_list[0].phys_entry;
7203 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7204 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7206 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7207 usc_InDmaReg( info, RDMR );
7208 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7210 /* Enable Receiver (RMR <1..0> = 10) */
7211 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7213 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7216 /*************************************************************/
7217 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7218 /*************************************************************/
7220 /* Wait 100ms for interrupt. */
7221 EndTime = jiffies + msecs_to_jiffies(100);
7224 if (time_after(jiffies, EndTime)) {
7229 spin_lock_irqsave(&info->irq_spinlock,flags);
7230 status = usc_InDmaReg( info, RDMR );
7231 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7233 if ( !(status & BIT4) && (status & BIT5) ) {
7234 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7235 /* BUSY (BIT 5) is active (channel still active). */
7236 /* This means the buffer entry read has completed. */
7242 /******************************/
7243 /* Program 16C32 transmitter. */
7244 /******************************/
7246 spin_lock_irqsave(&info->irq_spinlock,flags);
7248 /* Program the Transmit Character Length Register (TCLR) */
7249 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7251 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7252 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7254 /* Program the address of the 1st DMA Buffer Entry in linked list */
7256 phys_addr = info->tx_buffer_list[0].phys_entry;
7257 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7258 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7260 /* unlatch Tx status bits, and start transmit channel. */
7262 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7263 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7265 /* wait for DMA controller to fill transmit FIFO */
7267 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7269 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7272 /**********************************/
7273 /* WAIT FOR TRANSMIT FIFO TO FILL */
7274 /**********************************/
7277 EndTime = jiffies + msecs_to_jiffies(100);
7280 if (time_after(jiffies, EndTime)) {
7285 spin_lock_irqsave(&info->irq_spinlock,flags);
7286 FifoLevel = usc_InReg(info, TICR) >> 8;
7287 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7289 if ( FifoLevel < 16 )
7292 if ( FrameSize < 32 ) {
7293 /* This frame is smaller than the entire transmit FIFO */
7294 /* so wait for the entire frame to be loaded. */
7295 if ( FifoLevel <= (32 - FrameSize) )
7303 /* Enable 16C32 transmitter. */
7305 spin_lock_irqsave(&info->irq_spinlock,flags);
7307 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7308 usc_TCmd( info, TCmd_SendFrame );
7309 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7311 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7314 /******************************/
7315 /* WAIT FOR TRANSMIT COMPLETE */
7316 /******************************/
7319 EndTime = jiffies + msecs_to_jiffies(100);
7321 /* While timer not expired wait for transmit complete */
7323 spin_lock_irqsave(&info->irq_spinlock,flags);
7324 status = usc_InReg( info, TCSR );
7325 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7327 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7328 if (time_after(jiffies, EndTime)) {
7333 spin_lock_irqsave(&info->irq_spinlock,flags);
7334 status = usc_InReg( info, TCSR );
7335 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7341 /* CHECK FOR TRANSMIT ERRORS */
7342 if ( status & (BIT5 + BIT1) )
7347 /* WAIT FOR RECEIVE COMPLETE */
7350 EndTime = jiffies + msecs_to_jiffies(100);
7352 /* Wait for 16C32 to write receive status to buffer entry. */
7353 status=info->rx_buffer_list[0].status;
7354 while ( status == 0 ) {
7355 if (time_after(jiffies, EndTime)) {
7359 status=info->rx_buffer_list[0].status;
7365 /* CHECK FOR RECEIVE ERRORS */
7366 status = info->rx_buffer_list[0].status;
7368 if ( status & (BIT8 + BIT3 + BIT1) ) {
7369 /* receive error has occurred */
7372 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7373 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7379 spin_lock_irqsave(&info->irq_spinlock,flags);
7381 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7383 /* restore current port options */
7384 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7388 } /* end of mgsl_dma_test() */
7390 /* mgsl_adapter_test()
7392 * Perform the register, IRQ, and DMA tests for the 16C32.
7394 * Arguments: info pointer to device instance data
7395 * Return Value: 0 if success, otherwise -ENODEV
7397 static int mgsl_adapter_test( struct mgsl_struct *info )
7399 if ( debug_level >= DEBUG_LEVEL_INFO )
7400 printk( "%s(%d):Testing device %s\n",
7401 __FILE__,__LINE__,info->device_name );
7403 if ( !mgsl_register_test( info ) ) {
7404 info->init_error = DiagStatus_AddressFailure;
7405 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7406 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7410 if ( !mgsl_irq_test( info ) ) {
7411 info->init_error = DiagStatus_IrqFailure;
7412 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7413 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7417 if ( !mgsl_dma_test( info ) ) {
7418 info->init_error = DiagStatus_DmaFailure;
7419 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7420 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7424 if ( debug_level >= DEBUG_LEVEL_INFO )
7425 printk( "%s(%d):device %s passed diagnostics\n",
7426 __FILE__,__LINE__,info->device_name );
7430 } /* end of mgsl_adapter_test() */
7432 /* mgsl_memory_test()
7434 * Test the shared memory on a PCI adapter.
7436 * Arguments: info pointer to device instance data
7437 * Return Value: true if test passed, otherwise false
7439 static bool mgsl_memory_test( struct mgsl_struct *info )
7441 static unsigned long BitPatterns[] =
7442 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7443 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7445 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7446 unsigned long * TestAddr;
7448 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7451 TestAddr = (unsigned long *)info->memory_base;
7453 /* Test data lines with test pattern at one location. */
7455 for ( i = 0 ; i < Patterncount ; i++ ) {
7456 *TestAddr = BitPatterns[i];
7457 if ( *TestAddr != BitPatterns[i] )
7461 /* Test address lines with incrementing pattern over */
7462 /* entire address range. */
7464 for ( i = 0 ; i < TestLimit ; i++ ) {
7469 TestAddr = (unsigned long *)info->memory_base;
7471 for ( i = 0 ; i < TestLimit ; i++ ) {
7472 if ( *TestAddr != i * 4 )
7477 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7481 } /* End Of mgsl_memory_test() */
7484 /* mgsl_load_pci_memory()
7486 * Load a large block of data into the PCI shared memory.
7487 * Use this instead of memcpy() or memmove() to move data
7488 * into the PCI shared memory.
7492 * This function prevents the PCI9050 interface chip from hogging
7493 * the adapter local bus, which can starve the 16C32 by preventing
7494 * 16C32 bus master cycles.
7496 * The PCI9050 documentation says that the 9050 will always release
7497 * control of the local bus after completing the current read
7498 * or write operation.
7500 * It appears that as long as the PCI9050 write FIFO is full, the
7501 * PCI9050 treats all of the writes as a single burst transaction
7502 * and will not release the bus. This causes DMA latency problems
7503 * at high speeds when copying large data blocks to the shared
7506 * This function in effect, breaks the a large shared memory write
7507 * into multiple transations by interleaving a shared memory read
7508 * which will flush the write FIFO and 'complete' the write
7509 * transation. This allows any pending DMA request to gain control
7510 * of the local bus in a timely fasion.
7514 * TargetPtr pointer to target address in PCI shared memory
7515 * SourcePtr pointer to source buffer for data
7516 * count count in bytes of data to copy
7518 * Return Value: None
7520 static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7521 unsigned short count )
7523 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7524 #define PCI_LOAD_INTERVAL 64
7526 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7527 unsigned short Index;
7528 unsigned long Dummy;
7530 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7532 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7533 Dummy = *((volatile unsigned long *)TargetPtr);
7534 TargetPtr += PCI_LOAD_INTERVAL;
7535 SourcePtr += PCI_LOAD_INTERVAL;
7538 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7540 } /* End Of mgsl_load_pci_memory() */
7542 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7547 printk("%s tx data:\n",info->device_name);
7549 printk("%s rx data:\n",info->device_name);
7557 for(i=0;i<linecount;i++)
7558 printk("%02X ",(unsigned char)data[i]);
7561 for(i=0;i<linecount;i++) {
7562 if (data[i]>=040 && data[i]<=0176)
7563 printk("%c",data[i]);
7572 } /* end of mgsl_trace_block() */
7574 /* mgsl_tx_timeout()
7576 * called when HDLC frame times out
7577 * update stats and do tx completion processing
7579 * Arguments: context pointer to device instance data
7580 * Return Value: None
7582 static void mgsl_tx_timeout(unsigned long context)
7584 struct mgsl_struct *info = (struct mgsl_struct*)context;
7585 unsigned long flags;
7587 if ( debug_level >= DEBUG_LEVEL_INFO )
7588 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7589 __FILE__,__LINE__,info->device_name);
7590 if(info->tx_active &&
7591 (info->params.mode == MGSL_MODE_HDLC ||
7592 info->params.mode == MGSL_MODE_RAW) ) {
7593 info->icount.txtimeout++;
7595 spin_lock_irqsave(&info->irq_spinlock,flags);
7596 info->tx_active = false;
7597 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7599 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7600 usc_loopmode_cancel_transmit( info );
7602 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7604 #if SYNCLINK_GENERIC_HDLC
7606 hdlcdev_tx_done(info);
7609 mgsl_bh_transmit(info);
7611 } /* end of mgsl_tx_timeout() */
7613 /* signal that there are no more frames to send, so that
7614 * line is 'released' by echoing RxD to TxD when current
7615 * transmission is complete (or immediately if no tx in progress).
7617 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7619 unsigned long flags;
7621 spin_lock_irqsave(&info->irq_spinlock,flags);
7622 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7623 if (info->tx_active)
7624 info->loopmode_send_done_requested = true;
7626 usc_loopmode_send_done(info);
7628 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7633 /* release the line by echoing RxD to TxD
7634 * upon completion of a transmit frame
7636 static void usc_loopmode_send_done( struct mgsl_struct * info )
7638 info->loopmode_send_done_requested = false;
7639 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7640 info->cmr_value &= ~BIT13;
7641 usc_OutReg(info, CMR, info->cmr_value);
7644 /* abort a transmit in progress while in HDLC LoopMode
7646 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7648 /* reset tx dma channel and purge TxFifo */
7649 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7650 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7651 usc_loopmode_send_done( info );
7654 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7655 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7656 * we must clear CMR:13 to begin repeating TxData to RxData
7658 static void usc_loopmode_insert_request( struct mgsl_struct * info )
7660 info->loopmode_insert_requested = true;
7662 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7663 * begin repeating TxData on RxData (complete insertion)
7665 usc_OutReg( info, RICR,
7666 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7668 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7669 info->cmr_value |= BIT13;
7670 usc_OutReg(info, CMR, info->cmr_value);
7673 /* return 1 if station is inserted into the loop, otherwise 0
7675 static int usc_loopmode_active( struct mgsl_struct * info)
7677 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7680 #if SYNCLINK_GENERIC_HDLC
7683 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7684 * set encoding and frame check sequence (FCS) options
7686 * dev pointer to network device structure
7687 * encoding serial encoding setting
7688 * parity FCS setting
7690 * returns 0 if success, otherwise error code
7692 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7693 unsigned short parity)
7695 struct mgsl_struct *info = dev_to_port(dev);
7696 unsigned char new_encoding;
7697 unsigned short new_crctype;
7699 /* return error if TTY interface open */
7700 if (info->port.count)
7705 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7706 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7707 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7708 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7709 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7710 default: return -EINVAL;
7715 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7716 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7717 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7718 default: return -EINVAL;
7721 info->params.encoding = new_encoding;
7722 info->params.crc_type = new_crctype;
7724 /* if network interface up, reprogram hardware */
7726 mgsl_program_hw(info);
7732 * called by generic HDLC layer to send frame
7734 * skb socket buffer containing HDLC frame
7735 * dev pointer to network device structure
7737 * returns 0 if success, otherwise error code
7739 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
7741 struct mgsl_struct *info = dev_to_port(dev);
7742 unsigned long flags;
7744 if (debug_level >= DEBUG_LEVEL_INFO)
7745 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7747 /* stop sending until this frame completes */
7748 netif_stop_queue(dev);
7750 /* copy data to device buffers */
7751 info->xmit_cnt = skb->len;
7752 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7754 /* update network statistics */
7755 dev->stats.tx_packets++;
7756 dev->stats.tx_bytes += skb->len;
7758 /* done with socket buffer, so free it */
7761 /* save start time for transmit timeout detection */
7762 dev->trans_start = jiffies;
7764 /* start hardware transmitter if necessary */
7765 spin_lock_irqsave(&info->irq_spinlock,flags);
7766 if (!info->tx_active)
7767 usc_start_transmitter(info);
7768 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7774 * called by network layer when interface enabled
7775 * claim resources and initialize hardware
7777 * dev pointer to network device structure
7779 * returns 0 if success, otherwise error code
7781 static int hdlcdev_open(struct net_device *dev)
7783 struct mgsl_struct *info = dev_to_port(dev);
7785 unsigned long flags;
7787 if (debug_level >= DEBUG_LEVEL_INFO)
7788 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7790 /* generic HDLC layer open processing */
7791 if ((rc = hdlc_open(dev)))
7794 /* arbitrate between network and tty opens */
7795 spin_lock_irqsave(&info->netlock, flags);
7796 if (info->port.count != 0 || info->netcount != 0) {
7797 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7798 spin_unlock_irqrestore(&info->netlock, flags);
7802 spin_unlock_irqrestore(&info->netlock, flags);
7804 /* claim resources and init adapter */
7805 if ((rc = startup(info)) != 0) {
7806 spin_lock_irqsave(&info->netlock, flags);
7808 spin_unlock_irqrestore(&info->netlock, flags);
7812 /* assert DTR and RTS, apply hardware settings */
7813 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7814 mgsl_program_hw(info);
7816 /* enable network layer transmit */
7817 dev->trans_start = jiffies;
7818 netif_start_queue(dev);
7820 /* inform generic HDLC layer of current DCD status */
7821 spin_lock_irqsave(&info->irq_spinlock, flags);
7822 usc_get_serial_signals(info);
7823 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7824 if (info->serial_signals & SerialSignal_DCD)
7825 netif_carrier_on(dev);
7827 netif_carrier_off(dev);
7832 * called by network layer when interface is disabled
7833 * shutdown hardware and release resources
7835 * dev pointer to network device structure
7837 * returns 0 if success, otherwise error code
7839 static int hdlcdev_close(struct net_device *dev)
7841 struct mgsl_struct *info = dev_to_port(dev);
7842 unsigned long flags;
7844 if (debug_level >= DEBUG_LEVEL_INFO)
7845 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7847 netif_stop_queue(dev);
7849 /* shutdown adapter and release resources */
7854 spin_lock_irqsave(&info->netlock, flags);
7856 spin_unlock_irqrestore(&info->netlock, flags);
7862 * called by network layer to process IOCTL call to network device
7864 * dev pointer to network device structure
7865 * ifr pointer to network interface request structure
7866 * cmd IOCTL command code
7868 * returns 0 if success, otherwise error code
7870 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7872 const size_t size = sizeof(sync_serial_settings);
7873 sync_serial_settings new_line;
7874 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7875 struct mgsl_struct *info = dev_to_port(dev);
7878 if (debug_level >= DEBUG_LEVEL_INFO)
7879 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7881 /* return error if TTY interface open */
7882 if (info->port.count)
7885 if (cmd != SIOCWANDEV)
7886 return hdlc_ioctl(dev, ifr, cmd);
7888 switch(ifr->ifr_settings.type) {
7889 case IF_GET_IFACE: /* return current sync_serial_settings */
7891 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7892 if (ifr->ifr_settings.size < size) {
7893 ifr->ifr_settings.size = size; /* data size wanted */
7897 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7898 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7899 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7900 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7903 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7904 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7905 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7906 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7907 default: new_line.clock_type = CLOCK_DEFAULT;
7910 new_line.clock_rate = info->params.clock_speed;
7911 new_line.loopback = info->params.loopback ? 1:0;
7913 if (copy_to_user(line, &new_line, size))
7917 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7919 if(!capable(CAP_NET_ADMIN))
7921 if (copy_from_user(&new_line, line, size))
7924 switch (new_line.clock_type)
7926 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7927 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7928 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7929 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7930 case CLOCK_DEFAULT: flags = info->params.flags &
7931 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7932 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7933 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7934 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7935 default: return -EINVAL;
7938 if (new_line.loopback != 0 && new_line.loopback != 1)
7941 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7942 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7943 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7944 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7945 info->params.flags |= flags;
7947 info->params.loopback = new_line.loopback;
7949 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7950 info->params.clock_speed = new_line.clock_rate;
7952 info->params.clock_speed = 0;
7954 /* if network interface up, reprogram hardware */
7956 mgsl_program_hw(info);
7960 return hdlc_ioctl(dev, ifr, cmd);
7965 * called by network layer when transmit timeout is detected
7967 * dev pointer to network device structure
7969 static void hdlcdev_tx_timeout(struct net_device *dev)
7971 struct mgsl_struct *info = dev_to_port(dev);
7972 unsigned long flags;
7974 if (debug_level >= DEBUG_LEVEL_INFO)
7975 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7977 dev->stats.tx_errors++;
7978 dev->stats.tx_aborted_errors++;
7980 spin_lock_irqsave(&info->irq_spinlock,flags);
7981 usc_stop_transmitter(info);
7982 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7984 netif_wake_queue(dev);
7988 * called by device driver when transmit completes
7989 * reenable network layer transmit if stopped
7991 * info pointer to device instance information
7993 static void hdlcdev_tx_done(struct mgsl_struct *info)
7995 if (netif_queue_stopped(info->netdev))
7996 netif_wake_queue(info->netdev);
8000 * called by device driver when frame received
8001 * pass frame to network layer
8003 * info pointer to device instance information
8004 * buf pointer to buffer contianing frame data
8005 * size count of data bytes in buf
8007 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
8009 struct sk_buff *skb = dev_alloc_skb(size);
8010 struct net_device *dev = info->netdev;
8012 if (debug_level >= DEBUG_LEVEL_INFO)
8013 printk("hdlcdev_rx(%s)\n", dev->name);
8016 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
8018 dev->stats.rx_dropped++;
8022 memcpy(skb_put(skb, size), buf, size);
8024 skb->protocol = hdlc_type_trans(skb, dev);
8026 dev->stats.rx_packets++;
8027 dev->stats.rx_bytes += size;
8031 dev->last_rx = jiffies;
8035 * called by device driver when adding device instance
8036 * do generic HDLC initialization
8038 * info pointer to device instance information
8040 * returns 0 if success, otherwise error code
8042 static int hdlcdev_init(struct mgsl_struct *info)
8045 struct net_device *dev;
8048 /* allocate and initialize network and HDLC layer objects */
8050 if (!(dev = alloc_hdlcdev(info))) {
8051 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8055 /* for network layer reporting purposes only */
8056 dev->base_addr = info->io_base;
8057 dev->irq = info->irq_level;
8058 dev->dma = info->dma_level;
8060 /* network layer callbacks and settings */
8061 dev->do_ioctl = hdlcdev_ioctl;
8062 dev->open = hdlcdev_open;
8063 dev->stop = hdlcdev_close;
8064 dev->tx_timeout = hdlcdev_tx_timeout;
8065 dev->watchdog_timeo = 10*HZ;
8066 dev->tx_queue_len = 50;
8068 /* generic HDLC layer callbacks and settings */
8069 hdlc = dev_to_hdlc(dev);
8070 hdlc->attach = hdlcdev_attach;
8071 hdlc->xmit = hdlcdev_xmit;
8073 /* register objects with HDLC layer */
8074 if ((rc = register_hdlc_device(dev))) {
8075 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8085 * called by device driver when removing device instance
8086 * do generic HDLC cleanup
8088 * info pointer to device instance information
8090 static void hdlcdev_exit(struct mgsl_struct *info)
8092 unregister_hdlc_device(info->netdev);
8093 free_netdev(info->netdev);
8094 info->netdev = NULL;
8097 #endif /* CONFIG_HDLC */
8100 static int __devinit synclink_init_one (struct pci_dev *dev,
8101 const struct pci_device_id *ent)
8103 struct mgsl_struct *info;
8105 if (pci_enable_device(dev)) {
8106 printk("error enabling pci device %p\n", dev);
8110 if (!(info = mgsl_allocate_device())) {
8111 printk("can't allocate device instance data.\n");
8115 /* Copy user configuration info to device instance data */
8117 info->io_base = pci_resource_start(dev, 2);
8118 info->irq_level = dev->irq;
8119 info->phys_memory_base = pci_resource_start(dev, 3);
8121 /* Because veremap only works on page boundaries we must map
8122 * a larger area than is actually implemented for the LCR
8123 * memory range. We map a full page starting at the page boundary.
8125 info->phys_lcr_base = pci_resource_start(dev, 0);
8126 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8127 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8129 info->bus_type = MGSL_BUS_TYPE_PCI;
8130 info->io_addr_size = 8;
8131 info->irq_flags = IRQF_SHARED;
8133 if (dev->device == 0x0210) {
8134 /* Version 1 PCI9030 based universal PCI adapter */
8135 info->misc_ctrl_value = 0x007c4080;
8136 info->hw_version = 1;
8138 /* Version 0 PCI9050 based 5V PCI adapter
8139 * A PCI9050 bug prevents reading LCR registers if
8140 * LCR base address bit 7 is set. Maintain shadow
8141 * value so we can write to LCR misc control reg.
8143 info->misc_ctrl_value = 0x087e4546;
8144 info->hw_version = 0;
8147 mgsl_add_device(info);
8152 static void __devexit synclink_remove_one (struct pci_dev *dev)