2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #ifdef PCI_NUM_RESOURCES
44 #define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start)
46 #define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r])
49 #define ROCKET_PARANOIA_CHECK
50 #define ROCKET_DISABLE_SIMUSAGE
52 #undef ROCKET_SOFT_FLOW
53 #undef ROCKET_DEBUG_OPEN
54 #undef ROCKET_DEBUG_INTR
55 #undef ROCKET_DEBUG_WRITE
56 #undef ROCKET_DEBUG_FLOW
57 #undef ROCKET_DEBUG_THROTTLE
58 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
59 #undef ROCKET_DEBUG_RECEIVE
60 #undef ROCKET_DEBUG_HANGUP
62 #undef ROCKET_DEBUG_IO
64 #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
66 /****** Kernel includes ******/
68 #include <linux/module.h>
69 #include <linux/errno.h>
70 #include <linux/major.h>
71 #include <linux/kernel.h>
72 #include <linux/signal.h>
73 #include <linux/slab.h>
75 #include <linux/sched.h>
76 #include <linux/timer.h>
77 #include <linux/interrupt.h>
78 #include <linux/tty.h>
79 #include <linux/tty_driver.h>
80 #include <linux/tty_flip.h>
81 #include <linux/string.h>
82 #include <linux/fcntl.h>
83 #include <linux/ptrace.h>
84 #include <linux/ioport.h>
85 #include <linux/delay.h>
86 #include <linux/wait.h>
87 #include <linux/pci.h>
88 #include <asm/uaccess.h>
89 #include <asm/atomic.h>
90 #include <linux/bitops.h>
91 #include <linux/spinlock.h>
92 #include <asm/semaphore.h>
93 #include <linux/init.h>
95 /****** RocketPort includes ******/
97 #include "rocket_int.h"
100 #define ROCKET_VERSION "2.09"
101 #define ROCKET_DATE "12-June-2003"
103 /****** RocketPort Local Variables ******/
105 static void rp_do_poll(unsigned long dummy);
107 static struct tty_driver *rocket_driver;
109 static struct rocket_version driver_version = {
110 ROCKET_VERSION, ROCKET_DATE
113 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
114 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
115 /* eg. Bit 0 indicates port 0 has xmit data, ... */
116 static atomic_t rp_num_ports_open; /* Number of serial ports open */
117 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
119 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
120 static unsigned long board2;
121 static unsigned long board3;
122 static unsigned long board4;
123 static unsigned long controller;
124 static int support_low_speed;
125 static unsigned long modem1;
126 static unsigned long modem2;
127 static unsigned long modem3;
128 static unsigned long modem4;
129 static unsigned long pc104_1[8];
130 static unsigned long pc104_2[8];
131 static unsigned long pc104_3[8];
132 static unsigned long pc104_4[8];
133 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
135 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
136 static unsigned long rcktpt_io_addr[NUM_BOARDS];
137 static int rcktpt_type[NUM_BOARDS];
138 static int is_PCI[NUM_BOARDS];
139 static rocketModel_t rocketModel[NUM_BOARDS];
140 static int max_board;
143 * The following arrays define the interrupt bits corresponding to each AIOP.
144 * These bits are different between the ISA and regular PCI boards and the
145 * Universal PCI boards.
148 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
155 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
156 UPCI_AIOP_INTR_BIT_0,
157 UPCI_AIOP_INTR_BIT_1,
158 UPCI_AIOP_INTR_BIT_2,
162 static Byte_t RData[RDATASIZE] = {
163 0x00, 0x09, 0xf6, 0x82,
164 0x02, 0x09, 0x86, 0xfb,
165 0x04, 0x09, 0x00, 0x0a,
166 0x06, 0x09, 0x01, 0x0a,
167 0x08, 0x09, 0x8a, 0x13,
168 0x0a, 0x09, 0xc5, 0x11,
169 0x0c, 0x09, 0x86, 0x85,
170 0x0e, 0x09, 0x20, 0x0a,
171 0x10, 0x09, 0x21, 0x0a,
172 0x12, 0x09, 0x41, 0xff,
173 0x14, 0x09, 0x82, 0x00,
174 0x16, 0x09, 0x82, 0x7b,
175 0x18, 0x09, 0x8a, 0x7d,
176 0x1a, 0x09, 0x88, 0x81,
177 0x1c, 0x09, 0x86, 0x7a,
178 0x1e, 0x09, 0x84, 0x81,
179 0x20, 0x09, 0x82, 0x7c,
180 0x22, 0x09, 0x0a, 0x0a
183 static Byte_t RRegData[RREGDATASIZE] = {
184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
199 static CONTROLLER_T sController[CTL_SIZE] = {
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
210 static Byte_t sBitMapClrTbl[8] = {
211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
214 static Byte_t sBitMapSetTbl[8] = {
215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
218 static int sClockPrescale = 0x14;
221 * Line number is the ttySIx number (x), the Minor number. We
222 * assign them sequentially, starting at zero. The following
223 * array keeps track of the line number assigned to a given board/aiop/channel.
225 static unsigned char lineNumbers[MAX_RP_PORTS];
226 static unsigned long nextLineNumber;
228 /***** RocketPort Static Prototypes *********/
229 static int __init init_ISA(int i);
230 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231 static void rp_flush_buffer(struct tty_struct *tty);
232 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
233 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
234 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
235 static void rp_start(struct tty_struct *tty);
236 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
238 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
239 static void sFlushRxFIFO(CHANNEL_T * ChP);
240 static void sFlushTxFIFO(CHANNEL_T * ChP);
241 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
242 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
243 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
244 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
245 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
246 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
247 ByteIO_t * AiopIOList, int AiopIOListSize,
248 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
249 int PeriodicOnly, int altChanRingIndicator,
251 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
252 ByteIO_t * AiopIOList, int AiopIOListSize,
253 int IRQNum, Byte_t Frequency, int PeriodicOnly);
254 static int sReadAiopID(ByteIO_t io);
255 static int sReadAiopNumChan(WordIO_t io);
257 MODULE_AUTHOR("Theodore Ts'o");
258 MODULE_DESCRIPTION("Comtrol RocketPort driver");
259 module_param(board1, ulong, 0);
260 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
261 module_param(board2, ulong, 0);
262 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
263 module_param(board3, ulong, 0);
264 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
265 module_param(board4, ulong, 0);
266 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
267 module_param(controller, ulong, 0);
268 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
269 module_param(support_low_speed, bool, 0);
270 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
271 module_param(modem1, ulong, 0);
272 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
273 module_param(modem2, ulong, 0);
274 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
275 module_param(modem3, ulong, 0);
276 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
277 module_param(modem4, ulong, 0);
278 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
279 module_param_array(pc104_1, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
281 module_param_array(pc104_2, ulong, NULL, 0);
282 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
283 module_param_array(pc104_3, ulong, NULL, 0);
284 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
285 module_param_array(pc104_4, ulong, NULL, 0);
286 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
288 static int rp_init(void);
289 static void rp_cleanup_module(void);
291 module_init(rp_init);
292 module_exit(rp_cleanup_module);
295 MODULE_LICENSE("Dual BSD/GPL");
297 /*************************************************************************/
298 /* Module code starts here */
300 static inline int rocket_paranoia_check(struct r_port *info,
303 #ifdef ROCKET_PARANOIA_CHECK
306 if (info->magic != RPORT_MAGIC) {
307 printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n",
316 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
317 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
320 static void rp_do_receive(struct r_port *info,
321 struct tty_struct *tty,
322 CHANNEL_t * cp, unsigned int ChanStatus)
324 unsigned int CharNStat;
325 int ToRecv, wRecv, space;
328 ToRecv = sGetRxCnt(cp);
329 #ifdef ROCKET_DEBUG_INTR
330 printk(KERN_INFO "rp_do_receive(%d)...", ToRecv);
336 * if status indicates there are errored characters in the
337 * FIFO, then enter status mode (a word in FIFO holds
338 * character and status).
340 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
341 if (!(ChanStatus & STATMODE)) {
342 #ifdef ROCKET_DEBUG_RECEIVE
343 printk(KERN_INFO "Entering STATMODE...");
345 ChanStatus |= STATMODE;
351 * if we previously entered status mode, then read down the
352 * FIFO one word at a time, pulling apart the character and
353 * the status. Update error counters depending on status
355 if (ChanStatus & STATMODE) {
356 #ifdef ROCKET_DEBUG_RECEIVE
357 printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask,
358 info->read_status_mask);
363 CharNStat = sInW(sGetTxRxDataIO(cp));
364 #ifdef ROCKET_DEBUG_RECEIVE
365 printk(KERN_INFO "%x...", CharNStat);
367 if (CharNStat & STMBREAKH)
368 CharNStat &= ~(STMFRAMEH | STMPARITYH);
369 if (CharNStat & info->ignore_status_mask) {
373 CharNStat &= info->read_status_mask;
374 if (CharNStat & STMBREAKH)
376 else if (CharNStat & STMPARITYH)
378 else if (CharNStat & STMFRAMEH)
380 else if (CharNStat & STMRCVROVRH)
384 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
389 * after we've emptied the FIFO in status mode, turn
390 * status mode back off
392 if (sGetRxCnt(cp) == 0) {
393 #ifdef ROCKET_DEBUG_RECEIVE
394 printk(KERN_INFO "Status mode off.\n");
396 sDisRxStatusMode(cp);
400 * we aren't in status mode, so read down the FIFO two
401 * characters at time by doing repeated word IO
404 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
405 if (space < ToRecv) {
406 #ifdef ROCKET_DEBUG_RECEIVE
407 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
415 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
417 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
419 /* Push the data up to the tty layer */
420 tty_flip_buffer_push(tty);
424 * Serial port transmit data function. Called from the timer polling loop as a
425 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
426 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
427 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
429 static void rp_do_transmit(struct r_port *info)
432 CHANNEL_t *cp = &info->channel;
433 struct tty_struct *tty;
436 #ifdef ROCKET_DEBUG_INTR
437 printk(KERN_INFO "rp_do_transmit ");
442 printk(KERN_INFO "rp: WARNING rp_do_transmit called with info->tty==NULL\n");
443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
447 spin_lock_irqsave(&info->slock, flags);
449 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
451 /* Loop sending data to FIFO until done or FIFO full */
453 if (tty->stopped || tty->hw_stopped)
455 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
456 if (c <= 0 || info->xmit_fifo_room <= 0)
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
464 info->xmit_fifo_room -= c;
465 #ifdef ROCKET_DEBUG_INTR
466 printk(KERN_INFO "tx %d chars...", c);
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
473 if (info->xmit_cnt < WAKEUP_CHARS) {
475 #ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
480 spin_unlock_irqrestore(&info->slock, flags);
482 #ifdef ROCKET_DEBUG_INTR
483 printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head,
484 info->xmit_tail, info->xmit_fifo_room);
489 * Called when a serial port signals it has read data in it's RX FIFO.
490 * It checks what interrupts are pending and services them, including
491 * receiving serial data.
493 static void rp_handle_port(struct r_port *info)
496 struct tty_struct *tty;
497 unsigned int IntMask, ChanStatus;
502 if ((info->flags & ROCKET_INITIALIZED) == 0) {
503 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n");
507 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n");
513 IntMask = sGetChanIntID(cp) & info->intmask;
514 #ifdef ROCKET_DEBUG_INTR
515 printk(KERN_INFO "rp_interrupt %02x...", IntMask);
517 ChanStatus = sGetChanStatus(cp);
518 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
519 rp_do_receive(info, tty, cp, ChanStatus);
521 if (IntMask & DELTA_CD) { /* CD change */
522 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
523 printk(KERN_INFO "ttyR%d CD now %s...", info->line,
524 (ChanStatus & CD_ACT) ? "on" : "off");
526 if (!(ChanStatus & CD_ACT) && info->cd_status) {
527 #ifdef ROCKET_DEBUG_HANGUP
528 printk(KERN_INFO "CD drop, calling hangup.\n");
532 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
533 wake_up_interruptible(&info->open_wait);
535 #ifdef ROCKET_DEBUG_INTR
536 if (IntMask & DELTA_CTS) { /* CTS change */
537 printk(KERN_INFO "CTS change...\n");
539 if (IntMask & DELTA_DSR) { /* DSR change */
540 printk(KERN_INFO "DSR change...\n");
546 * The top level polling routine. Repeats every 1/100 HZ (10ms).
548 static void rp_do_poll(unsigned long dummy)
551 int ctrl, aiop, ch, line, i;
552 unsigned int xmitmask;
553 unsigned int CtlMask;
554 unsigned char AiopMask;
557 /* Walk through all the boards (ctrl's) */
558 for (ctrl = 0; ctrl < max_board; ctrl++) {
559 if (rcktpt_io_addr[ctrl] <= 0)
562 /* Get a ptr to the board's control struct */
563 ctlp = sCtlNumToCtlPtr(ctrl);
565 /* Get the interupt status from the board */
567 if (ctlp->BusType == isPCI)
568 CtlMask = sPCIGetControllerIntStatus(ctlp);
571 CtlMask = sGetControllerIntStatus(ctlp);
573 /* Check if any AIOP read bits are set */
574 for (aiop = 0; CtlMask; aiop++) {
575 bit = ctlp->AiopIntrBits[aiop];
578 AiopMask = sGetAiopIntStatus(ctlp, aiop);
580 /* Check if any port read bits are set */
581 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
584 /* Get the line number (/dev/ttyRx number). */
585 /* Read the data from the port. */
586 line = GetLineNumber(ctrl, aiop, ch);
587 rp_handle_port(rp_table[line]);
593 xmitmask = xmit_flags[ctrl];
596 * xmit_flags contains bit-significant flags, indicating there is data
597 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
598 * 1, ... (32 total possible). The variable i has the aiop and ch
599 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
602 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
603 if (xmitmask & (1 << i)) {
604 aiop = (i & 0x18) >> 3;
606 line = GetLineNumber(ctrl, aiop, ch);
607 rp_do_transmit(rp_table[line]);
614 * Reset the timer so we get called at the next clock tick (10ms).
616 if (atomic_read(&rp_num_ports_open))
617 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
621 * Initializes the r_port structure for a port, as well as enabling the port on
623 * Inputs: board, aiop, chan numbers
625 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
632 /* Get the next available line number */
633 line = SetLineNumber(board, aiop, chan);
635 ctlp = sCtlNumToCtlPtr(board);
637 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
638 info = kmalloc(sizeof (struct r_port), GFP_KERNEL);
640 printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line);
643 memset(info, 0, sizeof (struct r_port));
645 info->magic = RPORT_MAGIC;
651 info->closing_wait = 3000;
652 info->close_delay = 50;
653 init_waitqueue_head(&info->open_wait);
654 init_waitqueue_head(&info->close_wait);
655 info->flags &= ~ROCKET_MODE_MASK;
656 switch (pc104[board][line]) {
658 info->flags |= ROCKET_MODE_RS422;
661 info->flags |= ROCKET_MODE_RS485;
665 info->flags |= ROCKET_MODE_RS232;
669 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
670 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
671 printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan);
676 rocketMode = info->flags & ROCKET_MODE_MASK;
678 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
679 sEnRTSToggle(&info->channel);
681 sDisRTSToggle(&info->channel);
683 if (ctlp->boardType == ROCKET_TYPE_PC104) {
684 switch (rocketMode) {
685 case ROCKET_MODE_RS485:
686 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
688 case ROCKET_MODE_RS422:
689 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
691 case ROCKET_MODE_RS232:
693 if (info->flags & ROCKET_RTS_TOGGLE)
694 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
696 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
700 spin_lock_init(&info->slock);
701 sema_init(&info->write_sem, 1);
702 rp_table[line] = info;
704 tty_register_device(rocket_driver, line, &pci_dev->dev);
708 * Configures a rocketport port according to its termio settings. Called from
709 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
711 static void configure_r_port(struct r_port *info,
712 struct ktermios *old_termios)
717 int bits, baud, divisor;
720 if (!info->tty || !info->tty->termios)
723 cflag = info->tty->termios->c_cflag;
725 /* Byte size and parity */
726 if ((cflag & CSIZE) == CS8) {
733 if (cflag & CSTOPB) {
740 if (cflag & PARENB) {
743 if (cflag & PARODD) {
753 baud = tty_get_baud_rate(info->tty);
756 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
757 if ((divisor >= 8192 || divisor < 0) && old_termios) {
758 info->tty->termios->c_cflag &= ~CBAUD;
759 info->tty->termios->c_cflag |=
760 (old_termios->c_cflag & CBAUD);
761 baud = tty_get_baud_rate(info->tty);
764 divisor = (rp_baud_base[info->board] / baud) - 1;
766 if (divisor >= 8192 || divisor < 0) {
768 divisor = (rp_baud_base[info->board] / baud) - 1;
770 info->cps = baud / bits;
771 sSetBaud(cp, divisor);
773 if (cflag & CRTSCTS) {
774 info->intmask |= DELTA_CTS;
777 info->intmask &= ~DELTA_CTS;
780 if (cflag & CLOCAL) {
781 info->intmask &= ~DELTA_CD;
783 spin_lock_irqsave(&info->slock, flags);
784 if (sGetChanStatus(cp) & CD_ACT)
788 info->intmask |= DELTA_CD;
789 spin_unlock_irqrestore(&info->slock, flags);
793 * Handle software flow control in the board
795 #ifdef ROCKET_SOFT_FLOW
796 if (I_IXON(info->tty)) {
797 sEnTxSoftFlowCtl(cp);
798 if (I_IXANY(info->tty)) {
803 sSetTxXONChar(cp, START_CHAR(info->tty));
804 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
806 sDisTxSoftFlowCtl(cp);
813 * Set up ignore/read mask words
815 info->read_status_mask = STMRCVROVRH | 0xFF;
816 if (I_INPCK(info->tty))
817 info->read_status_mask |= STMFRAMEH | STMPARITYH;
818 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
819 info->read_status_mask |= STMBREAKH;
822 * Characters to ignore
824 info->ignore_status_mask = 0;
825 if (I_IGNPAR(info->tty))
826 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
827 if (I_IGNBRK(info->tty)) {
828 info->ignore_status_mask |= STMBREAKH;
830 * If we're ignoring parity and break indicators,
831 * ignore overruns too. (For real raw support).
833 if (I_IGNPAR(info->tty))
834 info->ignore_status_mask |= STMRCVROVRH;
837 rocketMode = info->flags & ROCKET_MODE_MASK;
839 if ((info->flags & ROCKET_RTS_TOGGLE)
840 || (rocketMode == ROCKET_MODE_RS485))
845 sSetRTS(&info->channel);
847 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
848 switch (rocketMode) {
849 case ROCKET_MODE_RS485:
850 sSetInterfaceMode(cp, InterfaceModeRS485);
852 case ROCKET_MODE_RS422:
853 sSetInterfaceMode(cp, InterfaceModeRS422);
855 case ROCKET_MODE_RS232:
857 if (info->flags & ROCKET_RTS_TOGGLE)
858 sSetInterfaceMode(cp, InterfaceModeRS232T);
860 sSetInterfaceMode(cp, InterfaceModeRS232);
866 /* info->count is considered critical, protected by spinlocks. */
867 static int block_til_ready(struct tty_struct *tty, struct file *filp,
870 DECLARE_WAITQUEUE(wait, current);
872 int do_clocal = 0, extra_count = 0;
876 * If the device is in the middle of being closed, then block
877 * until it's done, and then try again.
879 if (tty_hung_up_p(filp))
880 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
881 if (info->flags & ROCKET_CLOSING) {
882 interruptible_sleep_on(&info->close_wait);
883 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
887 * If non-blocking mode is set, or the port is not enabled,
888 * then make the check up front and then exit.
890 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
891 info->flags |= ROCKET_NORMAL_ACTIVE;
894 if (tty->termios->c_cflag & CLOCAL)
898 * Block waiting for the carrier detect and the line to become free. While we are in
899 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
900 * We restore it upon exit, either normal or abnormal.
903 add_wait_queue(&info->open_wait, &wait);
904 #ifdef ROCKET_DEBUG_OPEN
905 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
907 spin_lock_irqsave(&info->slock, flags);
909 #ifdef ROCKET_DISABLE_SIMUSAGE
910 info->flags |= ROCKET_NORMAL_ACTIVE;
912 if (!tty_hung_up_p(filp)) {
917 info->blocked_open++;
919 spin_unlock_irqrestore(&info->slock, flags);
922 if (tty->termios->c_cflag & CBAUD) {
923 sSetDTR(&info->channel);
924 sSetRTS(&info->channel);
926 set_current_state(TASK_INTERRUPTIBLE);
927 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
928 if (info->flags & ROCKET_HUP_NOTIFY)
931 retval = -ERESTARTSYS;
934 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
936 if (signal_pending(current)) {
937 retval = -ERESTARTSYS;
940 #ifdef ROCKET_DEBUG_OPEN
941 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
942 info->line, info->count, info->flags);
944 schedule(); /* Don't hold spinlock here, will hang PC */
946 current->state = TASK_RUNNING;
947 remove_wait_queue(&info->open_wait, &wait);
949 spin_lock_irqsave(&info->slock, flags);
953 info->blocked_open--;
955 spin_unlock_irqrestore(&info->slock, flags);
957 #ifdef ROCKET_DEBUG_OPEN
958 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
959 info->line, info->count);
963 info->flags |= ROCKET_NORMAL_ACTIVE;
968 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
969 * port's r_port struct. Initializes the port hardware.
971 static int rp_open(struct tty_struct *tty, struct file *filp)
974 int line = 0, retval;
978 line = TTY_GET_LINE(tty);
979 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
982 page = __get_free_page(GFP_KERNEL);
986 if (info->flags & ROCKET_CLOSING) {
987 interruptible_sleep_on(&info->close_wait);
989 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
993 * We must not sleep from here until the port is marked fully in use.
998 info->xmit_buf = (unsigned char *) page;
1000 tty->driver_data = info;
1003 if (info->count++ == 0) {
1004 atomic_inc(&rp_num_ports_open);
1006 #ifdef ROCKET_DEBUG_OPEN
1007 printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open));
1010 #ifdef ROCKET_DEBUG_OPEN
1011 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1015 * Info->count is now 1; so it's safe to sleep now.
1017 info->session = process_session(current);
1018 info->pgrp = process_group(current);
1020 if ((info->flags & ROCKET_INITIALIZED) == 0) {
1021 cp = &info->channel;
1022 sSetRxTrigger(cp, TRIG_1);
1023 if (sGetChanStatus(cp) & CD_ACT)
1024 info->cd_status = 1;
1026 info->cd_status = 0;
1027 sDisRxStatusMode(cp);
1031 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1032 sSetRxTrigger(cp, TRIG_1);
1035 sDisRxStatusMode(cp);
1039 sDisTxSoftFlowCtl(cp);
1044 info->flags |= ROCKET_INITIALIZED;
1047 * Set up the tty->alt_speed kludge
1049 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1050 info->tty->alt_speed = 57600;
1051 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1052 info->tty->alt_speed = 115200;
1053 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1054 info->tty->alt_speed = 230400;
1055 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1056 info->tty->alt_speed = 460800;
1058 configure_r_port(info, NULL);
1059 if (tty->termios->c_cflag & CBAUD) {
1064 /* Starts (or resets) the maint polling loop */
1065 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1067 retval = block_til_ready(tty, filp, info);
1069 #ifdef ROCKET_DEBUG_OPEN
1070 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1078 * Exception handler that closes a serial port. info->count is considered critical.
1080 static void rp_close(struct tty_struct *tty, struct file *filp)
1082 struct r_port *info = (struct r_port *) tty->driver_data;
1083 unsigned long flags;
1087 if (rocket_paranoia_check(info, "rp_close"))
1090 #ifdef ROCKET_DEBUG_OPEN
1091 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1094 if (tty_hung_up_p(filp))
1096 spin_lock_irqsave(&info->slock, flags);
1098 if ((tty->count == 1) && (info->count != 1)) {
1100 * Uh, oh. tty->count is 1, which means that the tty
1101 * structure will be freed. Info->count should always
1102 * be one in these conditions. If it's greater than
1103 * one, we've got real problems, since it means the
1104 * serial port won't be shutdown.
1106 printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, "
1107 "info->count is %d\n", info->count);
1110 if (--info->count < 0) {
1111 printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n",
1112 info->line, info->count);
1116 spin_unlock_irqrestore(&info->slock, flags);
1119 info->flags |= ROCKET_CLOSING;
1120 spin_unlock_irqrestore(&info->slock, flags);
1122 cp = &info->channel;
1125 * Notify the line discpline to only process XON/XOFF characters
1130 * If transmission was throttled by the application request,
1131 * just flush the xmit buffer.
1133 if (tty->flow_stopped)
1134 rp_flush_buffer(tty);
1137 * Wait for the transmit buffer to clear
1139 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1140 tty_wait_until_sent(tty, info->closing_wait);
1142 * Before we drop DTR, make sure the UART transmitter
1143 * has completely drained; this is especially
1144 * important if there is a transmit FIFO!
1146 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1149 rp_wait_until_sent(tty, timeout);
1150 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1153 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1155 sDisTxSoftFlowCtl(cp);
1163 if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty))
1164 TTY_DRIVER_FLUSH_BUFFER(tty);
1166 tty_ldisc_flush(tty);
1168 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1170 if (info->blocked_open) {
1171 if (info->close_delay) {
1172 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1174 wake_up_interruptible(&info->open_wait);
1176 if (info->xmit_buf) {
1177 free_page((unsigned long) info->xmit_buf);
1178 info->xmit_buf = NULL;
1181 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1183 wake_up_interruptible(&info->close_wait);
1184 atomic_dec(&rp_num_ports_open);
1186 #ifdef ROCKET_DEBUG_OPEN
1187 printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open));
1188 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1193 static void rp_set_termios(struct tty_struct *tty,
1194 struct ktermios *old_termios)
1196 struct r_port *info = (struct r_port *) tty->driver_data;
1200 if (rocket_paranoia_check(info, "rp_set_termios"))
1203 cflag = tty->termios->c_cflag;
1205 if (cflag == old_termios->c_cflag)
1209 * This driver doesn't support CS5 or CS6
1211 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1212 tty->termios->c_cflag =
1213 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1215 configure_r_port(info, old_termios);
1217 cp = &info->channel;
1219 /* Handle transition to B0 status */
1220 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1225 /* Handle transition away from B0 status */
1226 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1227 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1232 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1233 tty->hw_stopped = 0;
1238 static void rp_break(struct tty_struct *tty, int break_state)
1240 struct r_port *info = (struct r_port *) tty->driver_data;
1241 unsigned long flags;
1243 if (rocket_paranoia_check(info, "rp_break"))
1246 spin_lock_irqsave(&info->slock, flags);
1247 if (break_state == -1)
1248 sSendBreak(&info->channel);
1250 sClrBreak(&info->channel);
1251 spin_unlock_irqrestore(&info->slock, flags);
1255 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1256 * the UPCI boards was added, it was decided to make this a function because
1257 * the macro was getting too complicated. All cases except the first one
1258 * (UPCIRingInd) are taken directly from the original macro.
1260 static int sGetChanRI(CHANNEL_T * ChP)
1262 CONTROLLER_t *CtlP = ChP->CtlP;
1263 int ChanNum = ChP->ChanNum;
1266 if (CtlP->UPCIRingInd)
1267 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1268 else if (CtlP->AltChanRingIndicator)
1269 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1270 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1271 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1276 /********************************************************************************************/
1277 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1280 * Returns the state of the serial modem control lines. These next 2 functions
1281 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1283 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1285 struct r_port *info = (struct r_port *)tty->driver_data;
1286 unsigned int control, result, ChanStatus;
1288 ChanStatus = sGetChanStatusLo(&info->channel);
1289 control = info->channel.TxControl[3];
1290 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1291 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1292 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1293 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1294 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1295 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1301 * Sets the modem control lines
1303 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1304 unsigned int set, unsigned int clear)
1306 struct r_port *info = (struct r_port *)tty->driver_data;
1308 if (set & TIOCM_RTS)
1309 info->channel.TxControl[3] |= SET_RTS;
1310 if (set & TIOCM_DTR)
1311 info->channel.TxControl[3] |= SET_DTR;
1312 if (clear & TIOCM_RTS)
1313 info->channel.TxControl[3] &= ~SET_RTS;
1314 if (clear & TIOCM_DTR)
1315 info->channel.TxControl[3] &= ~SET_DTR;
1317 sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
1321 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1323 struct rocket_config tmp;
1327 memset(&tmp, 0, sizeof (tmp));
1328 tmp.line = info->line;
1329 tmp.flags = info->flags;
1330 tmp.close_delay = info->close_delay;
1331 tmp.closing_wait = info->closing_wait;
1332 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1334 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1339 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1341 struct rocket_config new_serial;
1343 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1346 if (!capable(CAP_SYS_ADMIN))
1348 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1350 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1351 configure_r_port(info, NULL);
1355 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1356 info->close_delay = new_serial.close_delay;
1357 info->closing_wait = new_serial.closing_wait;
1359 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1360 info->tty->alt_speed = 57600;
1361 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1362 info->tty->alt_speed = 115200;
1363 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1364 info->tty->alt_speed = 230400;
1365 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1366 info->tty->alt_speed = 460800;
1368 configure_r_port(info, NULL);
1373 * This function fills in a rocket_ports struct with information
1374 * about what boards/ports are in the system. This info is passed
1375 * to user space. See setrocket.c where the info is used to create
1376 * the /dev/ttyRx ports.
1378 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1380 struct rocket_ports tmp;
1385 memset(&tmp, 0, sizeof (tmp));
1386 tmp.tty_major = rocket_driver->major;
1388 for (board = 0; board < 4; board++) {
1389 tmp.rocketModel[board].model = rocketModel[board].model;
1390 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1391 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1392 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1393 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1395 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1400 static int reset_rm2(struct r_port *info, void __user *arg)
1404 if (copy_from_user(&reset, arg, sizeof (int)))
1409 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1410 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1413 if (info->ctlp->BusType == isISA)
1414 sModemReset(info->ctlp, info->chan, reset);
1416 sPCIModemReset(info->ctlp, info->chan, reset);
1421 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1423 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1428 /* IOCTL call handler into the driver */
1429 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1430 unsigned int cmd, unsigned long arg)
1432 struct r_port *info = (struct r_port *) tty->driver_data;
1433 void __user *argp = (void __user *)arg;
1435 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1439 case RCKP_GET_STRUCT:
1440 if (copy_to_user(argp, info, sizeof (struct r_port)))
1443 case RCKP_GET_CONFIG:
1444 return get_config(info, argp);
1445 case RCKP_SET_CONFIG:
1446 return set_config(info, argp);
1447 case RCKP_GET_PORTS:
1448 return get_ports(info, argp);
1449 case RCKP_RESET_RM2:
1450 return reset_rm2(info, argp);
1451 case RCKP_GET_VERSION:
1452 return get_version(info, argp);
1454 return -ENOIOCTLCMD;
1459 static void rp_send_xchar(struct tty_struct *tty, char ch)
1461 struct r_port *info = (struct r_port *) tty->driver_data;
1464 if (rocket_paranoia_check(info, "rp_send_xchar"))
1467 cp = &info->channel;
1469 sWriteTxPrioByte(cp, ch);
1471 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1474 static void rp_throttle(struct tty_struct *tty)
1476 struct r_port *info = (struct r_port *) tty->driver_data;
1479 #ifdef ROCKET_DEBUG_THROTTLE
1480 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1481 tty->ldisc.chars_in_buffer(tty));
1484 if (rocket_paranoia_check(info, "rp_throttle"))
1487 cp = &info->channel;
1489 rp_send_xchar(tty, STOP_CHAR(tty));
1491 sClrRTS(&info->channel);
1494 static void rp_unthrottle(struct tty_struct *tty)
1496 struct r_port *info = (struct r_port *) tty->driver_data;
1498 #ifdef ROCKET_DEBUG_THROTTLE
1499 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1500 tty->ldisc.chars_in_buffer(tty));
1503 if (rocket_paranoia_check(info, "rp_throttle"))
1506 cp = &info->channel;
1508 rp_send_xchar(tty, START_CHAR(tty));
1510 sSetRTS(&info->channel);
1514 * ------------------------------------------------------------
1515 * rp_stop() and rp_start()
1517 * This routines are called before setting or resetting tty->stopped.
1518 * They enable or disable transmitter interrupts, as necessary.
1519 * ------------------------------------------------------------
1521 static void rp_stop(struct tty_struct *tty)
1523 struct r_port *info = (struct r_port *) tty->driver_data;
1525 #ifdef ROCKET_DEBUG_FLOW
1526 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1527 info->xmit_cnt, info->xmit_fifo_room);
1530 if (rocket_paranoia_check(info, "rp_stop"))
1533 if (sGetTxCnt(&info->channel))
1534 sDisTransmit(&info->channel);
1537 static void rp_start(struct tty_struct *tty)
1539 struct r_port *info = (struct r_port *) tty->driver_data;
1541 #ifdef ROCKET_DEBUG_FLOW
1542 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1543 info->xmit_cnt, info->xmit_fifo_room);
1546 if (rocket_paranoia_check(info, "rp_stop"))
1549 sEnTransmit(&info->channel);
1550 set_bit((info->aiop * 8) + info->chan,
1551 (void *) &xmit_flags[info->board]);
1555 * rp_wait_until_sent() --- wait until the transmitter is empty
1557 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1559 struct r_port *info = (struct r_port *) tty->driver_data;
1561 unsigned long orig_jiffies;
1562 int check_time, exit_time;
1565 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1568 cp = &info->channel;
1570 orig_jiffies = jiffies;
1571 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1572 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout,
1574 printk(KERN_INFO "cps=%d...", info->cps);
1577 txcnt = sGetTxCnt(cp);
1579 if (sGetChanStatusLo(cp) & TXSHRMT)
1581 check_time = (HZ / info->cps) / 5;
1583 check_time = HZ * txcnt / info->cps;
1586 exit_time = orig_jiffies + timeout - jiffies;
1589 if (exit_time < check_time)
1590 check_time = exit_time;
1592 if (check_time == 0)
1594 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1595 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time);
1597 msleep_interruptible(jiffies_to_msecs(check_time));
1598 if (signal_pending(current))
1601 current->state = TASK_RUNNING;
1602 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1603 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1608 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1610 static void rp_hangup(struct tty_struct *tty)
1613 struct r_port *info = (struct r_port *) tty->driver_data;
1615 if (rocket_paranoia_check(info, "rp_hangup"))
1618 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1619 printk(KERN_INFO "rp_hangup of ttyR%d...", info->line);
1621 rp_flush_buffer(tty);
1622 if (info->flags & ROCKET_CLOSING)
1625 atomic_dec(&rp_num_ports_open);
1626 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1629 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1632 cp = &info->channel;
1635 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1637 sDisTxSoftFlowCtl(cp);
1639 info->flags &= ~ROCKET_INITIALIZED;
1641 wake_up_interruptible(&info->open_wait);
1645 * Exception handler - write char routine. The RocketPort driver uses a
1646 * double-buffering strategy, with the twist that if the in-memory CPU
1647 * buffer is empty, and there's space in the transmit FIFO, the
1648 * writing routines will write directly to transmit FIFO.
1649 * Write buffer and counters protected by spinlocks
1651 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1653 struct r_port *info = (struct r_port *) tty->driver_data;
1655 unsigned long flags;
1657 if (rocket_paranoia_check(info, "rp_put_char"))
1660 /* Grab the port write semaphore, locking out other processes that try to write to this port */
1661 down(&info->write_sem);
1663 #ifdef ROCKET_DEBUG_WRITE
1664 printk(KERN_INFO "rp_put_char %c...", ch);
1667 spin_lock_irqsave(&info->slock, flags);
1668 cp = &info->channel;
1670 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1671 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1673 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1674 info->xmit_buf[info->xmit_head++] = ch;
1675 info->xmit_head &= XMIT_BUF_SIZE - 1;
1677 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1679 sOutB(sGetTxRxDataIO(cp), ch);
1680 info->xmit_fifo_room--;
1682 spin_unlock_irqrestore(&info->slock, flags);
1683 up(&info->write_sem);
1687 * Exception handler - write routine, called when user app writes to the device.
1688 * A per port write semaphore is used to protect from another process writing to
1689 * this port at the same time. This other process could be running on the other CPU
1690 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1691 * Spinlocks protect the info xmit members.
1693 static int rp_write(struct tty_struct *tty,
1694 const unsigned char *buf, int count)
1696 struct r_port *info = (struct r_port *) tty->driver_data;
1698 const unsigned char *b;
1700 unsigned long flags;
1702 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1705 down_interruptible(&info->write_sem);
1707 #ifdef ROCKET_DEBUG_WRITE
1708 printk(KERN_INFO "rp_write %d chars...", count);
1710 cp = &info->channel;
1712 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1713 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1716 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1717 * into FIFO. Use the write queue for temp storage.
1719 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1720 c = min(count, info->xmit_fifo_room);
1723 /* Push data into FIFO, 2 bytes at a time */
1724 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1726 /* If there is a byte remaining, write it */
1728 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1734 spin_lock_irqsave(&info->slock, flags);
1735 info->xmit_fifo_room -= c;
1736 spin_unlock_irqrestore(&info->slock, flags);
1739 /* If count is zero, we wrote it all and are done */
1743 /* Write remaining data into the port's xmit_buf */
1745 if (info->tty == 0) /* Seemingly obligatory check... */
1748 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1753 memcpy(info->xmit_buf + info->xmit_head, b, c);
1755 spin_lock_irqsave(&info->slock, flags);
1757 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1758 info->xmit_cnt += c;
1759 spin_unlock_irqrestore(&info->slock, flags);
1766 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1767 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1770 if (info->xmit_cnt < WAKEUP_CHARS) {
1772 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1773 wake_up_interruptible(&tty->poll_wait);
1776 up(&info->write_sem);
1781 * Return the number of characters that can be sent. We estimate
1782 * only using the in-memory transmit buffer only, and ignore the
1783 * potential space in the transmit FIFO.
1785 static int rp_write_room(struct tty_struct *tty)
1787 struct r_port *info = (struct r_port *) tty->driver_data;
1790 if (rocket_paranoia_check(info, "rp_write_room"))
1793 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1796 #ifdef ROCKET_DEBUG_WRITE
1797 printk(KERN_INFO "rp_write_room returns %d...", ret);
1803 * Return the number of characters in the buffer. Again, this only
1804 * counts those characters in the in-memory transmit buffer.
1806 static int rp_chars_in_buffer(struct tty_struct *tty)
1808 struct r_port *info = (struct r_port *) tty->driver_data;
1811 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1814 cp = &info->channel;
1816 #ifdef ROCKET_DEBUG_WRITE
1817 printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt);
1819 return info->xmit_cnt;
1823 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1824 * r_port struct for the port. Note that spinlock are used to protect info members,
1825 * do not call this function if the spinlock is already held.
1827 static void rp_flush_buffer(struct tty_struct *tty)
1829 struct r_port *info = (struct r_port *) tty->driver_data;
1831 unsigned long flags;
1833 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1836 spin_lock_irqsave(&info->slock, flags);
1837 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1838 spin_unlock_irqrestore(&info->slock, flags);
1840 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1841 wake_up_interruptible(&tty->poll_wait);
1845 cp = &info->channel;
1852 * Called when a PCI card is found. Retrieves and stores model information,
1853 * init's aiopic and serial port hardware.
1854 * Inputs: i is the board number (0-n)
1856 static __init int register_PCI(int i, struct pci_dev *dev)
1858 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1859 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1860 char *str, *board_type;
1864 int altChanRingIndicator = 0;
1865 int ports_per_aiop = 8;
1867 unsigned int class_rev;
1868 WordIO_t ConfigIO = 0;
1869 ByteIO_t UPCIRingInd = 0;
1871 if (!dev || pci_enable_device(dev))
1874 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1875 ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1878 printk(KERN_INFO " Error during register_PCI(), unable to read config dword \n");
1882 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1883 rocketModel[i].loadrm2 = 0;
1884 rocketModel[i].startingPortNumber = nextLineNumber;
1886 /* Depending on the model, set up some config variables */
1887 switch (dev->device) {
1888 case PCI_DEVICE_ID_RP4QUAD:
1892 rocketModel[i].model = MODEL_RP4QUAD;
1893 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1894 rocketModel[i].numPorts = 4;
1896 case PCI_DEVICE_ID_RP8OCTA:
1899 rocketModel[i].model = MODEL_RP8OCTA;
1900 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1901 rocketModel[i].numPorts = 8;
1903 case PCI_DEVICE_ID_URP8OCTA:
1906 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1907 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1908 rocketModel[i].numPorts = 8;
1910 case PCI_DEVICE_ID_RP8INTF:
1913 rocketModel[i].model = MODEL_RP8INTF;
1914 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1915 rocketModel[i].numPorts = 8;
1917 case PCI_DEVICE_ID_URP8INTF:
1920 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1921 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1922 rocketModel[i].numPorts = 8;
1924 case PCI_DEVICE_ID_RP8J:
1927 rocketModel[i].model = MODEL_RP8J;
1928 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1929 rocketModel[i].numPorts = 8;
1931 case PCI_DEVICE_ID_RP4J:
1935 rocketModel[i].model = MODEL_RP4J;
1936 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1937 rocketModel[i].numPorts = 4;
1939 case PCI_DEVICE_ID_RP8SNI:
1940 str = "8 (DB78 Custom)";
1942 rocketModel[i].model = MODEL_RP8SNI;
1943 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1944 rocketModel[i].numPorts = 8;
1946 case PCI_DEVICE_ID_RP16SNI:
1947 str = "16 (DB78 Custom)";
1949 rocketModel[i].model = MODEL_RP16SNI;
1950 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1951 rocketModel[i].numPorts = 16;
1953 case PCI_DEVICE_ID_RP16INTF:
1956 rocketModel[i].model = MODEL_RP16INTF;
1957 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1958 rocketModel[i].numPorts = 16;
1960 case PCI_DEVICE_ID_URP16INTF:
1963 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1964 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1965 rocketModel[i].numPorts = 16;
1967 case PCI_DEVICE_ID_CRP16INTF:
1970 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1971 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1972 rocketModel[i].numPorts = 16;
1974 case PCI_DEVICE_ID_RP32INTF:
1977 rocketModel[i].model = MODEL_RP32INTF;
1978 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1979 rocketModel[i].numPorts = 32;
1981 case PCI_DEVICE_ID_URP32INTF:
1984 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1985 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1986 rocketModel[i].numPorts = 32;
1988 case PCI_DEVICE_ID_RPP4:
1989 str = "Plus Quadcable";
1992 altChanRingIndicator++;
1994 rocketModel[i].model = MODEL_RPP4;
1995 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1996 rocketModel[i].numPorts = 4;
1998 case PCI_DEVICE_ID_RPP8:
1999 str = "Plus Octacable";
2002 altChanRingIndicator++;
2004 rocketModel[i].model = MODEL_RPP8;
2005 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2006 rocketModel[i].numPorts = 8;
2008 case PCI_DEVICE_ID_RP2_232:
2009 str = "Plus 2 (RS-232)";
2012 altChanRingIndicator++;
2014 rocketModel[i].model = MODEL_RP2_232;
2015 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2016 rocketModel[i].numPorts = 2;
2018 case PCI_DEVICE_ID_RP2_422:
2019 str = "Plus 2 (RS-422)";
2022 altChanRingIndicator++;
2024 rocketModel[i].model = MODEL_RP2_422;
2025 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2026 rocketModel[i].numPorts = 2;
2028 case PCI_DEVICE_ID_RP6M:
2034 /* If class_rev is 1, the rocketmodem flash must be loaded. If it is 2 it is a "socketed" version. */
2035 if ((class_rev & 0xFF) == 1) {
2036 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2037 rocketModel[i].loadrm2 = 1;
2039 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2042 rocketModel[i].model = MODEL_RP6M;
2043 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2044 rocketModel[i].numPorts = 6;
2046 case PCI_DEVICE_ID_RP4M:
2050 if ((class_rev & 0xFF) == 1) {
2051 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2052 rocketModel[i].loadrm2 = 1;
2054 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2057 rocketModel[i].model = MODEL_RP4M;
2058 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2059 rocketModel[i].numPorts = 4;
2062 str = "(unknown/unsupported)";
2068 * Check for UPCI boards.
2071 switch (dev->device) {
2072 case PCI_DEVICE_ID_URP32INTF:
2073 case PCI_DEVICE_ID_URP8INTF:
2074 case PCI_DEVICE_ID_URP16INTF:
2075 case PCI_DEVICE_ID_CRP16INTF:
2076 case PCI_DEVICE_ID_URP8OCTA:
2077 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2078 ConfigIO = pci_resource_start(dev, 1);
2079 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2080 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2083 * Check for octa or quad cable.
2086 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2087 PCI_GPIO_CTRL_8PORT)) {
2090 rocketModel[i].numPorts = 4;
2094 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2097 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2098 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2099 rocketModel[i].numPorts = 8;
2100 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2101 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2102 ConfigIO = pci_resource_start(dev, 1);
2103 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2105 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2108 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2109 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2110 rocketModel[i].numPorts = 4;
2111 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2112 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2113 ConfigIO = pci_resource_start(dev, 1);
2114 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2120 switch (rcktpt_type[i]) {
2121 case ROCKET_TYPE_MODEM:
2122 board_type = "RocketModem";
2124 case ROCKET_TYPE_MODEMII:
2125 board_type = "RocketModem II";
2127 case ROCKET_TYPE_MODEMIII:
2128 board_type = "RocketModem III";
2131 board_type = "RocketPort";
2136 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2137 rp_baud_base[i] = 921600;
2140 * If support_low_speed is set, use the slow clock
2141 * prescale, which supports 50 bps
2143 if (support_low_speed) {
2144 /* mod 9 (divide by 10) prescale */
2145 sClockPrescale = 0x19;
2146 rp_baud_base[i] = 230400;
2148 /* mod 4 (devide by 5) prescale */
2149 sClockPrescale = 0x14;
2150 rp_baud_base[i] = 460800;
2154 for (aiop = 0; aiop < max_num_aiops; aiop++)
2155 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2156 ctlp = sCtlNumToCtlPtr(i);
2157 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2158 for (aiop = 0; aiop < max_num_aiops; aiop++)
2159 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2161 printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, "
2162 "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev),
2163 rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString);
2164 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2165 rocketModel[i].modelString,
2166 rocketModel[i].startingPortNumber,
2167 rocketModel[i].startingPortNumber +
2168 rocketModel[i].numPorts - 1);
2170 if (num_aiops <= 0) {
2171 rcktpt_io_addr[i] = 0;
2176 /* Reset the AIOPIC, init the serial ports */
2177 for (aiop = 0; aiop < num_aiops; aiop++) {
2178 sResetAiopByNum(ctlp, aiop);
2179 num_chan = ports_per_aiop;
2180 for (chan = 0; chan < num_chan; chan++)
2181 init_r_port(i, aiop, chan, dev);
2184 /* Rocket modems must be reset */
2185 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2186 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2187 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2188 num_chan = ports_per_aiop;
2189 for (chan = 0; chan < num_chan; chan++)
2190 sPCIModemReset(ctlp, chan, 1);
2192 for (chan = 0; chan < num_chan; chan++)
2193 sPCIModemReset(ctlp, chan, 0);
2195 rmSpeakerReset(ctlp, rocketModel[i].model);
2201 * Probes for PCI cards, inits them if found
2202 * Input: board_found = number of ISA boards already found, or the
2203 * starting board number
2204 * Returns: Number of PCI boards found
2206 static int __init init_PCI(int boards_found)
2208 struct pci_dev *dev = NULL;
2211 /* Work through the PCI device list, pulling out ours */
2212 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2213 if (register_PCI(count + boards_found, dev))
2219 #endif /* CONFIG_PCI */
2222 * Probes for ISA cards
2223 * Input: i = the board number to look for
2224 * Returns: 1 if board found, 0 else
2226 static int __init init_ISA(int i)
2228 int num_aiops, num_chan = 0, total_num_chan = 0;
2230 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2234 /* If io_addr is zero, no board configured */
2235 if (rcktpt_io_addr[i] == 0)
2238 /* Reserve the IO region */
2239 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2240 printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]);
2241 rcktpt_io_addr[i] = 0;
2245 ctlp = sCtlNumToCtlPtr(i);
2247 ctlp->boardType = rcktpt_type[i];
2249 switch (rcktpt_type[i]) {
2250 case ROCKET_TYPE_PC104:
2251 type_string = "(PC104)";
2253 case ROCKET_TYPE_MODEM:
2254 type_string = "(RocketModem)";
2256 case ROCKET_TYPE_MODEMII:
2257 type_string = "(RocketModem II)";
2265 * If support_low_speed is set, use the slow clock prescale,
2266 * which supports 50 bps
2268 if (support_low_speed) {
2269 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2270 rp_baud_base[i] = 230400;
2272 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2273 rp_baud_base[i] = 460800;
2276 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2277 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2279 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2281 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2282 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2283 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2286 /* If something went wrong initing the AIOP's release the ISA IO memory */
2287 if (num_aiops <= 0) {
2288 release_region(rcktpt_io_addr[i], 64);
2289 rcktpt_io_addr[i] = 0;
2293 rocketModel[i].startingPortNumber = nextLineNumber;
2295 for (aiop = 0; aiop < num_aiops; aiop++) {
2296 sResetAiopByNum(ctlp, aiop);
2297 sEnAiop(ctlp, aiop);
2298 num_chan = sGetAiopNumChan(ctlp, aiop);
2299 total_num_chan += num_chan;
2300 for (chan = 0; chan < num_chan; chan++)
2301 init_r_port(i, aiop, chan, NULL);
2304 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2305 num_chan = sGetAiopNumChan(ctlp, 0);
2306 total_num_chan = num_chan;
2307 for (chan = 0; chan < num_chan; chan++)
2308 sModemReset(ctlp, chan, 1);
2310 for (chan = 0; chan < num_chan; chan++)
2311 sModemReset(ctlp, chan, 0);
2313 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2315 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2317 rocketModel[i].numPorts = total_num_chan;
2318 rocketModel[i].model = MODEL_ISA;
2320 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2321 i, rcktpt_io_addr[i], num_aiops, type_string);
2323 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2324 rocketModel[i].modelString,
2325 rocketModel[i].startingPortNumber,
2326 rocketModel[i].startingPortNumber +
2327 rocketModel[i].numPorts - 1);
2332 static const struct tty_operations rocket_ops = {
2336 .put_char = rp_put_char,
2337 .write_room = rp_write_room,
2338 .chars_in_buffer = rp_chars_in_buffer,
2339 .flush_buffer = rp_flush_buffer,
2341 .throttle = rp_throttle,
2342 .unthrottle = rp_unthrottle,
2343 .set_termios = rp_set_termios,
2346 .hangup = rp_hangup,
2347 .break_ctl = rp_break,
2348 .send_xchar = rp_send_xchar,
2349 .wait_until_sent = rp_wait_until_sent,
2350 .tiocmget = rp_tiocmget,
2351 .tiocmset = rp_tiocmset,
2355 * The module "startup" routine; it's run when the module is loaded.
2357 static int __init rp_init(void)
2359 int retval, pci_boards_found, isa_boards_found, i;
2361 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2362 ROCKET_VERSION, ROCKET_DATE);
2364 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2369 * Initialize the array of pointers to our own internal state
2372 memset(rp_table, 0, sizeof (rp_table));
2373 memset(xmit_flags, 0, sizeof (xmit_flags));
2375 for (i = 0; i < MAX_RP_PORTS; i++)
2378 memset(rocketModel, 0, sizeof (rocketModel));
2381 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2382 * zero, use the default controller IO address of board1 + 0x40.
2385 if (controller == 0)
2386 controller = board1 + 0x40;
2388 controller = 0; /* Used as a flag, meaning no ISA boards */
2391 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2392 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2393 printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx. Driver exiting \n", controller);
2397 /* Store ISA variable retrieved from command line or .conf file. */
2398 rcktpt_io_addr[0] = board1;
2399 rcktpt_io_addr[1] = board2;
2400 rcktpt_io_addr[2] = board3;
2401 rcktpt_io_addr[3] = board4;
2403 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2404 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2405 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2406 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2407 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2408 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2409 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2410 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2413 * Set up the tty driver structure and then register this
2414 * driver with the tty layer.
2417 rocket_driver->owner = THIS_MODULE;
2418 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2419 rocket_driver->name = "ttyR";
2420 rocket_driver->driver_name = "Comtrol RocketPort";
2421 rocket_driver->major = TTY_ROCKET_MAJOR;
2422 rocket_driver->minor_start = 0;
2423 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2424 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2425 rocket_driver->init_termios = tty_std_termios;
2426 rocket_driver->init_termios.c_cflag =
2427 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2428 rocket_driver->init_termios.c_ispeed = 9600;
2429 rocket_driver->init_termios.c_ospeed = 9600;
2430 #ifdef ROCKET_SOFT_FLOW
2431 rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
2433 tty_set_operations(rocket_driver, &rocket_ops);
2435 retval = tty_register_driver(rocket_driver);
2437 printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval);
2438 put_tty_driver(rocket_driver);
2442 #ifdef ROCKET_DEBUG_OPEN
2443 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2447 * OK, let's probe each of the controllers looking for boards. Any boards found
2448 * will be initialized here.
2450 isa_boards_found = 0;
2451 pci_boards_found = 0;
2453 for (i = 0; i < NUM_BOARDS; i++) {
2459 if (isa_boards_found < NUM_BOARDS)
2460 pci_boards_found = init_PCI(isa_boards_found);
2463 max_board = pci_boards_found + isa_boards_found;
2465 if (max_board == 0) {
2466 printk(KERN_INFO "No rocketport ports found; unloading driver.\n");
2467 del_timer_sync(&rocket_timer);
2468 tty_unregister_driver(rocket_driver);
2469 put_tty_driver(rocket_driver);
2477 static void rp_cleanup_module(void)
2482 del_timer_sync(&rocket_timer);
2484 retval = tty_unregister_driver(rocket_driver);
2486 printk(KERN_INFO "Error %d while trying to unregister "
2487 "rocketport driver\n", -retval);
2488 put_tty_driver(rocket_driver);
2490 for (i = 0; i < MAX_RP_PORTS; i++)
2493 for (i = 0; i < NUM_BOARDS; i++) {
2494 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2496 release_region(rcktpt_io_addr[i], 64);
2499 release_region(controller, 4);
2502 /***************************************************************************
2503 Function: sInitController
2504 Purpose: Initialization of controller global registers and controller
2506 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2507 IRQNum,Frequency,PeriodicOnly)
2508 CONTROLLER_T *CtlP; Ptr to controller structure
2509 int CtlNum; Controller number
2510 ByteIO_t MudbacIO; Mudbac base I/O address.
2511 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2512 This list must be in the order the AIOPs will be found on the
2513 controller. Once an AIOP in the list is not found, it is
2514 assumed that there are no more AIOPs on the controller.
2515 int AiopIOListSize; Number of addresses in AiopIOList
2516 int IRQNum; Interrupt Request number. Can be any of the following:
2517 0: Disable global interrupts
2526 Byte_t Frequency: A flag identifying the frequency
2527 of the periodic interrupt, can be any one of the following:
2528 FREQ_DIS - periodic interrupt disabled
2529 FREQ_137HZ - 137 Hertz
2530 FREQ_69HZ - 69 Hertz
2531 FREQ_34HZ - 34 Hertz
2532 FREQ_17HZ - 17 Hertz
2535 If IRQNum is set to 0 the Frequency parameter is
2536 overidden, it is forced to a value of FREQ_DIS.
2537 int PeriodicOnly: 1 if all interrupts except the periodic
2538 interrupt are to be blocked.
2539 0 is both the periodic interrupt and
2540 other channel interrupts are allowed.
2541 If IRQNum is set to 0 the PeriodicOnly parameter is
2542 overidden, it is forced to a value of 0.
2543 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2544 initialization failed.
2547 If periodic interrupts are to be disabled but AIOP interrupts
2548 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2550 If interrupts are to be completely disabled set IRQNum to 0.
2552 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2553 invalid combination.
2555 This function performs initialization of global interrupt modes,
2556 but it does not actually enable global interrupts. To enable
2557 and disable global interrupts use functions sEnGlobalInt() and
2558 sDisGlobalInt(). Enabling of global interrupts is normally not
2559 done until all other initializations are complete.
2561 Even if interrupts are globally enabled, they must also be
2562 individually enabled for each channel that is to generate
2565 Warnings: No range checking on any of the parameters is done.
2567 No context switches are allowed while executing this function.
2569 After this function all AIOPs on the controller are disabled,
2570 they can be enabled with sEnAiop().
2572 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2573 ByteIO_t * AiopIOList, int AiopIOListSize,
2574 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2580 CtlP->AiopIntrBits = aiop_intr_bits;
2581 CtlP->AltChanRingIndicator = 0;
2582 CtlP->CtlNum = CtlNum;
2583 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2584 CtlP->BusType = isISA;
2585 CtlP->MBaseIO = MudbacIO;
2586 CtlP->MReg1IO = MudbacIO + 1;
2587 CtlP->MReg2IO = MudbacIO + 2;
2588 CtlP->MReg3IO = MudbacIO + 3;
2590 CtlP->MReg2 = 0; /* interrupt disable */
2591 CtlP->MReg3 = 0; /* no periodic interrupts */
2593 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2594 CtlP->MReg2 = 0; /* interrupt disable */
2595 CtlP->MReg3 = 0; /* no periodic interrupts */
2597 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2598 CtlP->MReg3 = Frequency; /* set frequency */
2599 if (PeriodicOnly) { /* periodic interrupt only */
2600 CtlP->MReg3 |= PERIODIC_ONLY;
2604 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2605 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2606 sControllerEOI(CtlP); /* clear EOI if warm init */
2609 for (i = done = 0; i < AiopIOListSize; i++) {
2611 CtlP->AiopIO[i] = (WordIO_t) io;
2612 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2613 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2614 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2617 sEnAiop(CtlP, i); /* enable the AIOP */
2618 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2619 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2620 done = 1; /* done looking for AIOPs */
2622 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2623 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2624 sOutB(io + _INDX_DATA, sClockPrescale);
2625 CtlP->NumAiop++; /* bump count of AIOPs */
2627 sDisAiop(CtlP, i); /* disable AIOP */
2630 if (CtlP->NumAiop == 0)
2633 return (CtlP->NumAiop);
2636 /***************************************************************************
2637 Function: sPCIInitController
2638 Purpose: Initialization of controller global registers and controller
2640 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2641 IRQNum,Frequency,PeriodicOnly)
2642 CONTROLLER_T *CtlP; Ptr to controller structure
2643 int CtlNum; Controller number
2644 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2645 This list must be in the order the AIOPs will be found on the
2646 controller. Once an AIOP in the list is not found, it is
2647 assumed that there are no more AIOPs on the controller.
2648 int AiopIOListSize; Number of addresses in AiopIOList
2649 int IRQNum; Interrupt Request number. Can be any of the following:
2650 0: Disable global interrupts
2659 Byte_t Frequency: A flag identifying the frequency
2660 of the periodic interrupt, can be any one of the following:
2661 FREQ_DIS - periodic interrupt disabled
2662 FREQ_137HZ - 137 Hertz
2663 FREQ_69HZ - 69 Hertz
2664 FREQ_34HZ - 34 Hertz
2665 FREQ_17HZ - 17 Hertz
2668 If IRQNum is set to 0 the Frequency parameter is
2669 overidden, it is forced to a value of FREQ_DIS.
2670 int PeriodicOnly: 1 if all interrupts except the periodic
2671 interrupt are to be blocked.
2672 0 is both the periodic interrupt and
2673 other channel interrupts are allowed.
2674 If IRQNum is set to 0 the PeriodicOnly parameter is
2675 overidden, it is forced to a value of 0.
2676 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2677 initialization failed.
2680 If periodic interrupts are to be disabled but AIOP interrupts
2681 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2683 If interrupts are to be completely disabled set IRQNum to 0.
2685 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2686 invalid combination.
2688 This function performs initialization of global interrupt modes,
2689 but it does not actually enable global interrupts. To enable
2690 and disable global interrupts use functions sEnGlobalInt() and
2691 sDisGlobalInt(). Enabling of global interrupts is normally not
2692 done until all other initializations are complete.
2694 Even if interrupts are globally enabled, they must also be
2695 individually enabled for each channel that is to generate
2698 Warnings: No range checking on any of the parameters is done.
2700 No context switches are allowed while executing this function.
2702 After this function all AIOPs on the controller are disabled,
2703 they can be enabled with sEnAiop().
2705 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2706 ByteIO_t * AiopIOList, int AiopIOListSize,
2707 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2708 int PeriodicOnly, int altChanRingIndicator,
2714 CtlP->AltChanRingIndicator = altChanRingIndicator;
2715 CtlP->UPCIRingInd = UPCIRingInd;
2716 CtlP->CtlNum = CtlNum;
2717 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2718 CtlP->BusType = isPCI; /* controller release 1 */
2722 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2723 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2724 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2728 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2729 CtlP->AiopIntrBits = aiop_intr_bits;
2732 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2735 for (i = 0; i < AiopIOListSize; i++) {
2737 CtlP->AiopIO[i] = (WordIO_t) io;
2738 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2740 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2741 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2742 break; /* done looking for AIOPs */
2744 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2745 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2746 sOutB(io + _INDX_DATA, sClockPrescale);
2747 CtlP->NumAiop++; /* bump count of AIOPs */
2750 if (CtlP->NumAiop == 0)
2753 return (CtlP->NumAiop);
2756 /***************************************************************************
2757 Function: sReadAiopID
2758 Purpose: Read the AIOP idenfication number directly from an AIOP.
2759 Call: sReadAiopID(io)
2760 ByteIO_t io: AIOP base I/O address
2761 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2762 is replace by an identifying number.
2763 Flag AIOPID_NULL if no valid AIOP is found
2764 Warnings: No context switches are allowed while executing this function.
2767 static int sReadAiopID(ByteIO_t io)
2769 Byte_t AiopID; /* ID byte from AIOP */
2771 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2772 sOutB(io + _CMD_REG, 0x0);
2773 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2776 else /* AIOP does not exist */
2780 /***************************************************************************
2781 Function: sReadAiopNumChan
2782 Purpose: Read the number of channels available in an AIOP directly from
2784 Call: sReadAiopNumChan(io)
2785 WordIO_t io: AIOP base I/O address
2786 Return: int: The number of channels available
2787 Comments: The number of channels is determined by write/reads from identical
2788 offsets within the SRAM address spaces for channels 0 and 4.
2789 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2790 AIOP, otherwise it is an 8 channel.
2791 Warnings: No context switches are allowed while executing this function.
2793 static int sReadAiopNumChan(WordIO_t io)
2796 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2798 /* write to chan 0 SRAM */
2799 sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
2800 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2801 x = sInW(io + _INDX_DATA);
2802 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2803 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2809 /***************************************************************************
2811 Purpose: Initialization of a channel and channel structure
2812 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2813 CONTROLLER_T *CtlP; Ptr to controller structure
2814 CHANNEL_T *ChP; Ptr to channel structure
2815 int AiopNum; AIOP number within controller
2816 int ChanNum; Channel number within AIOP
2817 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2818 number exceeds number of channels available in AIOP.
2819 Comments: This function must be called before a channel can be used.
2820 Warnings: No range checking on any of the parameters is done.
2822 No context switches are allowed while executing this function.
2824 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2835 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2836 return 0; /* exceeds num chans in AIOP */
2838 /* Channel, AIOP, and controller identifiers */
2840 ChP->ChanID = CtlP->AiopID[AiopNum];
2841 ChP->AiopNum = AiopNum;
2842 ChP->ChanNum = ChanNum;
2844 /* Global direct addresses */
2845 AiopIO = CtlP->AiopIO[AiopNum];
2846 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2847 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2848 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2849 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2850 ChP->IndexData = AiopIO + _INDX_DATA;
2852 /* Channel direct addresses */
2853 ChIOOff = AiopIO + ChP->ChanNum * 2;
2854 ChP->TxRxData = ChIOOff + _TD0;
2855 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2856 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2857 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2859 /* Initialize the channel from the RData array */
2860 for (i = 0; i < RDATASIZE; i += 4) {
2862 R[1] = RData[i + 1] + 0x10 * ChanNum;
2863 R[2] = RData[i + 2];
2864 R[3] = RData[i + 3];
2865 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
2869 for (i = 0; i < RREGDATASIZE; i += 4) {
2870 ChR[i] = RRegData[i];
2871 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2872 ChR[i + 2] = RRegData[i + 2];
2873 ChR[i + 3] = RRegData[i + 3];
2876 /* Indexed registers */
2877 ChOff = (Word_t) ChanNum *0x1000;
2879 if (sClockPrescale == 0x14)
2884 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2885 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2886 ChP->BaudDiv[2] = (Byte_t) brd9600;
2887 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2888 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
2890 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2891 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2892 ChP->TxControl[2] = 0;
2893 ChP->TxControl[3] = 0;
2894 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
2896 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2897 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2898 ChP->RxControl[2] = 0;
2899 ChP->RxControl[3] = 0;
2900 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
2902 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2903 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2904 ChP->TxEnables[2] = 0;
2905 ChP->TxEnables[3] = 0;
2906 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
2908 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2909 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2910 ChP->TxCompare[2] = 0;
2911 ChP->TxCompare[3] = 0;
2912 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
2914 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2915 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2916 ChP->TxReplace1[2] = 0;
2917 ChP->TxReplace1[3] = 0;
2918 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
2920 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2921 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2922 ChP->TxReplace2[2] = 0;
2923 ChP->TxReplace2[3] = 0;
2924 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
2926 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2927 ChP->TxFIFO = ChOff + _TX_FIFO;
2929 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2930 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2931 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2932 sOutW(ChP->IndexData, 0);
2933 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2934 ChP->RxFIFO = ChOff + _RX_FIFO;
2936 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2937 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2938 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2939 sOutW(ChP->IndexData, 0);
2940 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2941 sOutW(ChP->IndexData, 0);
2942 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2943 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2944 sOutB(ChP->IndexData, 0);
2945 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2946 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2947 sOutB(ChP->IndexData, 0);
2948 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2949 sEnRxProcessor(ChP); /* start the Rx processor */
2954 /***************************************************************************
2955 Function: sStopRxProcessor
2956 Purpose: Stop the receive processor from processing a channel.
2957 Call: sStopRxProcessor(ChP)
2958 CHANNEL_T *ChP; Ptr to channel structure
2960 Comments: The receive processor can be started again with sStartRxProcessor().
2961 This function causes the receive processor to skip over the
2962 stopped channel. It does not stop it from processing other channels.
2964 Warnings: No context switches are allowed while executing this function.
2966 Do not leave the receive processor stopped for more than one
2969 After calling this function a delay of 4 uS is required to ensure
2970 that the receive processor is no longer processing this channel.
2972 static void sStopRxProcessor(CHANNEL_T * ChP)
2980 sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
2983 /***************************************************************************
2984 Function: sFlushRxFIFO
2985 Purpose: Flush the Rx FIFO
2986 Call: sFlushRxFIFO(ChP)
2987 CHANNEL_T *ChP; Ptr to channel structure
2989 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2990 while it is being flushed the receive processor is stopped
2991 and the transmitter is disabled. After these operations a
2992 4 uS delay is done before clearing the pointers to allow
2993 the receive processor to stop. These items are handled inside
2995 Warnings: No context switches are allowed while executing this function.
2997 static void sFlushRxFIFO(CHANNEL_T * ChP)
3000 Byte_t Ch; /* channel number within AIOP */
3001 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
3003 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3004 return; /* don't need to flush */
3007 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3009 sDisRxFIFO(ChP); /* disable it */
3010 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3011 sInB(ChP->IntChan); /* depends on bus i/o timing */
3013 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3014 Ch = (Byte_t) sGetChanNum(ChP);
3015 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3016 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3017 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3018 sOutW(ChP->IndexData, 0);
3019 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3020 sOutW(ChP->IndexData, 0);
3022 sEnRxFIFO(ChP); /* enable Rx FIFO */
3025 /***************************************************************************
3026 Function: sFlushTxFIFO
3027 Purpose: Flush the Tx FIFO
3028 Call: sFlushTxFIFO(ChP)
3029 CHANNEL_T *ChP; Ptr to channel structure
3031 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3032 while it is being flushed the receive processor is stopped
3033 and the transmitter is disabled. After these operations a
3034 4 uS delay is done before clearing the pointers to allow
3035 the receive processor to stop. These items are handled inside
3037 Warnings: No context switches are allowed while executing this function.
3039 static void sFlushTxFIFO(CHANNEL_T * ChP)
3042 Byte_t Ch; /* channel number within AIOP */
3043 int TxEnabled; /* 1 if transmitter enabled */
3045 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3046 return; /* don't need to flush */
3049 if (ChP->TxControl[3] & TX_ENABLE) {
3051 sDisTransmit(ChP); /* disable transmitter */
3053 sStopRxProcessor(ChP); /* stop Rx processor */
3054 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3055 sInB(ChP->IntChan); /* depends on bus i/o timing */
3056 Ch = (Byte_t) sGetChanNum(ChP);
3057 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3058 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3059 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3060 sOutW(ChP->IndexData, 0);
3062 sEnTransmit(ChP); /* enable transmitter */
3063 sStartRxProcessor(ChP); /* restart Rx processor */
3066 /***************************************************************************
3067 Function: sWriteTxPrioByte
3068 Purpose: Write a byte of priority transmit data to a channel
3069 Call: sWriteTxPrioByte(ChP,Data)
3070 CHANNEL_T *ChP; Ptr to channel structure
3071 Byte_t Data; The transmit data byte
3073 Return: int: 1 if the bytes is successfully written, otherwise 0.
3075 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3077 Warnings: No context switches are allowed while executing this function.
3079 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3081 Byte_t DWBuf[4]; /* buffer for double word writes */
3082 Word_t *WordPtr; /* must be far because Win SS != DS */
3083 register DWordIO_t IndexAddr;
3085 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3086 IndexAddr = ChP->IndexAddr;
3087 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3088 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3089 return (0); /* nothing sent */
3091 WordPtr = (Word_t *) (&DWBuf[0]);
3092 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3094 DWBuf[2] = Data; /* data byte value */
3095 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3097 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3099 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3100 DWBuf[3] = 0; /* priority buffer pointer */
3101 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3102 } else { /* write it to Tx FIFO */
3104 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3106 return (1); /* 1 byte sent */
3109 /***************************************************************************
3110 Function: sEnInterrupts
3111 Purpose: Enable one or more interrupts for a channel
3112 Call: sEnInterrupts(ChP,Flags)
3113 CHANNEL_T *ChP; Ptr to channel structure
3114 Word_t Flags: Interrupt enable flags, can be any combination
3115 of the following flags:
3116 TXINT_EN: Interrupt on Tx FIFO empty
3117 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3119 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3120 MCINT_EN: Interrupt on modem input change
3121 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3122 Interrupt Channel Register.
3124 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3125 enabled. If an interrupt enable flag is not set in Flags, that
3126 interrupt will not be changed. Interrupts can be disabled with
3127 function sDisInterrupts().
3129 This function sets the appropriate bit for the channel in the AIOP's
3130 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3131 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3133 Interrupts must also be globally enabled before channel interrupts
3134 will be passed on to the host. This is done with function
3137 In some cases it may be desirable to disable interrupts globally but
3138 enable channel interrupts. This would allow the global interrupt
3139 status register to be used to determine which AIOPs need service.
3141 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3143 Byte_t Mask; /* Interrupt Mask Register */
3145 ChP->RxControl[2] |=
3146 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3148 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3150 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3152 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3154 if (Flags & CHANINT_EN) {
3155 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3156 sOutB(ChP->IntMask, Mask);
3160 /***************************************************************************
3161 Function: sDisInterrupts
3162 Purpose: Disable one or more interrupts for a channel
3163 Call: sDisInterrupts(ChP,Flags)
3164 CHANNEL_T *ChP; Ptr to channel structure
3165 Word_t Flags: Interrupt flags, can be any combination
3166 of the following flags:
3167 TXINT_EN: Interrupt on Tx FIFO empty
3168 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3170 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3171 MCINT_EN: Interrupt on modem input change
3172 CHANINT_EN: Disable channel interrupt signal to the
3173 AIOP's Interrupt Channel Register.
3175 Comments: If an interrupt flag is set in Flags, that interrupt will be
3176 disabled. If an interrupt flag is not set in Flags, that
3177 interrupt will not be changed. Interrupts can be enabled with
3178 function sEnInterrupts().
3180 This function clears the appropriate bit for the channel in the AIOP's
3181 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3182 this channel's bit from being set in the AIOP's Interrupt Channel
3185 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3187 Byte_t Mask; /* Interrupt Mask Register */
3189 ChP->RxControl[2] &=
3190 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3191 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3192 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3193 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3195 if (Flags & CHANINT_EN) {
3196 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3197 sOutB(ChP->IntMask, Mask);
3201 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3203 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3207 * Not an official SSCI function, but how to reset RocketModems.
3210 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3215 addr = CtlP->AiopIO[0] + 0x400;
3216 val = sInB(CtlP->MReg3IO);
3217 /* if AIOP[1] is not enabled, enable it */
3218 if ((val & 2) == 0) {
3219 val = sInB(CtlP->MReg2IO);
3220 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3221 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3227 sOutB(addr + chan, 0); /* apply or remove reset */
3232 * Not an official SSCI function, but how to reset RocketModems.
3235 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3239 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3242 sOutB(addr + chan, 0); /* apply or remove reset */
3245 /* Resets the speaker controller on RocketModem II and III devices */
3246 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3250 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3251 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3252 addr = CtlP->AiopIO[0] + 0x4F;
3256 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3257 if ((model == MODEL_UPCI_RM3_8PORT)
3258 || (model == MODEL_UPCI_RM3_4PORT)) {
3259 addr = CtlP->AiopIO[0] + 0x88;
3264 /* Returns the line number given the controller (board), aiop and channel number */
3265 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3267 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3271 * Stores the line number associated with a given controller (board), aiop
3272 * and channel number.
3273 * Returns: The line number assigned
3275 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3277 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3278 return (nextLineNumber - 1);