2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
56 #undef ROCKET_DEBUG_IO
58 #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
60 /****** Kernel includes ******/
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/string.h>
76 #include <linux/fcntl.h>
77 #include <linux/ptrace.h>
78 #include <linux/mutex.h>
79 #include <linux/ioport.h>
80 #include <linux/delay.h>
81 #include <linux/completion.h>
82 #include <linux/wait.h>
83 #include <linux/pci.h>
84 #include <asm/uaccess.h>
85 #include <asm/atomic.h>
86 #include <asm/unaligned.h>
87 #include <linux/bitops.h>
88 #include <linux/spinlock.h>
89 #include <linux/init.h>
91 /****** RocketPort includes ******/
93 #include "rocket_int.h"
96 #define ROCKET_VERSION "2.09"
97 #define ROCKET_DATE "12-June-2003"
99 /****** RocketPort Local Variables ******/
101 static void rp_do_poll(unsigned long dummy);
103 static struct tty_driver *rocket_driver;
105 static struct rocket_version driver_version = {
106 ROCKET_VERSION, ROCKET_DATE
109 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
110 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
111 /* eg. Bit 0 indicates port 0 has xmit data, ... */
112 static atomic_t rp_num_ports_open; /* Number of serial ports open */
113 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
115 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
116 static unsigned long board2;
117 static unsigned long board3;
118 static unsigned long board4;
119 static unsigned long controller;
120 static int support_low_speed;
121 static unsigned long modem1;
122 static unsigned long modem2;
123 static unsigned long modem3;
124 static unsigned long modem4;
125 static unsigned long pc104_1[8];
126 static unsigned long pc104_2[8];
127 static unsigned long pc104_3[8];
128 static unsigned long pc104_4[8];
129 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
132 static unsigned long rcktpt_io_addr[NUM_BOARDS];
133 static int rcktpt_type[NUM_BOARDS];
134 static int is_PCI[NUM_BOARDS];
135 static rocketModel_t rocketModel[NUM_BOARDS];
136 static int max_board;
139 * The following arrays define the interrupt bits corresponding to each AIOP.
140 * These bits are different between the ISA and regular PCI boards and the
141 * Universal PCI boards.
144 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
151 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
152 UPCI_AIOP_INTR_BIT_0,
153 UPCI_AIOP_INTR_BIT_1,
154 UPCI_AIOP_INTR_BIT_2,
158 static Byte_t RData[RDATASIZE] = {
159 0x00, 0x09, 0xf6, 0x82,
160 0x02, 0x09, 0x86, 0xfb,
161 0x04, 0x09, 0x00, 0x0a,
162 0x06, 0x09, 0x01, 0x0a,
163 0x08, 0x09, 0x8a, 0x13,
164 0x0a, 0x09, 0xc5, 0x11,
165 0x0c, 0x09, 0x86, 0x85,
166 0x0e, 0x09, 0x20, 0x0a,
167 0x10, 0x09, 0x21, 0x0a,
168 0x12, 0x09, 0x41, 0xff,
169 0x14, 0x09, 0x82, 0x00,
170 0x16, 0x09, 0x82, 0x7b,
171 0x18, 0x09, 0x8a, 0x7d,
172 0x1a, 0x09, 0x88, 0x81,
173 0x1c, 0x09, 0x86, 0x7a,
174 0x1e, 0x09, 0x84, 0x81,
175 0x20, 0x09, 0x82, 0x7c,
176 0x22, 0x09, 0x0a, 0x0a
179 static Byte_t RRegData[RREGDATASIZE] = {
180 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
181 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
182 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
183 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
184 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
185 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
186 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
187 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
188 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
189 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
190 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
191 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
192 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
195 static CONTROLLER_T sController[CTL_SIZE] = {
196 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
197 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
206 static Byte_t sBitMapClrTbl[8] = {
207 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
210 static Byte_t sBitMapSetTbl[8] = {
211 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
214 static int sClockPrescale = 0x14;
217 * Line number is the ttySIx number (x), the Minor number. We
218 * assign them sequentially, starting at zero. The following
219 * array keeps track of the line number assigned to a given board/aiop/channel.
221 static unsigned char lineNumbers[MAX_RP_PORTS];
222 static unsigned long nextLineNumber;
224 /***** RocketPort Static Prototypes *********/
225 static int __init init_ISA(int i);
226 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
227 static void rp_flush_buffer(struct tty_struct *tty);
228 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
229 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
230 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
231 static void rp_start(struct tty_struct *tty);
232 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
234 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
235 static void sFlushRxFIFO(CHANNEL_T * ChP);
236 static void sFlushTxFIFO(CHANNEL_T * ChP);
237 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
238 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
239 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
240 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
241 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
242 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
243 ByteIO_t * AiopIOList, int AiopIOListSize,
244 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
245 int PeriodicOnly, int altChanRingIndicator,
247 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
248 ByteIO_t * AiopIOList, int AiopIOListSize,
249 int IRQNum, Byte_t Frequency, int PeriodicOnly);
250 static int sReadAiopID(ByteIO_t io);
251 static int sReadAiopNumChan(WordIO_t io);
253 MODULE_AUTHOR("Theodore Ts'o");
254 MODULE_DESCRIPTION("Comtrol RocketPort driver");
255 module_param(board1, ulong, 0);
256 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
257 module_param(board2, ulong, 0);
258 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
259 module_param(board3, ulong, 0);
260 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
261 module_param(board4, ulong, 0);
262 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
263 module_param(controller, ulong, 0);
264 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
265 module_param(support_low_speed, bool, 0);
266 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
267 module_param(modem1, ulong, 0);
268 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
269 module_param(modem2, ulong, 0);
270 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
271 module_param(modem3, ulong, 0);
272 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
273 module_param(modem4, ulong, 0);
274 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
275 module_param_array(pc104_1, ulong, NULL, 0);
276 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
277 module_param_array(pc104_2, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
279 module_param_array(pc104_3, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
281 module_param_array(pc104_4, ulong, NULL, 0);
282 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
284 static int rp_init(void);
285 static void rp_cleanup_module(void);
287 module_init(rp_init);
288 module_exit(rp_cleanup_module);
291 MODULE_LICENSE("Dual BSD/GPL");
293 /*************************************************************************/
294 /* Module code starts here */
296 static inline int rocket_paranoia_check(struct r_port *info,
299 #ifdef ROCKET_PARANOIA_CHECK
302 if (info->magic != RPORT_MAGIC) {
303 printk(KERN_WARNING "Warning: bad magic number for rocketport "
304 "struct in %s\n", routine);
312 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
313 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
316 static void rp_do_receive(struct r_port *info,
317 struct tty_struct *tty,
318 CHANNEL_t * cp, unsigned int ChanStatus)
320 unsigned int CharNStat;
321 int ToRecv, wRecv, space;
324 ToRecv = sGetRxCnt(cp);
325 #ifdef ROCKET_DEBUG_INTR
326 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
332 * if status indicates there are errored characters in the
333 * FIFO, then enter status mode (a word in FIFO holds
334 * character and status).
336 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
337 if (!(ChanStatus & STATMODE)) {
338 #ifdef ROCKET_DEBUG_RECEIVE
339 printk(KERN_INFO "Entering STATMODE...\n");
341 ChanStatus |= STATMODE;
347 * if we previously entered status mode, then read down the
348 * FIFO one word at a time, pulling apart the character and
349 * the status. Update error counters depending on status
351 if (ChanStatus & STATMODE) {
352 #ifdef ROCKET_DEBUG_RECEIVE
353 printk(KERN_INFO "Ignore %x, read %x...\n",
354 info->ignore_status_mask, info->read_status_mask);
359 CharNStat = sInW(sGetTxRxDataIO(cp));
360 #ifdef ROCKET_DEBUG_RECEIVE
361 printk(KERN_INFO "%x...\n", CharNStat);
363 if (CharNStat & STMBREAKH)
364 CharNStat &= ~(STMFRAMEH | STMPARITYH);
365 if (CharNStat & info->ignore_status_mask) {
369 CharNStat &= info->read_status_mask;
370 if (CharNStat & STMBREAKH)
372 else if (CharNStat & STMPARITYH)
374 else if (CharNStat & STMFRAMEH)
376 else if (CharNStat & STMRCVROVRH)
380 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
385 * after we've emptied the FIFO in status mode, turn
386 * status mode back off
388 if (sGetRxCnt(cp) == 0) {
389 #ifdef ROCKET_DEBUG_RECEIVE
390 printk(KERN_INFO "Status mode off.\n");
392 sDisRxStatusMode(cp);
396 * we aren't in status mode, so read down the FIFO two
397 * characters at time by doing repeated word IO
400 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
401 if (space < ToRecv) {
402 #ifdef ROCKET_DEBUG_RECEIVE
403 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
411 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
413 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
415 /* Push the data up to the tty layer */
416 tty_flip_buffer_push(tty);
420 * Serial port transmit data function. Called from the timer polling loop as a
421 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
422 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
423 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
425 static void rp_do_transmit(struct r_port *info)
428 CHANNEL_t *cp = &info->channel;
429 struct tty_struct *tty;
432 #ifdef ROCKET_DEBUG_INTR
433 printk(KERN_DEBUG "%s\n", __func__);
438 printk(KERN_WARNING "rp: WARNING %s called with "
439 "info->tty==NULL\n", __func__);
440 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
444 spin_lock_irqsave(&info->slock, flags);
446 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
448 /* Loop sending data to FIFO until done or FIFO full */
450 if (tty->stopped || tty->hw_stopped)
452 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
453 if (c <= 0 || info->xmit_fifo_room <= 0)
455 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
457 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
458 info->xmit_tail += c;
459 info->xmit_tail &= XMIT_BUF_SIZE - 1;
461 info->xmit_fifo_room -= c;
462 #ifdef ROCKET_DEBUG_INTR
463 printk(KERN_INFO "tx %d chars...\n", c);
467 if (info->xmit_cnt == 0)
468 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
470 if (info->xmit_cnt < WAKEUP_CHARS) {
472 #ifdef ROCKETPORT_HAVE_POLL_WAIT
473 wake_up_interruptible(&tty->poll_wait);
477 spin_unlock_irqrestore(&info->slock, flags);
479 #ifdef ROCKET_DEBUG_INTR
480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
481 info->xmit_tail, info->xmit_fifo_room);
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
490 static void rp_handle_port(struct r_port *info)
493 struct tty_struct *tty;
494 unsigned int IntMask, ChanStatus;
499 if ((info->flags & ROCKET_INITIALIZED) == 0) {
500 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
501 "info->flags & NOT_INIT\n");
505 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
506 "info->tty==NULL\n");
512 IntMask = sGetChanIntID(cp) & info->intmask;
513 #ifdef ROCKET_DEBUG_INTR
514 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
516 ChanStatus = sGetChanStatus(cp);
517 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
518 rp_do_receive(info, tty, cp, ChanStatus);
520 if (IntMask & DELTA_CD) { /* CD change */
521 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
522 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
523 (ChanStatus & CD_ACT) ? "on" : "off");
525 if (!(ChanStatus & CD_ACT) && info->cd_status) {
526 #ifdef ROCKET_DEBUG_HANGUP
527 printk(KERN_INFO "CD drop, calling hangup.\n");
531 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
532 wake_up_interruptible(&info->open_wait);
534 #ifdef ROCKET_DEBUG_INTR
535 if (IntMask & DELTA_CTS) { /* CTS change */
536 printk(KERN_INFO "CTS change...\n");
538 if (IntMask & DELTA_DSR) { /* DSR change */
539 printk(KERN_INFO "DSR change...\n");
545 * The top level polling routine. Repeats every 1/100 HZ (10ms).
547 static void rp_do_poll(unsigned long dummy)
550 int ctrl, aiop, ch, line;
551 unsigned int xmitmask, i;
552 unsigned int CtlMask;
553 unsigned char AiopMask;
556 /* Walk through all the boards (ctrl's) */
557 for (ctrl = 0; ctrl < max_board; ctrl++) {
558 if (rcktpt_io_addr[ctrl] <= 0)
561 /* Get a ptr to the board's control struct */
562 ctlp = sCtlNumToCtlPtr(ctrl);
564 /* Get the interrupt status from the board */
566 if (ctlp->BusType == isPCI)
567 CtlMask = sPCIGetControllerIntStatus(ctlp);
570 CtlMask = sGetControllerIntStatus(ctlp);
572 /* Check if any AIOP read bits are set */
573 for (aiop = 0; CtlMask; aiop++) {
574 bit = ctlp->AiopIntrBits[aiop];
577 AiopMask = sGetAiopIntStatus(ctlp, aiop);
579 /* Check if any port read bits are set */
580 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
583 /* Get the line number (/dev/ttyRx number). */
584 /* Read the data from the port. */
585 line = GetLineNumber(ctrl, aiop, ch);
586 rp_handle_port(rp_table[line]);
592 xmitmask = xmit_flags[ctrl];
595 * xmit_flags contains bit-significant flags, indicating there is data
596 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
597 * 1, ... (32 total possible). The variable i has the aiop and ch
598 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
601 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
602 if (xmitmask & (1 << i)) {
603 aiop = (i & 0x18) >> 3;
605 line = GetLineNumber(ctrl, aiop, ch);
606 rp_do_transmit(rp_table[line]);
613 * Reset the timer so we get called at the next clock tick (10ms).
615 if (atomic_read(&rp_num_ports_open))
616 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
620 * Initializes the r_port structure for a port, as well as enabling the port on
622 * Inputs: board, aiop, chan numbers
624 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
631 /* Get the next available line number */
632 line = SetLineNumber(board, aiop, chan);
634 ctlp = sCtlNumToCtlPtr(board);
636 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
637 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
639 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
644 info->magic = RPORT_MAGIC;
650 info->closing_wait = 3000;
651 info->close_delay = 50;
652 init_waitqueue_head(&info->open_wait);
653 init_completion(&info->close_wait);
654 info->flags &= ~ROCKET_MODE_MASK;
655 switch (pc104[board][line]) {
657 info->flags |= ROCKET_MODE_RS422;
660 info->flags |= ROCKET_MODE_RS485;
664 info->flags |= ROCKET_MODE_RS232;
668 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
669 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
670 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
676 rocketMode = info->flags & ROCKET_MODE_MASK;
678 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
679 sEnRTSToggle(&info->channel);
681 sDisRTSToggle(&info->channel);
683 if (ctlp->boardType == ROCKET_TYPE_PC104) {
684 switch (rocketMode) {
685 case ROCKET_MODE_RS485:
686 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
688 case ROCKET_MODE_RS422:
689 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
691 case ROCKET_MODE_RS232:
693 if (info->flags & ROCKET_RTS_TOGGLE)
694 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
696 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
700 spin_lock_init(&info->slock);
701 mutex_init(&info->write_mtx);
702 rp_table[line] = info;
703 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
708 * Configures a rocketport port according to its termio settings. Called from
709 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
711 static void configure_r_port(struct r_port *info,
712 struct ktermios *old_termios)
717 int bits, baud, divisor;
719 struct ktermios *t = info->tty->termios;
724 /* Byte size and parity */
725 if ((cflag & CSIZE) == CS8) {
732 if (cflag & CSTOPB) {
739 if (cflag & PARENB) {
742 if (cflag & PARODD) {
752 baud = tty_get_baud_rate(info->tty);
755 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
756 if ((divisor >= 8192 || divisor < 0) && old_termios) {
757 baud = tty_termios_baud_rate(old_termios);
760 divisor = (rp_baud_base[info->board] / baud) - 1;
762 if (divisor >= 8192 || divisor < 0) {
764 divisor = (rp_baud_base[info->board] / baud) - 1;
766 info->cps = baud / bits;
767 sSetBaud(cp, divisor);
769 /* FIXME: Should really back compute a baud rate from the divisor */
770 tty_encode_baud_rate(info->tty, baud, baud);
772 if (cflag & CRTSCTS) {
773 info->intmask |= DELTA_CTS;
776 info->intmask &= ~DELTA_CTS;
779 if (cflag & CLOCAL) {
780 info->intmask &= ~DELTA_CD;
782 spin_lock_irqsave(&info->slock, flags);
783 if (sGetChanStatus(cp) & CD_ACT)
787 info->intmask |= DELTA_CD;
788 spin_unlock_irqrestore(&info->slock, flags);
792 * Handle software flow control in the board
794 #ifdef ROCKET_SOFT_FLOW
795 if (I_IXON(info->tty)) {
796 sEnTxSoftFlowCtl(cp);
797 if (I_IXANY(info->tty)) {
802 sSetTxXONChar(cp, START_CHAR(info->tty));
803 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
805 sDisTxSoftFlowCtl(cp);
812 * Set up ignore/read mask words
814 info->read_status_mask = STMRCVROVRH | 0xFF;
815 if (I_INPCK(info->tty))
816 info->read_status_mask |= STMFRAMEH | STMPARITYH;
817 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
818 info->read_status_mask |= STMBREAKH;
821 * Characters to ignore
823 info->ignore_status_mask = 0;
824 if (I_IGNPAR(info->tty))
825 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
826 if (I_IGNBRK(info->tty)) {
827 info->ignore_status_mask |= STMBREAKH;
829 * If we're ignoring parity and break indicators,
830 * ignore overruns too. (For real raw support).
832 if (I_IGNPAR(info->tty))
833 info->ignore_status_mask |= STMRCVROVRH;
836 rocketMode = info->flags & ROCKET_MODE_MASK;
838 if ((info->flags & ROCKET_RTS_TOGGLE)
839 || (rocketMode == ROCKET_MODE_RS485))
844 sSetRTS(&info->channel);
846 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
847 switch (rocketMode) {
848 case ROCKET_MODE_RS485:
849 sSetInterfaceMode(cp, InterfaceModeRS485);
851 case ROCKET_MODE_RS422:
852 sSetInterfaceMode(cp, InterfaceModeRS422);
854 case ROCKET_MODE_RS232:
856 if (info->flags & ROCKET_RTS_TOGGLE)
857 sSetInterfaceMode(cp, InterfaceModeRS232T);
859 sSetInterfaceMode(cp, InterfaceModeRS232);
865 /* info->count is considered critical, protected by spinlocks. */
866 static int block_til_ready(struct tty_struct *tty, struct file *filp,
869 DECLARE_WAITQUEUE(wait, current);
871 int do_clocal = 0, extra_count = 0;
875 * If the device is in the middle of being closed, then block
876 * until it's done, and then try again.
878 if (tty_hung_up_p(filp))
879 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
880 if (info->flags & ROCKET_CLOSING) {
881 if (wait_for_completion_interruptible(&info->close_wait))
883 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
887 * If non-blocking mode is set, or the port is not enabled,
888 * then make the check up front and then exit.
890 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
891 info->flags |= ROCKET_NORMAL_ACTIVE;
894 if (tty->termios->c_cflag & CLOCAL)
898 * Block waiting for the carrier detect and the line to become free. While we are in
899 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
900 * We restore it upon exit, either normal or abnormal.
903 add_wait_queue(&info->open_wait, &wait);
904 #ifdef ROCKET_DEBUG_OPEN
905 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
907 spin_lock_irqsave(&info->slock, flags);
909 #ifdef ROCKET_DISABLE_SIMUSAGE
910 info->flags |= ROCKET_NORMAL_ACTIVE;
912 if (!tty_hung_up_p(filp)) {
917 info->blocked_open++;
919 spin_unlock_irqrestore(&info->slock, flags);
922 if (tty->termios->c_cflag & CBAUD) {
923 sSetDTR(&info->channel);
924 sSetRTS(&info->channel);
926 set_current_state(TASK_INTERRUPTIBLE);
927 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
928 if (info->flags & ROCKET_HUP_NOTIFY)
931 retval = -ERESTARTSYS;
934 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
936 if (signal_pending(current)) {
937 retval = -ERESTARTSYS;
940 #ifdef ROCKET_DEBUG_OPEN
941 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
942 info->line, info->count, info->flags);
944 schedule(); /* Don't hold spinlock here, will hang PC */
946 __set_current_state(TASK_RUNNING);
947 remove_wait_queue(&info->open_wait, &wait);
949 spin_lock_irqsave(&info->slock, flags);
953 info->blocked_open--;
955 spin_unlock_irqrestore(&info->slock, flags);
957 #ifdef ROCKET_DEBUG_OPEN
958 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
959 info->line, info->count);
963 info->flags |= ROCKET_NORMAL_ACTIVE;
968 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
969 * port's r_port struct. Initializes the port hardware.
971 static int rp_open(struct tty_struct *tty, struct file *filp)
974 int line = 0, retval;
979 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
982 page = __get_free_page(GFP_KERNEL);
986 if (info->flags & ROCKET_CLOSING) {
987 retval = wait_for_completion_interruptible(&info->close_wait);
991 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
995 * We must not sleep from here until the port is marked fully in use.
1000 info->xmit_buf = (unsigned char *) page;
1002 tty->driver_data = info;
1005 if (info->count++ == 0) {
1006 atomic_inc(&rp_num_ports_open);
1008 #ifdef ROCKET_DEBUG_OPEN
1009 printk(KERN_INFO "rocket mod++ = %d...\n",
1010 atomic_read(&rp_num_ports_open));
1013 #ifdef ROCKET_DEBUG_OPEN
1014 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1018 * Info->count is now 1; so it's safe to sleep now.
1020 if ((info->flags & ROCKET_INITIALIZED) == 0) {
1021 cp = &info->channel;
1022 sSetRxTrigger(cp, TRIG_1);
1023 if (sGetChanStatus(cp) & CD_ACT)
1024 info->cd_status = 1;
1026 info->cd_status = 0;
1027 sDisRxStatusMode(cp);
1031 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1032 sSetRxTrigger(cp, TRIG_1);
1035 sDisRxStatusMode(cp);
1039 sDisTxSoftFlowCtl(cp);
1044 info->flags |= ROCKET_INITIALIZED;
1047 * Set up the tty->alt_speed kludge
1049 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1050 info->tty->alt_speed = 57600;
1051 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1052 info->tty->alt_speed = 115200;
1053 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1054 info->tty->alt_speed = 230400;
1055 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1056 info->tty->alt_speed = 460800;
1058 configure_r_port(info, NULL);
1059 if (tty->termios->c_cflag & CBAUD) {
1064 /* Starts (or resets) the maint polling loop */
1065 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1067 retval = block_til_ready(tty, filp, info);
1069 #ifdef ROCKET_DEBUG_OPEN
1070 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1078 * Exception handler that closes a serial port. info->count is considered critical.
1080 static void rp_close(struct tty_struct *tty, struct file *filp)
1082 struct r_port *info = (struct r_port *) tty->driver_data;
1083 unsigned long flags;
1087 if (rocket_paranoia_check(info, "rp_close"))
1090 #ifdef ROCKET_DEBUG_OPEN
1091 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1094 if (tty_hung_up_p(filp))
1096 spin_lock_irqsave(&info->slock, flags);
1098 if ((tty->count == 1) && (info->count != 1)) {
1100 * Uh, oh. tty->count is 1, which means that the tty
1101 * structure will be freed. Info->count should always
1102 * be one in these conditions. If it's greater than
1103 * one, we've got real problems, since it means the
1104 * serial port won't be shutdown.
1106 printk(KERN_WARNING "rp_close: bad serial port count; "
1107 "tty->count is 1, info->count is %d\n", info->count);
1110 if (--info->count < 0) {
1111 printk(KERN_WARNING "rp_close: bad serial port count for "
1112 "ttyR%d: %d\n", info->line, info->count);
1116 spin_unlock_irqrestore(&info->slock, flags);
1119 info->flags |= ROCKET_CLOSING;
1120 spin_unlock_irqrestore(&info->slock, flags);
1122 cp = &info->channel;
1125 * Notify the line discpline to only process XON/XOFF characters
1130 * If transmission was throttled by the application request,
1131 * just flush the xmit buffer.
1133 if (tty->flow_stopped)
1134 rp_flush_buffer(tty);
1137 * Wait for the transmit buffer to clear
1139 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1140 tty_wait_until_sent(tty, info->closing_wait);
1142 * Before we drop DTR, make sure the UART transmitter
1143 * has completely drained; this is especially
1144 * important if there is a transmit FIFO!
1146 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1149 rp_wait_until_sent(tty, timeout);
1150 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1153 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1155 sDisTxSoftFlowCtl(cp);
1163 rp_flush_buffer(tty);
1165 tty_ldisc_flush(tty);
1167 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1169 if (info->blocked_open) {
1170 if (info->close_delay) {
1171 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1173 wake_up_interruptible(&info->open_wait);
1175 if (info->xmit_buf) {
1176 free_page((unsigned long) info->xmit_buf);
1177 info->xmit_buf = NULL;
1180 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1182 complete_all(&info->close_wait);
1183 atomic_dec(&rp_num_ports_open);
1185 #ifdef ROCKET_DEBUG_OPEN
1186 printk(KERN_INFO "rocket mod-- = %d...\n",
1187 atomic_read(&rp_num_ports_open));
1188 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1193 static void rp_set_termios(struct tty_struct *tty,
1194 struct ktermios *old_termios)
1196 struct r_port *info = (struct r_port *) tty->driver_data;
1200 if (rocket_paranoia_check(info, "rp_set_termios"))
1203 cflag = tty->termios->c_cflag;
1206 * This driver doesn't support CS5 or CS6
1208 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1209 tty->termios->c_cflag =
1210 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1212 tty->termios->c_cflag &= ~CMSPAR;
1214 configure_r_port(info, old_termios);
1216 cp = &info->channel;
1218 /* Handle transition to B0 status */
1219 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1224 /* Handle transition away from B0 status */
1225 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1226 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1231 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1232 tty->hw_stopped = 0;
1237 static void rp_break(struct tty_struct *tty, int break_state)
1239 struct r_port *info = (struct r_port *) tty->driver_data;
1240 unsigned long flags;
1242 if (rocket_paranoia_check(info, "rp_break"))
1245 spin_lock_irqsave(&info->slock, flags);
1246 if (break_state == -1)
1247 sSendBreak(&info->channel);
1249 sClrBreak(&info->channel);
1250 spin_unlock_irqrestore(&info->slock, flags);
1254 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1255 * the UPCI boards was added, it was decided to make this a function because
1256 * the macro was getting too complicated. All cases except the first one
1257 * (UPCIRingInd) are taken directly from the original macro.
1259 static int sGetChanRI(CHANNEL_T * ChP)
1261 CONTROLLER_t *CtlP = ChP->CtlP;
1262 int ChanNum = ChP->ChanNum;
1265 if (CtlP->UPCIRingInd)
1266 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1267 else if (CtlP->AltChanRingIndicator)
1268 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1269 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1270 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1275 /********************************************************************************************/
1276 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1279 * Returns the state of the serial modem control lines. These next 2 functions
1280 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1282 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1284 struct r_port *info = (struct r_port *)tty->driver_data;
1285 unsigned int control, result, ChanStatus;
1287 ChanStatus = sGetChanStatusLo(&info->channel);
1288 control = info->channel.TxControl[3];
1289 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1290 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1291 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1292 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1293 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1294 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1300 * Sets the modem control lines
1302 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1303 unsigned int set, unsigned int clear)
1305 struct r_port *info = (struct r_port *)tty->driver_data;
1307 if (set & TIOCM_RTS)
1308 info->channel.TxControl[3] |= SET_RTS;
1309 if (set & TIOCM_DTR)
1310 info->channel.TxControl[3] |= SET_DTR;
1311 if (clear & TIOCM_RTS)
1312 info->channel.TxControl[3] &= ~SET_RTS;
1313 if (clear & TIOCM_DTR)
1314 info->channel.TxControl[3] &= ~SET_DTR;
1316 out32(info->channel.IndexAddr, info->channel.TxControl);
1320 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1322 struct rocket_config tmp;
1326 memset(&tmp, 0, sizeof (tmp));
1327 tmp.line = info->line;
1328 tmp.flags = info->flags;
1329 tmp.close_delay = info->close_delay;
1330 tmp.closing_wait = info->closing_wait;
1331 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1333 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1338 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1340 struct rocket_config new_serial;
1342 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1345 if (!capable(CAP_SYS_ADMIN))
1347 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1349 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1350 configure_r_port(info, NULL);
1354 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1355 info->close_delay = new_serial.close_delay;
1356 info->closing_wait = new_serial.closing_wait;
1358 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1359 info->tty->alt_speed = 57600;
1360 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1361 info->tty->alt_speed = 115200;
1362 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1363 info->tty->alt_speed = 230400;
1364 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1365 info->tty->alt_speed = 460800;
1367 configure_r_port(info, NULL);
1372 * This function fills in a rocket_ports struct with information
1373 * about what boards/ports are in the system. This info is passed
1374 * to user space. See setrocket.c where the info is used to create
1375 * the /dev/ttyRx ports.
1377 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1379 struct rocket_ports tmp;
1384 memset(&tmp, 0, sizeof (tmp));
1385 tmp.tty_major = rocket_driver->major;
1387 for (board = 0; board < 4; board++) {
1388 tmp.rocketModel[board].model = rocketModel[board].model;
1389 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1390 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1391 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1392 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1394 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1399 static int reset_rm2(struct r_port *info, void __user *arg)
1403 if (!capable(CAP_SYS_ADMIN))
1406 if (copy_from_user(&reset, arg, sizeof (int)))
1411 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1412 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1415 if (info->ctlp->BusType == isISA)
1416 sModemReset(info->ctlp, info->chan, reset);
1418 sPCIModemReset(info->ctlp, info->chan, reset);
1423 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1425 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1430 /* IOCTL call handler into the driver */
1431 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1432 unsigned int cmd, unsigned long arg)
1434 struct r_port *info = (struct r_port *) tty->driver_data;
1435 void __user *argp = (void __user *)arg;
1438 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1444 case RCKP_GET_STRUCT:
1445 if (copy_to_user(argp, info, sizeof (struct r_port)))
1448 case RCKP_GET_CONFIG:
1449 ret = get_config(info, argp);
1451 case RCKP_SET_CONFIG:
1452 ret = set_config(info, argp);
1454 case RCKP_GET_PORTS:
1455 ret = get_ports(info, argp);
1457 case RCKP_RESET_RM2:
1458 ret = reset_rm2(info, argp);
1460 case RCKP_GET_VERSION:
1461 ret = get_version(info, argp);
1470 static void rp_send_xchar(struct tty_struct *tty, char ch)
1472 struct r_port *info = (struct r_port *) tty->driver_data;
1475 if (rocket_paranoia_check(info, "rp_send_xchar"))
1478 cp = &info->channel;
1480 sWriteTxPrioByte(cp, ch);
1482 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1485 static void rp_throttle(struct tty_struct *tty)
1487 struct r_port *info = (struct r_port *) tty->driver_data;
1490 #ifdef ROCKET_DEBUG_THROTTLE
1491 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1492 tty->ldisc.chars_in_buffer(tty));
1495 if (rocket_paranoia_check(info, "rp_throttle"))
1498 cp = &info->channel;
1500 rp_send_xchar(tty, STOP_CHAR(tty));
1502 sClrRTS(&info->channel);
1505 static void rp_unthrottle(struct tty_struct *tty)
1507 struct r_port *info = (struct r_port *) tty->driver_data;
1509 #ifdef ROCKET_DEBUG_THROTTLE
1510 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1511 tty->ldisc.chars_in_buffer(tty));
1514 if (rocket_paranoia_check(info, "rp_throttle"))
1517 cp = &info->channel;
1519 rp_send_xchar(tty, START_CHAR(tty));
1521 sSetRTS(&info->channel);
1525 * ------------------------------------------------------------
1526 * rp_stop() and rp_start()
1528 * This routines are called before setting or resetting tty->stopped.
1529 * They enable or disable transmitter interrupts, as necessary.
1530 * ------------------------------------------------------------
1532 static void rp_stop(struct tty_struct *tty)
1534 struct r_port *info = (struct r_port *) tty->driver_data;
1536 #ifdef ROCKET_DEBUG_FLOW
1537 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1538 info->xmit_cnt, info->xmit_fifo_room);
1541 if (rocket_paranoia_check(info, "rp_stop"))
1544 if (sGetTxCnt(&info->channel))
1545 sDisTransmit(&info->channel);
1548 static void rp_start(struct tty_struct *tty)
1550 struct r_port *info = (struct r_port *) tty->driver_data;
1552 #ifdef ROCKET_DEBUG_FLOW
1553 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1554 info->xmit_cnt, info->xmit_fifo_room);
1557 if (rocket_paranoia_check(info, "rp_stop"))
1560 sEnTransmit(&info->channel);
1561 set_bit((info->aiop * 8) + info->chan,
1562 (void *) &xmit_flags[info->board]);
1566 * rp_wait_until_sent() --- wait until the transmitter is empty
1568 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1570 struct r_port *info = (struct r_port *) tty->driver_data;
1572 unsigned long orig_jiffies;
1573 int check_time, exit_time;
1576 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1579 cp = &info->channel;
1581 orig_jiffies = jiffies;
1582 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1583 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1585 printk(KERN_INFO "cps=%d...\n", info->cps);
1588 txcnt = sGetTxCnt(cp);
1590 if (sGetChanStatusLo(cp) & TXSHRMT)
1592 check_time = (HZ / info->cps) / 5;
1594 check_time = HZ * txcnt / info->cps;
1597 exit_time = orig_jiffies + timeout - jiffies;
1600 if (exit_time < check_time)
1601 check_time = exit_time;
1603 if (check_time == 0)
1605 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1606 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1607 jiffies, check_time);
1609 msleep_interruptible(jiffies_to_msecs(check_time));
1610 if (signal_pending(current))
1613 __set_current_state(TASK_RUNNING);
1614 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1615 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1620 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1622 static void rp_hangup(struct tty_struct *tty)
1625 struct r_port *info = (struct r_port *) tty->driver_data;
1627 if (rocket_paranoia_check(info, "rp_hangup"))
1630 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1631 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1633 rp_flush_buffer(tty);
1634 if (info->flags & ROCKET_CLOSING)
1637 atomic_dec(&rp_num_ports_open);
1638 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1641 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1644 cp = &info->channel;
1647 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1649 sDisTxSoftFlowCtl(cp);
1651 info->flags &= ~ROCKET_INITIALIZED;
1653 wake_up_interruptible(&info->open_wait);
1657 * Exception handler - write char routine. The RocketPort driver uses a
1658 * double-buffering strategy, with the twist that if the in-memory CPU
1659 * buffer is empty, and there's space in the transmit FIFO, the
1660 * writing routines will write directly to transmit FIFO.
1661 * Write buffer and counters protected by spinlocks
1663 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1665 struct r_port *info = (struct r_port *) tty->driver_data;
1667 unsigned long flags;
1669 if (rocket_paranoia_check(info, "rp_put_char"))
1673 * Grab the port write mutex, locking out other processes that try to
1674 * write to this port
1676 mutex_lock(&info->write_mtx);
1678 #ifdef ROCKET_DEBUG_WRITE
1679 printk(KERN_INFO "rp_put_char %c...\n", ch);
1682 spin_lock_irqsave(&info->slock, flags);
1683 cp = &info->channel;
1685 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1686 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1688 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1689 info->xmit_buf[info->xmit_head++] = ch;
1690 info->xmit_head &= XMIT_BUF_SIZE - 1;
1692 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1694 sOutB(sGetTxRxDataIO(cp), ch);
1695 info->xmit_fifo_room--;
1697 spin_unlock_irqrestore(&info->slock, flags);
1698 mutex_unlock(&info->write_mtx);
1702 * Exception handler - write routine, called when user app writes to the device.
1703 * A per port write mutex is used to protect from another process writing to
1704 * this port at the same time. This other process could be running on the other CPU
1705 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1706 * Spinlocks protect the info xmit members.
1708 static int rp_write(struct tty_struct *tty,
1709 const unsigned char *buf, int count)
1711 struct r_port *info = (struct r_port *) tty->driver_data;
1713 const unsigned char *b;
1715 unsigned long flags;
1717 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1720 if (mutex_lock_interruptible(&info->write_mtx))
1721 return -ERESTARTSYS;
1723 #ifdef ROCKET_DEBUG_WRITE
1724 printk(KERN_INFO "rp_write %d chars...\n", count);
1726 cp = &info->channel;
1728 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1729 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1732 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1733 * into FIFO. Use the write queue for temp storage.
1735 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1736 c = min(count, info->xmit_fifo_room);
1739 /* Push data into FIFO, 2 bytes at a time */
1740 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1742 /* If there is a byte remaining, write it */
1744 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1750 spin_lock_irqsave(&info->slock, flags);
1751 info->xmit_fifo_room -= c;
1752 spin_unlock_irqrestore(&info->slock, flags);
1755 /* If count is zero, we wrote it all and are done */
1759 /* Write remaining data into the port's xmit_buf */
1761 if (!info->tty) /* Seemingly obligatory check... */
1764 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1769 memcpy(info->xmit_buf + info->xmit_head, b, c);
1771 spin_lock_irqsave(&info->slock, flags);
1773 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1774 info->xmit_cnt += c;
1775 spin_unlock_irqrestore(&info->slock, flags);
1782 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1783 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1786 if (info->xmit_cnt < WAKEUP_CHARS) {
1788 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1789 wake_up_interruptible(&tty->poll_wait);
1792 mutex_unlock(&info->write_mtx);
1797 * Return the number of characters that can be sent. We estimate
1798 * only using the in-memory transmit buffer only, and ignore the
1799 * potential space in the transmit FIFO.
1801 static int rp_write_room(struct tty_struct *tty)
1803 struct r_port *info = (struct r_port *) tty->driver_data;
1806 if (rocket_paranoia_check(info, "rp_write_room"))
1809 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1812 #ifdef ROCKET_DEBUG_WRITE
1813 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1819 * Return the number of characters in the buffer. Again, this only
1820 * counts those characters in the in-memory transmit buffer.
1822 static int rp_chars_in_buffer(struct tty_struct *tty)
1824 struct r_port *info = (struct r_port *) tty->driver_data;
1827 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1830 cp = &info->channel;
1832 #ifdef ROCKET_DEBUG_WRITE
1833 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1835 return info->xmit_cnt;
1839 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1840 * r_port struct for the port. Note that spinlock are used to protect info members,
1841 * do not call this function if the spinlock is already held.
1843 static void rp_flush_buffer(struct tty_struct *tty)
1845 struct r_port *info = (struct r_port *) tty->driver_data;
1847 unsigned long flags;
1849 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1852 spin_lock_irqsave(&info->slock, flags);
1853 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1854 spin_unlock_irqrestore(&info->slock, flags);
1856 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1857 wake_up_interruptible(&tty->poll_wait);
1861 cp = &info->channel;
1867 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1868 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1871 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1874 * Called when a PCI card is found. Retrieves and stores model information,
1875 * init's aiopic and serial port hardware.
1876 * Inputs: i is the board number (0-n)
1878 static __init int register_PCI(int i, struct pci_dev *dev)
1880 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1881 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1882 char *str, *board_type;
1886 int altChanRingIndicator = 0;
1887 int ports_per_aiop = 8;
1888 WordIO_t ConfigIO = 0;
1889 ByteIO_t UPCIRingInd = 0;
1891 if (!dev || pci_enable_device(dev))
1894 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1896 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1897 rocketModel[i].loadrm2 = 0;
1898 rocketModel[i].startingPortNumber = nextLineNumber;
1900 /* Depending on the model, set up some config variables */
1901 switch (dev->device) {
1902 case PCI_DEVICE_ID_RP4QUAD:
1906 rocketModel[i].model = MODEL_RP4QUAD;
1907 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1908 rocketModel[i].numPorts = 4;
1910 case PCI_DEVICE_ID_RP8OCTA:
1913 rocketModel[i].model = MODEL_RP8OCTA;
1914 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1915 rocketModel[i].numPorts = 8;
1917 case PCI_DEVICE_ID_URP8OCTA:
1920 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1921 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1922 rocketModel[i].numPorts = 8;
1924 case PCI_DEVICE_ID_RP8INTF:
1927 rocketModel[i].model = MODEL_RP8INTF;
1928 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1929 rocketModel[i].numPorts = 8;
1931 case PCI_DEVICE_ID_URP8INTF:
1934 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1935 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1936 rocketModel[i].numPorts = 8;
1938 case PCI_DEVICE_ID_RP8J:
1941 rocketModel[i].model = MODEL_RP8J;
1942 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1943 rocketModel[i].numPorts = 8;
1945 case PCI_DEVICE_ID_RP4J:
1949 rocketModel[i].model = MODEL_RP4J;
1950 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1951 rocketModel[i].numPorts = 4;
1953 case PCI_DEVICE_ID_RP8SNI:
1954 str = "8 (DB78 Custom)";
1956 rocketModel[i].model = MODEL_RP8SNI;
1957 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1958 rocketModel[i].numPorts = 8;
1960 case PCI_DEVICE_ID_RP16SNI:
1961 str = "16 (DB78 Custom)";
1963 rocketModel[i].model = MODEL_RP16SNI;
1964 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1965 rocketModel[i].numPorts = 16;
1967 case PCI_DEVICE_ID_RP16INTF:
1970 rocketModel[i].model = MODEL_RP16INTF;
1971 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1972 rocketModel[i].numPorts = 16;
1974 case PCI_DEVICE_ID_URP16INTF:
1977 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1978 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1979 rocketModel[i].numPorts = 16;
1981 case PCI_DEVICE_ID_CRP16INTF:
1984 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1985 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1986 rocketModel[i].numPorts = 16;
1988 case PCI_DEVICE_ID_RP32INTF:
1991 rocketModel[i].model = MODEL_RP32INTF;
1992 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1993 rocketModel[i].numPorts = 32;
1995 case PCI_DEVICE_ID_URP32INTF:
1998 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1999 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2000 rocketModel[i].numPorts = 32;
2002 case PCI_DEVICE_ID_RPP4:
2003 str = "Plus Quadcable";
2006 altChanRingIndicator++;
2008 rocketModel[i].model = MODEL_RPP4;
2009 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2010 rocketModel[i].numPorts = 4;
2012 case PCI_DEVICE_ID_RPP8:
2013 str = "Plus Octacable";
2016 altChanRingIndicator++;
2018 rocketModel[i].model = MODEL_RPP8;
2019 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2020 rocketModel[i].numPorts = 8;
2022 case PCI_DEVICE_ID_RP2_232:
2023 str = "Plus 2 (RS-232)";
2026 altChanRingIndicator++;
2028 rocketModel[i].model = MODEL_RP2_232;
2029 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2030 rocketModel[i].numPorts = 2;
2032 case PCI_DEVICE_ID_RP2_422:
2033 str = "Plus 2 (RS-422)";
2036 altChanRingIndicator++;
2038 rocketModel[i].model = MODEL_RP2_422;
2039 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2040 rocketModel[i].numPorts = 2;
2042 case PCI_DEVICE_ID_RP6M:
2048 /* If revision is 1, the rocketmodem flash must be loaded.
2049 * If it is 2 it is a "socketed" version. */
2050 if (dev->revision == 1) {
2051 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2052 rocketModel[i].loadrm2 = 1;
2054 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2057 rocketModel[i].model = MODEL_RP6M;
2058 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2059 rocketModel[i].numPorts = 6;
2061 case PCI_DEVICE_ID_RP4M:
2065 if (dev->revision == 1) {
2066 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2067 rocketModel[i].loadrm2 = 1;
2069 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2072 rocketModel[i].model = MODEL_RP4M;
2073 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2074 rocketModel[i].numPorts = 4;
2077 str = "(unknown/unsupported)";
2083 * Check for UPCI boards.
2086 switch (dev->device) {
2087 case PCI_DEVICE_ID_URP32INTF:
2088 case PCI_DEVICE_ID_URP8INTF:
2089 case PCI_DEVICE_ID_URP16INTF:
2090 case PCI_DEVICE_ID_CRP16INTF:
2091 case PCI_DEVICE_ID_URP8OCTA:
2092 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2093 ConfigIO = pci_resource_start(dev, 1);
2094 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2095 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2098 * Check for octa or quad cable.
2101 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2102 PCI_GPIO_CTRL_8PORT)) {
2105 rocketModel[i].numPorts = 4;
2109 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2112 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2113 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2114 rocketModel[i].numPorts = 8;
2115 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2116 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2117 ConfigIO = pci_resource_start(dev, 1);
2118 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2120 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2123 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2124 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2125 rocketModel[i].numPorts = 4;
2126 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2127 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2128 ConfigIO = pci_resource_start(dev, 1);
2129 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2135 switch (rcktpt_type[i]) {
2136 case ROCKET_TYPE_MODEM:
2137 board_type = "RocketModem";
2139 case ROCKET_TYPE_MODEMII:
2140 board_type = "RocketModem II";
2142 case ROCKET_TYPE_MODEMIII:
2143 board_type = "RocketModem III";
2146 board_type = "RocketPort";
2151 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2152 rp_baud_base[i] = 921600;
2155 * If support_low_speed is set, use the slow clock
2156 * prescale, which supports 50 bps
2158 if (support_low_speed) {
2159 /* mod 9 (divide by 10) prescale */
2160 sClockPrescale = 0x19;
2161 rp_baud_base[i] = 230400;
2163 /* mod 4 (devide by 5) prescale */
2164 sClockPrescale = 0x14;
2165 rp_baud_base[i] = 460800;
2169 for (aiop = 0; aiop < max_num_aiops; aiop++)
2170 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2171 ctlp = sCtlNumToCtlPtr(i);
2172 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2173 for (aiop = 0; aiop < max_num_aiops; aiop++)
2174 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2176 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2177 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2178 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2179 rocketModel[i].startingPortNumber,
2180 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2182 if (num_aiops <= 0) {
2183 rcktpt_io_addr[i] = 0;
2188 /* Reset the AIOPIC, init the serial ports */
2189 for (aiop = 0; aiop < num_aiops; aiop++) {
2190 sResetAiopByNum(ctlp, aiop);
2191 num_chan = ports_per_aiop;
2192 for (chan = 0; chan < num_chan; chan++)
2193 init_r_port(i, aiop, chan, dev);
2196 /* Rocket modems must be reset */
2197 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2198 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2199 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2200 num_chan = ports_per_aiop;
2201 for (chan = 0; chan < num_chan; chan++)
2202 sPCIModemReset(ctlp, chan, 1);
2204 for (chan = 0; chan < num_chan; chan++)
2205 sPCIModemReset(ctlp, chan, 0);
2207 rmSpeakerReset(ctlp, rocketModel[i].model);
2213 * Probes for PCI cards, inits them if found
2214 * Input: board_found = number of ISA boards already found, or the
2215 * starting board number
2216 * Returns: Number of PCI boards found
2218 static int __init init_PCI(int boards_found)
2220 struct pci_dev *dev = NULL;
2223 /* Work through the PCI device list, pulling out ours */
2224 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2225 if (register_PCI(count + boards_found, dev))
2231 #endif /* CONFIG_PCI */
2234 * Probes for ISA cards
2235 * Input: i = the board number to look for
2236 * Returns: 1 if board found, 0 else
2238 static int __init init_ISA(int i)
2240 int num_aiops, num_chan = 0, total_num_chan = 0;
2242 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2246 /* If io_addr is zero, no board configured */
2247 if (rcktpt_io_addr[i] == 0)
2250 /* Reserve the IO region */
2251 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2252 printk(KERN_ERR "Unable to reserve IO region for configured "
2253 "ISA RocketPort at address 0x%lx, board not "
2254 "installed...\n", rcktpt_io_addr[i]);
2255 rcktpt_io_addr[i] = 0;
2259 ctlp = sCtlNumToCtlPtr(i);
2261 ctlp->boardType = rcktpt_type[i];
2263 switch (rcktpt_type[i]) {
2264 case ROCKET_TYPE_PC104:
2265 type_string = "(PC104)";
2267 case ROCKET_TYPE_MODEM:
2268 type_string = "(RocketModem)";
2270 case ROCKET_TYPE_MODEMII:
2271 type_string = "(RocketModem II)";
2279 * If support_low_speed is set, use the slow clock prescale,
2280 * which supports 50 bps
2282 if (support_low_speed) {
2283 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2284 rp_baud_base[i] = 230400;
2286 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2287 rp_baud_base[i] = 460800;
2290 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2291 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2293 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2295 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2296 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2297 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2300 /* If something went wrong initing the AIOP's release the ISA IO memory */
2301 if (num_aiops <= 0) {
2302 release_region(rcktpt_io_addr[i], 64);
2303 rcktpt_io_addr[i] = 0;
2307 rocketModel[i].startingPortNumber = nextLineNumber;
2309 for (aiop = 0; aiop < num_aiops; aiop++) {
2310 sResetAiopByNum(ctlp, aiop);
2311 sEnAiop(ctlp, aiop);
2312 num_chan = sGetAiopNumChan(ctlp, aiop);
2313 total_num_chan += num_chan;
2314 for (chan = 0; chan < num_chan; chan++)
2315 init_r_port(i, aiop, chan, NULL);
2318 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2319 num_chan = sGetAiopNumChan(ctlp, 0);
2320 total_num_chan = num_chan;
2321 for (chan = 0; chan < num_chan; chan++)
2322 sModemReset(ctlp, chan, 1);
2324 for (chan = 0; chan < num_chan; chan++)
2325 sModemReset(ctlp, chan, 0);
2327 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2329 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2331 rocketModel[i].numPorts = total_num_chan;
2332 rocketModel[i].model = MODEL_ISA;
2334 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2335 i, rcktpt_io_addr[i], num_aiops, type_string);
2337 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2338 rocketModel[i].modelString,
2339 rocketModel[i].startingPortNumber,
2340 rocketModel[i].startingPortNumber +
2341 rocketModel[i].numPorts - 1);
2346 static const struct tty_operations rocket_ops = {
2350 .put_char = rp_put_char,
2351 .write_room = rp_write_room,
2352 .chars_in_buffer = rp_chars_in_buffer,
2353 .flush_buffer = rp_flush_buffer,
2355 .throttle = rp_throttle,
2356 .unthrottle = rp_unthrottle,
2357 .set_termios = rp_set_termios,
2360 .hangup = rp_hangup,
2361 .break_ctl = rp_break,
2362 .send_xchar = rp_send_xchar,
2363 .wait_until_sent = rp_wait_until_sent,
2364 .tiocmget = rp_tiocmget,
2365 .tiocmset = rp_tiocmset,
2369 * The module "startup" routine; it's run when the module is loaded.
2371 static int __init rp_init(void)
2373 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2375 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2376 ROCKET_VERSION, ROCKET_DATE);
2378 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2383 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2384 * zero, use the default controller IO address of board1 + 0x40.
2387 if (controller == 0)
2388 controller = board1 + 0x40;
2390 controller = 0; /* Used as a flag, meaning no ISA boards */
2393 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2394 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2395 printk(KERN_ERR "Unable to reserve IO region for first "
2396 "configured ISA RocketPort controller 0x%lx. "
2397 "Driver exiting\n", controller);
2402 /* Store ISA variable retrieved from command line or .conf file. */
2403 rcktpt_io_addr[0] = board1;
2404 rcktpt_io_addr[1] = board2;
2405 rcktpt_io_addr[2] = board3;
2406 rcktpt_io_addr[3] = board4;
2408 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2409 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2410 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2411 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2412 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2413 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2414 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2415 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2418 * Set up the tty driver structure and then register this
2419 * driver with the tty layer.
2422 rocket_driver->owner = THIS_MODULE;
2423 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2424 rocket_driver->name = "ttyR";
2425 rocket_driver->driver_name = "Comtrol RocketPort";
2426 rocket_driver->major = TTY_ROCKET_MAJOR;
2427 rocket_driver->minor_start = 0;
2428 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2429 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2430 rocket_driver->init_termios = tty_std_termios;
2431 rocket_driver->init_termios.c_cflag =
2432 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2433 rocket_driver->init_termios.c_ispeed = 9600;
2434 rocket_driver->init_termios.c_ospeed = 9600;
2435 #ifdef ROCKET_SOFT_FLOW
2436 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2438 tty_set_operations(rocket_driver, &rocket_ops);
2440 ret = tty_register_driver(rocket_driver);
2442 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2446 #ifdef ROCKET_DEBUG_OPEN
2447 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2451 * OK, let's probe each of the controllers looking for boards. Any boards found
2452 * will be initialized here.
2454 isa_boards_found = 0;
2455 pci_boards_found = 0;
2457 for (i = 0; i < NUM_BOARDS; i++) {
2463 if (isa_boards_found < NUM_BOARDS)
2464 pci_boards_found = init_PCI(isa_boards_found);
2467 max_board = pci_boards_found + isa_boards_found;
2469 if (max_board == 0) {
2470 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2477 tty_unregister_driver(rocket_driver);
2479 put_tty_driver(rocket_driver);
2485 static void rp_cleanup_module(void)
2490 del_timer_sync(&rocket_timer);
2492 retval = tty_unregister_driver(rocket_driver);
2494 printk(KERN_ERR "Error %d while trying to unregister "
2495 "rocketport driver\n", -retval);
2497 for (i = 0; i < MAX_RP_PORTS; i++)
2499 tty_unregister_device(rocket_driver, i);
2503 put_tty_driver(rocket_driver);
2505 for (i = 0; i < NUM_BOARDS; i++) {
2506 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2508 release_region(rcktpt_io_addr[i], 64);
2511 release_region(controller, 4);
2514 /***************************************************************************
2515 Function: sInitController
2516 Purpose: Initialization of controller global registers and controller
2518 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2519 IRQNum,Frequency,PeriodicOnly)
2520 CONTROLLER_T *CtlP; Ptr to controller structure
2521 int CtlNum; Controller number
2522 ByteIO_t MudbacIO; Mudbac base I/O address.
2523 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2524 This list must be in the order the AIOPs will be found on the
2525 controller. Once an AIOP in the list is not found, it is
2526 assumed that there are no more AIOPs on the controller.
2527 int AiopIOListSize; Number of addresses in AiopIOList
2528 int IRQNum; Interrupt Request number. Can be any of the following:
2529 0: Disable global interrupts
2538 Byte_t Frequency: A flag identifying the frequency
2539 of the periodic interrupt, can be any one of the following:
2540 FREQ_DIS - periodic interrupt disabled
2541 FREQ_137HZ - 137 Hertz
2542 FREQ_69HZ - 69 Hertz
2543 FREQ_34HZ - 34 Hertz
2544 FREQ_17HZ - 17 Hertz
2547 If IRQNum is set to 0 the Frequency parameter is
2548 overidden, it is forced to a value of FREQ_DIS.
2549 int PeriodicOnly: 1 if all interrupts except the periodic
2550 interrupt are to be blocked.
2551 0 is both the periodic interrupt and
2552 other channel interrupts are allowed.
2553 If IRQNum is set to 0 the PeriodicOnly parameter is
2554 overidden, it is forced to a value of 0.
2555 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2556 initialization failed.
2559 If periodic interrupts are to be disabled but AIOP interrupts
2560 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2562 If interrupts are to be completely disabled set IRQNum to 0.
2564 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2565 invalid combination.
2567 This function performs initialization of global interrupt modes,
2568 but it does not actually enable global interrupts. To enable
2569 and disable global interrupts use functions sEnGlobalInt() and
2570 sDisGlobalInt(). Enabling of global interrupts is normally not
2571 done until all other initializations are complete.
2573 Even if interrupts are globally enabled, they must also be
2574 individually enabled for each channel that is to generate
2577 Warnings: No range checking on any of the parameters is done.
2579 No context switches are allowed while executing this function.
2581 After this function all AIOPs on the controller are disabled,
2582 they can be enabled with sEnAiop().
2584 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2585 ByteIO_t * AiopIOList, int AiopIOListSize,
2586 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2592 CtlP->AiopIntrBits = aiop_intr_bits;
2593 CtlP->AltChanRingIndicator = 0;
2594 CtlP->CtlNum = CtlNum;
2595 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2596 CtlP->BusType = isISA;
2597 CtlP->MBaseIO = MudbacIO;
2598 CtlP->MReg1IO = MudbacIO + 1;
2599 CtlP->MReg2IO = MudbacIO + 2;
2600 CtlP->MReg3IO = MudbacIO + 3;
2602 CtlP->MReg2 = 0; /* interrupt disable */
2603 CtlP->MReg3 = 0; /* no periodic interrupts */
2605 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2606 CtlP->MReg2 = 0; /* interrupt disable */
2607 CtlP->MReg3 = 0; /* no periodic interrupts */
2609 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2610 CtlP->MReg3 = Frequency; /* set frequency */
2611 if (PeriodicOnly) { /* periodic interrupt only */
2612 CtlP->MReg3 |= PERIODIC_ONLY;
2616 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2617 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2618 sControllerEOI(CtlP); /* clear EOI if warm init */
2621 for (i = done = 0; i < AiopIOListSize; i++) {
2623 CtlP->AiopIO[i] = (WordIO_t) io;
2624 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2625 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2626 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2629 sEnAiop(CtlP, i); /* enable the AIOP */
2630 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2631 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2632 done = 1; /* done looking for AIOPs */
2634 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2635 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2636 sOutB(io + _INDX_DATA, sClockPrescale);
2637 CtlP->NumAiop++; /* bump count of AIOPs */
2639 sDisAiop(CtlP, i); /* disable AIOP */
2642 if (CtlP->NumAiop == 0)
2645 return (CtlP->NumAiop);
2648 /***************************************************************************
2649 Function: sPCIInitController
2650 Purpose: Initialization of controller global registers and controller
2652 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2653 IRQNum,Frequency,PeriodicOnly)
2654 CONTROLLER_T *CtlP; Ptr to controller structure
2655 int CtlNum; Controller number
2656 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2657 This list must be in the order the AIOPs will be found on the
2658 controller. Once an AIOP in the list is not found, it is
2659 assumed that there are no more AIOPs on the controller.
2660 int AiopIOListSize; Number of addresses in AiopIOList
2661 int IRQNum; Interrupt Request number. Can be any of the following:
2662 0: Disable global interrupts
2671 Byte_t Frequency: A flag identifying the frequency
2672 of the periodic interrupt, can be any one of the following:
2673 FREQ_DIS - periodic interrupt disabled
2674 FREQ_137HZ - 137 Hertz
2675 FREQ_69HZ - 69 Hertz
2676 FREQ_34HZ - 34 Hertz
2677 FREQ_17HZ - 17 Hertz
2680 If IRQNum is set to 0 the Frequency parameter is
2681 overidden, it is forced to a value of FREQ_DIS.
2682 int PeriodicOnly: 1 if all interrupts except the periodic
2683 interrupt are to be blocked.
2684 0 is both the periodic interrupt and
2685 other channel interrupts are allowed.
2686 If IRQNum is set to 0 the PeriodicOnly parameter is
2687 overidden, it is forced to a value of 0.
2688 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2689 initialization failed.
2692 If periodic interrupts are to be disabled but AIOP interrupts
2693 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2695 If interrupts are to be completely disabled set IRQNum to 0.
2697 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2698 invalid combination.
2700 This function performs initialization of global interrupt modes,
2701 but it does not actually enable global interrupts. To enable
2702 and disable global interrupts use functions sEnGlobalInt() and
2703 sDisGlobalInt(). Enabling of global interrupts is normally not
2704 done until all other initializations are complete.
2706 Even if interrupts are globally enabled, they must also be
2707 individually enabled for each channel that is to generate
2710 Warnings: No range checking on any of the parameters is done.
2712 No context switches are allowed while executing this function.
2714 After this function all AIOPs on the controller are disabled,
2715 they can be enabled with sEnAiop().
2717 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2718 ByteIO_t * AiopIOList, int AiopIOListSize,
2719 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2720 int PeriodicOnly, int altChanRingIndicator,
2726 CtlP->AltChanRingIndicator = altChanRingIndicator;
2727 CtlP->UPCIRingInd = UPCIRingInd;
2728 CtlP->CtlNum = CtlNum;
2729 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2730 CtlP->BusType = isPCI; /* controller release 1 */
2734 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2735 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2736 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2740 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2741 CtlP->AiopIntrBits = aiop_intr_bits;
2744 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2747 for (i = 0; i < AiopIOListSize; i++) {
2749 CtlP->AiopIO[i] = (WordIO_t) io;
2750 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2752 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2753 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2754 break; /* done looking for AIOPs */
2756 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2757 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2758 sOutB(io + _INDX_DATA, sClockPrescale);
2759 CtlP->NumAiop++; /* bump count of AIOPs */
2762 if (CtlP->NumAiop == 0)
2765 return (CtlP->NumAiop);
2768 /***************************************************************************
2769 Function: sReadAiopID
2770 Purpose: Read the AIOP idenfication number directly from an AIOP.
2771 Call: sReadAiopID(io)
2772 ByteIO_t io: AIOP base I/O address
2773 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2774 is replace by an identifying number.
2775 Flag AIOPID_NULL if no valid AIOP is found
2776 Warnings: No context switches are allowed while executing this function.
2779 static int sReadAiopID(ByteIO_t io)
2781 Byte_t AiopID; /* ID byte from AIOP */
2783 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2784 sOutB(io + _CMD_REG, 0x0);
2785 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2788 else /* AIOP does not exist */
2792 /***************************************************************************
2793 Function: sReadAiopNumChan
2794 Purpose: Read the number of channels available in an AIOP directly from
2796 Call: sReadAiopNumChan(io)
2797 WordIO_t io: AIOP base I/O address
2798 Return: int: The number of channels available
2799 Comments: The number of channels is determined by write/reads from identical
2800 offsets within the SRAM address spaces for channels 0 and 4.
2801 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2802 AIOP, otherwise it is an 8 channel.
2803 Warnings: No context switches are allowed while executing this function.
2805 static int sReadAiopNumChan(WordIO_t io)
2808 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2810 /* write to chan 0 SRAM */
2811 out32((DWordIO_t) io + _INDX_ADDR, R);
2812 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2813 x = sInW(io + _INDX_DATA);
2814 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2815 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2821 /***************************************************************************
2823 Purpose: Initialization of a channel and channel structure
2824 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2825 CONTROLLER_T *CtlP; Ptr to controller structure
2826 CHANNEL_T *ChP; Ptr to channel structure
2827 int AiopNum; AIOP number within controller
2828 int ChanNum; Channel number within AIOP
2829 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2830 number exceeds number of channels available in AIOP.
2831 Comments: This function must be called before a channel can be used.
2832 Warnings: No range checking on any of the parameters is done.
2834 No context switches are allowed while executing this function.
2836 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2847 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2848 return 0; /* exceeds num chans in AIOP */
2850 /* Channel, AIOP, and controller identifiers */
2852 ChP->ChanID = CtlP->AiopID[AiopNum];
2853 ChP->AiopNum = AiopNum;
2854 ChP->ChanNum = ChanNum;
2856 /* Global direct addresses */
2857 AiopIO = CtlP->AiopIO[AiopNum];
2858 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2859 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2860 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2861 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2862 ChP->IndexData = AiopIO + _INDX_DATA;
2864 /* Channel direct addresses */
2865 ChIOOff = AiopIO + ChP->ChanNum * 2;
2866 ChP->TxRxData = ChIOOff + _TD0;
2867 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2868 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2869 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2871 /* Initialize the channel from the RData array */
2872 for (i = 0; i < RDATASIZE; i += 4) {
2874 R[1] = RData[i + 1] + 0x10 * ChanNum;
2875 R[2] = RData[i + 2];
2876 R[3] = RData[i + 3];
2877 out32(ChP->IndexAddr, R);
2881 for (i = 0; i < RREGDATASIZE; i += 4) {
2882 ChR[i] = RRegData[i];
2883 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2884 ChR[i + 2] = RRegData[i + 2];
2885 ChR[i + 3] = RRegData[i + 3];
2888 /* Indexed registers */
2889 ChOff = (Word_t) ChanNum *0x1000;
2891 if (sClockPrescale == 0x14)
2896 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2897 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2898 ChP->BaudDiv[2] = (Byte_t) brd9600;
2899 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2900 out32(ChP->IndexAddr, ChP->BaudDiv);
2902 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2903 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2904 ChP->TxControl[2] = 0;
2905 ChP->TxControl[3] = 0;
2906 out32(ChP->IndexAddr, ChP->TxControl);
2908 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2909 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2910 ChP->RxControl[2] = 0;
2911 ChP->RxControl[3] = 0;
2912 out32(ChP->IndexAddr, ChP->RxControl);
2914 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2915 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2916 ChP->TxEnables[2] = 0;
2917 ChP->TxEnables[3] = 0;
2918 out32(ChP->IndexAddr, ChP->TxEnables);
2920 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2921 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2922 ChP->TxCompare[2] = 0;
2923 ChP->TxCompare[3] = 0;
2924 out32(ChP->IndexAddr, ChP->TxCompare);
2926 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2927 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2928 ChP->TxReplace1[2] = 0;
2929 ChP->TxReplace1[3] = 0;
2930 out32(ChP->IndexAddr, ChP->TxReplace1);
2932 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2933 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2934 ChP->TxReplace2[2] = 0;
2935 ChP->TxReplace2[3] = 0;
2936 out32(ChP->IndexAddr, ChP->TxReplace2);
2938 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2939 ChP->TxFIFO = ChOff + _TX_FIFO;
2941 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2942 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2943 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2944 sOutW(ChP->IndexData, 0);
2945 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2946 ChP->RxFIFO = ChOff + _RX_FIFO;
2948 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2949 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2950 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2951 sOutW(ChP->IndexData, 0);
2952 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2953 sOutW(ChP->IndexData, 0);
2954 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2955 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2956 sOutB(ChP->IndexData, 0);
2957 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2958 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2959 sOutB(ChP->IndexData, 0);
2960 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2961 sEnRxProcessor(ChP); /* start the Rx processor */
2966 /***************************************************************************
2967 Function: sStopRxProcessor
2968 Purpose: Stop the receive processor from processing a channel.
2969 Call: sStopRxProcessor(ChP)
2970 CHANNEL_T *ChP; Ptr to channel structure
2972 Comments: The receive processor can be started again with sStartRxProcessor().
2973 This function causes the receive processor to skip over the
2974 stopped channel. It does not stop it from processing other channels.
2976 Warnings: No context switches are allowed while executing this function.
2978 Do not leave the receive processor stopped for more than one
2981 After calling this function a delay of 4 uS is required to ensure
2982 that the receive processor is no longer processing this channel.
2984 static void sStopRxProcessor(CHANNEL_T * ChP)
2992 out32(ChP->IndexAddr, R);
2995 /***************************************************************************
2996 Function: sFlushRxFIFO
2997 Purpose: Flush the Rx FIFO
2998 Call: sFlushRxFIFO(ChP)
2999 CHANNEL_T *ChP; Ptr to channel structure
3001 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3002 while it is being flushed the receive processor is stopped
3003 and the transmitter is disabled. After these operations a
3004 4 uS delay is done before clearing the pointers to allow
3005 the receive processor to stop. These items are handled inside
3007 Warnings: No context switches are allowed while executing this function.
3009 static void sFlushRxFIFO(CHANNEL_T * ChP)
3012 Byte_t Ch; /* channel number within AIOP */
3013 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
3015 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3016 return; /* don't need to flush */
3019 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3021 sDisRxFIFO(ChP); /* disable it */
3022 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3023 sInB(ChP->IntChan); /* depends on bus i/o timing */
3025 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3026 Ch = (Byte_t) sGetChanNum(ChP);
3027 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3028 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3029 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3030 sOutW(ChP->IndexData, 0);
3031 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3032 sOutW(ChP->IndexData, 0);
3034 sEnRxFIFO(ChP); /* enable Rx FIFO */
3037 /***************************************************************************
3038 Function: sFlushTxFIFO
3039 Purpose: Flush the Tx FIFO
3040 Call: sFlushTxFIFO(ChP)
3041 CHANNEL_T *ChP; Ptr to channel structure
3043 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3044 while it is being flushed the receive processor is stopped
3045 and the transmitter is disabled. After these operations a
3046 4 uS delay is done before clearing the pointers to allow
3047 the receive processor to stop. These items are handled inside
3049 Warnings: No context switches are allowed while executing this function.
3051 static void sFlushTxFIFO(CHANNEL_T * ChP)
3054 Byte_t Ch; /* channel number within AIOP */
3055 int TxEnabled; /* 1 if transmitter enabled */
3057 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3058 return; /* don't need to flush */
3061 if (ChP->TxControl[3] & TX_ENABLE) {
3063 sDisTransmit(ChP); /* disable transmitter */
3065 sStopRxProcessor(ChP); /* stop Rx processor */
3066 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3067 sInB(ChP->IntChan); /* depends on bus i/o timing */
3068 Ch = (Byte_t) sGetChanNum(ChP);
3069 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3070 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3071 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3072 sOutW(ChP->IndexData, 0);
3074 sEnTransmit(ChP); /* enable transmitter */
3075 sStartRxProcessor(ChP); /* restart Rx processor */
3078 /***************************************************************************
3079 Function: sWriteTxPrioByte
3080 Purpose: Write a byte of priority transmit data to a channel
3081 Call: sWriteTxPrioByte(ChP,Data)
3082 CHANNEL_T *ChP; Ptr to channel structure
3083 Byte_t Data; The transmit data byte
3085 Return: int: 1 if the bytes is successfully written, otherwise 0.
3087 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3089 Warnings: No context switches are allowed while executing this function.
3091 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3093 Byte_t DWBuf[4]; /* buffer for double word writes */
3094 Word_t *WordPtr; /* must be far because Win SS != DS */
3095 register DWordIO_t IndexAddr;
3097 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3098 IndexAddr = ChP->IndexAddr;
3099 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3100 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3101 return (0); /* nothing sent */
3103 WordPtr = (Word_t *) (&DWBuf[0]);
3104 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3106 DWBuf[2] = Data; /* data byte value */
3107 out32(IndexAddr, DWBuf); /* write it out */
3109 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3111 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3112 DWBuf[3] = 0; /* priority buffer pointer */
3113 out32(IndexAddr, DWBuf); /* write it out */
3114 } else { /* write it to Tx FIFO */
3116 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3118 return (1); /* 1 byte sent */
3121 /***************************************************************************
3122 Function: sEnInterrupts
3123 Purpose: Enable one or more interrupts for a channel
3124 Call: sEnInterrupts(ChP,Flags)
3125 CHANNEL_T *ChP; Ptr to channel structure
3126 Word_t Flags: Interrupt enable flags, can be any combination
3127 of the following flags:
3128 TXINT_EN: Interrupt on Tx FIFO empty
3129 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3131 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3132 MCINT_EN: Interrupt on modem input change
3133 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3134 Interrupt Channel Register.
3136 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3137 enabled. If an interrupt enable flag is not set in Flags, that
3138 interrupt will not be changed. Interrupts can be disabled with
3139 function sDisInterrupts().
3141 This function sets the appropriate bit for the channel in the AIOP's
3142 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3143 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3145 Interrupts must also be globally enabled before channel interrupts
3146 will be passed on to the host. This is done with function
3149 In some cases it may be desirable to disable interrupts globally but
3150 enable channel interrupts. This would allow the global interrupt
3151 status register to be used to determine which AIOPs need service.
3153 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3155 Byte_t Mask; /* Interrupt Mask Register */
3157 ChP->RxControl[2] |=
3158 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3160 out32(ChP->IndexAddr, ChP->RxControl);
3162 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3164 out32(ChP->IndexAddr, ChP->TxControl);
3166 if (Flags & CHANINT_EN) {
3167 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3168 sOutB(ChP->IntMask, Mask);
3172 /***************************************************************************
3173 Function: sDisInterrupts
3174 Purpose: Disable one or more interrupts for a channel
3175 Call: sDisInterrupts(ChP,Flags)
3176 CHANNEL_T *ChP; Ptr to channel structure
3177 Word_t Flags: Interrupt flags, can be any combination
3178 of the following flags:
3179 TXINT_EN: Interrupt on Tx FIFO empty
3180 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3182 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3183 MCINT_EN: Interrupt on modem input change
3184 CHANINT_EN: Disable channel interrupt signal to the
3185 AIOP's Interrupt Channel Register.
3187 Comments: If an interrupt flag is set in Flags, that interrupt will be
3188 disabled. If an interrupt flag is not set in Flags, that
3189 interrupt will not be changed. Interrupts can be enabled with
3190 function sEnInterrupts().
3192 This function clears the appropriate bit for the channel in the AIOP's
3193 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3194 this channel's bit from being set in the AIOP's Interrupt Channel
3197 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3199 Byte_t Mask; /* Interrupt Mask Register */
3201 ChP->RxControl[2] &=
3202 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3203 out32(ChP->IndexAddr, ChP->RxControl);
3204 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3205 out32(ChP->IndexAddr, ChP->TxControl);
3207 if (Flags & CHANINT_EN) {
3208 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3209 sOutB(ChP->IntMask, Mask);
3213 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3215 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3219 * Not an official SSCI function, but how to reset RocketModems.
3222 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3227 addr = CtlP->AiopIO[0] + 0x400;
3228 val = sInB(CtlP->MReg3IO);
3229 /* if AIOP[1] is not enabled, enable it */
3230 if ((val & 2) == 0) {
3231 val = sInB(CtlP->MReg2IO);
3232 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3233 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3239 sOutB(addr + chan, 0); /* apply or remove reset */
3244 * Not an official SSCI function, but how to reset RocketModems.
3247 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3251 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3254 sOutB(addr + chan, 0); /* apply or remove reset */
3257 /* Resets the speaker controller on RocketModem II and III devices */
3258 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3262 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3263 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3264 addr = CtlP->AiopIO[0] + 0x4F;
3268 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3269 if ((model == MODEL_UPCI_RM3_8PORT)
3270 || (model == MODEL_UPCI_RM3_4PORT)) {
3271 addr = CtlP->AiopIO[0] + 0x88;
3276 /* Returns the line number given the controller (board), aiop and channel number */
3277 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3279 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3283 * Stores the line number associated with a given controller (board), aiop
3284 * and channel number.
3285 * Returns: The line number assigned
3287 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3289 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3290 return (nextLineNumber - 1);