2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
56 #undef ROCKET_DEBUG_IO
58 #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
60 /****** Kernel includes ******/
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/mutex.h>
80 #include <linux/ioport.h>
81 #include <linux/delay.h>
82 #include <linux/completion.h>
83 #include <linux/wait.h>
84 #include <linux/pci.h>
85 #include <linux/uaccess.h>
86 #include <asm/atomic.h>
87 #include <asm/unaligned.h>
88 #include <linux/bitops.h>
89 #include <linux/spinlock.h>
90 #include <linux/init.h>
92 /****** RocketPort includes ******/
94 #include "rocket_int.h"
97 #define ROCKET_VERSION "2.09"
98 #define ROCKET_DATE "12-June-2003"
100 /****** RocketPort Local Variables ******/
102 static void rp_do_poll(unsigned long dummy);
104 static struct tty_driver *rocket_driver;
106 static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
110 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113 static atomic_t rp_num_ports_open; /* Number of serial ports open */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
116 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static int support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
132 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
153 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
154 UPCI_AIOP_INTR_BIT_0,
155 UPCI_AIOP_INTR_BIT_1,
156 UPCI_AIOP_INTR_BIT_2,
160 static Byte_t RData[RDATASIZE] = {
161 0x00, 0x09, 0xf6, 0x82,
162 0x02, 0x09, 0x86, 0xfb,
163 0x04, 0x09, 0x00, 0x0a,
164 0x06, 0x09, 0x01, 0x0a,
165 0x08, 0x09, 0x8a, 0x13,
166 0x0a, 0x09, 0xc5, 0x11,
167 0x0c, 0x09, 0x86, 0x85,
168 0x0e, 0x09, 0x20, 0x0a,
169 0x10, 0x09, 0x21, 0x0a,
170 0x12, 0x09, 0x41, 0xff,
171 0x14, 0x09, 0x82, 0x00,
172 0x16, 0x09, 0x82, 0x7b,
173 0x18, 0x09, 0x8a, 0x7d,
174 0x1a, 0x09, 0x88, 0x81,
175 0x1c, 0x09, 0x86, 0x7a,
176 0x1e, 0x09, 0x84, 0x81,
177 0x20, 0x09, 0x82, 0x7c,
178 0x22, 0x09, 0x0a, 0x0a
181 static Byte_t RRegData[RREGDATASIZE] = {
182 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
183 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
184 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
185 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
186 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
187 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
188 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
189 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
190 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
191 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
192 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
193 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
194 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197 static CONTROLLER_T sController[CTL_SIZE] = {
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208 static Byte_t sBitMapClrTbl[8] = {
209 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212 static Byte_t sBitMapSetTbl[8] = {
213 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216 static int sClockPrescale = 0x14;
219 * Line number is the ttySIx number (x), the Minor number. We
220 * assign them sequentially, starting at zero. The following
221 * array keeps track of the line number assigned to a given board/aiop/channel.
223 static unsigned char lineNumbers[MAX_RP_PORTS];
224 static unsigned long nextLineNumber;
226 /***** RocketPort Static Prototypes *********/
227 static int __init init_ISA(int i);
228 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
229 static void rp_flush_buffer(struct tty_struct *tty);
230 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
231 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
232 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
233 static void rp_start(struct tty_struct *tty);
234 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237 static void sFlushRxFIFO(CHANNEL_T * ChP);
238 static void sFlushTxFIFO(CHANNEL_T * ChP);
239 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
242 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
244 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
245 ByteIO_t * AiopIOList, int AiopIOListSize,
246 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
247 int PeriodicOnly, int altChanRingIndicator,
249 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
250 ByteIO_t * AiopIOList, int AiopIOListSize,
251 int IRQNum, Byte_t Frequency, int PeriodicOnly);
252 static int sReadAiopID(ByteIO_t io);
253 static int sReadAiopNumChan(WordIO_t io);
255 MODULE_AUTHOR("Theodore Ts'o");
256 MODULE_DESCRIPTION("Comtrol RocketPort driver");
257 module_param(board1, ulong, 0);
258 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
259 module_param(board2, ulong, 0);
260 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
261 module_param(board3, ulong, 0);
262 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
263 module_param(board4, ulong, 0);
264 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
265 module_param(controller, ulong, 0);
266 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
267 module_param(support_low_speed, bool, 0);
268 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
269 module_param(modem1, ulong, 0);
270 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
271 module_param(modem2, ulong, 0);
272 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
273 module_param(modem3, ulong, 0);
274 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
275 module_param(modem4, ulong, 0);
276 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
277 module_param_array(pc104_1, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
279 module_param_array(pc104_2, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
281 module_param_array(pc104_3, ulong, NULL, 0);
282 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
283 module_param_array(pc104_4, ulong, NULL, 0);
284 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
286 static int rp_init(void);
287 static void rp_cleanup_module(void);
289 module_init(rp_init);
290 module_exit(rp_cleanup_module);
293 MODULE_LICENSE("Dual BSD/GPL");
295 /*************************************************************************/
296 /* Module code starts here */
298 static inline int rocket_paranoia_check(struct r_port *info,
301 #ifdef ROCKET_PARANOIA_CHECK
304 if (info->magic != RPORT_MAGIC) {
305 printk(KERN_WARNING "Warning: bad magic number for rocketport "
306 "struct in %s\n", routine);
314 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
315 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
318 static void rp_do_receive(struct r_port *info,
319 struct tty_struct *tty,
320 CHANNEL_t * cp, unsigned int ChanStatus)
322 unsigned int CharNStat;
323 int ToRecv, wRecv, space;
326 ToRecv = sGetRxCnt(cp);
327 #ifdef ROCKET_DEBUG_INTR
328 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
334 * if status indicates there are errored characters in the
335 * FIFO, then enter status mode (a word in FIFO holds
336 * character and status).
338 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
339 if (!(ChanStatus & STATMODE)) {
340 #ifdef ROCKET_DEBUG_RECEIVE
341 printk(KERN_INFO "Entering STATMODE...\n");
343 ChanStatus |= STATMODE;
349 * if we previously entered status mode, then read down the
350 * FIFO one word at a time, pulling apart the character and
351 * the status. Update error counters depending on status
353 if (ChanStatus & STATMODE) {
354 #ifdef ROCKET_DEBUG_RECEIVE
355 printk(KERN_INFO "Ignore %x, read %x...\n",
356 info->ignore_status_mask, info->read_status_mask);
361 CharNStat = sInW(sGetTxRxDataIO(cp));
362 #ifdef ROCKET_DEBUG_RECEIVE
363 printk(KERN_INFO "%x...\n", CharNStat);
365 if (CharNStat & STMBREAKH)
366 CharNStat &= ~(STMFRAMEH | STMPARITYH);
367 if (CharNStat & info->ignore_status_mask) {
371 CharNStat &= info->read_status_mask;
372 if (CharNStat & STMBREAKH)
374 else if (CharNStat & STMPARITYH)
376 else if (CharNStat & STMFRAMEH)
378 else if (CharNStat & STMRCVROVRH)
382 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
387 * after we've emptied the FIFO in status mode, turn
388 * status mode back off
390 if (sGetRxCnt(cp) == 0) {
391 #ifdef ROCKET_DEBUG_RECEIVE
392 printk(KERN_INFO "Status mode off.\n");
394 sDisRxStatusMode(cp);
398 * we aren't in status mode, so read down the FIFO two
399 * characters at time by doing repeated word IO
402 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
403 if (space < ToRecv) {
404 #ifdef ROCKET_DEBUG_RECEIVE
405 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
413 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
415 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
417 /* Push the data up to the tty layer */
418 tty_flip_buffer_push(tty);
422 * Serial port transmit data function. Called from the timer polling loop as a
423 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
424 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
425 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
427 static void rp_do_transmit(struct r_port *info)
430 CHANNEL_t *cp = &info->channel;
431 struct tty_struct *tty;
434 #ifdef ROCKET_DEBUG_INTR
435 printk(KERN_DEBUG "%s\n", __func__);
439 if (!info->port.tty) {
440 printk(KERN_WARNING "rp: WARNING %s called with "
441 "info->port.tty==NULL\n", __func__);
442 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
446 spin_lock_irqsave(&info->slock, flags);
447 tty = info->port.tty;
448 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
450 /* Loop sending data to FIFO until done or FIFO full */
452 if (tty->stopped || tty->hw_stopped)
454 c = min(info->xmit_fifo_room, info->xmit_cnt);
455 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
456 if (c <= 0 || info->xmit_fifo_room <= 0)
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
464 info->xmit_fifo_room -= c;
465 #ifdef ROCKET_DEBUG_INTR
466 printk(KERN_INFO "tx %d chars...\n", c);
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
473 if (info->xmit_cnt < WAKEUP_CHARS) {
475 #ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
480 spin_unlock_irqrestore(&info->slock, flags);
482 #ifdef ROCKET_DEBUG_INTR
483 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
484 info->xmit_tail, info->xmit_fifo_room);
489 * Called when a serial port signals it has read data in it's RX FIFO.
490 * It checks what interrupts are pending and services them, including
491 * receiving serial data.
493 static void rp_handle_port(struct r_port *info)
496 struct tty_struct *tty;
497 unsigned int IntMask, ChanStatus;
502 if ((info->flags & ROCKET_INITIALIZED) == 0) {
503 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
504 "info->flags & NOT_INIT\n");
507 if (!info->port.tty) {
508 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
509 "info->port.tty==NULL\n");
513 tty = info->port.tty;
515 IntMask = sGetChanIntID(cp) & info->intmask;
516 #ifdef ROCKET_DEBUG_INTR
517 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
519 ChanStatus = sGetChanStatus(cp);
520 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
521 rp_do_receive(info, tty, cp, ChanStatus);
523 if (IntMask & DELTA_CD) { /* CD change */
524 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
525 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
526 (ChanStatus & CD_ACT) ? "on" : "off");
528 if (!(ChanStatus & CD_ACT) && info->cd_status) {
529 #ifdef ROCKET_DEBUG_HANGUP
530 printk(KERN_INFO "CD drop, calling hangup.\n");
534 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
535 wake_up_interruptible(&info->port.open_wait);
537 #ifdef ROCKET_DEBUG_INTR
538 if (IntMask & DELTA_CTS) { /* CTS change */
539 printk(KERN_INFO "CTS change...\n");
541 if (IntMask & DELTA_DSR) { /* DSR change */
542 printk(KERN_INFO "DSR change...\n");
548 * The top level polling routine. Repeats every 1/100 HZ (10ms).
550 static void rp_do_poll(unsigned long dummy)
553 int ctrl, aiop, ch, line;
554 unsigned int xmitmask, i;
555 unsigned int CtlMask;
556 unsigned char AiopMask;
559 /* Walk through all the boards (ctrl's) */
560 for (ctrl = 0; ctrl < max_board; ctrl++) {
561 if (rcktpt_io_addr[ctrl] <= 0)
564 /* Get a ptr to the board's control struct */
565 ctlp = sCtlNumToCtlPtr(ctrl);
567 /* Get the interrupt status from the board */
569 if (ctlp->BusType == isPCI)
570 CtlMask = sPCIGetControllerIntStatus(ctlp);
573 CtlMask = sGetControllerIntStatus(ctlp);
575 /* Check if any AIOP read bits are set */
576 for (aiop = 0; CtlMask; aiop++) {
577 bit = ctlp->AiopIntrBits[aiop];
580 AiopMask = sGetAiopIntStatus(ctlp, aiop);
582 /* Check if any port read bits are set */
583 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
586 /* Get the line number (/dev/ttyRx number). */
587 /* Read the data from the port. */
588 line = GetLineNumber(ctrl, aiop, ch);
589 rp_handle_port(rp_table[line]);
595 xmitmask = xmit_flags[ctrl];
598 * xmit_flags contains bit-significant flags, indicating there is data
599 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
600 * 1, ... (32 total possible). The variable i has the aiop and ch
601 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
604 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
605 if (xmitmask & (1 << i)) {
606 aiop = (i & 0x18) >> 3;
608 line = GetLineNumber(ctrl, aiop, ch);
609 rp_do_transmit(rp_table[line]);
616 * Reset the timer so we get called at the next clock tick (10ms).
618 if (atomic_read(&rp_num_ports_open))
619 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
623 * Initializes the r_port structure for a port, as well as enabling the port on
625 * Inputs: board, aiop, chan numbers
627 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
634 /* Get the next available line number */
635 line = SetLineNumber(board, aiop, chan);
637 ctlp = sCtlNumToCtlPtr(board);
639 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
640 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
642 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
647 info->magic = RPORT_MAGIC;
653 tty_port_init(&info->port);
654 info->port.ops = &rocket_port_ops;
655 init_completion(&info->close_wait);
656 info->flags &= ~ROCKET_MODE_MASK;
657 switch (pc104[board][line]) {
659 info->flags |= ROCKET_MODE_RS422;
662 info->flags |= ROCKET_MODE_RS485;
666 info->flags |= ROCKET_MODE_RS232;
670 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
671 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
672 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
678 rocketMode = info->flags & ROCKET_MODE_MASK;
680 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
681 sEnRTSToggle(&info->channel);
683 sDisRTSToggle(&info->channel);
685 if (ctlp->boardType == ROCKET_TYPE_PC104) {
686 switch (rocketMode) {
687 case ROCKET_MODE_RS485:
688 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
690 case ROCKET_MODE_RS422:
691 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
693 case ROCKET_MODE_RS232:
695 if (info->flags & ROCKET_RTS_TOGGLE)
696 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
698 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
702 spin_lock_init(&info->slock);
703 mutex_init(&info->write_mtx);
704 rp_table[line] = info;
705 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
710 * Configures a rocketport port according to its termio settings. Called from
711 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
713 static void configure_r_port(struct r_port *info,
714 struct ktermios *old_termios)
719 int bits, baud, divisor;
721 struct ktermios *t = info->port.tty->termios;
726 /* Byte size and parity */
727 if ((cflag & CSIZE) == CS8) {
734 if (cflag & CSTOPB) {
741 if (cflag & PARENB) {
744 if (cflag & PARODD) {
754 baud = tty_get_baud_rate(info->port.tty);
757 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
758 if ((divisor >= 8192 || divisor < 0) && old_termios) {
759 baud = tty_termios_baud_rate(old_termios);
762 divisor = (rp_baud_base[info->board] / baud) - 1;
764 if (divisor >= 8192 || divisor < 0) {
766 divisor = (rp_baud_base[info->board] / baud) - 1;
768 info->cps = baud / bits;
769 sSetBaud(cp, divisor);
771 /* FIXME: Should really back compute a baud rate from the divisor */
772 tty_encode_baud_rate(info->port.tty, baud, baud);
774 if (cflag & CRTSCTS) {
775 info->intmask |= DELTA_CTS;
778 info->intmask &= ~DELTA_CTS;
781 if (cflag & CLOCAL) {
782 info->intmask &= ~DELTA_CD;
784 spin_lock_irqsave(&info->slock, flags);
785 if (sGetChanStatus(cp) & CD_ACT)
789 info->intmask |= DELTA_CD;
790 spin_unlock_irqrestore(&info->slock, flags);
794 * Handle software flow control in the board
796 #ifdef ROCKET_SOFT_FLOW
797 if (I_IXON(info->port.tty)) {
798 sEnTxSoftFlowCtl(cp);
799 if (I_IXANY(info->port.tty)) {
804 sSetTxXONChar(cp, START_CHAR(info->port.tty));
805 sSetTxXOFFChar(cp, STOP_CHAR(info->port.tty));
807 sDisTxSoftFlowCtl(cp);
814 * Set up ignore/read mask words
816 info->read_status_mask = STMRCVROVRH | 0xFF;
817 if (I_INPCK(info->port.tty))
818 info->read_status_mask |= STMFRAMEH | STMPARITYH;
819 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
820 info->read_status_mask |= STMBREAKH;
823 * Characters to ignore
825 info->ignore_status_mask = 0;
826 if (I_IGNPAR(info->port.tty))
827 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
828 if (I_IGNBRK(info->port.tty)) {
829 info->ignore_status_mask |= STMBREAKH;
831 * If we're ignoring parity and break indicators,
832 * ignore overruns too. (For real raw support).
834 if (I_IGNPAR(info->port.tty))
835 info->ignore_status_mask |= STMRCVROVRH;
838 rocketMode = info->flags & ROCKET_MODE_MASK;
840 if ((info->flags & ROCKET_RTS_TOGGLE)
841 || (rocketMode == ROCKET_MODE_RS485))
846 sSetRTS(&info->channel);
848 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
849 switch (rocketMode) {
850 case ROCKET_MODE_RS485:
851 sSetInterfaceMode(cp, InterfaceModeRS485);
853 case ROCKET_MODE_RS422:
854 sSetInterfaceMode(cp, InterfaceModeRS422);
856 case ROCKET_MODE_RS232:
858 if (info->flags & ROCKET_RTS_TOGGLE)
859 sSetInterfaceMode(cp, InterfaceModeRS232T);
861 sSetInterfaceMode(cp, InterfaceModeRS232);
867 static int carrier_raised(struct tty_port *port)
869 struct r_port *info = container_of(port, struct r_port, port);
870 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
873 /* info->port.count is considered critical, protected by spinlocks. */
874 static int block_til_ready(struct tty_struct *tty, struct file *filp,
877 DECLARE_WAITQUEUE(wait, current);
878 struct tty_port *port = &info->port;
880 int do_clocal = 0, extra_count = 0;
884 * If the device is in the middle of being closed, then block
885 * until it's done, and then try again.
887 if (tty_hung_up_p(filp))
888 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
889 if (info->flags & ROCKET_CLOSING) {
890 if (wait_for_completion_interruptible(&info->close_wait))
892 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
896 * If non-blocking mode is set, or the port is not enabled,
897 * then make the check up front and then exit.
899 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
900 info->flags |= ROCKET_NORMAL_ACTIVE;
903 if (tty->termios->c_cflag & CLOCAL)
907 * Block waiting for the carrier detect and the line to become free. While we are in
908 * this loop, port->count is dropped by one, so that rp_close() knows when to free things.
909 * We restore it upon exit, either normal or abnormal.
912 add_wait_queue(&port->open_wait, &wait);
913 #ifdef ROCKET_DEBUG_OPEN
914 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, port->count);
916 spin_lock_irqsave(&info->slock, flags);
918 #ifdef ROCKET_DISABLE_SIMUSAGE
919 info->flags |= ROCKET_NORMAL_ACTIVE;
921 if (!tty_hung_up_p(filp)) {
926 port->blocked_open++;
928 spin_unlock_irqrestore(&info->slock, flags);
931 if (tty->termios->c_cflag & CBAUD) {
932 sSetDTR(&info->channel);
933 sSetRTS(&info->channel);
935 set_current_state(TASK_INTERRUPTIBLE);
936 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
937 if (info->flags & ROCKET_HUP_NOTIFY)
940 retval = -ERESTARTSYS;
943 if (!(info->flags & ROCKET_CLOSING) &&
944 (do_clocal || tty_port_carrier_raised(port)))
946 if (signal_pending(current)) {
947 retval = -ERESTARTSYS;
950 #ifdef ROCKET_DEBUG_OPEN
951 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
952 info->line, port->count, info->flags);
954 schedule(); /* Don't hold spinlock here, will hang PC */
956 __set_current_state(TASK_RUNNING);
957 remove_wait_queue(&port->open_wait, &wait);
959 spin_lock_irqsave(&info->slock, flags);
963 port->blocked_open--;
965 spin_unlock_irqrestore(&info->slock, flags);
967 #ifdef ROCKET_DEBUG_OPEN
968 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
969 info->line, port->count);
973 info->flags |= ROCKET_NORMAL_ACTIVE;
978 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
979 * port's r_port struct. Initializes the port hardware.
981 static int rp_open(struct tty_struct *tty, struct file *filp)
984 int line = 0, retval;
989 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
992 page = __get_free_page(GFP_KERNEL);
996 if (info->flags & ROCKET_CLOSING) {
997 retval = wait_for_completion_interruptible(&info->close_wait);
1001 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
1005 * We must not sleep from here until the port is marked fully in use.
1010 info->xmit_buf = (unsigned char *) page;
1012 tty->driver_data = info;
1013 info->port.tty = tty;
1015 if (info->port.count++ == 0) {
1016 atomic_inc(&rp_num_ports_open);
1018 #ifdef ROCKET_DEBUG_OPEN
1019 printk(KERN_INFO "rocket mod++ = %d...\n",
1020 atomic_read(&rp_num_ports_open));
1023 #ifdef ROCKET_DEBUG_OPEN
1024 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
1028 * Info->count is now 1; so it's safe to sleep now.
1030 if ((info->flags & ROCKET_INITIALIZED) == 0) {
1031 cp = &info->channel;
1032 sSetRxTrigger(cp, TRIG_1);
1033 if (sGetChanStatus(cp) & CD_ACT)
1034 info->cd_status = 1;
1036 info->cd_status = 0;
1037 sDisRxStatusMode(cp);
1041 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1042 sSetRxTrigger(cp, TRIG_1);
1045 sDisRxStatusMode(cp);
1049 sDisTxSoftFlowCtl(cp);
1054 info->flags |= ROCKET_INITIALIZED;
1057 * Set up the tty->alt_speed kludge
1059 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1060 info->port.tty->alt_speed = 57600;
1061 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1062 info->port.tty->alt_speed = 115200;
1063 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1064 info->port.tty->alt_speed = 230400;
1065 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1066 info->port.tty->alt_speed = 460800;
1068 configure_r_port(info, NULL);
1069 if (tty->termios->c_cflag & CBAUD) {
1074 /* Starts (or resets) the maint polling loop */
1075 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1077 retval = block_til_ready(tty, filp, info);
1079 #ifdef ROCKET_DEBUG_OPEN
1080 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1088 * Exception handler that closes a serial port. info->port.count is considered critical.
1090 static void rp_close(struct tty_struct *tty, struct file *filp)
1092 struct r_port *info = (struct r_port *) tty->driver_data;
1093 unsigned long flags;
1097 if (rocket_paranoia_check(info, "rp_close"))
1100 #ifdef ROCKET_DEBUG_OPEN
1101 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1104 if (tty_hung_up_p(filp))
1106 spin_lock_irqsave(&info->slock, flags);
1108 if ((tty->count == 1) && (info->port.count != 1)) {
1110 * Uh, oh. tty->count is 1, which means that the tty
1111 * structure will be freed. Info->count should always
1112 * be one in these conditions. If it's greater than
1113 * one, we've got real problems, since it means the
1114 * serial port won't be shutdown.
1116 printk(KERN_WARNING "rp_close: bad serial port count; "
1117 "tty->count is 1, info->port.count is %d\n", info->port.count);
1118 info->port.count = 1;
1120 if (--info->port.count < 0) {
1121 printk(KERN_WARNING "rp_close: bad serial port count for "
1122 "ttyR%d: %d\n", info->line, info->port.count);
1123 info->port.count = 0;
1125 if (info->port.count) {
1126 spin_unlock_irqrestore(&info->slock, flags);
1129 info->flags |= ROCKET_CLOSING;
1130 spin_unlock_irqrestore(&info->slock, flags);
1132 cp = &info->channel;
1135 * Notify the line discpline to only process XON/XOFF characters
1140 * If transmission was throttled by the application request,
1141 * just flush the xmit buffer.
1143 if (tty->flow_stopped)
1144 rp_flush_buffer(tty);
1147 * Wait for the transmit buffer to clear
1149 if (info->port.closing_wait != ROCKET_CLOSING_WAIT_NONE)
1150 tty_wait_until_sent(tty, info->port.closing_wait);
1152 * Before we drop DTR, make sure the UART transmitter
1153 * has completely drained; this is especially
1154 * important if there is a transmit FIFO!
1156 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1159 rp_wait_until_sent(tty, timeout);
1160 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1163 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1165 sDisTxSoftFlowCtl(cp);
1173 rp_flush_buffer(tty);
1175 tty_ldisc_flush(tty);
1177 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1179 if (info->port.blocked_open) {
1180 if (info->port.close_delay) {
1181 msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
1183 wake_up_interruptible(&info->port.open_wait);
1185 if (info->xmit_buf) {
1186 free_page((unsigned long) info->xmit_buf);
1187 info->xmit_buf = NULL;
1190 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1192 complete_all(&info->close_wait);
1193 atomic_dec(&rp_num_ports_open);
1195 #ifdef ROCKET_DEBUG_OPEN
1196 printk(KERN_INFO "rocket mod-- = %d...\n",
1197 atomic_read(&rp_num_ports_open));
1198 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1203 static void rp_set_termios(struct tty_struct *tty,
1204 struct ktermios *old_termios)
1206 struct r_port *info = (struct r_port *) tty->driver_data;
1210 if (rocket_paranoia_check(info, "rp_set_termios"))
1213 cflag = tty->termios->c_cflag;
1216 * This driver doesn't support CS5 or CS6
1218 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1219 tty->termios->c_cflag =
1220 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1222 tty->termios->c_cflag &= ~CMSPAR;
1224 configure_r_port(info, old_termios);
1226 cp = &info->channel;
1228 /* Handle transition to B0 status */
1229 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1234 /* Handle transition away from B0 status */
1235 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1236 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1241 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1242 tty->hw_stopped = 0;
1247 static int rp_break(struct tty_struct *tty, int break_state)
1249 struct r_port *info = (struct r_port *) tty->driver_data;
1250 unsigned long flags;
1252 if (rocket_paranoia_check(info, "rp_break"))
1255 spin_lock_irqsave(&info->slock, flags);
1256 if (break_state == -1)
1257 sSendBreak(&info->channel);
1259 sClrBreak(&info->channel);
1260 spin_unlock_irqrestore(&info->slock, flags);
1265 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1266 * the UPCI boards was added, it was decided to make this a function because
1267 * the macro was getting too complicated. All cases except the first one
1268 * (UPCIRingInd) are taken directly from the original macro.
1270 static int sGetChanRI(CHANNEL_T * ChP)
1272 CONTROLLER_t *CtlP = ChP->CtlP;
1273 int ChanNum = ChP->ChanNum;
1276 if (CtlP->UPCIRingInd)
1277 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1278 else if (CtlP->AltChanRingIndicator)
1279 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1280 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1281 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1286 /********************************************************************************************/
1287 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1290 * Returns the state of the serial modem control lines. These next 2 functions
1291 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1293 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1295 struct r_port *info = (struct r_port *)tty->driver_data;
1296 unsigned int control, result, ChanStatus;
1298 ChanStatus = sGetChanStatusLo(&info->channel);
1299 control = info->channel.TxControl[3];
1300 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1301 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1302 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1303 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1304 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1305 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1311 * Sets the modem control lines
1313 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1314 unsigned int set, unsigned int clear)
1316 struct r_port *info = (struct r_port *)tty->driver_data;
1318 if (set & TIOCM_RTS)
1319 info->channel.TxControl[3] |= SET_RTS;
1320 if (set & TIOCM_DTR)
1321 info->channel.TxControl[3] |= SET_DTR;
1322 if (clear & TIOCM_RTS)
1323 info->channel.TxControl[3] &= ~SET_RTS;
1324 if (clear & TIOCM_DTR)
1325 info->channel.TxControl[3] &= ~SET_DTR;
1327 out32(info->channel.IndexAddr, info->channel.TxControl);
1331 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1333 struct rocket_config tmp;
1337 memset(&tmp, 0, sizeof (tmp));
1338 tmp.line = info->line;
1339 tmp.flags = info->flags;
1340 tmp.close_delay = info->port.close_delay;
1341 tmp.closing_wait = info->port.closing_wait;
1342 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1344 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1349 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1351 struct rocket_config new_serial;
1353 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1356 if (!capable(CAP_SYS_ADMIN))
1358 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1360 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1361 configure_r_port(info, NULL);
1365 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1366 info->port.close_delay = new_serial.close_delay;
1367 info->port.closing_wait = new_serial.closing_wait;
1369 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1370 info->port.tty->alt_speed = 57600;
1371 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1372 info->port.tty->alt_speed = 115200;
1373 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1374 info->port.tty->alt_speed = 230400;
1375 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1376 info->port.tty->alt_speed = 460800;
1378 configure_r_port(info, NULL);
1383 * This function fills in a rocket_ports struct with information
1384 * about what boards/ports are in the system. This info is passed
1385 * to user space. See setrocket.c where the info is used to create
1386 * the /dev/ttyRx ports.
1388 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1390 struct rocket_ports tmp;
1395 memset(&tmp, 0, sizeof (tmp));
1396 tmp.tty_major = rocket_driver->major;
1398 for (board = 0; board < 4; board++) {
1399 tmp.rocketModel[board].model = rocketModel[board].model;
1400 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1401 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1402 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1403 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1405 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1410 static int reset_rm2(struct r_port *info, void __user *arg)
1414 if (!capable(CAP_SYS_ADMIN))
1417 if (copy_from_user(&reset, arg, sizeof (int)))
1422 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1423 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1426 if (info->ctlp->BusType == isISA)
1427 sModemReset(info->ctlp, info->chan, reset);
1429 sPCIModemReset(info->ctlp, info->chan, reset);
1434 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1436 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1441 /* IOCTL call handler into the driver */
1442 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1443 unsigned int cmd, unsigned long arg)
1445 struct r_port *info = (struct r_port *) tty->driver_data;
1446 void __user *argp = (void __user *)arg;
1449 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1455 case RCKP_GET_STRUCT:
1456 if (copy_to_user(argp, info, sizeof (struct r_port)))
1459 case RCKP_GET_CONFIG:
1460 ret = get_config(info, argp);
1462 case RCKP_SET_CONFIG:
1463 ret = set_config(info, argp);
1465 case RCKP_GET_PORTS:
1466 ret = get_ports(info, argp);
1468 case RCKP_RESET_RM2:
1469 ret = reset_rm2(info, argp);
1471 case RCKP_GET_VERSION:
1472 ret = get_version(info, argp);
1481 static void rp_send_xchar(struct tty_struct *tty, char ch)
1483 struct r_port *info = (struct r_port *) tty->driver_data;
1486 if (rocket_paranoia_check(info, "rp_send_xchar"))
1489 cp = &info->channel;
1491 sWriteTxPrioByte(cp, ch);
1493 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1496 static void rp_throttle(struct tty_struct *tty)
1498 struct r_port *info = (struct r_port *) tty->driver_data;
1501 #ifdef ROCKET_DEBUG_THROTTLE
1502 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1503 tty->ldisc.chars_in_buffer(tty));
1506 if (rocket_paranoia_check(info, "rp_throttle"))
1509 cp = &info->channel;
1511 rp_send_xchar(tty, STOP_CHAR(tty));
1513 sClrRTS(&info->channel);
1516 static void rp_unthrottle(struct tty_struct *tty)
1518 struct r_port *info = (struct r_port *) tty->driver_data;
1520 #ifdef ROCKET_DEBUG_THROTTLE
1521 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1522 tty->ldisc.chars_in_buffer(tty));
1525 if (rocket_paranoia_check(info, "rp_throttle"))
1528 cp = &info->channel;
1530 rp_send_xchar(tty, START_CHAR(tty));
1532 sSetRTS(&info->channel);
1536 * ------------------------------------------------------------
1537 * rp_stop() and rp_start()
1539 * This routines are called before setting or resetting tty->stopped.
1540 * They enable or disable transmitter interrupts, as necessary.
1541 * ------------------------------------------------------------
1543 static void rp_stop(struct tty_struct *tty)
1545 struct r_port *info = (struct r_port *) tty->driver_data;
1547 #ifdef ROCKET_DEBUG_FLOW
1548 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1549 info->xmit_cnt, info->xmit_fifo_room);
1552 if (rocket_paranoia_check(info, "rp_stop"))
1555 if (sGetTxCnt(&info->channel))
1556 sDisTransmit(&info->channel);
1559 static void rp_start(struct tty_struct *tty)
1561 struct r_port *info = (struct r_port *) tty->driver_data;
1563 #ifdef ROCKET_DEBUG_FLOW
1564 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1565 info->xmit_cnt, info->xmit_fifo_room);
1568 if (rocket_paranoia_check(info, "rp_stop"))
1571 sEnTransmit(&info->channel);
1572 set_bit((info->aiop * 8) + info->chan,
1573 (void *) &xmit_flags[info->board]);
1577 * rp_wait_until_sent() --- wait until the transmitter is empty
1579 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1581 struct r_port *info = (struct r_port *) tty->driver_data;
1583 unsigned long orig_jiffies;
1584 int check_time, exit_time;
1587 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1590 cp = &info->channel;
1592 orig_jiffies = jiffies;
1593 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1594 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1596 printk(KERN_INFO "cps=%d...\n", info->cps);
1600 txcnt = sGetTxCnt(cp);
1602 if (sGetChanStatusLo(cp) & TXSHRMT)
1604 check_time = (HZ / info->cps) / 5;
1606 check_time = HZ * txcnt / info->cps;
1609 exit_time = orig_jiffies + timeout - jiffies;
1612 if (exit_time < check_time)
1613 check_time = exit_time;
1615 if (check_time == 0)
1617 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1618 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1619 jiffies, check_time);
1621 msleep_interruptible(jiffies_to_msecs(check_time));
1622 if (signal_pending(current))
1625 __set_current_state(TASK_RUNNING);
1627 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1628 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1633 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1635 static void rp_hangup(struct tty_struct *tty)
1638 struct r_port *info = (struct r_port *) tty->driver_data;
1640 if (rocket_paranoia_check(info, "rp_hangup"))
1643 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1644 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1646 rp_flush_buffer(tty);
1647 if (info->flags & ROCKET_CLOSING)
1649 if (info->port.count)
1650 atomic_dec(&rp_num_ports_open);
1651 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1653 info->port.count = 0;
1654 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1655 info->port.tty = NULL;
1657 cp = &info->channel;
1660 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1662 sDisTxSoftFlowCtl(cp);
1664 info->flags &= ~ROCKET_INITIALIZED;
1666 wake_up_interruptible(&info->port.open_wait);
1670 * Exception handler - write char routine. The RocketPort driver uses a
1671 * double-buffering strategy, with the twist that if the in-memory CPU
1672 * buffer is empty, and there's space in the transmit FIFO, the
1673 * writing routines will write directly to transmit FIFO.
1674 * Write buffer and counters protected by spinlocks
1676 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1678 struct r_port *info = (struct r_port *) tty->driver_data;
1680 unsigned long flags;
1682 if (rocket_paranoia_check(info, "rp_put_char"))
1686 * Grab the port write mutex, locking out other processes that try to
1687 * write to this port
1689 mutex_lock(&info->write_mtx);
1691 #ifdef ROCKET_DEBUG_WRITE
1692 printk(KERN_INFO "rp_put_char %c...\n", ch);
1695 spin_lock_irqsave(&info->slock, flags);
1696 cp = &info->channel;
1698 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1699 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1701 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1702 info->xmit_buf[info->xmit_head++] = ch;
1703 info->xmit_head &= XMIT_BUF_SIZE - 1;
1705 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1707 sOutB(sGetTxRxDataIO(cp), ch);
1708 info->xmit_fifo_room--;
1710 spin_unlock_irqrestore(&info->slock, flags);
1711 mutex_unlock(&info->write_mtx);
1716 * Exception handler - write routine, called when user app writes to the device.
1717 * A per port write mutex is used to protect from another process writing to
1718 * this port at the same time. This other process could be running on the other CPU
1719 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1720 * Spinlocks protect the info xmit members.
1722 static int rp_write(struct tty_struct *tty,
1723 const unsigned char *buf, int count)
1725 struct r_port *info = (struct r_port *) tty->driver_data;
1727 const unsigned char *b;
1729 unsigned long flags;
1731 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1734 if (mutex_lock_interruptible(&info->write_mtx))
1735 return -ERESTARTSYS;
1737 #ifdef ROCKET_DEBUG_WRITE
1738 printk(KERN_INFO "rp_write %d chars...\n", count);
1740 cp = &info->channel;
1742 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1743 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1746 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1747 * into FIFO. Use the write queue for temp storage.
1749 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1750 c = min(count, info->xmit_fifo_room);
1753 /* Push data into FIFO, 2 bytes at a time */
1754 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1756 /* If there is a byte remaining, write it */
1758 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1764 spin_lock_irqsave(&info->slock, flags);
1765 info->xmit_fifo_room -= c;
1766 spin_unlock_irqrestore(&info->slock, flags);
1769 /* If count is zero, we wrote it all and are done */
1773 /* Write remaining data into the port's xmit_buf */
1775 if (!info->port.tty) /* Seemingly obligatory check... */
1777 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1778 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1783 memcpy(info->xmit_buf + info->xmit_head, b, c);
1785 spin_lock_irqsave(&info->slock, flags);
1787 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1788 info->xmit_cnt += c;
1789 spin_unlock_irqrestore(&info->slock, flags);
1796 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1797 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1800 if (info->xmit_cnt < WAKEUP_CHARS) {
1802 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1803 wake_up_interruptible(&tty->poll_wait);
1806 mutex_unlock(&info->write_mtx);
1811 * Return the number of characters that can be sent. We estimate
1812 * only using the in-memory transmit buffer only, and ignore the
1813 * potential space in the transmit FIFO.
1815 static int rp_write_room(struct tty_struct *tty)
1817 struct r_port *info = (struct r_port *) tty->driver_data;
1820 if (rocket_paranoia_check(info, "rp_write_room"))
1823 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1826 #ifdef ROCKET_DEBUG_WRITE
1827 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1833 * Return the number of characters in the buffer. Again, this only
1834 * counts those characters in the in-memory transmit buffer.
1836 static int rp_chars_in_buffer(struct tty_struct *tty)
1838 struct r_port *info = (struct r_port *) tty->driver_data;
1841 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1844 cp = &info->channel;
1846 #ifdef ROCKET_DEBUG_WRITE
1847 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1849 return info->xmit_cnt;
1853 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1854 * r_port struct for the port. Note that spinlock are used to protect info members,
1855 * do not call this function if the spinlock is already held.
1857 static void rp_flush_buffer(struct tty_struct *tty)
1859 struct r_port *info = (struct r_port *) tty->driver_data;
1861 unsigned long flags;
1863 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1866 spin_lock_irqsave(&info->slock, flags);
1867 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1868 spin_unlock_irqrestore(&info->slock, flags);
1870 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1871 wake_up_interruptible(&tty->poll_wait);
1875 cp = &info->channel;
1881 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1882 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1885 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1888 * Called when a PCI card is found. Retrieves and stores model information,
1889 * init's aiopic and serial port hardware.
1890 * Inputs: i is the board number (0-n)
1892 static __init int register_PCI(int i, struct pci_dev *dev)
1894 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1895 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1896 char *str, *board_type;
1900 int altChanRingIndicator = 0;
1901 int ports_per_aiop = 8;
1902 WordIO_t ConfigIO = 0;
1903 ByteIO_t UPCIRingInd = 0;
1905 if (!dev || pci_enable_device(dev))
1908 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1910 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1911 rocketModel[i].loadrm2 = 0;
1912 rocketModel[i].startingPortNumber = nextLineNumber;
1914 /* Depending on the model, set up some config variables */
1915 switch (dev->device) {
1916 case PCI_DEVICE_ID_RP4QUAD:
1920 rocketModel[i].model = MODEL_RP4QUAD;
1921 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1922 rocketModel[i].numPorts = 4;
1924 case PCI_DEVICE_ID_RP8OCTA:
1927 rocketModel[i].model = MODEL_RP8OCTA;
1928 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1929 rocketModel[i].numPorts = 8;
1931 case PCI_DEVICE_ID_URP8OCTA:
1934 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1935 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1936 rocketModel[i].numPorts = 8;
1938 case PCI_DEVICE_ID_RP8INTF:
1941 rocketModel[i].model = MODEL_RP8INTF;
1942 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1943 rocketModel[i].numPorts = 8;
1945 case PCI_DEVICE_ID_URP8INTF:
1948 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1949 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1950 rocketModel[i].numPorts = 8;
1952 case PCI_DEVICE_ID_RP8J:
1955 rocketModel[i].model = MODEL_RP8J;
1956 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1957 rocketModel[i].numPorts = 8;
1959 case PCI_DEVICE_ID_RP4J:
1963 rocketModel[i].model = MODEL_RP4J;
1964 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1965 rocketModel[i].numPorts = 4;
1967 case PCI_DEVICE_ID_RP8SNI:
1968 str = "8 (DB78 Custom)";
1970 rocketModel[i].model = MODEL_RP8SNI;
1971 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1972 rocketModel[i].numPorts = 8;
1974 case PCI_DEVICE_ID_RP16SNI:
1975 str = "16 (DB78 Custom)";
1977 rocketModel[i].model = MODEL_RP16SNI;
1978 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1979 rocketModel[i].numPorts = 16;
1981 case PCI_DEVICE_ID_RP16INTF:
1984 rocketModel[i].model = MODEL_RP16INTF;
1985 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1986 rocketModel[i].numPorts = 16;
1988 case PCI_DEVICE_ID_URP16INTF:
1991 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1992 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1993 rocketModel[i].numPorts = 16;
1995 case PCI_DEVICE_ID_CRP16INTF:
1998 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1999 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
2000 rocketModel[i].numPorts = 16;
2002 case PCI_DEVICE_ID_RP32INTF:
2005 rocketModel[i].model = MODEL_RP32INTF;
2006 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2007 rocketModel[i].numPorts = 32;
2009 case PCI_DEVICE_ID_URP32INTF:
2012 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2013 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2014 rocketModel[i].numPorts = 32;
2016 case PCI_DEVICE_ID_RPP4:
2017 str = "Plus Quadcable";
2020 altChanRingIndicator++;
2022 rocketModel[i].model = MODEL_RPP4;
2023 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2024 rocketModel[i].numPorts = 4;
2026 case PCI_DEVICE_ID_RPP8:
2027 str = "Plus Octacable";
2030 altChanRingIndicator++;
2032 rocketModel[i].model = MODEL_RPP8;
2033 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2034 rocketModel[i].numPorts = 8;
2036 case PCI_DEVICE_ID_RP2_232:
2037 str = "Plus 2 (RS-232)";
2040 altChanRingIndicator++;
2042 rocketModel[i].model = MODEL_RP2_232;
2043 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2044 rocketModel[i].numPorts = 2;
2046 case PCI_DEVICE_ID_RP2_422:
2047 str = "Plus 2 (RS-422)";
2050 altChanRingIndicator++;
2052 rocketModel[i].model = MODEL_RP2_422;
2053 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2054 rocketModel[i].numPorts = 2;
2056 case PCI_DEVICE_ID_RP6M:
2062 /* If revision is 1, the rocketmodem flash must be loaded.
2063 * If it is 2 it is a "socketed" version. */
2064 if (dev->revision == 1) {
2065 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2066 rocketModel[i].loadrm2 = 1;
2068 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2071 rocketModel[i].model = MODEL_RP6M;
2072 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2073 rocketModel[i].numPorts = 6;
2075 case PCI_DEVICE_ID_RP4M:
2079 if (dev->revision == 1) {
2080 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2081 rocketModel[i].loadrm2 = 1;
2083 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2086 rocketModel[i].model = MODEL_RP4M;
2087 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2088 rocketModel[i].numPorts = 4;
2091 str = "(unknown/unsupported)";
2097 * Check for UPCI boards.
2100 switch (dev->device) {
2101 case PCI_DEVICE_ID_URP32INTF:
2102 case PCI_DEVICE_ID_URP8INTF:
2103 case PCI_DEVICE_ID_URP16INTF:
2104 case PCI_DEVICE_ID_CRP16INTF:
2105 case PCI_DEVICE_ID_URP8OCTA:
2106 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2107 ConfigIO = pci_resource_start(dev, 1);
2108 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2109 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2112 * Check for octa or quad cable.
2115 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2116 PCI_GPIO_CTRL_8PORT)) {
2119 rocketModel[i].numPorts = 4;
2123 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2126 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2127 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2128 rocketModel[i].numPorts = 8;
2129 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2130 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2131 ConfigIO = pci_resource_start(dev, 1);
2132 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2134 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2137 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2138 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2139 rocketModel[i].numPorts = 4;
2140 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2141 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2142 ConfigIO = pci_resource_start(dev, 1);
2143 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2149 switch (rcktpt_type[i]) {
2150 case ROCKET_TYPE_MODEM:
2151 board_type = "RocketModem";
2153 case ROCKET_TYPE_MODEMII:
2154 board_type = "RocketModem II";
2156 case ROCKET_TYPE_MODEMIII:
2157 board_type = "RocketModem III";
2160 board_type = "RocketPort";
2165 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2166 rp_baud_base[i] = 921600;
2169 * If support_low_speed is set, use the slow clock
2170 * prescale, which supports 50 bps
2172 if (support_low_speed) {
2173 /* mod 9 (divide by 10) prescale */
2174 sClockPrescale = 0x19;
2175 rp_baud_base[i] = 230400;
2177 /* mod 4 (devide by 5) prescale */
2178 sClockPrescale = 0x14;
2179 rp_baud_base[i] = 460800;
2183 for (aiop = 0; aiop < max_num_aiops; aiop++)
2184 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2185 ctlp = sCtlNumToCtlPtr(i);
2186 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2187 for (aiop = 0; aiop < max_num_aiops; aiop++)
2188 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2190 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2191 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2192 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2193 rocketModel[i].startingPortNumber,
2194 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2196 if (num_aiops <= 0) {
2197 rcktpt_io_addr[i] = 0;
2202 /* Reset the AIOPIC, init the serial ports */
2203 for (aiop = 0; aiop < num_aiops; aiop++) {
2204 sResetAiopByNum(ctlp, aiop);
2205 num_chan = ports_per_aiop;
2206 for (chan = 0; chan < num_chan; chan++)
2207 init_r_port(i, aiop, chan, dev);
2210 /* Rocket modems must be reset */
2211 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2212 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2213 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2214 num_chan = ports_per_aiop;
2215 for (chan = 0; chan < num_chan; chan++)
2216 sPCIModemReset(ctlp, chan, 1);
2218 for (chan = 0; chan < num_chan; chan++)
2219 sPCIModemReset(ctlp, chan, 0);
2221 rmSpeakerReset(ctlp, rocketModel[i].model);
2227 * Probes for PCI cards, inits them if found
2228 * Input: board_found = number of ISA boards already found, or the
2229 * starting board number
2230 * Returns: Number of PCI boards found
2232 static int __init init_PCI(int boards_found)
2234 struct pci_dev *dev = NULL;
2237 /* Work through the PCI device list, pulling out ours */
2238 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2239 if (register_PCI(count + boards_found, dev))
2245 #endif /* CONFIG_PCI */
2248 * Probes for ISA cards
2249 * Input: i = the board number to look for
2250 * Returns: 1 if board found, 0 else
2252 static int __init init_ISA(int i)
2254 int num_aiops, num_chan = 0, total_num_chan = 0;
2256 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2260 /* If io_addr is zero, no board configured */
2261 if (rcktpt_io_addr[i] == 0)
2264 /* Reserve the IO region */
2265 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2266 printk(KERN_ERR "Unable to reserve IO region for configured "
2267 "ISA RocketPort at address 0x%lx, board not "
2268 "installed...\n", rcktpt_io_addr[i]);
2269 rcktpt_io_addr[i] = 0;
2273 ctlp = sCtlNumToCtlPtr(i);
2275 ctlp->boardType = rcktpt_type[i];
2277 switch (rcktpt_type[i]) {
2278 case ROCKET_TYPE_PC104:
2279 type_string = "(PC104)";
2281 case ROCKET_TYPE_MODEM:
2282 type_string = "(RocketModem)";
2284 case ROCKET_TYPE_MODEMII:
2285 type_string = "(RocketModem II)";
2293 * If support_low_speed is set, use the slow clock prescale,
2294 * which supports 50 bps
2296 if (support_low_speed) {
2297 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2298 rp_baud_base[i] = 230400;
2300 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2301 rp_baud_base[i] = 460800;
2304 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2305 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2307 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2309 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2310 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2311 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2314 /* If something went wrong initing the AIOP's release the ISA IO memory */
2315 if (num_aiops <= 0) {
2316 release_region(rcktpt_io_addr[i], 64);
2317 rcktpt_io_addr[i] = 0;
2321 rocketModel[i].startingPortNumber = nextLineNumber;
2323 for (aiop = 0; aiop < num_aiops; aiop++) {
2324 sResetAiopByNum(ctlp, aiop);
2325 sEnAiop(ctlp, aiop);
2326 num_chan = sGetAiopNumChan(ctlp, aiop);
2327 total_num_chan += num_chan;
2328 for (chan = 0; chan < num_chan; chan++)
2329 init_r_port(i, aiop, chan, NULL);
2332 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2333 num_chan = sGetAiopNumChan(ctlp, 0);
2334 total_num_chan = num_chan;
2335 for (chan = 0; chan < num_chan; chan++)
2336 sModemReset(ctlp, chan, 1);
2338 for (chan = 0; chan < num_chan; chan++)
2339 sModemReset(ctlp, chan, 0);
2341 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2343 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2345 rocketModel[i].numPorts = total_num_chan;
2346 rocketModel[i].model = MODEL_ISA;
2348 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2349 i, rcktpt_io_addr[i], num_aiops, type_string);
2351 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2352 rocketModel[i].modelString,
2353 rocketModel[i].startingPortNumber,
2354 rocketModel[i].startingPortNumber +
2355 rocketModel[i].numPorts - 1);
2360 static const struct tty_operations rocket_ops = {
2364 .put_char = rp_put_char,
2365 .write_room = rp_write_room,
2366 .chars_in_buffer = rp_chars_in_buffer,
2367 .flush_buffer = rp_flush_buffer,
2369 .throttle = rp_throttle,
2370 .unthrottle = rp_unthrottle,
2371 .set_termios = rp_set_termios,
2374 .hangup = rp_hangup,
2375 .break_ctl = rp_break,
2376 .send_xchar = rp_send_xchar,
2377 .wait_until_sent = rp_wait_until_sent,
2378 .tiocmget = rp_tiocmget,
2379 .tiocmset = rp_tiocmset,
2382 static const struct tty_port_operations rocket_port_ops = {
2383 .carrier_raised = carrier_raised,
2387 * The module "startup" routine; it's run when the module is loaded.
2389 static int __init rp_init(void)
2391 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2393 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2394 ROCKET_VERSION, ROCKET_DATE);
2396 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2401 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2402 * zero, use the default controller IO address of board1 + 0x40.
2405 if (controller == 0)
2406 controller = board1 + 0x40;
2408 controller = 0; /* Used as a flag, meaning no ISA boards */
2411 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2412 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2413 printk(KERN_ERR "Unable to reserve IO region for first "
2414 "configured ISA RocketPort controller 0x%lx. "
2415 "Driver exiting\n", controller);
2420 /* Store ISA variable retrieved from command line or .conf file. */
2421 rcktpt_io_addr[0] = board1;
2422 rcktpt_io_addr[1] = board2;
2423 rcktpt_io_addr[2] = board3;
2424 rcktpt_io_addr[3] = board4;
2426 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2427 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2428 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2429 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2430 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2431 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2432 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2433 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2436 * Set up the tty driver structure and then register this
2437 * driver with the tty layer.
2440 rocket_driver->owner = THIS_MODULE;
2441 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2442 rocket_driver->name = "ttyR";
2443 rocket_driver->driver_name = "Comtrol RocketPort";
2444 rocket_driver->major = TTY_ROCKET_MAJOR;
2445 rocket_driver->minor_start = 0;
2446 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2447 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2448 rocket_driver->init_termios = tty_std_termios;
2449 rocket_driver->init_termios.c_cflag =
2450 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2451 rocket_driver->init_termios.c_ispeed = 9600;
2452 rocket_driver->init_termios.c_ospeed = 9600;
2453 #ifdef ROCKET_SOFT_FLOW
2454 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2456 tty_set_operations(rocket_driver, &rocket_ops);
2458 ret = tty_register_driver(rocket_driver);
2460 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2464 #ifdef ROCKET_DEBUG_OPEN
2465 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2469 * OK, let's probe each of the controllers looking for boards. Any boards found
2470 * will be initialized here.
2472 isa_boards_found = 0;
2473 pci_boards_found = 0;
2475 for (i = 0; i < NUM_BOARDS; i++) {
2481 if (isa_boards_found < NUM_BOARDS)
2482 pci_boards_found = init_PCI(isa_boards_found);
2485 max_board = pci_boards_found + isa_boards_found;
2487 if (max_board == 0) {
2488 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2495 tty_unregister_driver(rocket_driver);
2497 put_tty_driver(rocket_driver);
2503 static void rp_cleanup_module(void)
2508 del_timer_sync(&rocket_timer);
2510 retval = tty_unregister_driver(rocket_driver);
2512 printk(KERN_ERR "Error %d while trying to unregister "
2513 "rocketport driver\n", -retval);
2515 for (i = 0; i < MAX_RP_PORTS; i++)
2517 tty_unregister_device(rocket_driver, i);
2521 put_tty_driver(rocket_driver);
2523 for (i = 0; i < NUM_BOARDS; i++) {
2524 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2526 release_region(rcktpt_io_addr[i], 64);
2529 release_region(controller, 4);
2532 /***************************************************************************
2533 Function: sInitController
2534 Purpose: Initialization of controller global registers and controller
2536 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2537 IRQNum,Frequency,PeriodicOnly)
2538 CONTROLLER_T *CtlP; Ptr to controller structure
2539 int CtlNum; Controller number
2540 ByteIO_t MudbacIO; Mudbac base I/O address.
2541 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2542 This list must be in the order the AIOPs will be found on the
2543 controller. Once an AIOP in the list is not found, it is
2544 assumed that there are no more AIOPs on the controller.
2545 int AiopIOListSize; Number of addresses in AiopIOList
2546 int IRQNum; Interrupt Request number. Can be any of the following:
2547 0: Disable global interrupts
2556 Byte_t Frequency: A flag identifying the frequency
2557 of the periodic interrupt, can be any one of the following:
2558 FREQ_DIS - periodic interrupt disabled
2559 FREQ_137HZ - 137 Hertz
2560 FREQ_69HZ - 69 Hertz
2561 FREQ_34HZ - 34 Hertz
2562 FREQ_17HZ - 17 Hertz
2565 If IRQNum is set to 0 the Frequency parameter is
2566 overidden, it is forced to a value of FREQ_DIS.
2567 int PeriodicOnly: 1 if all interrupts except the periodic
2568 interrupt are to be blocked.
2569 0 is both the periodic interrupt and
2570 other channel interrupts are allowed.
2571 If IRQNum is set to 0 the PeriodicOnly parameter is
2572 overidden, it is forced to a value of 0.
2573 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2574 initialization failed.
2577 If periodic interrupts are to be disabled but AIOP interrupts
2578 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2580 If interrupts are to be completely disabled set IRQNum to 0.
2582 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2583 invalid combination.
2585 This function performs initialization of global interrupt modes,
2586 but it does not actually enable global interrupts. To enable
2587 and disable global interrupts use functions sEnGlobalInt() and
2588 sDisGlobalInt(). Enabling of global interrupts is normally not
2589 done until all other initializations are complete.
2591 Even if interrupts are globally enabled, they must also be
2592 individually enabled for each channel that is to generate
2595 Warnings: No range checking on any of the parameters is done.
2597 No context switches are allowed while executing this function.
2599 After this function all AIOPs on the controller are disabled,
2600 they can be enabled with sEnAiop().
2602 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2603 ByteIO_t * AiopIOList, int AiopIOListSize,
2604 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2610 CtlP->AiopIntrBits = aiop_intr_bits;
2611 CtlP->AltChanRingIndicator = 0;
2612 CtlP->CtlNum = CtlNum;
2613 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2614 CtlP->BusType = isISA;
2615 CtlP->MBaseIO = MudbacIO;
2616 CtlP->MReg1IO = MudbacIO + 1;
2617 CtlP->MReg2IO = MudbacIO + 2;
2618 CtlP->MReg3IO = MudbacIO + 3;
2620 CtlP->MReg2 = 0; /* interrupt disable */
2621 CtlP->MReg3 = 0; /* no periodic interrupts */
2623 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2624 CtlP->MReg2 = 0; /* interrupt disable */
2625 CtlP->MReg3 = 0; /* no periodic interrupts */
2627 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2628 CtlP->MReg3 = Frequency; /* set frequency */
2629 if (PeriodicOnly) { /* periodic interrupt only */
2630 CtlP->MReg3 |= PERIODIC_ONLY;
2634 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2635 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2636 sControllerEOI(CtlP); /* clear EOI if warm init */
2639 for (i = done = 0; i < AiopIOListSize; i++) {
2641 CtlP->AiopIO[i] = (WordIO_t) io;
2642 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2643 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2644 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2647 sEnAiop(CtlP, i); /* enable the AIOP */
2648 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2649 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2650 done = 1; /* done looking for AIOPs */
2652 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2653 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2654 sOutB(io + _INDX_DATA, sClockPrescale);
2655 CtlP->NumAiop++; /* bump count of AIOPs */
2657 sDisAiop(CtlP, i); /* disable AIOP */
2660 if (CtlP->NumAiop == 0)
2663 return (CtlP->NumAiop);
2666 /***************************************************************************
2667 Function: sPCIInitController
2668 Purpose: Initialization of controller global registers and controller
2670 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2671 IRQNum,Frequency,PeriodicOnly)
2672 CONTROLLER_T *CtlP; Ptr to controller structure
2673 int CtlNum; Controller number
2674 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2675 This list must be in the order the AIOPs will be found on the
2676 controller. Once an AIOP in the list is not found, it is
2677 assumed that there are no more AIOPs on the controller.
2678 int AiopIOListSize; Number of addresses in AiopIOList
2679 int IRQNum; Interrupt Request number. Can be any of the following:
2680 0: Disable global interrupts
2689 Byte_t Frequency: A flag identifying the frequency
2690 of the periodic interrupt, can be any one of the following:
2691 FREQ_DIS - periodic interrupt disabled
2692 FREQ_137HZ - 137 Hertz
2693 FREQ_69HZ - 69 Hertz
2694 FREQ_34HZ - 34 Hertz
2695 FREQ_17HZ - 17 Hertz
2698 If IRQNum is set to 0 the Frequency parameter is
2699 overidden, it is forced to a value of FREQ_DIS.
2700 int PeriodicOnly: 1 if all interrupts except the periodic
2701 interrupt are to be blocked.
2702 0 is both the periodic interrupt and
2703 other channel interrupts are allowed.
2704 If IRQNum is set to 0 the PeriodicOnly parameter is
2705 overidden, it is forced to a value of 0.
2706 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2707 initialization failed.
2710 If periodic interrupts are to be disabled but AIOP interrupts
2711 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2713 If interrupts are to be completely disabled set IRQNum to 0.
2715 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2716 invalid combination.
2718 This function performs initialization of global interrupt modes,
2719 but it does not actually enable global interrupts. To enable
2720 and disable global interrupts use functions sEnGlobalInt() and
2721 sDisGlobalInt(). Enabling of global interrupts is normally not
2722 done until all other initializations are complete.
2724 Even if interrupts are globally enabled, they must also be
2725 individually enabled for each channel that is to generate
2728 Warnings: No range checking on any of the parameters is done.
2730 No context switches are allowed while executing this function.
2732 After this function all AIOPs on the controller are disabled,
2733 they can be enabled with sEnAiop().
2735 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2736 ByteIO_t * AiopIOList, int AiopIOListSize,
2737 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2738 int PeriodicOnly, int altChanRingIndicator,
2744 CtlP->AltChanRingIndicator = altChanRingIndicator;
2745 CtlP->UPCIRingInd = UPCIRingInd;
2746 CtlP->CtlNum = CtlNum;
2747 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2748 CtlP->BusType = isPCI; /* controller release 1 */
2752 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2753 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2754 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2758 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2759 CtlP->AiopIntrBits = aiop_intr_bits;
2762 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2765 for (i = 0; i < AiopIOListSize; i++) {
2767 CtlP->AiopIO[i] = (WordIO_t) io;
2768 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2770 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2771 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2772 break; /* done looking for AIOPs */
2774 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2775 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2776 sOutB(io + _INDX_DATA, sClockPrescale);
2777 CtlP->NumAiop++; /* bump count of AIOPs */
2780 if (CtlP->NumAiop == 0)
2783 return (CtlP->NumAiop);
2786 /***************************************************************************
2787 Function: sReadAiopID
2788 Purpose: Read the AIOP idenfication number directly from an AIOP.
2789 Call: sReadAiopID(io)
2790 ByteIO_t io: AIOP base I/O address
2791 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2792 is replace by an identifying number.
2793 Flag AIOPID_NULL if no valid AIOP is found
2794 Warnings: No context switches are allowed while executing this function.
2797 static int sReadAiopID(ByteIO_t io)
2799 Byte_t AiopID; /* ID byte from AIOP */
2801 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2802 sOutB(io + _CMD_REG, 0x0);
2803 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2806 else /* AIOP does not exist */
2810 /***************************************************************************
2811 Function: sReadAiopNumChan
2812 Purpose: Read the number of channels available in an AIOP directly from
2814 Call: sReadAiopNumChan(io)
2815 WordIO_t io: AIOP base I/O address
2816 Return: int: The number of channels available
2817 Comments: The number of channels is determined by write/reads from identical
2818 offsets within the SRAM address spaces for channels 0 and 4.
2819 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2820 AIOP, otherwise it is an 8 channel.
2821 Warnings: No context switches are allowed while executing this function.
2823 static int sReadAiopNumChan(WordIO_t io)
2826 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2828 /* write to chan 0 SRAM */
2829 out32((DWordIO_t) io + _INDX_ADDR, R);
2830 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2831 x = sInW(io + _INDX_DATA);
2832 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2833 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2839 /***************************************************************************
2841 Purpose: Initialization of a channel and channel structure
2842 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2843 CONTROLLER_T *CtlP; Ptr to controller structure
2844 CHANNEL_T *ChP; Ptr to channel structure
2845 int AiopNum; AIOP number within controller
2846 int ChanNum; Channel number within AIOP
2847 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2848 number exceeds number of channels available in AIOP.
2849 Comments: This function must be called before a channel can be used.
2850 Warnings: No range checking on any of the parameters is done.
2852 No context switches are allowed while executing this function.
2854 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2865 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2866 return 0; /* exceeds num chans in AIOP */
2868 /* Channel, AIOP, and controller identifiers */
2870 ChP->ChanID = CtlP->AiopID[AiopNum];
2871 ChP->AiopNum = AiopNum;
2872 ChP->ChanNum = ChanNum;
2874 /* Global direct addresses */
2875 AiopIO = CtlP->AiopIO[AiopNum];
2876 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2877 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2878 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2879 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2880 ChP->IndexData = AiopIO + _INDX_DATA;
2882 /* Channel direct addresses */
2883 ChIOOff = AiopIO + ChP->ChanNum * 2;
2884 ChP->TxRxData = ChIOOff + _TD0;
2885 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2886 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2887 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2889 /* Initialize the channel from the RData array */
2890 for (i = 0; i < RDATASIZE; i += 4) {
2892 R[1] = RData[i + 1] + 0x10 * ChanNum;
2893 R[2] = RData[i + 2];
2894 R[3] = RData[i + 3];
2895 out32(ChP->IndexAddr, R);
2899 for (i = 0; i < RREGDATASIZE; i += 4) {
2900 ChR[i] = RRegData[i];
2901 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2902 ChR[i + 2] = RRegData[i + 2];
2903 ChR[i + 3] = RRegData[i + 3];
2906 /* Indexed registers */
2907 ChOff = (Word_t) ChanNum *0x1000;
2909 if (sClockPrescale == 0x14)
2914 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2915 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2916 ChP->BaudDiv[2] = (Byte_t) brd9600;
2917 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2918 out32(ChP->IndexAddr, ChP->BaudDiv);
2920 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2921 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2922 ChP->TxControl[2] = 0;
2923 ChP->TxControl[3] = 0;
2924 out32(ChP->IndexAddr, ChP->TxControl);
2926 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2927 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2928 ChP->RxControl[2] = 0;
2929 ChP->RxControl[3] = 0;
2930 out32(ChP->IndexAddr, ChP->RxControl);
2932 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2933 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2934 ChP->TxEnables[2] = 0;
2935 ChP->TxEnables[3] = 0;
2936 out32(ChP->IndexAddr, ChP->TxEnables);
2938 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2939 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2940 ChP->TxCompare[2] = 0;
2941 ChP->TxCompare[3] = 0;
2942 out32(ChP->IndexAddr, ChP->TxCompare);
2944 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2945 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2946 ChP->TxReplace1[2] = 0;
2947 ChP->TxReplace1[3] = 0;
2948 out32(ChP->IndexAddr, ChP->TxReplace1);
2950 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2951 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2952 ChP->TxReplace2[2] = 0;
2953 ChP->TxReplace2[3] = 0;
2954 out32(ChP->IndexAddr, ChP->TxReplace2);
2956 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2957 ChP->TxFIFO = ChOff + _TX_FIFO;
2959 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2960 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2961 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2962 sOutW(ChP->IndexData, 0);
2963 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2964 ChP->RxFIFO = ChOff + _RX_FIFO;
2966 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2967 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2968 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2969 sOutW(ChP->IndexData, 0);
2970 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2971 sOutW(ChP->IndexData, 0);
2972 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2973 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2974 sOutB(ChP->IndexData, 0);
2975 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2976 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2977 sOutB(ChP->IndexData, 0);
2978 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2979 sEnRxProcessor(ChP); /* start the Rx processor */
2984 /***************************************************************************
2985 Function: sStopRxProcessor
2986 Purpose: Stop the receive processor from processing a channel.
2987 Call: sStopRxProcessor(ChP)
2988 CHANNEL_T *ChP; Ptr to channel structure
2990 Comments: The receive processor can be started again with sStartRxProcessor().
2991 This function causes the receive processor to skip over the
2992 stopped channel. It does not stop it from processing other channels.
2994 Warnings: No context switches are allowed while executing this function.
2996 Do not leave the receive processor stopped for more than one
2999 After calling this function a delay of 4 uS is required to ensure
3000 that the receive processor is no longer processing this channel.
3002 static void sStopRxProcessor(CHANNEL_T * ChP)
3010 out32(ChP->IndexAddr, R);
3013 /***************************************************************************
3014 Function: sFlushRxFIFO
3015 Purpose: Flush the Rx FIFO
3016 Call: sFlushRxFIFO(ChP)
3017 CHANNEL_T *ChP; Ptr to channel structure
3019 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3020 while it is being flushed the receive processor is stopped
3021 and the transmitter is disabled. After these operations a
3022 4 uS delay is done before clearing the pointers to allow
3023 the receive processor to stop. These items are handled inside
3025 Warnings: No context switches are allowed while executing this function.
3027 static void sFlushRxFIFO(CHANNEL_T * ChP)
3030 Byte_t Ch; /* channel number within AIOP */
3031 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
3033 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3034 return; /* don't need to flush */
3037 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3039 sDisRxFIFO(ChP); /* disable it */
3040 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3041 sInB(ChP->IntChan); /* depends on bus i/o timing */
3043 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3044 Ch = (Byte_t) sGetChanNum(ChP);
3045 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3046 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3047 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3048 sOutW(ChP->IndexData, 0);
3049 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3050 sOutW(ChP->IndexData, 0);
3052 sEnRxFIFO(ChP); /* enable Rx FIFO */
3055 /***************************************************************************
3056 Function: sFlushTxFIFO
3057 Purpose: Flush the Tx FIFO
3058 Call: sFlushTxFIFO(ChP)
3059 CHANNEL_T *ChP; Ptr to channel structure
3061 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3062 while it is being flushed the receive processor is stopped
3063 and the transmitter is disabled. After these operations a
3064 4 uS delay is done before clearing the pointers to allow
3065 the receive processor to stop. These items are handled inside
3067 Warnings: No context switches are allowed while executing this function.
3069 static void sFlushTxFIFO(CHANNEL_T * ChP)
3072 Byte_t Ch; /* channel number within AIOP */
3073 int TxEnabled; /* 1 if transmitter enabled */
3075 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3076 return; /* don't need to flush */
3079 if (ChP->TxControl[3] & TX_ENABLE) {
3081 sDisTransmit(ChP); /* disable transmitter */
3083 sStopRxProcessor(ChP); /* stop Rx processor */
3084 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3085 sInB(ChP->IntChan); /* depends on bus i/o timing */
3086 Ch = (Byte_t) sGetChanNum(ChP);
3087 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3088 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3089 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3090 sOutW(ChP->IndexData, 0);
3092 sEnTransmit(ChP); /* enable transmitter */
3093 sStartRxProcessor(ChP); /* restart Rx processor */
3096 /***************************************************************************
3097 Function: sWriteTxPrioByte
3098 Purpose: Write a byte of priority transmit data to a channel
3099 Call: sWriteTxPrioByte(ChP,Data)
3100 CHANNEL_T *ChP; Ptr to channel structure
3101 Byte_t Data; The transmit data byte
3103 Return: int: 1 if the bytes is successfully written, otherwise 0.
3105 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3107 Warnings: No context switches are allowed while executing this function.
3109 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3111 Byte_t DWBuf[4]; /* buffer for double word writes */
3112 Word_t *WordPtr; /* must be far because Win SS != DS */
3113 register DWordIO_t IndexAddr;
3115 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3116 IndexAddr = ChP->IndexAddr;
3117 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3118 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3119 return (0); /* nothing sent */
3121 WordPtr = (Word_t *) (&DWBuf[0]);
3122 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3124 DWBuf[2] = Data; /* data byte value */
3125 out32(IndexAddr, DWBuf); /* write it out */
3127 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3129 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3130 DWBuf[3] = 0; /* priority buffer pointer */
3131 out32(IndexAddr, DWBuf); /* write it out */
3132 } else { /* write it to Tx FIFO */
3134 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3136 return (1); /* 1 byte sent */
3139 /***************************************************************************
3140 Function: sEnInterrupts
3141 Purpose: Enable one or more interrupts for a channel
3142 Call: sEnInterrupts(ChP,Flags)
3143 CHANNEL_T *ChP; Ptr to channel structure
3144 Word_t Flags: Interrupt enable flags, can be any combination
3145 of the following flags:
3146 TXINT_EN: Interrupt on Tx FIFO empty
3147 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3149 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3150 MCINT_EN: Interrupt on modem input change
3151 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3152 Interrupt Channel Register.
3154 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3155 enabled. If an interrupt enable flag is not set in Flags, that
3156 interrupt will not be changed. Interrupts can be disabled with
3157 function sDisInterrupts().
3159 This function sets the appropriate bit for the channel in the AIOP's
3160 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3161 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3163 Interrupts must also be globally enabled before channel interrupts
3164 will be passed on to the host. This is done with function
3167 In some cases it may be desirable to disable interrupts globally but
3168 enable channel interrupts. This would allow the global interrupt
3169 status register to be used to determine which AIOPs need service.
3171 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3173 Byte_t Mask; /* Interrupt Mask Register */
3175 ChP->RxControl[2] |=
3176 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3178 out32(ChP->IndexAddr, ChP->RxControl);
3180 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3182 out32(ChP->IndexAddr, ChP->TxControl);
3184 if (Flags & CHANINT_EN) {
3185 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3186 sOutB(ChP->IntMask, Mask);
3190 /***************************************************************************
3191 Function: sDisInterrupts
3192 Purpose: Disable one or more interrupts for a channel
3193 Call: sDisInterrupts(ChP,Flags)
3194 CHANNEL_T *ChP; Ptr to channel structure
3195 Word_t Flags: Interrupt flags, can be any combination
3196 of the following flags:
3197 TXINT_EN: Interrupt on Tx FIFO empty
3198 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3200 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3201 MCINT_EN: Interrupt on modem input change
3202 CHANINT_EN: Disable channel interrupt signal to the
3203 AIOP's Interrupt Channel Register.
3205 Comments: If an interrupt flag is set in Flags, that interrupt will be
3206 disabled. If an interrupt flag is not set in Flags, that
3207 interrupt will not be changed. Interrupts can be enabled with
3208 function sEnInterrupts().
3210 This function clears the appropriate bit for the channel in the AIOP's
3211 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3212 this channel's bit from being set in the AIOP's Interrupt Channel
3215 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3217 Byte_t Mask; /* Interrupt Mask Register */
3219 ChP->RxControl[2] &=
3220 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3221 out32(ChP->IndexAddr, ChP->RxControl);
3222 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3223 out32(ChP->IndexAddr, ChP->TxControl);
3225 if (Flags & CHANINT_EN) {
3226 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3227 sOutB(ChP->IntMask, Mask);
3231 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3233 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3237 * Not an official SSCI function, but how to reset RocketModems.
3240 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3245 addr = CtlP->AiopIO[0] + 0x400;
3246 val = sInB(CtlP->MReg3IO);
3247 /* if AIOP[1] is not enabled, enable it */
3248 if ((val & 2) == 0) {
3249 val = sInB(CtlP->MReg2IO);
3250 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3251 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3257 sOutB(addr + chan, 0); /* apply or remove reset */
3262 * Not an official SSCI function, but how to reset RocketModems.
3265 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3269 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3272 sOutB(addr + chan, 0); /* apply or remove reset */
3275 /* Resets the speaker controller on RocketModem II and III devices */
3276 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3280 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3281 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3282 addr = CtlP->AiopIO[0] + 0x4F;
3286 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3287 if ((model == MODEL_UPCI_RM3_8PORT)
3288 || (model == MODEL_UPCI_RM3_4PORT)) {
3289 addr = CtlP->AiopIO[0] + 0x88;
3294 /* Returns the line number given the controller (board), aiop and channel number */
3295 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3297 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3301 * Stores the line number associated with a given controller (board), aiop
3302 * and channel number.
3303 * Returns: The line number assigned
3305 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3307 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3308 return (nextLineNumber - 1);