SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/char/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35 #include "r300_reg.h"
  36
  37 #include "radeon_microcode.h"
  38
  39 #define RADEON_FIFO_DEBUG       0
  40
  41 static int radeon_do_cleanup_cp(struct drm_device * dev);
  42
  43 static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  44 {
  45         u32 ret;
  46         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  47         ret = RADEON_READ(R520_MC_IND_DATA);
  48         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  49         return ret;
  50 }
  51
  52 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  53 {
  54         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  55         return RADEON_READ(RS690_MC_DATA);
  56 }
  57
  58 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  59 {
  60
  61         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  62                 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
  63         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  64                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
  65         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  66                 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
  67         else
  68                 return RADEON_READ(RADEON_MC_FB_LOCATION);
  69 }
  70
  71 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
  72 {
  73         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  74                 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
  75         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  76                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
  77         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  78                 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
  79         else
  80                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
  81 }
  82
  83 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
  84 {
  85         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  86                 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
  87         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  88                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
  89         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  90                 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
  91         else
  92                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
  93 }
  94
  95 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
  96 {
  97         drm_radeon_private_t *dev_priv = dev->dev_private;
  98
  99         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 100         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 101 }
 102
 103 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 104 {
 105         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 106         return RADEON_READ(RADEON_PCIE_DATA);
 107 }
 108
 109 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
 110 {
 111         u32 ret;
 112         RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
 113         ret = RADEON_READ(RADEON_IGPGART_DATA);
 114         RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
 115         return ret;
 116 }
 117
 118 #if RADEON_FIFO_DEBUG
 119 static void radeon_status(drm_radeon_private_t * dev_priv)
 120 {
 121         printk("%s:\n", __func__);
 122         printk("RBBM_STATUS = 0x%08x\n",
 123                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 124         printk("CP_RB_RTPR = 0x%08x\n",
 125                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 126         printk("CP_RB_WTPR = 0x%08x\n",
 127                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 128         printk("AIC_CNTL = 0x%08x\n",
 129                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 130         printk("AIC_STAT = 0x%08x\n",
 131                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 132         printk("AIC_PT_BASE = 0x%08x\n",
 133                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 134         printk("TLB_ADDR = 0x%08x\n",
 135                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 136         printk("TLB_DATA = 0x%08x\n",
 137                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 138 }
 139 #endif
 140
 141 /* ================================================================
 142  * Engine, FIFO control
 143  */
 144
 145 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 146 {
 147         u32 tmp;
 148         int i;
 149
 150         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 151
 152         tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 153         tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 154         RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 155
 156         for (i = 0; i < dev_priv->usec_timeout; i++) {
 157                 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 158                       & RADEON_RB3D_DC_BUSY)) {
 159                         return 0;
 160                 }
 161                 DRM_UDELAY(1);
 162         }
 163
 164 #if RADEON_FIFO_DEBUG
 165         DRM_ERROR("failed!\n");
 166         radeon_status(dev_priv);
 167 #endif
 168         return -EBUSY;
 169 }
 170
 171 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 172 {
 173         int i;
 174
 175         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 176
 177         for (i = 0; i < dev_priv->usec_timeout; i++) {
 178                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 179                              & RADEON_RBBM_FIFOCNT_MASK);
 180                 if (slots >= entries)
 181                         return 0;
 182                 DRM_UDELAY(1);
 183         }
 184
 185 #if RADEON_FIFO_DEBUG
 186         DRM_ERROR("failed!\n");
 187         radeon_status(dev_priv);
 188 #endif
 189         return -EBUSY;
 190 }
 191
 192 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 193 {
 194         int i, ret;
 195
 196         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 197
 198         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 199         if (ret)
 200                 return ret;
 201
 202         for (i = 0; i < dev_priv->usec_timeout; i++) {
 203                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 204                       & RADEON_RBBM_ACTIVE)) {
 205                         radeon_do_pixcache_flush(dev_priv);
 206                         return 0;
 207                 }
 208                 DRM_UDELAY(1);
 209         }
 210
 211 #if RADEON_FIFO_DEBUG
 212         DRM_ERROR("failed!\n");
 213         radeon_status(dev_priv);
 214 #endif
 215         return -EBUSY;
 216 }
 217
 218 /* ================================================================
 219  * CP control, initialization
 220  */
 221
 222 /* Load the microcode for the CP */
 223 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 224 {
 225         int i;
 226         DRM_DEBUG("\n");
 227
 228         radeon_do_wait_for_idle(dev_priv);
 229
 230         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 231         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 232             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 233             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 234             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 235             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 236                 DRM_INFO("Loading R100 Microcode\n");
 237                 for (i = 0; i < 256; i++) {
 238                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 239                                      R100_cp_microcode[i][1]);
 240                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 241                                      R100_cp_microcode[i][0]);
 242                 }
 243         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 244                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 245                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 246                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 247                 DRM_INFO("Loading R200 Microcode\n");
 248                 for (i = 0; i < 256; i++) {
 249                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 250                                      R200_cp_microcode[i][1]);
 251                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 252                                      R200_cp_microcode[i][0]);
 253                 }
 254         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 255                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 256                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 257                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 258                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400)) {
 259                 DRM_INFO("Loading R300 Microcode\n");
 260                 for (i = 0; i < 256; i++) {
 261                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 262                                      R300_cp_microcode[i][1]);
 263                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 264                                      R300_cp_microcode[i][0]);
 265                 }
 266         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 267                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 268                 DRM_INFO("Loading R400 Microcode\n");
 269                 for (i = 0; i < 256; i++) {
 270                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 271                                      R420_cp_microcode[i][1]);
 272                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 273                                      R420_cp_microcode[i][0]);
 274                 }
 275         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 276                 DRM_INFO("Loading RS690 Microcode\n");
 277                 for (i = 0; i < 256; i++) {
 278                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 279                                      RS690_cp_microcode[i][1]);
 280                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 281                                      RS690_cp_microcode[i][0]);
 282                 }
 283         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 284                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 285                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 286                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 287                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 288                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 289                 DRM_INFO("Loading R500 Microcode\n");
 290                 for (i = 0; i < 256; i++) {
 291                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 292                                      R520_cp_microcode[i][1]);
 293                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 294                                      R520_cp_microcode[i][0]);
 295                 }
 296         }
 297 }
 298
 299 /* Flush any pending commands to the CP.  This should only be used just
 300  * prior to a wait for idle, as it informs the engine that the command
 301  * stream is ending.
 302  */
 303 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 304 {
 305         DRM_DEBUG("\n");
 306 #if 0
 307         u32 tmp;
 308
 309         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 310         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 311 #endif
 312 }
 313
 314 /* Wait for the CP to go idle.
 315  */
 316 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 317 {
 318         RING_LOCALS;
 319         DRM_DEBUG("\n");
 320
 321         BEGIN_RING(6);
 322
 323         RADEON_PURGE_CACHE();
 324         RADEON_PURGE_ZCACHE();
 325         RADEON_WAIT_UNTIL_IDLE();
 326
 327         ADVANCE_RING();
 328         COMMIT_RING();
 329
 330         return radeon_do_wait_for_idle(dev_priv);
 331 }
 332
 333 /* Start the Command Processor.
 334  */
 335 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 336 {
 337         RING_LOCALS;
 338         DRM_DEBUG("\n");
 339
 340         radeon_do_wait_for_idle(dev_priv);
 341
 342         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 343
 344         dev_priv->cp_running = 1;
 345
 346         BEGIN_RING(6);
 347
 348         RADEON_PURGE_CACHE();
 349         RADEON_PURGE_ZCACHE();
 350         RADEON_WAIT_UNTIL_IDLE();
 351
 352         ADVANCE_RING();
 353         COMMIT_RING();
 354 }
 355
 356 /* Reset the Command Processor.  This will not flush any pending
 357  * commands, so you must wait for the CP command stream to complete
 358  * before calling this routine.
 359  */
 360 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 361 {
 362         u32 cur_read_ptr;
 363         DRM_DEBUG("\n");
 364
 365         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 366         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 367         SET_RING_HEAD(dev_priv, cur_read_ptr);
 368         dev_priv->ring.tail = cur_read_ptr;
 369 }
 370
 371 /* Stop the Command Processor.  This will not flush any pending
 372  * commands, so you must flush the command stream and wait for the CP
 373  * to go idle before calling this routine.
 374  */
 375 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 376 {
 377         DRM_DEBUG("\n");
 378
 379         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 380
 381         dev_priv->cp_running = 0;
 382 }
 383
 384 /* Reset the engine.  This will stop the CP if it is running.
 385  */
 386 static int radeon_do_engine_reset(struct drm_device * dev)
 387 {
 388         drm_radeon_private_t *dev_priv = dev->dev_private;
 389         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 390         DRM_DEBUG("\n");
 391
 392         radeon_do_pixcache_flush(dev_priv);
 393
 394         if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
 395                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 396                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 397
 398                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 399                                                     RADEON_FORCEON_MCLKA |
 400                                                     RADEON_FORCEON_MCLKB |
 401                                                     RADEON_FORCEON_YCLKA |
 402                                                     RADEON_FORCEON_YCLKB |
 403                                                     RADEON_FORCEON_MC |
 404                                                     RADEON_FORCEON_AIC));
 405
 406                 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 407
 408                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 409                                                       RADEON_SOFT_RESET_CP |
 410                                                       RADEON_SOFT_RESET_HI |
 411                                                       RADEON_SOFT_RESET_SE |
 412                                                       RADEON_SOFT_RESET_RE |
 413                                                       RADEON_SOFT_RESET_PP |
 414                                                       RADEON_SOFT_RESET_E2 |
 415                                                       RADEON_SOFT_RESET_RB));
 416                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 417                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 418                                                       ~(RADEON_SOFT_RESET_CP |
 419                                                         RADEON_SOFT_RESET_HI |
 420                                                         RADEON_SOFT_RESET_SE |
 421                                                         RADEON_SOFT_RESET_RE |
 422                                                         RADEON_SOFT_RESET_PP |
 423                                                         RADEON_SOFT_RESET_E2 |
 424                                                         RADEON_SOFT_RESET_RB)));
 425                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 426
 427                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 428                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 429                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 430         }
 431
 432         /* Reset the CP ring */
 433         radeon_do_cp_reset(dev_priv);
 434
 435         /* The CP is no longer running after an engine reset */
 436         dev_priv->cp_running = 0;
 437
 438         /* Reset any pending vertex, indirect buffers */
 439         radeon_freelist_reset(dev);
 440
 441         return 0;
 442 }
 443
 444 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 445                                        drm_radeon_private_t * dev_priv)
 446 {
 447         u32 ring_start, cur_read_ptr;
 448         u32 tmp;
 449
 450         /* Initialize the memory controller. With new memory map, the fb location
 451          * is not changed, it should have been properly initialized already. Part
 452          * of the problem is that the code below is bogus, assuming the GART is
 453          * always appended to the fb which is not necessarily the case
 454          */
 455         if (!dev_priv->new_memmap)
 456                 radeon_write_fb_location(dev_priv,
 457                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 458                              | (dev_priv->fb_location >> 16));
 459
 460 #if __OS_HAS_AGP
 461         if (dev_priv->flags & RADEON_IS_AGP) {
 462                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
 463                 radeon_write_agp_location(dev_priv,
 464                              (((dev_priv->gart_vm_start - 1 +
 465                                 dev_priv->gart_size) & 0xffff0000) |
 466                               (dev_priv->gart_vm_start >> 16)));
 467
 468                 ring_start = (dev_priv->cp_ring->offset
 469                               - dev->agp->base
 470                               + dev_priv->gart_vm_start);
 471         } else
 472 #endif
 473                 ring_start = (dev_priv->cp_ring->offset
 474                               - (unsigned long)dev->sg->virtual
 475                               + dev_priv->gart_vm_start);
 476
 477         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 478
 479         /* Set the write pointer delay */
 480         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 481
 482         /* Initialize the ring buffer's read and write pointers */
 483         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 484         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 485         SET_RING_HEAD(dev_priv, cur_read_ptr);
 486         dev_priv->ring.tail = cur_read_ptr;
 487
 488 #if __OS_HAS_AGP
 489         if (dev_priv->flags & RADEON_IS_AGP) {
 490                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 491                              dev_priv->ring_rptr->offset
 492                              - dev->agp->base + dev_priv->gart_vm_start);
 493         } else
 494 #endif
 495         {
 496                 struct drm_sg_mem *entry = dev->sg;
 497                 unsigned long tmp_ofs, page_ofs;
 498
 499                 tmp_ofs = dev_priv->ring_rptr->offset -
 500                                 (unsigned long)dev->sg->virtual;
 501                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 502
 503                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 504                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 505                           (unsigned long)entry->busaddr[page_ofs],
 506                           entry->handle + tmp_ofs);
 507         }
 508
 509         /* Set ring buffer size */
 510 #ifdef __BIG_ENDIAN
 511         RADEON_WRITE(RADEON_CP_RB_CNTL,
 512                      RADEON_BUF_SWAP_32BIT |
 513                      (dev_priv->ring.fetch_size_l2ow << 18) |
 514                      (dev_priv->ring.rptr_update_l2qw << 8) |
 515                      dev_priv->ring.size_l2qw);
 516 #else
 517         RADEON_WRITE(RADEON_CP_RB_CNTL,
 518                      (dev_priv->ring.fetch_size_l2ow << 18) |
 519                      (dev_priv->ring.rptr_update_l2qw << 8) |
 520                      dev_priv->ring.size_l2qw);
 521 #endif
 522
 523         /* Start with assuming that writeback doesn't work */
 524         dev_priv->writeback_works = 0;
 525
 526         /* Initialize the scratch register pointer.  This will cause
 527          * the scratch register values to be written out to memory
 528          * whenever they are updated.
 529          *
 530          * We simply put this behind the ring read pointer, this works
 531          * with PCI GART as well as (whatever kind of) AGP GART
 532          */
 533         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 534                      + RADEON_SCRATCH_REG_OFFSET);
 535
 536         dev_priv->scratch = ((__volatile__ u32 *)
 537                              dev_priv->ring_rptr->handle +
 538                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 539
 540         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 541
 542         /* Turn on bus mastering */
 543         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 544         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 545
 546         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 547         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 548
 549         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 550         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
 551                      dev_priv->sarea_priv->last_dispatch);
 552
 553         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 554         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 555
 556         radeon_do_wait_for_idle(dev_priv);
 557
 558         /* Sync everything up */
 559         RADEON_WRITE(RADEON_ISYNC_CNTL,
 560                      (RADEON_ISYNC_ANY2D_IDLE3D |
 561                       RADEON_ISYNC_ANY3D_IDLE2D |
 562                       RADEON_ISYNC_WAIT_IDLEGUI |
 563                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 564
 565 }
 566
 567 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 568 {
 569         u32 tmp;
 570
 571         /* Writeback doesn't seem to work everywhere, test it here and possibly
 572          * enable it if it appears to work
 573          */
 574         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
 575         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 576
 577         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 578                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
 579                     0xdeadbeef)
 580                         break;
 581                 DRM_UDELAY(1);
 582         }
 583
 584         if (tmp < dev_priv->usec_timeout) {
 585                 dev_priv->writeback_works = 1;
 586                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 587         } else {
 588                 dev_priv->writeback_works = 0;
 589                 DRM_INFO("writeback test failed\n");
 590         }
 591         if (radeon_no_wb == 1) {
 592                 dev_priv->writeback_works = 0;
 593                 DRM_INFO("writeback forced off\n");
 594         }
 595
 596         if (!dev_priv->writeback_works) {
 597                 /* Disable writeback to avoid unnecessary bus master transfer */
 598                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 599                              RADEON_RB_NO_UPDATE);
 600                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 601         }
 602 }
 603
 604 /* Enable or disable IGP GART on the chip */
 605 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 606 {
 607         u32 temp, tmp;
 608
 609         tmp = RADEON_READ(RADEON_AIC_CNTL);
 610         if (on) {
 611                 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
 612                          dev_priv->gart_vm_start,
 613                          (long)dev_priv->gart_info.bus_addr,
 614                          dev_priv->gart_size);
 615
 616                 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
 617                 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
 618                 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
 619                 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
 620                                      dev_priv->gart_info.bus_addr);
 621
 622                 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
 623                 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
 624
 625                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
 626                 dev_priv->gart_size = 32*1024*1024;
 627                 radeon_write_agp_location(dev_priv,
 628                              (((dev_priv->gart_vm_start - 1 +
 629                                dev_priv->gart_size) & 0xffff0000) |
 630                              (dev_priv->gart_vm_start >> 16)));
 631
 632                 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
 633                 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
 634
 635                 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
 636                 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
 637                 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
 638                 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
 639        }
 640 }
 641
 642 /* Enable or disable RS690 GART on the chip */
 643 static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
 644 {
 645         u32 temp;
 646
 647         if (on) {
 648                 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
 649                           dev_priv->gart_vm_start,
 650                           (long)dev_priv->gart_info.bus_addr,
 651                           dev_priv->gart_size);
 652
 653                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
 654                 RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
 655
 656                 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
 657                                   RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
 658
 659                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
 660                 RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
 661
 662                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 663                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 664                 RS690_WRITE_MCIND(RS690_MC_GART_BASE, temp);
 665
 666                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
 667                 RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
 668
 669                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
 670                                   (unsigned int)dev_priv->gart_vm_start);
 671
 672                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
 673
 674                 dev_priv->gart_size = 32*1024*1024;
 675                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 676                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 677
 678                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
 679
 680                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
 681                 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
 682                                   RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
 683
 684                 do {
 685                         temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
 686                         if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
 687                             RS690_MC_GART_CLEAR_DONE)
 688                                 break;
 689                         DRM_UDELAY(1);
 690                 } while (1);
 691
 692                 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
 693                                   RS690_MC_GART_CC_CLEAR);
 694                 do {
 695                         temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
 696                         if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
 697                                    RS690_MC_GART_CLEAR_DONE)
 698                                 break;
 699                         DRM_UDELAY(1);
 700                 } while (1);
 701
 702                 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
 703                                   RS690_MC_GART_CC_NO_CHANGE);
 704         } else {
 705                 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
 706         }
 707 }
 708
 709 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 710 {
 711         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 712         if (on) {
 713
 714                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 715                           dev_priv->gart_vm_start,
 716                           (long)dev_priv->gart_info.bus_addr,
 717                           dev_priv->gart_size);
 718                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 719                                   dev_priv->gart_vm_start);
 720                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 721                                   dev_priv->gart_info.bus_addr);
 722                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 723                                   dev_priv->gart_vm_start);
 724                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 725                                   dev_priv->gart_vm_start +
 726                                   dev_priv->gart_size - 1);
 727
 728                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 729
 730                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 731                                   RADEON_PCIE_TX_GART_EN);
 732         } else {
 733                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 734                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 735         }
 736 }
 737
 738 /* Enable or disable PCI GART on the chip */
 739 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 740 {
 741         u32 tmp;
 742
 743         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 744                 radeon_set_rs690gart(dev_priv, on);
 745                 return;
 746         }
 747
 748         if (dev_priv->flags & RADEON_IS_IGPGART) {
 749                 radeon_set_igpgart(dev_priv, on);
 750                 return;
 751         }
 752
 753         if (dev_priv->flags & RADEON_IS_PCIE) {
 754                 radeon_set_pciegart(dev_priv, on);
 755                 return;
 756         }
 757
 758         tmp = RADEON_READ(RADEON_AIC_CNTL);
 759
 760         if (on) {
 761                 RADEON_WRITE(RADEON_AIC_CNTL,
 762                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 763
 764                 /* set PCI GART page-table base address
 765                  */
 766                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 767
 768                 /* set address range for PCI address translate
 769                  */
 770                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 771                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 772                              + dev_priv->gart_size - 1);
 773
 774                 /* Turn off AGP aperture -- is this required for PCI GART?
 775                  */
 776                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 777                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 778         } else {
 779                 RADEON_WRITE(RADEON_AIC_CNTL,
 780                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 781         }
 782 }
 783
 784 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 785 {
 786         drm_radeon_private_t *dev_priv = dev->dev_private;
 787
 788         DRM_DEBUG("\n");
 789
 790         /* if we require new memory map but we don't have it fail */
 791         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 792                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 793                 radeon_do_cleanup_cp(dev);
 794                 return -EINVAL;
 795         }
 796
 797         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
 798                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 799                 dev_priv->flags &= ~RADEON_IS_AGP;
 800         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 801                    && !init->is_pci) {
 802                 DRM_DEBUG("Restoring AGP flag\n");
 803                 dev_priv->flags |= RADEON_IS_AGP;
 804         }
 805
 806         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 807                 DRM_ERROR("PCI GART memory not allocated!\n");
 808                 radeon_do_cleanup_cp(dev);
 809                 return -EINVAL;
 810         }
 811
 812         dev_priv->usec_timeout = init->usec_timeout;
 813         if (dev_priv->usec_timeout < 1 ||
 814             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 815                 DRM_DEBUG("TIMEOUT problem!\n");
 816                 radeon_do_cleanup_cp(dev);
 817                 return -EINVAL;
 818         }
 819
 820         /* Enable vblank on CRTC1 for older X servers
 821          */
 822         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 823
 824         switch(init->func) {
 825         case RADEON_INIT_R200_CP:
 826                 dev_priv->microcode_version = UCODE_R200;
 827                 break;
 828         case RADEON_INIT_R300_CP:
 829                 dev_priv->microcode_version = UCODE_R300;
 830                 break;
 831         default:
 832                 dev_priv->microcode_version = UCODE_R100;
 833         }
 834
 835         dev_priv->do_boxes = 0;
 836         dev_priv->cp_mode = init->cp_mode;
 837
 838         /* We don't support anything other than bus-mastering ring mode,
 839          * but the ring can be in either AGP or PCI space for the ring
 840          * read pointer.
 841          */
 842         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
 843             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
 844                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 845                 radeon_do_cleanup_cp(dev);
 846                 return -EINVAL;
 847         }
 848
 849         switch (init->fb_bpp) {
 850         case 16:
 851                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 852                 break;
 853         case 32:
 854         default:
 855                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 856                 break;
 857         }
 858         dev_priv->front_offset = init->front_offset;
 859         dev_priv->front_pitch = init->front_pitch;
 860         dev_priv->back_offset = init->back_offset;
 861         dev_priv->back_pitch = init->back_pitch;
 862
 863         switch (init->depth_bpp) {
 864         case 16:
 865                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 866                 break;
 867         case 32:
 868         default:
 869                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 870                 break;
 871         }
 872         dev_priv->depth_offset = init->depth_offset;
 873         dev_priv->depth_pitch = init->depth_pitch;
 874
 875         /* Hardware state for depth clears.  Remove this if/when we no
 876          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 877          * all values to prevent unwanted 3D state from slipping through
 878          * and screwing with the clear operation.
 879          */
 880         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 881                                            (dev_priv->color_fmt << 10) |
 882                                            (dev_priv->microcode_version ==
 883                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
 884
 885         dev_priv->depth_clear.rb3d_zstencilcntl =
 886             (dev_priv->depth_fmt |
 887              RADEON_Z_TEST_ALWAYS |
 888              RADEON_STENCIL_TEST_ALWAYS |
 889              RADEON_STENCIL_S_FAIL_REPLACE |
 890              RADEON_STENCIL_ZPASS_REPLACE |
 891              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 892
 893         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 894                                          RADEON_BFACE_SOLID |
 895                                          RADEON_FFACE_SOLID |
 896                                          RADEON_FLAT_SHADE_VTX_LAST |
 897                                          RADEON_DIFFUSE_SHADE_FLAT |
 898                                          RADEON_ALPHA_SHADE_FLAT |
 899                                          RADEON_SPECULAR_SHADE_FLAT |
 900                                          RADEON_FOG_SHADE_FLAT |
 901                                          RADEON_VTX_PIX_CENTER_OGL |
 902                                          RADEON_ROUND_MODE_TRUNC |
 903                                          RADEON_ROUND_PREC_8TH_PIX);
 904
 905
 906         dev_priv->ring_offset = init->ring_offset;
 907         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 908         dev_priv->buffers_offset = init->buffers_offset;
 909         dev_priv->gart_textures_offset = init->gart_textures_offset;
 910
 911         dev_priv->sarea = drm_getsarea(dev);
 912         if (!dev_priv->sarea) {
 913                 DRM_ERROR("could not find sarea!\n");
 914                 radeon_do_cleanup_cp(dev);
 915                 return -EINVAL;
 916         }
 917
 918         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
 919         if (!dev_priv->cp_ring) {
 920                 DRM_ERROR("could not find cp ring region!\n");
 921                 radeon_do_cleanup_cp(dev);
 922                 return -EINVAL;
 923         }
 924         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
 925         if (!dev_priv->ring_rptr) {
 926                 DRM_ERROR("could not find ring read pointer!\n");
 927                 radeon_do_cleanup_cp(dev);
 928                 return -EINVAL;
 929         }
 930         dev->agp_buffer_token = init->buffers_offset;
 931         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
 932         if (!dev->agp_buffer_map) {
 933                 DRM_ERROR("could not find dma buffer region!\n");
 934                 radeon_do_cleanup_cp(dev);
 935                 return -EINVAL;
 936         }
 937
 938         if (init->gart_textures_offset) {
 939                 dev_priv->gart_textures =
 940                     drm_core_findmap(dev, init->gart_textures_offset);
 941                 if (!dev_priv->gart_textures) {
 942                         DRM_ERROR("could not find GART texture region!\n");
 943                         radeon_do_cleanup_cp(dev);
 944                         return -EINVAL;
 945                 }
 946         }
 947
 948         dev_priv->sarea_priv =
 949             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 950                                     init->sarea_priv_offset);
 951
 952 #if __OS_HAS_AGP
 953         if (dev_priv->flags & RADEON_IS_AGP) {
 954                 drm_core_ioremap(dev_priv->cp_ring, dev);
 955                 drm_core_ioremap(dev_priv->ring_rptr, dev);
 956                 drm_core_ioremap(dev->agp_buffer_map, dev);
 957                 if (!dev_priv->cp_ring->handle ||
 958                     !dev_priv->ring_rptr->handle ||
 959                     !dev->agp_buffer_map->handle) {
 960                         DRM_ERROR("could not find ioremap agp regions!\n");
 961                         radeon_do_cleanup_cp(dev);
 962                         return -EINVAL;
 963                 }
 964         } else
 965 #endif
 966         {
 967                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
 968                 dev_priv->ring_rptr->handle =
 969                     (void *)dev_priv->ring_rptr->offset;
 970                 dev->agp_buffer_map->handle =
 971                     (void *)dev->agp_buffer_map->offset;
 972
 973                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
 974                           dev_priv->cp_ring->handle);
 975                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
 976                           dev_priv->ring_rptr->handle);
 977                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
 978                           dev->agp_buffer_map->handle);
 979         }
 980
 981         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
 982         dev_priv->fb_size =
 983                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
 984                 - dev_priv->fb_location;
 985
 986         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
 987                                         ((dev_priv->front_offset
 988                                           + dev_priv->fb_location) >> 10));
 989
 990         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
 991                                        ((dev_priv->back_offset
 992                                          + dev_priv->fb_location) >> 10));
 993
 994         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
 995                                         ((dev_priv->depth_offset
 996                                           + dev_priv->fb_location) >> 10));
 997
 998         dev_priv->gart_size = init->gart_size;
 999
1000         /* New let's set the memory map ... */
1001         if (dev_priv->new_memmap) {
1002                 u32 base = 0;
1003
1004                 DRM_INFO("Setting GART location based on new memory map\n");
1005
1006                 /* If using AGP, try to locate the AGP aperture at the same
1007                  * location in the card and on the bus, though we have to
1008                  * align it down.
1009                  */
1010 #if __OS_HAS_AGP
1011                 if (dev_priv->flags & RADEON_IS_AGP) {
1012                         base = dev->agp->base;
1013                         /* Check if valid */
1014                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1015                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1016                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1017                                          dev->agp->base);
1018                                 base = 0;
1019                         }
1020                 }
1021 #endif
1022                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1023                 if (base == 0) {
1024                         base = dev_priv->fb_location + dev_priv->fb_size;
1025                         if (base < dev_priv->fb_location ||
1026                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1027                                 base = dev_priv->fb_location
1028                                         - dev_priv->gart_size;
1029                 }
1030                 dev_priv->gart_vm_start = base & 0xffc00000u;
1031                 if (dev_priv->gart_vm_start != base)
1032                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1033                                  base, dev_priv->gart_vm_start);
1034         } else {
1035                 DRM_INFO("Setting GART location based on old memory map\n");
1036                 dev_priv->gart_vm_start = dev_priv->fb_location +
1037                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1038         }
1039
1040 #if __OS_HAS_AGP
1041         if (dev_priv->flags & RADEON_IS_AGP)
1042                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1043                                                  - dev->agp->base
1044                                                  + dev_priv->gart_vm_start);
1045         else
1046 #endif
1047                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1048                                         - (unsigned long)dev->sg->virtual
1049                                         + dev_priv->gart_vm_start);
1050
1051         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1052         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1053         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1054                   dev_priv->gart_buffers_offset);
1055
1056         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1057         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1058                               + init->ring_size / sizeof(u32));
1059         dev_priv->ring.size = init->ring_size;
1060         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1061
1062         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1063         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1064
1065         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1066         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1067         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1068
1069         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1070
1071 #if __OS_HAS_AGP
1072         if (dev_priv->flags & RADEON_IS_AGP) {
1073                 /* Turn off PCI GART */
1074                 radeon_set_pcigart(dev_priv, 0);
1075         } else
1076 #endif
1077         {
1078                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1079                 /* if we have an offset set from userspace */
1080                 if (dev_priv->pcigart_offset_set) {
1081                         dev_priv->gart_info.bus_addr =
1082                             dev_priv->pcigart_offset + dev_priv->fb_location;
1083                         dev_priv->gart_info.mapping.offset =
1084                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1085                         dev_priv->gart_info.mapping.size =
1086                             dev_priv->gart_info.table_size;
1087
1088                         drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1089                         dev_priv->gart_info.addr =
1090                             dev_priv->gart_info.mapping.handle;
1091
1092                         if (dev_priv->flags & RADEON_IS_PCIE)
1093                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1094                         else
1095                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1096                         dev_priv->gart_info.gart_table_location =
1097                             DRM_ATI_GART_FB;
1098
1099                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1100                                   dev_priv->gart_info.addr,
1101                                   dev_priv->pcigart_offset);
1102                 } else {
1103                         if (dev_priv->flags & RADEON_IS_IGPGART)
1104                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1105                         else
1106                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1107                         dev_priv->gart_info.gart_table_location =
1108                             DRM_ATI_GART_MAIN;
1109                         dev_priv->gart_info.addr = NULL;
1110                         dev_priv->gart_info.bus_addr = 0;
1111                         if (dev_priv->flags & RADEON_IS_PCIE) {
1112                                 DRM_ERROR
1113                                     ("Cannot use PCI Express without GART in FB memory\n");
1114                                 radeon_do_cleanup_cp(dev);
1115                                 return -EINVAL;
1116                         }
1117                 }
1118
1119                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1120                         DRM_ERROR("failed to init PCI GART!\n");
1121                         radeon_do_cleanup_cp(dev);
1122                         return -ENOMEM;
1123                 }
1124
1125                 /* Turn on PCI GART */
1126                 radeon_set_pcigart(dev_priv, 1);
1127         }
1128
1129         radeon_cp_load_microcode(dev_priv);
1130         radeon_cp_init_ring_buffer(dev, dev_priv);
1131
1132         dev_priv->last_buf = 0;
1133
1134         radeon_do_engine_reset(dev);
1135         radeon_test_writeback(dev_priv);
1136
1137         return 0;
1138 }
1139
1140 static int radeon_do_cleanup_cp(struct drm_device * dev)
1141 {
1142         drm_radeon_private_t *dev_priv = dev->dev_private;
1143         DRM_DEBUG("\n");
1144
1145         /* Make sure interrupts are disabled here because the uninstall ioctl
1146          * may not have been called from userspace and after dev_private
1147          * is freed, it's too late.
1148          */
1149         if (dev->irq_enabled)
1150                 drm_irq_uninstall(dev);
1151
1152 #if __OS_HAS_AGP
1153         if (dev_priv->flags & RADEON_IS_AGP) {
1154                 if (dev_priv->cp_ring != NULL) {
1155                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1156                         dev_priv->cp_ring = NULL;
1157                 }
1158                 if (dev_priv->ring_rptr != NULL) {
1159                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1160                         dev_priv->ring_rptr = NULL;
1161                 }
1162                 if (dev->agp_buffer_map != NULL) {
1163                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1164                         dev->agp_buffer_map = NULL;
1165                 }
1166         } else
1167 #endif
1168         {
1169
1170                 if (dev_priv->gart_info.bus_addr) {
1171                         /* Turn off PCI GART */
1172                         radeon_set_pcigart(dev_priv, 0);
1173                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1174                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1175                 }
1176
1177                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1178                 {
1179                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1180                         dev_priv->gart_info.addr = 0;
1181                 }
1182         }
1183         /* only clear to the start of flags */
1184         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1185
1186         return 0;
1187 }
1188
1189 /* This code will reinit the Radeon CP hardware after a resume from disc.
1190  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1191  * here we make sure that all Radeon hardware initialisation is re-done without
1192  * affecting running applications.
1193  *
1194  * Charl P. Botha <http://cpbotha.net>
1195  */
1196 static int radeon_do_resume_cp(struct drm_device * dev)
1197 {
1198         drm_radeon_private_t *dev_priv = dev->dev_private;
1199
1200         if (!dev_priv) {
1201                 DRM_ERROR("Called with no initialization\n");
1202                 return -EINVAL;
1203         }
1204
1205         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1206
1207 #if __OS_HAS_AGP
1208         if (dev_priv->flags & RADEON_IS_AGP) {
1209                 /* Turn off PCI GART */
1210                 radeon_set_pcigart(dev_priv, 0);
1211         } else
1212 #endif
1213         {
1214                 /* Turn on PCI GART */
1215                 radeon_set_pcigart(dev_priv, 1);
1216         }
1217
1218         radeon_cp_load_microcode(dev_priv);
1219         radeon_cp_init_ring_buffer(dev, dev_priv);
1220
1221         radeon_do_engine_reset(dev);
1222
1223         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1224
1225         return 0;
1226 }
1227
1228 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1229 {
1230         drm_radeon_init_t *init = data;
1231
1232         LOCK_TEST_WITH_RETURN(dev, file_priv);
1233
1234         if (init->func == RADEON_INIT_R300_CP)
1235                 r300_init_reg_flags(dev);
1236
1237         switch (init->func) {
1238         case RADEON_INIT_CP:
1239         case RADEON_INIT_R200_CP:
1240         case RADEON_INIT_R300_CP:
1241                 return radeon_do_init_cp(dev, init);
1242         case RADEON_CLEANUP_CP:
1243                 return radeon_do_cleanup_cp(dev);
1244         }
1245
1246         return -EINVAL;
1247 }
1248
1249 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1250 {
1251         drm_radeon_private_t *dev_priv = dev->dev_private;
1252         DRM_DEBUG("\n");
1253
1254         LOCK_TEST_WITH_RETURN(dev, file_priv);
1255
1256         if (dev_priv->cp_running) {
1257                 DRM_DEBUG("while CP running\n");
1258                 return 0;
1259         }
1260         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1261                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1262                           dev_priv->cp_mode);
1263                 return 0;
1264         }
1265
1266         radeon_do_cp_start(dev_priv);
1267
1268         return 0;
1269 }
1270
1271 /* Stop the CP.  The engine must have been idled before calling this
1272  * routine.
1273  */
1274 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1275 {
1276         drm_radeon_private_t *dev_priv = dev->dev_private;
1277         drm_radeon_cp_stop_t *stop = data;
1278         int ret;
1279         DRM_DEBUG("\n");
1280
1281         LOCK_TEST_WITH_RETURN(dev, file_priv);
1282
1283         if (!dev_priv->cp_running)
1284                 return 0;
1285
1286         /* Flush any pending CP commands.  This ensures any outstanding
1287          * commands are exectuted by the engine before we turn it off.
1288          */
1289         if (stop->flush) {
1290                 radeon_do_cp_flush(dev_priv);
1291         }
1292
1293         /* If we fail to make the engine go idle, we return an error
1294          * code so that the DRM ioctl wrapper can try again.
1295          */
1296         if (stop->idle) {
1297                 ret = radeon_do_cp_idle(dev_priv);
1298                 if (ret)
1299                         return ret;
1300         }
1301
1302         /* Finally, we can turn off the CP.  If the engine isn't idle,
1303          * we will get some dropped triangles as they won't be fully
1304          * rendered before the CP is shut down.
1305          */
1306         radeon_do_cp_stop(dev_priv);
1307
1308         /* Reset the engine */
1309         radeon_do_engine_reset(dev);
1310
1311         return 0;
1312 }
1313
1314 void radeon_do_release(struct drm_device * dev)
1315 {
1316         drm_radeon_private_t *dev_priv = dev->dev_private;
1317         int i, ret;
1318
1319         if (dev_priv) {
1320                 if (dev_priv->cp_running) {
1321                         /* Stop the cp */
1322                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1323                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1324 #ifdef __linux__
1325                                 schedule();
1326 #else
1327                                 tsleep(&ret, PZERO, "rdnrel", 1);
1328 #endif
1329                         }
1330                         radeon_do_cp_stop(dev_priv);
1331                         radeon_do_engine_reset(dev);
1332                 }
1333
1334                 /* Disable *all* interrupts */
1335                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1336                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1337
1338                 if (dev_priv->mmio) {   /* remove all surfaces */
1339                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1340                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1341                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1342                                              16 * i, 0);
1343                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1344                                              16 * i, 0);
1345                         }
1346                 }
1347
1348                 /* Free memory heap structures */
1349                 radeon_mem_takedown(&(dev_priv->gart_heap));
1350                 radeon_mem_takedown(&(dev_priv->fb_heap));
1351
1352                 /* deallocate kernel resources */
1353                 radeon_do_cleanup_cp(dev);
1354         }
1355 }
1356
1357 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1358  */
1359 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1360 {
1361         drm_radeon_private_t *dev_priv = dev->dev_private;
1362         DRM_DEBUG("\n");
1363
1364         LOCK_TEST_WITH_RETURN(dev, file_priv);
1365
1366         if (!dev_priv) {
1367                 DRM_DEBUG("called before init done\n");
1368                 return -EINVAL;
1369         }
1370
1371         radeon_do_cp_reset(dev_priv);
1372
1373         /* The CP is no longer running after an engine reset */
1374         dev_priv->cp_running = 0;
1375
1376         return 0;
1377 }
1378
1379 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1380 {
1381         drm_radeon_private_t *dev_priv = dev->dev_private;
1382         DRM_DEBUG("\n");
1383
1384         LOCK_TEST_WITH_RETURN(dev, file_priv);
1385
1386         return radeon_do_cp_idle(dev_priv);
1387 }
1388
1389 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1390  */
1391 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1392 {
1393
1394         return radeon_do_resume_cp(dev);
1395 }
1396
1397 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1398 {
1399         DRM_DEBUG("\n");
1400
1401         LOCK_TEST_WITH_RETURN(dev, file_priv);
1402
1403         return radeon_do_engine_reset(dev);
1404 }
1405
1406 /* ================================================================
1407  * Fullscreen mode
1408  */
1409
1410 /* KW: Deprecated to say the least:
1411  */
1412 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1413 {
1414         return 0;
1415 }
1416
1417 /* ================================================================
1418  * Freelist management
1419  */
1420
1421 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1422  *   bufs until freelist code is used.  Note this hides a problem with
1423  *   the scratch register * (used to keep track of last buffer
1424  *   completed) being written to before * the last buffer has actually
1425  *   completed rendering.
1426  *
1427  * KW:  It's also a good way to find free buffers quickly.
1428  *
1429  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1430  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1431  * we essentially have to do this, else old clients will break.
1432  *
1433  * However, it does leave open a potential deadlock where all the
1434  * buffers are held by other clients, which can't release them because
1435  * they can't get the lock.
1436  */
1437
1438 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1439 {
1440         struct drm_device_dma *dma = dev->dma;
1441         drm_radeon_private_t *dev_priv = dev->dev_private;
1442         drm_radeon_buf_priv_t *buf_priv;
1443         struct drm_buf *buf;
1444         int i, t;
1445         int start;
1446
1447         if (++dev_priv->last_buf >= dma->buf_count)
1448                 dev_priv->last_buf = 0;
1449
1450         start = dev_priv->last_buf;
1451
1452         for (t = 0; t < dev_priv->usec_timeout; t++) {
1453                 u32 done_age = GET_SCRATCH(1);
1454                 DRM_DEBUG("done_age = %d\n", done_age);
1455                 for (i = start; i < dma->buf_count; i++) {
1456                         buf = dma->buflist[i];
1457                         buf_priv = buf->dev_private;
1458                         if (buf->file_priv == NULL || (buf->pending &&
1459                                                        buf_priv->age <=
1460                                                        done_age)) {
1461                                 dev_priv->stats.requested_bufs++;
1462                                 buf->pending = 0;
1463                                 return buf;
1464                         }
1465                         start = 0;
1466                 }
1467
1468                 if (t) {
1469                         DRM_UDELAY(1);
1470                         dev_priv->stats.freelist_loops++;
1471                 }
1472         }
1473
1474         DRM_DEBUG("returning NULL!\n");
1475         return NULL;
1476 }
1477
1478 #if 0
1479 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1480 {
1481         struct drm_device_dma *dma = dev->dma;
1482         drm_radeon_private_t *dev_priv = dev->dev_private;
1483         drm_radeon_buf_priv_t *buf_priv;
1484         struct drm_buf *buf;
1485         int i, t;
1486         int start;
1487         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1488
1489         if (++dev_priv->last_buf >= dma->buf_count)
1490                 dev_priv->last_buf = 0;
1491
1492         start = dev_priv->last_buf;
1493         dev_priv->stats.freelist_loops++;
1494
1495         for (t = 0; t < 2; t++) {
1496                 for (i = start; i < dma->buf_count; i++) {
1497                         buf = dma->buflist[i];
1498                         buf_priv = buf->dev_private;
1499                         if (buf->file_priv == 0 || (buf->pending &&
1500                                                     buf_priv->age <=
1501                                                     done_age)) {
1502                                 dev_priv->stats.requested_bufs++;
1503                                 buf->pending = 0;
1504                                 return buf;
1505                         }
1506                 }
1507                 start = 0;
1508         }
1509
1510         return NULL;
1511 }
1512 #endif
1513
1514 void radeon_freelist_reset(struct drm_device * dev)
1515 {
1516         struct drm_device_dma *dma = dev->dma;
1517         drm_radeon_private_t *dev_priv = dev->dev_private;
1518         int i;
1519
1520         dev_priv->last_buf = 0;
1521         for (i = 0; i < dma->buf_count; i++) {
1522                 struct drm_buf *buf = dma->buflist[i];
1523                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1524                 buf_priv->age = 0;
1525         }
1526 }
1527
1528 /* ================================================================
1529  * CP command submission
1530  */
1531
1532 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1533 {
1534         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1535         int i;
1536         u32 last_head = GET_RING_HEAD(dev_priv);
1537
1538         for (i = 0; i < dev_priv->usec_timeout; i++) {
1539                 u32 head = GET_RING_HEAD(dev_priv);
1540
1541                 ring->space = (head - ring->tail) * sizeof(u32);
1542                 if (ring->space <= 0)
1543                         ring->space += ring->size;
1544                 if (ring->space > n)
1545                         return 0;
1546
1547                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1548
1549                 if (head != last_head)
1550                         i = 0;
1551                 last_head = head;
1552
1553                 DRM_UDELAY(1);
1554         }
1555
1556         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1557 #if RADEON_FIFO_DEBUG
1558         radeon_status(dev_priv);
1559         DRM_ERROR("failed!\n");
1560 #endif
1561         return -EBUSY;
1562 }
1563
1564 static int radeon_cp_get_buffers(struct drm_device *dev,
1565                                  struct drm_file *file_priv,
1566                                  struct drm_dma * d)
1567 {
1568         int i;
1569         struct drm_buf *buf;
1570
1571         for (i = d->granted_count; i < d->request_count; i++) {
1572                 buf = radeon_freelist_get(dev);
1573                 if (!buf)
1574                         return -EBUSY;  /* NOTE: broken client */
1575
1576                 buf->file_priv = file_priv;
1577
1578                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1579                                      sizeof(buf->idx)))
1580                         return -EFAULT;
1581                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1582                                      sizeof(buf->total)))
1583                         return -EFAULT;
1584
1585                 d->granted_count++;
1586         }
1587         return 0;
1588 }
1589
1590 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1591 {
1592         struct drm_device_dma *dma = dev->dma;
1593         int ret = 0;
1594         struct drm_dma *d = data;
1595
1596         LOCK_TEST_WITH_RETURN(dev, file_priv);
1597
1598         /* Please don't send us buffers.
1599          */
1600         if (d->send_count != 0) {
1601                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1602                           DRM_CURRENTPID, d->send_count);
1603                 return -EINVAL;
1604         }
1605
1606         /* We'll send you buffers.
1607          */
1608         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1609                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1610                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1611                 return -EINVAL;
1612         }
1613
1614         d->granted_count = 0;
1615
1616         if (d->request_count) {
1617                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1618         }
1619
1620         return ret;
1621 }
1622
1623 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1624 {
1625         drm_radeon_private_t *dev_priv;
1626         int ret = 0;
1627
1628         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1629         if (dev_priv == NULL)
1630                 return -ENOMEM;
1631
1632         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1633         dev->dev_private = (void *)dev_priv;
1634         dev_priv->flags = flags;
1635
1636         switch (flags & RADEON_FAMILY_MASK) {
1637         case CHIP_R100:
1638         case CHIP_RV200:
1639         case CHIP_R200:
1640         case CHIP_R300:
1641         case CHIP_R350:
1642         case CHIP_R420:
1643         case CHIP_RV410:
1644         case CHIP_RV515:
1645         case CHIP_R520:
1646         case CHIP_RV570:
1647         case CHIP_R580:
1648                 dev_priv->flags |= RADEON_HAS_HIERZ;
1649                 break;
1650         default:
1651                 /* all other chips have no hierarchical z buffer */
1652                 break;
1653         }
1654
1655         if (drm_device_is_agp(dev))
1656                 dev_priv->flags |= RADEON_IS_AGP;
1657         else if (drm_device_is_pcie(dev))
1658                 dev_priv->flags |= RADEON_IS_PCIE;
1659         else
1660                 dev_priv->flags |= RADEON_IS_PCI;
1661
1662         DRM_DEBUG("%s card detected\n",
1663                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1664         return ret;
1665 }
1666
1667 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1668  * have to find them.
1669  */
1670 int radeon_driver_firstopen(struct drm_device *dev)
1671 {
1672         int ret;
1673         drm_local_map_t *map;
1674         drm_radeon_private_t *dev_priv = dev->dev_private;
1675
1676         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1677
1678         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1679                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1680                          _DRM_READ_ONLY, &dev_priv->mmio);
1681         if (ret != 0)
1682                 return ret;
1683
1684         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1685         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1686                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1687                          _DRM_WRITE_COMBINING, &map);
1688         if (ret != 0)
1689                 return ret;
1690
1691         return 0;
1692 }
1693
1694 int radeon_driver_unload(struct drm_device *dev)
1695 {
1696         drm_radeon_private_t *dev_priv = dev->dev_private;
1697
1698         DRM_DEBUG("\n");
1699         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1700
1701         dev->dev_private = NULL;
1702         return 0;
1703 }