1 /* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
3 * Copyright (C) The Weather Channel, Inc. 2002.
4 * Copyright (C) 2004 Nicolai Haehnle.
7 * The Weather Channel (TM) funded Tungsten Graphics to develop the
8 * initial release of the Radeon 8500 driver under the XFree86 license.
9 * This notice must be preserved.
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the next
19 * paragraph) shall be included in all copies or substantial portions of the
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
26 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 * Nicolai Haehnle <prefect_@gmx.net>
36 #include "radeon_drm.h"
37 #include "radeon_drv.h"
40 #define R300_SIMULTANEOUS_CLIPRECTS 4
42 /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
44 static const int r300_cliprect_cntl[4] = {
52 * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
53 * buffer, starting with index n.
55 static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
56 drm_radeon_kcmd_buffer_t *cmdbuf, int n)
63 nr = cmdbuf->nbox - n;
64 if (nr > R300_SIMULTANEOUS_CLIPRECTS)
65 nr = R300_SIMULTANEOUS_CLIPRECTS;
67 DRM_DEBUG("%i cliprects\n", nr);
70 BEGIN_RING(6 + nr * 2);
71 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
73 for (i = 0; i < nr; ++i) {
74 if (DRM_COPY_FROM_USER_UNCHECKED
75 (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
76 DRM_ERROR("copy cliprect faulted\n");
77 return DRM_ERR(EFAULT);
82 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
85 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
88 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
91 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
93 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
94 (box.y1 << R300_CLIPRECT_Y_SHIFT));
95 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
96 (box.y2 << R300_CLIPRECT_Y_SHIFT));
99 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
101 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
102 * client might be able to trample over memory.
103 * The impact should be very limited, but I'd rather be safe than
106 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
108 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
111 /* Why we allow zero cliprect rendering:
112 * There are some commands in a command buffer that must be submitted
113 * even when there are no cliprects, e.g. DMA buffer discard
114 * or state setting (though state setting could be avoided by
115 * simulating a loss of context).
117 * Now since the cmdbuf interface is so chaotic right now (and is
118 * bound to remain that way for a bit until things settle down),
119 * it is basically impossible to filter out the commands that are
120 * necessary and those that aren't.
122 * So I choose the safe way and don't do any filtering at all;
123 * instead, I simply set up the engine so that all rendering
124 * can't produce any fragments.
127 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0);
134 static u8 r300_reg_flags[0x10000 >> 2];
136 void r300_init_reg_flags(void)
139 memset(r300_reg_flags, 0, 0x10000 >> 2);
140 #define ADD_RANGE_MARK(reg, count,mark) \
141 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
142 r300_reg_flags[i]|=(mark);
145 #define MARK_CHECK_OFFSET 2
147 #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
149 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
150 ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
151 ADD_RANGE(0x2080, 1);
152 ADD_RANGE(R300_SE_VTE_CNTL, 2);
153 ADD_RANGE(0x2134, 2);
154 ADD_RANGE(0x2140, 1);
155 ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
156 ADD_RANGE(0x21DC, 1);
157 ADD_RANGE(0x221C, 1);
158 ADD_RANGE(0x2220, 4);
159 ADD_RANGE(0x2288, 1);
160 ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
161 ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
162 ADD_RANGE(R300_GB_ENABLE, 1);
163 ADD_RANGE(R300_GB_MSPOS0, 5);
164 ADD_RANGE(R300_TX_CNTL, 1);
165 ADD_RANGE(R300_TX_ENABLE, 1);
166 ADD_RANGE(0x4200, 4);
167 ADD_RANGE(0x4214, 1);
168 ADD_RANGE(R300_RE_POINTSIZE, 1);
169 ADD_RANGE(0x4230, 3);
170 ADD_RANGE(R300_RE_LINE_CNT, 1);
171 ADD_RANGE(0x4238, 1);
172 ADD_RANGE(0x4260, 3);
173 ADD_RANGE(0x4274, 4);
174 ADD_RANGE(0x4288, 5);
175 ADD_RANGE(0x42A0, 1);
176 ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
177 ADD_RANGE(0x42B4, 1);
178 ADD_RANGE(R300_RE_CULL_CNTL, 1);
179 ADD_RANGE(0x42C0, 2);
180 ADD_RANGE(R300_RS_CNTL_0, 2);
181 ADD_RANGE(R300_RS_INTERP_0, 8);
182 ADD_RANGE(R300_RS_ROUTE_0, 8);
183 ADD_RANGE(0x43A4, 2);
184 ADD_RANGE(0x43E8, 1);
185 ADD_RANGE(R300_PFS_CNTL_0, 3);
186 ADD_RANGE(R300_PFS_NODE_0, 4);
187 ADD_RANGE(R300_PFS_TEXI_0, 64);
188 ADD_RANGE(0x46A4, 5);
189 ADD_RANGE(R300_PFS_INSTR0_0, 64);
190 ADD_RANGE(R300_PFS_INSTR1_0, 64);
191 ADD_RANGE(R300_PFS_INSTR2_0, 64);
192 ADD_RANGE(R300_PFS_INSTR3_0, 64);
193 ADD_RANGE(0x4BC0, 1);
194 ADD_RANGE(0x4BC8, 3);
195 ADD_RANGE(R300_PP_ALPHA_TEST, 2);
196 ADD_RANGE(0x4BD8, 1);
197 ADD_RANGE(R300_PFS_PARAM_0_X, 64);
198 ADD_RANGE(0x4E00, 1);
199 ADD_RANGE(R300_RB3D_CBLEND, 2);
200 ADD_RANGE(R300_RB3D_COLORMASK, 1);
201 ADD_RANGE(0x4E10, 3);
202 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
203 ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
204 ADD_RANGE(0x4E50, 9);
205 ADD_RANGE(0x4E88, 1);
206 ADD_RANGE(0x4EA0, 2);
207 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
208 ADD_RANGE(0x4F10, 4);
209 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
210 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
211 ADD_RANGE(0x4F28, 1);
212 ADD_RANGE(0x4F30, 2);
213 ADD_RANGE(0x4F44, 1);
214 ADD_RANGE(0x4F54, 1);
216 ADD_RANGE(R300_TX_FILTER_0, 16);
217 ADD_RANGE(R300_TX_UNK1_0, 16);
218 ADD_RANGE(R300_TX_SIZE_0, 16);
219 ADD_RANGE(R300_TX_FORMAT_0, 16);
220 ADD_RANGE(R300_TX_PITCH_0, 16);
221 /* Texture offset is dangerous and needs more checking */
222 ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
223 ADD_RANGE(R300_TX_UNK4_0, 16);
224 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
226 /* Sporadic registers used as primitives are emitted */
227 ADD_RANGE(0x4f18, 1);
228 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
229 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
230 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
234 static __inline__ int r300_check_range(unsigned reg, int count)
239 for (i = (reg >> 2); i < (reg >> 2) + count; i++)
240 if (r300_reg_flags[i] != MARK_SAFE)
245 /* we expect offsets passed to the framebuffer to be either within video memory or
247 static __inline__ int r300_check_offset(drm_radeon_private_t *dev_priv,
250 /* we realy want to check against end of video aperture
251 but this value is not being kept.
252 This code is correct for now (does the same thing as the
253 code that sets MC_FB_LOCATION) in radeon_cp.c */
254 if ((offset >= dev_priv->fb_location) &&
255 (offset < dev_priv->gart_vm_start))
257 if ((offset >= dev_priv->gart_vm_start) &&
258 (offset < dev_priv->gart_vm_start + dev_priv->gart_size))
263 static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
265 drm_radeon_kcmd_buffer_t
267 drm_r300_cmd_header_t
276 sz = header.packet0.count;
277 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
279 if ((sz > 64) || (sz < 0)) {
281 ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
283 return DRM_ERR(EINVAL);
285 for (i = 0; i < sz; i++) {
286 values[i] = ((int *)cmdbuf->buf)[i];
287 switch (r300_reg_flags[(reg >> 2) + i]) {
290 case MARK_CHECK_OFFSET:
291 if (r300_check_offset(dev_priv, (u32) values[i])) {
293 ("Offset failed range check (reg=%04x sz=%d)\n",
295 return DRM_ERR(EINVAL);
299 DRM_ERROR("Register %04x failed check as flag=%02x\n",
300 reg + i * 4, r300_reg_flags[(reg >> 2) + i]);
301 return DRM_ERR(EINVAL);
306 OUT_RING(CP_PACKET0(reg, sz - 1));
307 OUT_RING_TABLE(values, sz);
310 cmdbuf->buf += sz * 4;
311 cmdbuf->bufsz -= sz * 4;
317 * Emits a packet0 setting arbitrary registers.
318 * Called by r300_do_cp_cmdbuf.
320 * Note that checks are performed on contents and addresses of the registers
322 static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
323 drm_radeon_kcmd_buffer_t *cmdbuf,
324 drm_r300_cmd_header_t header)
330 sz = header.packet0.count;
331 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
336 if (sz * 4 > cmdbuf->bufsz)
337 return DRM_ERR(EINVAL);
339 if (reg + sz * 4 >= 0x10000) {
340 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg,
342 return DRM_ERR(EINVAL);
345 if (r300_check_range(reg, sz)) {
346 /* go and check everything */
347 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
350 /* the rest of the data is safe to emit, whatever the values the user passed */
353 OUT_RING(CP_PACKET0(reg, sz - 1));
354 OUT_RING_TABLE((int *)cmdbuf->buf, sz);
357 cmdbuf->buf += sz * 4;
358 cmdbuf->bufsz -= sz * 4;
364 * Uploads user-supplied vertex program instructions or parameters onto
366 * Called by r300_do_cp_cmdbuf.
368 static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
369 drm_radeon_kcmd_buffer_t *cmdbuf,
370 drm_r300_cmd_header_t header)
376 sz = header.vpu.count;
377 addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
381 if (sz * 16 > cmdbuf->bufsz)
382 return DRM_ERR(EINVAL);
384 BEGIN_RING(5 + sz * 4);
385 /* Wait for VAP to come to senses.. */
386 /* there is no need to emit it multiple times, (only once before VAP is programmed,
387 but this optimization is for later */
388 OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0);
389 OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
390 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
391 OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
395 cmdbuf->buf += sz * 16;
396 cmdbuf->bufsz -= sz * 16;
402 * Emit a clear packet from userspace.
403 * Called by r300_emit_packet3.
405 static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
406 drm_radeon_kcmd_buffer_t *cmdbuf)
410 if (8 * 4 > cmdbuf->bufsz)
411 return DRM_ERR(EINVAL);
414 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
415 OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
416 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
417 OUT_RING_TABLE((int *)cmdbuf->buf, 8);
420 cmdbuf->buf += 8 * 4;
421 cmdbuf->bufsz -= 8 * 4;
426 static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
427 drm_radeon_kcmd_buffer_t *cmdbuf,
431 #define MAX_ARRAY_PACKET 64
432 u32 payload[MAX_ARRAY_PACKET];
436 count = (header >> 16) & 0x3fff;
438 if ((count + 1) > MAX_ARRAY_PACKET) {
439 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
441 return DRM_ERR(EINVAL);
443 memset(payload, 0, MAX_ARRAY_PACKET * 4);
444 memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4);
446 /* carefully check packet contents */
448 narrays = payload[0];
451 while ((k < narrays) && (i < (count + 1))) {
452 i++; /* skip attribute field */
453 if (r300_check_offset(dev_priv, payload[i])) {
455 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
457 return DRM_ERR(EINVAL);
463 /* have one more to process, they come in pairs */
464 if (r300_check_offset(dev_priv, payload[i])) {
466 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
468 return DRM_ERR(EINVAL);
473 /* do the counts match what we expect ? */
474 if ((k != narrays) || (i != (count + 1))) {
476 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
477 k, i, narrays, count + 1);
478 return DRM_ERR(EINVAL);
481 /* all clear, output packet */
483 BEGIN_RING(count + 2);
485 OUT_RING_TABLE(payload, count + 1);
488 cmdbuf->buf += (count + 2) * 4;
489 cmdbuf->bufsz -= (count + 2) * 4;
493 static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
494 drm_radeon_kcmd_buffer_t *cmdbuf)
496 u32 *cmd = (u32 *) cmdbuf->buf;
500 count=(cmd[0]>>16) & 0x3fff;
502 if (cmd[0] & 0x8000) {
505 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
506 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
507 offset = cmd[2] << 10;
508 ret = r300_check_offset(dev_priv, offset);
511 DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
512 return DRM_ERR(EINVAL);
516 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
517 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
518 offset = cmd[3] << 10;
519 ret = r300_check_offset(dev_priv, offset);
522 DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
523 return DRM_ERR(EINVAL);
531 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
534 cmdbuf->buf += (count+2)*4;
535 cmdbuf->bufsz -= (count+2)*4;
540 static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
541 drm_radeon_kcmd_buffer_t *cmdbuf)
547 if (4 > cmdbuf->bufsz)
548 return DRM_ERR(EINVAL);
550 /* Fixme !! This simply emits a packet without much checking.
551 We need to be smarter. */
553 /* obtain first word - actual packet3 header */
554 header = *(u32 *) cmdbuf->buf;
556 /* Is it packet 3 ? */
557 if ((header >> 30) != 0x3) {
558 DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
559 return DRM_ERR(EINVAL);
562 count = (header >> 16) & 0x3fff;
564 /* Check again now that we know how much data to expect */
565 if ((count + 2) * 4 > cmdbuf->bufsz) {
567 ("Expected packet3 of length %d but have only %d bytes left\n",
568 (count + 2) * 4, cmdbuf->bufsz);
569 return DRM_ERR(EINVAL);
572 /* Is it a packet type we know about ? */
573 switch (header & 0xff00) {
574 case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
575 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
577 case RADEON_CNTL_BITBLT_MULTI:
578 return r300_emit_bitblt_multi(dev_priv, cmdbuf);
580 case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
581 case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
582 case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
583 case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
584 case RADEON_WAIT_FOR_IDLE:
586 /* these packets are safe */
589 DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
590 return DRM_ERR(EINVAL);
593 BEGIN_RING(count + 2);
595 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
598 cmdbuf->buf += (count + 2) * 4;
599 cmdbuf->bufsz -= (count + 2) * 4;
605 * Emit a rendering packet3 from userspace.
606 * Called by r300_do_cp_cmdbuf.
608 static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
609 drm_radeon_kcmd_buffer_t *cmdbuf,
610 drm_r300_cmd_header_t header)
614 char *orig_buf = cmdbuf->buf;
615 int orig_bufsz = cmdbuf->bufsz;
617 /* This is a do-while-loop so that we run the interior at least once,
618 * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
622 if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
623 ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
627 cmdbuf->buf = orig_buf;
628 cmdbuf->bufsz = orig_bufsz;
631 switch (header.packet3.packet) {
632 case R300_CMD_PACKET3_CLEAR:
633 DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
634 ret = r300_emit_clear(dev_priv, cmdbuf);
636 DRM_ERROR("r300_emit_clear failed\n");
641 case R300_CMD_PACKET3_RAW:
642 DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
643 ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
645 DRM_ERROR("r300_emit_raw_packet3 failed\n");
651 DRM_ERROR("bad packet3 type %i at %p\n",
652 header.packet3.packet,
653 cmdbuf->buf - sizeof(header));
654 return DRM_ERR(EINVAL);
657 n += R300_SIMULTANEOUS_CLIPRECTS;
658 } while (n < cmdbuf->nbox);
663 /* Some of the R300 chips seem to be extremely touchy about the two registers
664 * that are configured in r300_pacify.
665 * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
666 * sends a command buffer that contains only state setting commands and a
667 * vertex program/parameter upload sequence, this will eventually lead to a
668 * lockup, unless the sequence is bracketed by calls to r300_pacify.
669 * So we should take great care to *always* call r300_pacify before
670 * *anything* 3D related, and again afterwards. This is what the
671 * call bracket in r300_do_cp_cmdbuf is for.
675 * Emit the sequence to pacify R300.
677 static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
682 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
684 OUT_RING(CP_PACKET0(0x4f18, 0));
686 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
692 * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
693 * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
694 * be careful about how this function is called.
696 static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
698 drm_radeon_private_t *dev_priv = dev->dev_private;
699 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
701 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
707 * Parses and validates a user-supplied command buffer and emits appropriate
708 * commands on the DMA ring buffer.
709 * Called by the ioctl handler function radeon_cp_cmdbuf.
711 int r300_do_cp_cmdbuf(drm_device_t *dev,
713 drm_file_t *filp_priv,
714 drm_radeon_kcmd_buffer_t *cmdbuf)
716 drm_radeon_private_t *dev_priv = dev->dev_private;
717 drm_device_dma_t *dma = dev->dma;
718 drm_buf_t *buf = NULL;
719 int emit_dispatch_age = 0;
724 /* See the comment above r300_emit_begin3d for why this call must be here,
725 * and what the cleanup gotos are for. */
726 r300_pacify(dev_priv);
728 if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
729 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
734 while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
736 drm_r300_cmd_header_t header;
738 header.u = *(unsigned int *)cmdbuf->buf;
740 cmdbuf->buf += sizeof(header);
741 cmdbuf->bufsz -= sizeof(header);
743 switch (header.header.cmd_type) {
744 case R300_CMD_PACKET0:
745 DRM_DEBUG("R300_CMD_PACKET0\n");
746 ret = r300_emit_packet0(dev_priv, cmdbuf, header);
748 DRM_ERROR("r300_emit_packet0 failed\n");
754 DRM_DEBUG("R300_CMD_VPU\n");
755 ret = r300_emit_vpu(dev_priv, cmdbuf, header);
757 DRM_ERROR("r300_emit_vpu failed\n");
762 case R300_CMD_PACKET3:
763 DRM_DEBUG("R300_CMD_PACKET3\n");
764 ret = r300_emit_packet3(dev_priv, cmdbuf, header);
766 DRM_ERROR("r300_emit_packet3 failed\n");
772 DRM_DEBUG("R300_CMD_END3D\n");
774 Ideally userspace driver should not need to issue this call,
775 i.e. the drm driver should issue it automatically and prevent
778 In practice, we do not understand why this call is needed and what
779 it does (except for some vague guesses that it has to do with cache
780 coherence) and so the user space driver does it.
782 Once we are sure which uses prevent lockups the code could be moved
783 into the kernel and the userspace driver will not
784 need to use this command.
786 Note that issuing this command does not hurt anything
787 except, possibly, performance */
788 r300_pacify(dev_priv);
791 case R300_CMD_CP_DELAY:
792 /* simple enough, we can do it here */
793 DRM_DEBUG("R300_CMD_CP_DELAY\n");
798 BEGIN_RING(header.delay.count);
799 for (i = 0; i < header.delay.count; i++)
800 OUT_RING(RADEON_CP_PACKET2);
805 case R300_CMD_DMA_DISCARD:
806 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
807 idx = header.dma.buf_idx;
808 if (idx < 0 || idx >= dma->buf_count) {
809 DRM_ERROR("buffer index %d (of %d max)\n",
810 idx, dma->buf_count - 1);
811 ret = DRM_ERR(EINVAL);
815 buf = dma->buflist[idx];
816 if (buf->filp != filp || buf->pending) {
817 DRM_ERROR("bad buffer %p %p %d\n",
818 buf->filp, filp, buf->pending);
819 ret = DRM_ERR(EINVAL);
823 emit_dispatch_age = 1;
824 r300_discard_buffer(dev, buf);
828 /* simple enough, we can do it here */
829 DRM_DEBUG("R300_CMD_WAIT\n");
830 if (header.wait.flags == 0)
831 break; /* nothing to do */
837 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
838 OUT_RING((header.wait.flags & 0xf) << 14);
844 DRM_ERROR("bad cmd_type %i at %p\n",
845 header.header.cmd_type,
846 cmdbuf->buf - sizeof(header));
847 ret = DRM_ERR(EINVAL);
855 r300_pacify(dev_priv);
857 /* We emit the vertex buffer age here, outside the pacifier "brackets"
859 * (1) This may coalesce multiple age emissions into a single one and
860 * (2) more importantly, some chips lock up hard when scratch registers
861 * are written inside the pacifier bracket.
863 if (emit_dispatch_age) {
866 /* Emit the vertex buffer age */
868 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);