2 * sata_sx4.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware documentation available under NDA.
37 The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
38 engine, DIMM memory, and four ATA engines (one per SATA port).
39 Data is copied to/from DIMM memory by the HDMA engine, before
40 handing off to one (or more) of the ATA engines. The ATA
41 engines operate solely on DIMM memory.
43 The SX4 behaves like a PATA chip, with no SATA controls or
44 knowledge whatsoever, leading to the presumption that
45 PATA<->SATA bridges exist on SX4 boards, external to the
48 The chip is quite capable, supporting an XOR engine and linked
49 hardware commands (permits a string to transactions to be
50 submitted and waited-on as a single unit), and an optional
53 The limiting factor is largely software. This Linux driver was
54 written to multiplex the single HDMA engine to copy disk
55 transactions into a fixed DIMM memory space, from where an ATA
56 engine takes over. As a result, each WRITE looks like this:
58 submit HDMA packet to hardware
59 hardware copies data from system memory to DIMM
60 hardware raises interrupt
62 submit ATA packet to hardware
63 hardware executes ATA WRITE command, w/ data in DIMM
64 hardware raises interrupt
66 and each READ looks like this:
68 submit ATA packet to hardware
69 hardware executes ATA READ command, w/ data in DIMM
70 hardware raises interrupt
72 submit HDMA packet to hardware
73 hardware copies data from DIMM to system memory
74 hardware raises interrupt
76 This is a very slow, lock-step way of doing things that can
77 certainly be improved by motivated kernel hackers.
81 #include <linux/kernel.h>
82 #include <linux/module.h>
83 #include <linux/pci.h>
84 #include <linux/slab.h>
85 #include <linux/init.h>
86 #include <linux/blkdev.h>
87 #include <linux/delay.h>
88 #include <linux/interrupt.h>
89 #include <linux/device.h>
90 #include <scsi/scsi_host.h>
91 #include <scsi/scsi_cmnd.h>
92 #include <linux/libata.h>
93 #include "sata_promise.h"
95 #define DRV_NAME "sata_sx4"
96 #define DRV_VERSION "0.12"
103 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
105 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
106 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
107 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
108 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
110 PDC_CTLSTAT = 0x60, /* IDEn control / status */
112 PDC_20621_SEQCTL = 0x400,
113 PDC_20621_SEQMASK = 0x480,
114 PDC_20621_GENERAL_CTL = 0x484,
115 PDC_20621_PAGE_SIZE = (32 * 1024),
117 /* chosen, not constant, values; we design our own DIMM mem map */
118 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
119 PDC_20621_DIMM_BASE = 0x00200000,
120 PDC_20621_DIMM_DATA = (64 * 1024),
121 PDC_DIMM_DATA_STEP = (256 * 1024),
122 PDC_DIMM_WINDOW_STEP = (8 * 1024),
123 PDC_DIMM_HOST_PRD = (6 * 1024),
124 PDC_DIMM_HOST_PKT = (128 * 0),
125 PDC_DIMM_HPKT_PRD = (128 * 1),
126 PDC_DIMM_ATA_PKT = (128 * 2),
127 PDC_DIMM_APKT_PRD = (128 * 3),
128 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
129 PDC_PAGE_WINDOW = 0x40,
130 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
131 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
132 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
134 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
136 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
139 board_20621 = 0, /* FastTrak S150 SX4 */
141 PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
142 PDC_RESET = (1 << 11), /* HDMA/ATA reset */
143 PDC_DMA_ENABLE = (1 << 7), /* DMA start/stop */
146 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
148 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
149 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
150 PDC_I2C_CONTROL = 0x48,
151 PDC_I2C_ADDR_DATA = 0x4C,
152 PDC_DIMM0_CONTROL = 0x80,
153 PDC_DIMM1_CONTROL = 0x84,
154 PDC_SDRAM_CONTROL = 0x88,
155 PDC_I2C_WRITE = 0, /* master -> slave */
156 PDC_I2C_READ = (1 << 6), /* master <- slave */
157 PDC_I2C_START = (1 << 7), /* start I2C proto */
158 PDC_I2C_MASK_INT = (1 << 5), /* mask I2C interrupt */
159 PDC_I2C_COMPLETE = (1 << 16), /* I2C normal compl. */
160 PDC_I2C_NO_ACK = (1 << 20), /* slave no-ack addr */
161 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
162 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
163 PDC_DIMM_SPD_ROW_NUM = 3,
164 PDC_DIMM_SPD_COLUMN_NUM = 4,
165 PDC_DIMM_SPD_MODULE_ROW = 5,
166 PDC_DIMM_SPD_TYPE = 11,
167 PDC_DIMM_SPD_FRESH_RATE = 12,
168 PDC_DIMM_SPD_BANK_NUM = 17,
169 PDC_DIMM_SPD_CAS_LATENCY = 18,
170 PDC_DIMM_SPD_ATTRIBUTE = 21,
171 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
172 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
173 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
174 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
175 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
176 PDC_CTL_STATUS = 0x08,
177 PDC_DIMM_WINDOW_CTLR = 0x0C,
178 PDC_TIME_CONTROL = 0x3C,
179 PDC_TIME_PERIOD = 0x40,
180 PDC_TIME_COUNTER = 0x44,
181 PDC_GENERAL_CTLR = 0x484,
182 PCI_PLL_INIT = 0x8A531824,
183 PCI_X_TCOUNT = 0xEE1E5CFF,
185 /* PDC_TIME_CONTROL bits */
186 PDC_TIMER_BUZZER = (1 << 10),
187 PDC_TIMER_MODE_PERIODIC = 0, /* bits 9:8 == 00 */
188 PDC_TIMER_MODE_ONCE = (1 << 8), /* bits 9:8 == 01 */
189 PDC_TIMER_ENABLE = (1 << 7),
190 PDC_TIMER_MASK_INT = (1 << 5),
191 PDC_TIMER_SEQ_MASK = 0x1f, /* SEQ ID for timer */
192 PDC_TIMER_DEFAULT = PDC_TIMER_MODE_ONCE |
197 #define ECC_ERASE_BUF_SZ (128 * 1024)
199 struct pdc_port_priv {
200 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
205 struct pdc_host_priv {
206 unsigned int doing_hdma;
207 unsigned int hdma_prod;
208 unsigned int hdma_cons;
210 struct ata_queued_cmd *qc;
212 unsigned long pkt_ofs;
217 static int pdc_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
218 static void pdc_error_handler(struct ata_port *ap);
219 static void pdc_freeze(struct ata_port *ap);
220 static void pdc_thaw(struct ata_port *ap);
221 static int pdc_port_start(struct ata_port *ap);
222 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
223 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
224 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
225 static unsigned int pdc20621_dimm_init(struct ata_host *host);
226 static int pdc20621_detect_dimm(struct ata_host *host);
227 static unsigned int pdc20621_i2c_read(struct ata_host *host,
228 u32 device, u32 subaddr, u32 *pdata);
229 static int pdc20621_prog_dimm0(struct ata_host *host);
230 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
231 #ifdef ATA_VERBOSE_DEBUG
232 static void pdc20621_get_from_dimm(struct ata_host *host,
233 void *psource, u32 offset, u32 size);
235 static void pdc20621_put_to_dimm(struct ata_host *host,
236 void *psource, u32 offset, u32 size);
237 static void pdc20621_irq_clear(struct ata_port *ap);
238 static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc);
239 static int pdc_softreset(struct ata_link *link, unsigned int *class,
240 unsigned long deadline);
241 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
242 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
245 static struct scsi_host_template pdc_sata_sht = {
246 ATA_BASE_SHT(DRV_NAME),
247 .sg_tablesize = LIBATA_MAX_PRD,
248 .dma_boundary = ATA_DMA_BOUNDARY,
251 /* TODO: inherit from base port_ops after converting to new EH */
252 static struct ata_port_operations pdc_20621_ops = {
253 .inherits = &ata_sff_port_ops,
255 .check_atapi_dma = pdc_check_atapi_dma,
256 .qc_prep = pdc20621_qc_prep,
257 .qc_issue = pdc20621_qc_issue,
259 .freeze = pdc_freeze,
261 .softreset = pdc_softreset,
262 .error_handler = pdc_error_handler,
263 .lost_interrupt = ATA_OP_NULL,
264 .post_internal_cmd = pdc_post_internal_cmd,
266 .port_start = pdc_port_start,
268 .sff_tf_load = pdc_tf_load_mmio,
269 .sff_exec_command = pdc_exec_command_mmio,
270 .sff_irq_clear = pdc20621_irq_clear,
273 static const struct ata_port_info pdc_port_info[] = {
276 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
277 ATA_FLAG_SRST | ATA_FLAG_MMIO |
278 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
279 .pio_mask = ATA_PIO4,
280 .mwdma_mask = ATA_MWDMA2,
281 .udma_mask = ATA_UDMA6,
282 .port_ops = &pdc_20621_ops,
287 static const struct pci_device_id pdc_sata_pci_tbl[] = {
288 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
290 { } /* terminate list */
293 static struct pci_driver pdc_sata_pci_driver = {
295 .id_table = pdc_sata_pci_tbl,
296 .probe = pdc_sata_init_one,
297 .remove = ata_pci_remove_one,
301 static int pdc_port_start(struct ata_port *ap)
303 struct device *dev = ap->host->dev;
304 struct pdc_port_priv *pp;
307 rc = ata_port_start(ap);
311 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
315 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
319 ap->private_data = pp;
324 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
326 unsigned int total_len)
329 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
330 __le32 *buf32 = (__le32 *) buf;
332 /* output ATA packet S/G table */
333 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
334 (PDC_DIMM_DATA_STEP * portno);
335 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
336 buf32[dw] = cpu_to_le32(addr);
337 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
339 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
340 PDC_20621_DIMM_BASE +
341 (PDC_DIMM_WINDOW_STEP * portno) +
343 buf32[dw], buf32[dw + 1]);
346 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
348 unsigned int total_len)
351 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
352 __le32 *buf32 = (__le32 *) buf;
354 /* output Host DMA packet S/G table */
355 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
356 (PDC_DIMM_DATA_STEP * portno);
358 buf32[dw] = cpu_to_le32(addr);
359 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
361 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
362 PDC_20621_DIMM_BASE +
363 (PDC_DIMM_WINDOW_STEP * portno) +
365 buf32[dw], buf32[dw + 1]);
368 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
369 unsigned int devno, u8 *buf,
373 __le32 *buf32 = (__le32 *) buf;
376 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
377 (PDC_DIMM_WINDOW_STEP * portno) +
379 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
381 i = PDC_DIMM_ATA_PKT;
386 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
387 buf[i++] = PDC_PKT_READ;
388 else if (tf->protocol == ATA_PROT_NODATA)
389 buf[i++] = PDC_PKT_NODATA;
392 buf[i++] = 0; /* reserved */
393 buf[i++] = portno + 1; /* seq. id */
394 buf[i++] = 0xff; /* delay seq. id */
396 /* dimm dma S/G, and next-pkt */
398 if (tf->protocol == ATA_PROT_NODATA)
401 buf32[dw] = cpu_to_le32(dimm_sg);
406 dev_reg = ATA_DEVICE_OBS;
408 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
411 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
414 /* device control register */
415 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
421 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
426 __le32 *buf32 = (__le32 *) buf;
428 unsigned int host_sg = PDC_20621_DIMM_BASE +
429 (PDC_DIMM_WINDOW_STEP * portno) +
431 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
432 (PDC_DIMM_WINDOW_STEP * portno) +
434 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
435 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
437 dw = PDC_DIMM_HOST_PKT >> 2;
440 * Set up Host DMA packet
442 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
446 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
447 tmp |= (0xff << 24); /* delay seq. id */
448 buf32[dw + 0] = cpu_to_le32(tmp);
449 buf32[dw + 1] = cpu_to_le32(host_sg);
450 buf32[dw + 2] = cpu_to_le32(dimm_sg);
453 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
454 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
462 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
464 struct scatterlist *sg;
465 struct ata_port *ap = qc->ap;
466 struct pdc_port_priv *pp = ap->private_data;
467 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
468 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
469 unsigned int portno = ap->port_no;
470 unsigned int i, si, idx, total_len = 0, sgt_len;
471 __le32 *buf = (__le32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
473 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
475 VPRINTK("ata%u: ENTER\n", ap->print_id);
477 /* hard-code chip #0 */
478 mmio += PDC_CHIP0_OFS;
484 for_each_sg(qc->sg, sg, qc->n_elem, si) {
485 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
486 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
487 total_len += sg_dma_len(sg);
489 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
493 * Build ATA, host DMA packets
495 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
496 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
498 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
499 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
501 if (qc->tf.flags & ATA_TFLAG_LBA48)
502 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
504 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
506 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
508 /* copy three S/G tables and two packets to DIMM MMIO window */
509 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
510 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
511 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
513 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
515 /* force host FIFO dump */
516 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
518 readl(dimm_mmio); /* MMIO PCI posting flush */
520 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
523 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
525 struct ata_port *ap = qc->ap;
526 struct pdc_port_priv *pp = ap->private_data;
527 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
528 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
529 unsigned int portno = ap->port_no;
532 VPRINTK("ata%u: ENTER\n", ap->print_id);
534 /* hard-code chip #0 */
535 mmio += PDC_CHIP0_OFS;
537 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
539 if (qc->tf.flags & ATA_TFLAG_LBA48)
540 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
542 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
544 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
546 /* copy three S/G tables and two packets to DIMM MMIO window */
547 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
548 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
550 /* force host FIFO dump */
551 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
553 readl(dimm_mmio); /* MMIO PCI posting flush */
555 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
558 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
560 switch (qc->tf.protocol) {
562 pdc20621_dma_prep(qc);
564 case ATA_PROT_NODATA:
565 pdc20621_nodata_prep(qc);
572 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
576 struct ata_port *ap = qc->ap;
577 struct ata_host *host = ap->host;
578 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
580 /* hard-code chip #0 */
581 mmio += PDC_CHIP0_OFS;
583 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
584 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
586 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
587 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
590 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
594 struct ata_port *ap = qc->ap;
595 struct pdc_host_priv *pp = ap->host->private_data;
596 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
598 if (!pp->doing_hdma) {
599 __pdc20621_push_hdma(qc, seq, pkt_ofs);
604 pp->hdma[idx].qc = qc;
605 pp->hdma[idx].seq = seq;
606 pp->hdma[idx].pkt_ofs = pkt_ofs;
610 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
612 struct ata_port *ap = qc->ap;
613 struct pdc_host_priv *pp = ap->host->private_data;
614 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
616 /* if nothing on queue, we're done */
617 if (pp->hdma_prod == pp->hdma_cons) {
622 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
623 pp->hdma[idx].pkt_ofs);
627 #ifdef ATA_VERBOSE_DEBUG
628 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
630 struct ata_port *ap = qc->ap;
631 unsigned int port_no = ap->port_no;
632 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
634 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
635 dimm_mmio += PDC_DIMM_HOST_PKT;
637 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
638 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
639 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
640 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
643 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
644 #endif /* ATA_VERBOSE_DEBUG */
646 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
648 struct ata_port *ap = qc->ap;
649 struct ata_host *host = ap->host;
650 unsigned int port_no = ap->port_no;
651 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
652 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
653 u8 seq = (u8) (port_no + 1);
654 unsigned int port_ofs;
656 /* hard-code chip #0 */
657 mmio += PDC_CHIP0_OFS;
659 VPRINTK("ata%u: ENTER\n", ap->print_id);
661 wmb(); /* flush PRD, pkt writes */
663 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
665 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
666 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
669 pdc20621_dump_hdma(qc);
670 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
671 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
672 port_ofs + PDC_DIMM_HOST_PKT,
673 port_ofs + PDC_DIMM_HOST_PKT,
676 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
677 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
679 writel(port_ofs + PDC_DIMM_ATA_PKT,
680 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
681 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
682 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
683 port_ofs + PDC_DIMM_ATA_PKT,
684 port_ofs + PDC_DIMM_ATA_PKT,
689 static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc)
691 switch (qc->tf.protocol) {
692 case ATA_PROT_NODATA:
693 if (qc->tf.flags & ATA_TFLAG_POLLING)
697 pdc20621_packet_start(qc);
708 return ata_sff_qc_issue(qc);
711 static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
712 struct ata_queued_cmd *qc,
713 unsigned int doing_hdma,
716 unsigned int port_no = ap->port_no;
717 unsigned int port_ofs =
718 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
720 unsigned int handled = 0;
724 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
725 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
727 /* step two - DMA from DIMM to host */
729 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
730 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
731 /* get drive status; clear intr; complete txn */
732 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
734 pdc20621_pop_hdma(qc);
737 /* step one - exec ATA command */
739 u8 seq = (u8) (port_no + 1 + 4);
740 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
741 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
743 /* submit hdma pkt */
744 pdc20621_dump_hdma(qc);
745 pdc20621_push_hdma(qc, seq,
746 port_ofs + PDC_DIMM_HOST_PKT);
750 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
752 /* step one - DMA from host to DIMM */
754 u8 seq = (u8) (port_no + 1);
755 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
756 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
759 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
760 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
761 writel(port_ofs + PDC_DIMM_ATA_PKT,
762 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
763 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
766 /* step two - execute ATA command */
768 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
769 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
770 /* get drive status; clear intr; complete txn */
771 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
773 pdc20621_pop_hdma(qc);
777 /* command completion, but no data xfer */
778 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
780 status = ata_sff_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
781 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
782 qc->err_mask |= ac_err_mask(status);
787 ap->stats.idle_irq++;
793 static void pdc20621_irq_clear(struct ata_port *ap)
795 ioread8(ap->ioaddr.status_addr);
798 static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
800 struct ata_host *host = dev_instance;
803 unsigned int i, tmp, port_no;
804 unsigned int handled = 0;
805 void __iomem *mmio_base;
809 if (!host || !host->iomap[PDC_MMIO_BAR]) {
810 VPRINTK("QUICK EXIT\n");
814 mmio_base = host->iomap[PDC_MMIO_BAR];
816 /* reading should also clear interrupts */
817 mmio_base += PDC_CHIP0_OFS;
818 mask = readl(mmio_base + PDC_20621_SEQMASK);
819 VPRINTK("mask == 0x%x\n", mask);
821 if (mask == 0xffffffff) {
822 VPRINTK("QUICK EXIT 2\n");
825 mask &= 0xffff; /* only 16 tags possible */
827 VPRINTK("QUICK EXIT 3\n");
831 spin_lock(&host->lock);
833 for (i = 1; i < 9; i++) {
837 if (port_no >= host->n_ports)
840 ap = host->ports[port_no];
841 tmp = mask & (1 << i);
842 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
844 struct ata_queued_cmd *qc;
846 qc = ata_qc_from_tag(ap, ap->link.active_tag);
847 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
848 handled += pdc20621_host_intr(ap, qc, (i > 4),
853 spin_unlock(&host->lock);
855 VPRINTK("mask == 0x%x\n", mask);
859 return IRQ_RETVAL(handled);
862 static void pdc_freeze(struct ata_port *ap)
864 void __iomem *mmio = ap->ioaddr.cmd_addr;
867 /* FIXME: if all 4 ATA engines are stopped, also stop HDMA engine */
869 tmp = readl(mmio + PDC_CTLSTAT);
871 tmp &= ~PDC_DMA_ENABLE;
872 writel(tmp, mmio + PDC_CTLSTAT);
873 readl(mmio + PDC_CTLSTAT); /* flush */
876 static void pdc_thaw(struct ata_port *ap)
878 void __iomem *mmio = ap->ioaddr.cmd_addr;
881 /* FIXME: start HDMA engine, if zero ATA engines running */
884 ioread8(ap->ioaddr.status_addr);
886 /* turn IRQ back on */
887 tmp = readl(mmio + PDC_CTLSTAT);
888 tmp &= ~PDC_MASK_INT;
889 writel(tmp, mmio + PDC_CTLSTAT);
890 readl(mmio + PDC_CTLSTAT); /* flush */
893 static void pdc_reset_port(struct ata_port *ap)
895 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
899 /* FIXME: handle HDMA copy engine */
901 for (i = 11; i > 0; i--) {
914 readl(mmio); /* flush */
917 static int pdc_softreset(struct ata_link *link, unsigned int *class,
918 unsigned long deadline)
920 pdc_reset_port(link->ap);
921 return ata_sff_softreset(link, class, deadline);
924 static void pdc_error_handler(struct ata_port *ap)
926 if (!(ap->pflags & ATA_PFLAG_FROZEN))
929 ata_std_error_handler(ap);
932 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
934 struct ata_port *ap = qc->ap;
936 /* make DMA engine forget about the failed command */
937 if (qc->flags & ATA_QCFLAG_FAILED)
941 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
943 u8 *scsicmd = qc->scsicmd->cmnd;
944 int pio = 1; /* atapi dma off by default */
946 /* Whitelist commands that may use DMA. */
947 switch (scsicmd[0]) {
954 case 0xad: /* READ_DVD_STRUCTURE */
955 case 0xbe: /* READ_CD */
958 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
959 if (scsicmd[0] == WRITE_10) {
965 if (lba >= 0xFFFF4FA2)
971 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
973 WARN_ON(tf->protocol == ATA_PROT_DMA ||
974 tf->protocol == ATAPI_PROT_DMA);
975 ata_sff_tf_load(ap, tf);
979 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
981 WARN_ON(tf->protocol == ATA_PROT_DMA ||
982 tf->protocol == ATAPI_PROT_DMA);
983 ata_sff_exec_command(ap, tf);
987 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
989 port->cmd_addr = base;
990 port->data_addr = base;
992 port->error_addr = base + 0x4;
993 port->nsect_addr = base + 0x8;
994 port->lbal_addr = base + 0xc;
995 port->lbam_addr = base + 0x10;
996 port->lbah_addr = base + 0x14;
997 port->device_addr = base + 0x18;
999 port->status_addr = base + 0x1c;
1000 port->altstatus_addr =
1001 port->ctl_addr = base + 0x38;
1005 #ifdef ATA_VERBOSE_DEBUG
1006 static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
1007 u32 offset, u32 size)
1013 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1014 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1016 /* hard-code chip #0 */
1017 mmio += PDC_CHIP0_OFS;
1020 window_size = 0x2000 * 4; /* 32K byte uchar size */
1021 idx = (u16) (offset / window_size);
1023 writel(0x01, mmio + PDC_GENERAL_CTLR);
1024 readl(mmio + PDC_GENERAL_CTLR);
1025 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1026 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1028 offset -= (idx * window_size);
1030 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
1031 (long) (window_size - offset);
1032 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
1037 for (; (long) size >= (long) window_size ;) {
1038 writel(0x01, mmio + PDC_GENERAL_CTLR);
1039 readl(mmio + PDC_GENERAL_CTLR);
1040 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1041 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1042 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1044 psource += window_size;
1045 size -= window_size;
1050 writel(0x01, mmio + PDC_GENERAL_CTLR);
1051 readl(mmio + PDC_GENERAL_CTLR);
1052 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1053 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1054 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1061 static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
1062 u32 offset, u32 size)
1068 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1069 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1071 /* hard-code chip #0 */
1072 mmio += PDC_CHIP0_OFS;
1075 window_size = 0x2000 * 4; /* 32K byte uchar size */
1076 idx = (u16) (offset / window_size);
1078 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1079 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1080 offset -= (idx * window_size);
1082 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1083 (long) (window_size - offset);
1084 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1085 writel(0x01, mmio + PDC_GENERAL_CTLR);
1086 readl(mmio + PDC_GENERAL_CTLR);
1090 for (; (long) size >= (long) window_size ;) {
1091 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1092 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1093 memcpy_toio(dimm_mmio, psource, window_size / 4);
1094 writel(0x01, mmio + PDC_GENERAL_CTLR);
1095 readl(mmio + PDC_GENERAL_CTLR);
1096 psource += window_size;
1097 size -= window_size;
1102 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1103 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1104 memcpy_toio(dimm_mmio, psource, size / 4);
1105 writel(0x01, mmio + PDC_GENERAL_CTLR);
1106 readl(mmio + PDC_GENERAL_CTLR);
1111 static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
1112 u32 subaddr, u32 *pdata)
1114 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1119 /* hard-code chip #0 */
1120 mmio += PDC_CHIP0_OFS;
1122 i2creg |= device << 24;
1123 i2creg |= subaddr << 16;
1125 /* Set the device and subaddress */
1126 writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1127 readl(mmio + PDC_I2C_ADDR_DATA);
1129 /* Write Control to perform read operation, mask int */
1130 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1131 mmio + PDC_I2C_CONTROL);
1133 for (count = 0; count <= 1000; count ++) {
1134 status = readl(mmio + PDC_I2C_CONTROL);
1135 if (status & PDC_I2C_COMPLETE) {
1136 status = readl(mmio + PDC_I2C_ADDR_DATA);
1138 } else if (count == 1000)
1142 *pdata = (status >> 8) & 0x000000ff;
1147 static int pdc20621_detect_dimm(struct ata_host *host)
1150 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1151 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1157 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1167 static int pdc20621_prog_dimm0(struct ata_host *host)
1173 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1174 static const struct {
1177 } pdc_i2c_read_data [] = {
1178 { PDC_DIMM_SPD_TYPE, 11 },
1179 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1180 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1181 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1182 { PDC_DIMM_SPD_ROW_NUM, 3 },
1183 { PDC_DIMM_SPD_BANK_NUM, 17 },
1184 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1185 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1186 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1187 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1188 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1189 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1192 /* hard-code chip #0 */
1193 mmio += PDC_CHIP0_OFS;
1195 for (i = 0; i < ARRAY_SIZE(pdc_i2c_read_data); i++)
1196 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1197 pdc_i2c_read_data[i].reg,
1198 &spd0[pdc_i2c_read_data[i].ofs]);
1200 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1201 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1202 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1203 data |= (((((spd0[29] > spd0[28])
1204 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1205 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1207 if (spd0[18] & 0x08)
1208 data |= ((0x03) << 14);
1209 else if (spd0[18] & 0x04)
1210 data |= ((0x02) << 14);
1211 else if (spd0[18] & 0x01)
1212 data |= ((0x01) << 14);
1217 Calculate the size of bDIMMSize (power of 2) and
1218 merge the DIMM size by program start/end address.
1221 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1222 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1223 data |= (((size / 16) - 1) << 16);
1226 writel(data, mmio + PDC_DIMM0_CONTROL);
1227 readl(mmio + PDC_DIMM0_CONTROL);
1232 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1236 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1238 /* hard-code chip #0 */
1239 mmio += PDC_CHIP0_OFS;
1242 Set To Default : DIMM Module Global Control Register (0x022259F1)
1243 DIMM Arbitration Disable (bit 20)
1244 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1245 Refresh Enable (bit 17)
1249 writel(data, mmio + PDC_SDRAM_CONTROL);
1250 readl(mmio + PDC_SDRAM_CONTROL);
1252 /* Turn on for ECC */
1253 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1254 PDC_DIMM_SPD_TYPE, &spd0);
1256 data |= (0x01 << 16);
1257 writel(data, mmio + PDC_SDRAM_CONTROL);
1258 readl(mmio + PDC_SDRAM_CONTROL);
1259 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1262 /* DIMM Initialization Select/Enable (bit 18/19) */
1265 writel(data, mmio + PDC_SDRAM_CONTROL);
1268 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1269 data = readl(mmio + PDC_SDRAM_CONTROL);
1270 if (!(data & (1<<19))) {
1280 static unsigned int pdc20621_dimm_init(struct ata_host *host)
1282 int speed, size, length;
1283 u32 addr, spd0, pci_status;
1284 u32 time_period = 0;
1289 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1291 /* hard-code chip #0 */
1292 mmio += PDC_CHIP0_OFS;
1294 /* Initialize PLL based upon PCI Bus Frequency */
1296 /* Initialize Time Period Register */
1297 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1298 time_period = readl(mmio + PDC_TIME_PERIOD);
1299 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1302 writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1303 readl(mmio + PDC_TIME_CONTROL);
1305 /* Wait 3 seconds */
1309 When timer is enabled, counter is decreased every internal
1313 tcount = readl(mmio + PDC_TIME_COUNTER);
1314 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1317 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1318 register should be >= (0xffffffff - 3x10^8).
1320 if (tcount >= PCI_X_TCOUNT) {
1321 ticks = (time_period - tcount);
1322 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1324 clock = (ticks / 300000);
1325 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1327 clock = (clock * 33);
1328 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1330 /* PLL F Param (bit 22:16) */
1331 fparam = (1400000 / clock) - 2;
1332 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1334 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1335 pci_status = (0x8a001824 | (fparam << 16));
1337 pci_status = PCI_PLL_INIT;
1339 /* Initialize PLL. */
1340 VPRINTK("pci_status: 0x%x\n", pci_status);
1341 writel(pci_status, mmio + PDC_CTL_STATUS);
1342 readl(mmio + PDC_CTL_STATUS);
1345 Read SPD of DIMM by I2C interface,
1346 and program the DIMM Module Controller.
1348 if (!(speed = pdc20621_detect_dimm(host))) {
1349 printk(KERN_ERR "Detect Local DIMM Fail\n");
1350 return 1; /* DIMM error */
1352 VPRINTK("Local DIMM Speed = %d\n", speed);
1354 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1355 size = pdc20621_prog_dimm0(host);
1356 VPRINTK("Local DIMM Size = %dMB\n", size);
1358 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1359 if (pdc20621_prog_dimm_global(host)) {
1360 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1364 #ifdef ATA_VERBOSE_DEBUG
1366 u8 test_parttern1[40] =
1367 {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1368 'N','o','t',' ','Y','e','t',' ',
1369 'D','e','f','i','n','e','d',' ',
1371 '9','8','0','3','1','6','1','2',0,0};
1372 u8 test_parttern2[40] = {0};
1374 pdc20621_put_to_dimm(host, test_parttern2, 0x10040, 40);
1375 pdc20621_put_to_dimm(host, test_parttern2, 0x40, 40);
1377 pdc20621_put_to_dimm(host, test_parttern1, 0x10040, 40);
1378 pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1379 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1380 test_parttern2[1], &(test_parttern2[2]));
1381 pdc20621_get_from_dimm(host, test_parttern2, 0x10040,
1383 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1384 test_parttern2[1], &(test_parttern2[2]));
1386 pdc20621_put_to_dimm(host, test_parttern1, 0x40, 40);
1387 pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1388 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1389 test_parttern2[1], &(test_parttern2[2]));
1393 /* ECC initiliazation. */
1395 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1396 PDC_DIMM_SPD_TYPE, &spd0);
1399 VPRINTK("Start ECC initialization\n");
1401 length = size * 1024 * 1024;
1402 buf = kzalloc(ECC_ERASE_BUF_SZ, GFP_KERNEL);
1403 while (addr < length) {
1404 pdc20621_put_to_dimm(host, buf, addr,
1406 addr += ECC_ERASE_BUF_SZ;
1409 VPRINTK("Finish ECC initialization\n");
1415 static void pdc_20621_init(struct ata_host *host)
1418 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1420 /* hard-code chip #0 */
1421 mmio += PDC_CHIP0_OFS;
1424 * Select page 0x40 for our 32k DIMM window
1426 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1427 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1428 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1433 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1435 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1436 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1440 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1442 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1443 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1446 static int pdc_sata_init_one(struct pci_dev *pdev,
1447 const struct pci_device_id *ent)
1449 static int printed_version;
1450 const struct ata_port_info *ppi[] =
1451 { &pdc_port_info[ent->driver_data], NULL };
1452 struct ata_host *host;
1453 struct pdc_host_priv *hpriv;
1456 if (!printed_version++)
1457 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1460 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1461 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1462 if (!host || !hpriv)
1465 host->private_data = hpriv;
1467 /* acquire resources and fill host */
1468 rc = pcim_enable_device(pdev);
1472 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1475 pcim_pin_device(pdev);
1478 host->iomap = pcim_iomap_table(pdev);
1480 for (i = 0; i < 4; i++) {
1481 struct ata_port *ap = host->ports[i];
1482 void __iomem *base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1483 unsigned int offset = 0x200 + i * 0x80;
1485 pdc_sata_setup_port(&ap->ioaddr, base + offset);
1487 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1488 ata_port_pbar_desc(ap, PDC_DIMM_BAR, -1, "dimm");
1489 ata_port_pbar_desc(ap, PDC_MMIO_BAR, offset, "port");
1492 /* configure and activate */
1493 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1496 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1500 if (pdc20621_dimm_init(host))
1502 pdc_20621_init(host);
1504 pci_set_master(pdev);
1505 return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1506 IRQF_SHARED, &pdc_sata_sht);
1510 static int __init pdc_sata_init(void)
1512 return pci_register_driver(&pdc_sata_pci_driver);
1516 static void __exit pdc_sata_exit(void)
1518 pci_unregister_driver(&pdc_sata_pci_driver);
1522 MODULE_AUTHOR("Jeff Garzik");
1523 MODULE_DESCRIPTION("Promise SATA low-level driver");
1524 MODULE_LICENSE("GPL");
1525 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1526 MODULE_VERSION(DRV_VERSION);
1528 module_init(pdc_sata_init);
1529 module_exit(pdc_sata_exit);