2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
47 #include "sata_promise.h"
49 #define DRV_NAME "sata_promise"
50 #define DRV_VERSION "1.05"
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
73 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
74 (1<<8) | (1<<9) | (1<<10),
76 board_2037x = 0, /* FastTrak S150 TX2plus */
77 board_20319 = 1, /* FastTrak S150 TX4 */
78 board_20619 = 2, /* FastTrak TX4000 */
79 board_2057x = 3, /* SATAII150 Tx2plus */
80 board_40518 = 4, /* SATAII150 Tx4 */
82 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
84 /* Sequence counter control registers bit definitions */
85 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
87 /* Feature register values */
88 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
89 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
91 /* Device/Head register values */
92 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
94 /* PDC_CTLSTAT bit definitions */
95 PDC_DMA_ENABLE = (1 << 7),
96 PDC_IRQ_DISABLE = (1 << 10),
97 PDC_RESET = (1 << 11), /* HDMA reset */
99 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
101 ATA_FLAG_PIO_POLLING,
104 PDC_FLAG_GEN_II = (1 << 0),
108 struct pdc_port_priv {
113 struct pdc_host_priv {
115 unsigned long port_flags[ATA_MAX_PORTS];
118 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
121 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
122 static void pdc_eng_timeout(struct ata_port *ap);
123 static int pdc_port_start(struct ata_port *ap);
124 static void pdc_port_stop(struct ata_port *ap);
125 static void pdc_pata_phy_reset(struct ata_port *ap);
126 static void pdc_qc_prep(struct ata_queued_cmd *qc);
127 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
128 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
129 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
130 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
131 static void pdc_irq_clear(struct ata_port *ap);
132 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
133 static void pdc_host_stop(struct ata_host *host);
134 static void pdc_freeze(struct ata_port *ap);
135 static void pdc_thaw(struct ata_port *ap);
136 static void pdc_error_handler(struct ata_port *ap);
137 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
140 static struct scsi_host_template pdc_ata_sht = {
141 .module = THIS_MODULE,
143 .ioctl = ata_scsi_ioctl,
144 .queuecommand = ata_scsi_queuecmd,
145 .can_queue = ATA_DEF_QUEUE,
146 .this_id = ATA_SHT_THIS_ID,
147 .sg_tablesize = LIBATA_MAX_PRD,
148 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
149 .emulated = ATA_SHT_EMULATED,
150 .use_clustering = ATA_SHT_USE_CLUSTERING,
151 .proc_name = DRV_NAME,
152 .dma_boundary = ATA_DMA_BOUNDARY,
153 .slave_configure = ata_scsi_slave_config,
154 .slave_destroy = ata_scsi_slave_destroy,
155 .bios_param = ata_std_bios_param,
158 static const struct ata_port_operations pdc_sata_ops = {
159 .port_disable = ata_port_disable,
160 .tf_load = pdc_tf_load_mmio,
161 .tf_read = ata_tf_read,
162 .check_status = ata_check_status,
163 .exec_command = pdc_exec_command_mmio,
164 .dev_select = ata_std_dev_select,
165 .check_atapi_dma = pdc_check_atapi_dma,
167 .qc_prep = pdc_qc_prep,
168 .qc_issue = pdc_qc_issue_prot,
169 .freeze = pdc_freeze,
171 .error_handler = pdc_error_handler,
172 .post_internal_cmd = pdc_post_internal_cmd,
173 .data_xfer = ata_mmio_data_xfer,
174 .irq_handler = pdc_interrupt,
175 .irq_clear = pdc_irq_clear,
177 .scr_read = pdc_sata_scr_read,
178 .scr_write = pdc_sata_scr_write,
179 .port_start = pdc_port_start,
180 .port_stop = pdc_port_stop,
181 .host_stop = pdc_host_stop,
184 /* First-generation chips need a more restrictive ->check_atapi_dma op */
185 static const struct ata_port_operations pdc_old_sata_ops = {
186 .port_disable = ata_port_disable,
187 .tf_load = pdc_tf_load_mmio,
188 .tf_read = ata_tf_read,
189 .check_status = ata_check_status,
190 .exec_command = pdc_exec_command_mmio,
191 .dev_select = ata_std_dev_select,
192 .check_atapi_dma = pdc_old_check_atapi_dma,
194 .qc_prep = pdc_qc_prep,
195 .qc_issue = pdc_qc_issue_prot,
196 .freeze = pdc_freeze,
198 .error_handler = pdc_error_handler,
199 .post_internal_cmd = pdc_post_internal_cmd,
200 .data_xfer = ata_mmio_data_xfer,
201 .irq_handler = pdc_interrupt,
202 .irq_clear = pdc_irq_clear,
204 .scr_read = pdc_sata_scr_read,
205 .scr_write = pdc_sata_scr_write,
206 .port_start = pdc_port_start,
207 .port_stop = pdc_port_stop,
208 .host_stop = pdc_host_stop,
211 static const struct ata_port_operations pdc_pata_ops = {
212 .port_disable = ata_port_disable,
213 .tf_load = pdc_tf_load_mmio,
214 .tf_read = ata_tf_read,
215 .check_status = ata_check_status,
216 .exec_command = pdc_exec_command_mmio,
217 .dev_select = ata_std_dev_select,
218 .check_atapi_dma = pdc_check_atapi_dma,
220 .phy_reset = pdc_pata_phy_reset,
222 .qc_prep = pdc_qc_prep,
223 .qc_issue = pdc_qc_issue_prot,
224 .data_xfer = ata_mmio_data_xfer,
225 .eng_timeout = pdc_eng_timeout,
226 .irq_handler = pdc_interrupt,
227 .irq_clear = pdc_irq_clear,
229 .port_start = pdc_port_start,
230 .port_stop = pdc_port_stop,
231 .host_stop = pdc_host_stop,
234 static const struct ata_port_info pdc_port_info[] = {
238 .flags = PDC_COMMON_FLAGS,
239 .pio_mask = 0x1f, /* pio0-4 */
240 .mwdma_mask = 0x07, /* mwdma0-2 */
241 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
242 .port_ops = &pdc_old_sata_ops,
248 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
249 .pio_mask = 0x1f, /* pio0-4 */
250 .mwdma_mask = 0x07, /* mwdma0-2 */
251 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
252 .port_ops = &pdc_old_sata_ops,
258 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
259 .pio_mask = 0x1f, /* pio0-4 */
260 .mwdma_mask = 0x07, /* mwdma0-2 */
261 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
262 .port_ops = &pdc_pata_ops,
268 .flags = PDC_COMMON_FLAGS,
269 .pio_mask = 0x1f, /* pio0-4 */
270 .mwdma_mask = 0x07, /* mwdma0-2 */
271 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
272 .port_ops = &pdc_sata_ops,
278 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
279 .pio_mask = 0x1f, /* pio0-4 */
280 .mwdma_mask = 0x07, /* mwdma0-2 */
281 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
282 .port_ops = &pdc_sata_ops,
286 static const struct pci_device_id pdc_ata_pci_tbl[] = {
287 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
288 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
289 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
290 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
291 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
293 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
294 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
295 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
296 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
298 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
299 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
300 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
301 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
302 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
303 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
305 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
307 { } /* terminate list */
311 static struct pci_driver pdc_ata_pci_driver = {
313 .id_table = pdc_ata_pci_tbl,
314 .probe = pdc_ata_init_one,
315 .remove = ata_pci_remove_one,
319 static int pdc_port_start(struct ata_port *ap)
321 struct device *dev = ap->host->dev;
322 struct pdc_host_priv *hp = ap->host->private_data;
323 struct pdc_port_priv *pp;
326 /* fix up port flags and cable type for SATA+PATA chips */
327 ap->flags |= hp->port_flags[ap->port_no];
328 if (ap->flags & ATA_FLAG_SATA)
329 ap->cbl = ATA_CBL_SATA;
331 rc = ata_port_start(ap);
335 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
341 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
347 ap->private_data = pp;
349 /* fix up PHYMODE4 align timing */
350 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
351 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
354 tmp = readl(mmio + 0x014);
355 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
356 writel(tmp, mmio + 0x014);
369 static void pdc_port_stop(struct ata_port *ap)
371 struct device *dev = ap->host->dev;
372 struct pdc_port_priv *pp = ap->private_data;
374 ap->private_data = NULL;
375 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
381 static void pdc_host_stop(struct ata_host *host)
383 struct pdc_host_priv *hp = host->private_data;
385 ata_pci_host_stop(host);
391 static void pdc_reset_port(struct ata_port *ap)
393 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
397 for (i = 11; i > 0; i--) {
410 readl(mmio); /* flush */
413 static void pdc_pata_cbl_detect(struct ata_port *ap)
416 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
421 ap->cbl = ATA_CBL_PATA40;
422 ap->udma_mask &= ATA_UDMA_MASK_40C;
424 ap->cbl = ATA_CBL_PATA80;
427 static void pdc_pata_phy_reset(struct ata_port *ap)
429 pdc_pata_cbl_detect(ap);
435 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
437 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
439 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
443 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
446 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
448 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
451 static void pdc_atapi_dma_pkt(struct ata_taskfile *tf,
453 unsigned int cdb_len, u8 *cdb,
456 u32 *buf32 = (u32 *) buf;
458 /* set control bits (byte 0), zero delay seq id (byte 3),
459 * and seq id (byte 2)
461 if (!(tf->flags & ATA_TFLAG_WRITE))
462 buf32[0] = cpu_to_le32(PDC_PKT_READ);
465 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
466 buf32[2] = 0; /* no next-packet */
468 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
469 BUG_ON(cdb_len & ~0x1E);
471 buf[12] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
472 memcpy(buf+13, cdb, cdb_len);
475 static void pdc_qc_prep(struct ata_queued_cmd *qc)
477 struct pdc_port_priv *pp = qc->ap->private_data;
482 switch (qc->tf.protocol) {
487 case ATA_PROT_NODATA:
488 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
489 qc->dev->devno, pp->pkt);
491 if (qc->tf.flags & ATA_TFLAG_LBA48)
492 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
494 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
496 pdc_pkt_footer(&qc->tf, pp->pkt, i);
500 case ATA_PROT_ATAPI_NODATA:
504 case ATA_PROT_ATAPI_DMA:
506 pdc_atapi_dma_pkt(&qc->tf, qc->ap->prd_dma, qc->dev->cdb_len, qc->cdb, pp->pkt);
514 static void pdc_freeze(struct ata_port *ap)
516 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
519 tmp = readl(mmio + PDC_CTLSTAT);
520 tmp |= PDC_IRQ_DISABLE;
521 tmp &= ~PDC_DMA_ENABLE;
522 writel(tmp, mmio + PDC_CTLSTAT);
523 readl(mmio + PDC_CTLSTAT); /* flush */
526 static void pdc_thaw(struct ata_port *ap)
528 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
532 readl(mmio + PDC_INT_SEQMASK);
534 /* turn IRQ back on */
535 tmp = readl(mmio + PDC_CTLSTAT);
536 tmp &= ~PDC_IRQ_DISABLE;
537 writel(tmp, mmio + PDC_CTLSTAT);
538 readl(mmio + PDC_CTLSTAT); /* flush */
541 static void pdc_error_handler(struct ata_port *ap)
543 ata_reset_fn_t hardreset;
545 if (!(ap->pflags & ATA_PFLAG_FROZEN))
549 if (sata_scr_valid(ap))
550 hardreset = sata_std_hardreset;
552 /* perform recovery */
553 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
557 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
559 struct ata_port *ap = qc->ap;
561 if (qc->flags & ATA_QCFLAG_FAILED)
562 qc->err_mask |= AC_ERR_OTHER;
564 /* make DMA engine forget about the failed command */
569 static void pdc_eng_timeout(struct ata_port *ap)
571 struct ata_host *host = ap->host;
573 struct ata_queued_cmd *qc;
578 spin_lock_irqsave(&host->lock, flags);
580 qc = ata_qc_from_tag(ap, ap->active_tag);
582 switch (qc->tf.protocol) {
584 case ATA_PROT_NODATA:
585 ata_port_printk(ap, KERN_ERR, "command timeout\n");
586 drv_stat = ata_wait_idle(ap);
587 qc->err_mask |= __ac_err_mask(drv_stat);
591 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
593 ata_port_printk(ap, KERN_ERR,
594 "unknown timeout, cmd 0x%x stat 0x%x\n",
595 qc->tf.command, drv_stat);
597 qc->err_mask |= ac_err_mask(drv_stat);
601 spin_unlock_irqrestore(&host->lock, flags);
602 ata_eh_qc_complete(qc);
606 static inline unsigned int pdc_host_intr( struct ata_port *ap,
607 struct ata_queued_cmd *qc)
609 unsigned int handled = 0;
611 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
614 if (tmp & PDC_ERR_MASK) {
615 qc->err_mask |= AC_ERR_DEV;
619 switch (qc->tf.protocol) {
621 case ATA_PROT_NODATA:
622 case ATA_PROT_ATAPI_DMA:
623 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
629 ap->stats.idle_irq++;
636 static void pdc_irq_clear(struct ata_port *ap)
638 struct ata_host *host = ap->host;
639 void __iomem *mmio = host->mmio_base;
641 readl(mmio + PDC_INT_SEQMASK);
644 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
646 struct ata_host *host = dev_instance;
650 unsigned int handled = 0;
651 void __iomem *mmio_base;
655 if (!host || !host->mmio_base) {
656 VPRINTK("QUICK EXIT\n");
660 mmio_base = host->mmio_base;
662 /* reading should also clear interrupts */
663 mask = readl(mmio_base + PDC_INT_SEQMASK);
665 if (mask == 0xffffffff) {
666 VPRINTK("QUICK EXIT 2\n");
670 spin_lock(&host->lock);
672 mask &= 0xffff; /* only 16 tags possible */
674 VPRINTK("QUICK EXIT 3\n");
678 writel(mask, mmio_base + PDC_INT_SEQMASK);
680 for (i = 0; i < host->n_ports; i++) {
681 VPRINTK("port %u\n", i);
683 tmp = mask & (1 << (i + 1));
685 !(ap->flags & ATA_FLAG_DISABLED)) {
686 struct ata_queued_cmd *qc;
688 qc = ata_qc_from_tag(ap, ap->active_tag);
689 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
690 handled += pdc_host_intr(ap, qc);
697 spin_unlock(&host->lock);
698 return IRQ_RETVAL(handled);
701 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
703 struct ata_port *ap = qc->ap;
704 struct pdc_port_priv *pp = ap->private_data;
705 unsigned int port_no = ap->port_no;
706 u8 seq = (u8) (port_no + 1);
708 VPRINTK("ENTER, ap %p\n", ap);
710 writel(0x00000001, ap->host->mmio_base + (seq * 4));
711 readl(ap->host->mmio_base + (seq * 4)); /* flush */
714 wmb(); /* flush PRD, pkt writes */
715 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
716 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
719 static unsigned int pdc_wait_for_drq(struct ata_port *ap)
721 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
725 /* Following pdc-ultra's WaitForDrq() we loop here until BSY
726 * is clear and DRQ is set in altstatus. We could possibly call
727 * ata_busy_wait() and loop until DRQ is set, but since we don't
728 * know how much time a call to ata_busy_wait() took, we don't
729 * know when to time out the outer loop.
731 for(i = 0; i < 1000; ++i) {
732 status = readb(port_mmio + PDC_ALTSTATUS);
735 if (status & ATA_BUSY)
737 else if (status & (ATA_DRQ | ATA_ERR))
742 ata_port_printk(ap, KERN_WARNING, "%s timed out\n", __FUNCTION__);
746 static unsigned int pdc_wait_on_busy(struct ata_port *ap)
748 unsigned int status = ata_busy_wait(ap, ATA_BUSY, 1000);
749 if (status != 0xff && (status & ATA_BUSY))
750 ata_port_printk(ap, KERN_WARNING, "%s timed out\n", __FUNCTION__);
754 static void pdc_issue_atapi_pkt_cmd(struct ata_queued_cmd *qc)
756 struct ata_port *ap = qc->ap;
757 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
758 void __iomem *host_mmio = ap->host->mmio_base;
762 writeb(0x00, port_mmio + PDC_CTLSTAT); /* route drive INT to SEQ 0 */
763 writeb(PDC_SEQCNTRL_INT_MASK, host_mmio + 0); /* but mask SEQ 0 INT */
766 if (sata_scr_valid(ap)) {
767 tmp = PDC_DEVICE_SATA;
769 tmp = ATA_DEVICE_OBS;
770 if (qc->dev->devno != 0)
773 writeb(tmp, port_mmio + PDC_DEVICE);
774 pdc_wait_on_busy(ap);
776 writeb(0x00, port_mmio + PDC_SECTOR_COUNT);
777 writeb(0x00, port_mmio + PDC_SECTOR_NUMBER);
779 /* set feature and byte counter registers */
780 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
781 tmp = PDC_FEATURE_ATAPI_PIO;
782 /* set byte counter register to real transfer byte count */
785 nbytes = qc->nsect << 9;
789 tmp = PDC_FEATURE_ATAPI_DMA;
790 /* set byte counter register to 0 */
793 writeb(tmp, port_mmio + PDC_FEATURE);
794 writeb(nbytes & 0xFF, port_mmio + PDC_CYLINDER_LOW);
795 writeb((nbytes >> 8) & 0xFF, port_mmio + PDC_CYLINDER_HIGH);
797 /* send ATAPI packet command 0xA0 */
798 writeb(ATA_CMD_PACKET, port_mmio + PDC_COMMAND);
800 /* pdc_qc_issue_prot() currently sends ATAPI PIO packets back
801 * to libata. If we start handling those packets ourselves,
802 * then we must busy-wait for INT (CTLSTAT bit 27) at this point
803 * if the device has ATA_DFLAG_CDB_INTR set.
806 pdc_wait_for_drq(ap);
808 /* now the device only waits for the CDB */
811 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
813 switch (qc->tf.protocol) {
814 case ATA_PROT_ATAPI_DMA:
815 pdc_issue_atapi_pkt_cmd(qc);
818 case ATA_PROT_NODATA:
819 pdc_packet_start(qc);
826 return ata_qc_issue_prot(qc);
829 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
831 WARN_ON (tf->protocol == ATA_PROT_DMA ||
832 tf->protocol == ATA_PROT_NODATA);
837 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
839 WARN_ON (tf->protocol == ATA_PROT_DMA ||
840 tf->protocol == ATA_PROT_NODATA);
841 ata_exec_command(ap, tf);
844 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
846 u8 *scsicmd = qc->scsicmd->cmnd;
847 int pio = 1; /* atapi dma off by default */
849 /* Whitelist commands that may use DMA. */
850 switch (scsicmd[0]) {
857 case 0xad: /* READ_DVD_STRUCTURE */
858 case 0xbe: /* READ_CD */
861 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
862 if (scsicmd[0] == WRITE_10) {
864 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
865 if (lba >= 0xFFFF4FA2)
871 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
873 struct ata_port *ap = qc->ap;
875 /* First generation chips cannot use ATAPI DMA on SATA ports */
876 if (sata_scr_valid(ap))
878 return pdc_check_atapi_dma(qc);
881 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
883 port->cmd_addr = base;
884 port->data_addr = base;
886 port->error_addr = base + 0x4;
887 port->nsect_addr = base + 0x8;
888 port->lbal_addr = base + 0xc;
889 port->lbam_addr = base + 0x10;
890 port->lbah_addr = base + 0x14;
891 port->device_addr = base + 0x18;
893 port->status_addr = base + 0x1c;
894 port->altstatus_addr =
895 port->ctl_addr = base + 0x38;
899 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
901 void __iomem *mmio = pe->mmio_base;
902 struct pdc_host_priv *hp = pe->private_data;
906 if (hp->flags & PDC_FLAG_GEN_II)
907 hotplug_offset = PDC2_SATA_PLUG_CSR;
909 hotplug_offset = PDC_SATA_PLUG_CSR;
912 * Except for the hotplug stuff, this is voodoo from the
913 * Promise driver. Label this entire section
914 * "TODO: figure out why we do this"
917 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
918 tmp = readl(mmio + PDC_FLASH_CTL);
919 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
920 if (!(hp->flags & PDC_FLAG_GEN_II))
921 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
922 writel(tmp, mmio + PDC_FLASH_CTL);
924 /* clear plug/unplug flags for all ports */
925 tmp = readl(mmio + hotplug_offset);
926 writel(tmp | 0xff, mmio + hotplug_offset);
928 /* mask plug/unplug ints */
929 tmp = readl(mmio + hotplug_offset);
930 writel(tmp | 0xff0000, mmio + hotplug_offset);
932 /* don't initialise TBG or SLEW on 2nd generation chips */
933 if (hp->flags & PDC_FLAG_GEN_II)
936 /* reduce TBG clock to 133 Mhz. */
937 tmp = readl(mmio + PDC_TBG_MODE);
938 tmp &= ~0x30000; /* clear bit 17, 16*/
939 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
940 writel(tmp, mmio + PDC_TBG_MODE);
942 readl(mmio + PDC_TBG_MODE); /* flush */
945 /* adjust slew rate control register. */
946 tmp = readl(mmio + PDC_SLEW_CTL);
947 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
948 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
949 writel(tmp, mmio + PDC_SLEW_CTL);
952 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
954 static int printed_version;
955 struct ata_probe_ent *probe_ent = NULL;
956 struct pdc_host_priv *hp;
958 void __iomem *mmio_base;
959 unsigned int board_idx = (unsigned int) ent->driver_data;
960 int pci_dev_busy = 0;
964 if (!printed_version++)
965 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
967 rc = pci_enable_device(pdev);
971 rc = pci_request_regions(pdev, DRV_NAME);
977 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
979 goto err_out_regions;
980 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
982 goto err_out_regions;
984 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
985 if (probe_ent == NULL) {
987 goto err_out_regions;
990 probe_ent->dev = pci_dev_to_dev(pdev);
991 INIT_LIST_HEAD(&probe_ent->node);
993 mmio_base = pci_iomap(pdev, 3, 0);
994 if (mmio_base == NULL) {
996 goto err_out_free_ent;
998 base = (unsigned long) mmio_base;
1000 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
1003 goto err_out_free_ent;
1006 probe_ent->private_data = hp;
1008 probe_ent->sht = pdc_port_info[board_idx].sht;
1009 probe_ent->port_flags = pdc_port_info[board_idx].flags;
1010 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1011 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1012 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1013 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1015 probe_ent->irq = pdev->irq;
1016 probe_ent->irq_flags = IRQF_SHARED;
1017 probe_ent->mmio_base = mmio_base;
1019 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
1020 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
1022 probe_ent->port[0].scr_addr = base + 0x400;
1023 probe_ent->port[1].scr_addr = base + 0x500;
1025 /* notice 4-port boards */
1026 switch (board_idx) {
1028 hp->flags |= PDC_FLAG_GEN_II;
1031 probe_ent->n_ports = 4;
1033 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1034 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
1036 probe_ent->port[2].scr_addr = base + 0x600;
1037 probe_ent->port[3].scr_addr = base + 0x700;
1040 hp->flags |= PDC_FLAG_GEN_II;
1043 /* TX2plus boards also have a PATA port */
1044 tmp = readb(mmio_base + PDC_FLASH_CTL+1);
1045 if (!(tmp & 0x80)) {
1046 probe_ent->n_ports = 3;
1047 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1048 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
1049 printk(KERN_INFO DRV_NAME " PATA port found\n");
1051 probe_ent->n_ports = 2;
1052 hp->port_flags[0] = ATA_FLAG_SATA;
1053 hp->port_flags[1] = ATA_FLAG_SATA;
1056 probe_ent->n_ports = 4;
1058 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1059 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
1061 probe_ent->port[2].scr_addr = base + 0x600;
1062 probe_ent->port[3].scr_addr = base + 0x700;
1069 pci_set_master(pdev);
1071 /* initialize adapter */
1072 pdc_host_init(board_idx, probe_ent);
1074 /* FIXME: Need any other frees than hp? */
1075 if (!ata_device_add(probe_ent))
1085 pci_release_regions(pdev);
1088 pci_disable_device(pdev);
1093 static int __init pdc_ata_init(void)
1095 return pci_register_driver(&pdc_ata_pci_driver);
1099 static void __exit pdc_ata_exit(void)
1101 pci_unregister_driver(&pdc_ata_pci_driver);
1105 MODULE_AUTHOR("Jeff Garzik");
1106 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1107 MODULE_LICENSE("GPL");
1108 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1109 MODULE_VERSION(DRV_VERSION);
1111 module_init(pdc_ata_init);
1112 module_exit(pdc_ata_exit);