2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "2.10"
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
73 /* PDC_GLOBAL_CTL bit definitions */
74 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
75 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
76 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
77 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
78 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
79 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
80 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
81 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
82 PDC_DRIVE_ERR = (1 << 21), /* drive error */
83 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
84 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
85 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
86 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR,
87 PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR
88 | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR
89 | PDC1_ERR_MASK | PDC2_ERR_MASK),
91 board_2037x = 0, /* FastTrak S150 TX2plus */
92 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
93 board_20319 = 2, /* FastTrak S150 TX4 */
94 board_20619 = 3, /* FastTrak TX4000 */
95 board_2057x = 4, /* SATAII150 Tx2plus */
96 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
97 board_40518 = 6, /* SATAII150 Tx4 */
99 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
101 /* Sequence counter control registers bit definitions */
102 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
104 /* Feature register values */
105 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
106 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
108 /* Device/Head register values */
109 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
111 /* PDC_CTLSTAT bit definitions */
112 PDC_DMA_ENABLE = (1 << 7),
113 PDC_IRQ_DISABLE = (1 << 10),
114 PDC_RESET = (1 << 11), /* HDMA reset */
116 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
118 ATA_FLAG_PIO_POLLING,
121 PDC_FLAG_GEN_II = (1 << 24),
122 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
123 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
126 struct pdc_port_priv {
131 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
132 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
133 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
134 static int pdc_common_port_start(struct ata_port *ap);
135 static int pdc_sata_port_start(struct ata_port *ap);
136 static void pdc_qc_prep(struct ata_queued_cmd *qc);
137 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
138 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
139 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
140 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
141 static void pdc_irq_clear(struct ata_port *ap);
142 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
143 static void pdc_freeze(struct ata_port *ap);
144 static void pdc_thaw(struct ata_port *ap);
145 static void pdc_pata_error_handler(struct ata_port *ap);
146 static void pdc_sata_error_handler(struct ata_port *ap);
147 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
148 static int pdc_pata_cable_detect(struct ata_port *ap);
149 static int pdc_sata_cable_detect(struct ata_port *ap);
151 static struct scsi_host_template pdc_ata_sht = {
152 .module = THIS_MODULE,
154 .ioctl = ata_scsi_ioctl,
155 .queuecommand = ata_scsi_queuecmd,
156 .can_queue = ATA_DEF_QUEUE,
157 .this_id = ATA_SHT_THIS_ID,
158 .sg_tablesize = LIBATA_MAX_PRD,
159 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
160 .emulated = ATA_SHT_EMULATED,
161 .use_clustering = ATA_SHT_USE_CLUSTERING,
162 .proc_name = DRV_NAME,
163 .dma_boundary = ATA_DMA_BOUNDARY,
164 .slave_configure = ata_scsi_slave_config,
165 .slave_destroy = ata_scsi_slave_destroy,
166 .bios_param = ata_std_bios_param,
169 static const struct ata_port_operations pdc_sata_ops = {
170 .port_disable = ata_port_disable,
171 .tf_load = pdc_tf_load_mmio,
172 .tf_read = ata_tf_read,
173 .check_status = ata_check_status,
174 .exec_command = pdc_exec_command_mmio,
175 .dev_select = ata_std_dev_select,
176 .check_atapi_dma = pdc_check_atapi_dma,
178 .qc_prep = pdc_qc_prep,
179 .qc_issue = pdc_qc_issue_prot,
180 .freeze = pdc_freeze,
182 .error_handler = pdc_sata_error_handler,
183 .post_internal_cmd = pdc_post_internal_cmd,
184 .cable_detect = pdc_sata_cable_detect,
185 .data_xfer = ata_data_xfer,
186 .irq_clear = pdc_irq_clear,
187 .irq_on = ata_irq_on,
189 .scr_read = pdc_sata_scr_read,
190 .scr_write = pdc_sata_scr_write,
191 .port_start = pdc_sata_port_start,
194 /* First-generation chips need a more restrictive ->check_atapi_dma op */
195 static const struct ata_port_operations pdc_old_sata_ops = {
196 .port_disable = ata_port_disable,
197 .tf_load = pdc_tf_load_mmio,
198 .tf_read = ata_tf_read,
199 .check_status = ata_check_status,
200 .exec_command = pdc_exec_command_mmio,
201 .dev_select = ata_std_dev_select,
202 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
204 .qc_prep = pdc_qc_prep,
205 .qc_issue = pdc_qc_issue_prot,
206 .freeze = pdc_freeze,
208 .error_handler = pdc_sata_error_handler,
209 .post_internal_cmd = pdc_post_internal_cmd,
210 .cable_detect = pdc_sata_cable_detect,
211 .data_xfer = ata_data_xfer,
212 .irq_clear = pdc_irq_clear,
213 .irq_on = ata_irq_on,
215 .scr_read = pdc_sata_scr_read,
216 .scr_write = pdc_sata_scr_write,
217 .port_start = pdc_sata_port_start,
220 static const struct ata_port_operations pdc_pata_ops = {
221 .port_disable = ata_port_disable,
222 .tf_load = pdc_tf_load_mmio,
223 .tf_read = ata_tf_read,
224 .check_status = ata_check_status,
225 .exec_command = pdc_exec_command_mmio,
226 .dev_select = ata_std_dev_select,
227 .check_atapi_dma = pdc_check_atapi_dma,
229 .qc_prep = pdc_qc_prep,
230 .qc_issue = pdc_qc_issue_prot,
231 .freeze = pdc_freeze,
233 .error_handler = pdc_pata_error_handler,
234 .post_internal_cmd = pdc_post_internal_cmd,
235 .cable_detect = pdc_pata_cable_detect,
236 .data_xfer = ata_data_xfer,
237 .irq_clear = pdc_irq_clear,
238 .irq_on = ata_irq_on,
240 .port_start = pdc_common_port_start,
243 static const struct ata_port_info pdc_port_info[] = {
246 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
248 .pio_mask = 0x1f, /* pio0-4 */
249 .mwdma_mask = 0x07, /* mwdma0-2 */
250 .udma_mask = ATA_UDMA6,
251 .port_ops = &pdc_old_sata_ops,
254 /* board_2037x_pata */
256 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
257 .pio_mask = 0x1f, /* pio0-4 */
258 .mwdma_mask = 0x07, /* mwdma0-2 */
259 .udma_mask = ATA_UDMA6,
260 .port_ops = &pdc_pata_ops,
265 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
267 .pio_mask = 0x1f, /* pio0-4 */
268 .mwdma_mask = 0x07, /* mwdma0-2 */
269 .udma_mask = ATA_UDMA6,
270 .port_ops = &pdc_old_sata_ops,
275 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
277 .pio_mask = 0x1f, /* pio0-4 */
278 .mwdma_mask = 0x07, /* mwdma0-2 */
279 .udma_mask = ATA_UDMA6,
280 .port_ops = &pdc_pata_ops,
285 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
286 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
287 .pio_mask = 0x1f, /* pio0-4 */
288 .mwdma_mask = 0x07, /* mwdma0-2 */
289 .udma_mask = ATA_UDMA6,
290 .port_ops = &pdc_sata_ops,
293 /* board_2057x_pata */
295 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
297 .pio_mask = 0x1f, /* pio0-4 */
298 .mwdma_mask = 0x07, /* mwdma0-2 */
299 .udma_mask = ATA_UDMA6,
300 .port_ops = &pdc_pata_ops,
305 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
306 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
307 .pio_mask = 0x1f, /* pio0-4 */
308 .mwdma_mask = 0x07, /* mwdma0-2 */
309 .udma_mask = ATA_UDMA6,
310 .port_ops = &pdc_sata_ops,
314 static const struct pci_device_id pdc_ata_pci_tbl[] = {
315 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
316 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
317 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
318 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
319 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
320 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
321 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
322 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
323 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
324 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
326 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
327 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
328 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
329 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
330 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
331 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
333 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
335 { } /* terminate list */
338 static struct pci_driver pdc_ata_pci_driver = {
340 .id_table = pdc_ata_pci_tbl,
341 .probe = pdc_ata_init_one,
342 .remove = ata_pci_remove_one,
345 static int pdc_common_port_start(struct ata_port *ap)
347 struct device *dev = ap->host->dev;
348 struct pdc_port_priv *pp;
351 rc = ata_port_start(ap);
355 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
359 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
363 ap->private_data = pp;
368 static int pdc_sata_port_start(struct ata_port *ap)
372 rc = pdc_common_port_start(ap);
376 /* fix up PHYMODE4 align timing */
377 if (ap->flags & PDC_FLAG_GEN_II) {
378 void __iomem *mmio = ap->ioaddr.scr_addr;
381 tmp = readl(mmio + 0x014);
382 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
383 writel(tmp, mmio + 0x014);
389 static void pdc_reset_port(struct ata_port *ap)
391 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
395 for (i = 11; i > 0; i--) {
408 readl(mmio); /* flush */
411 static int pdc_pata_cable_detect(struct ata_port *ap)
414 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
418 return ATA_CBL_PATA40;
419 return ATA_CBL_PATA80;
422 static int pdc_sata_cable_detect(struct ata_port *ap)
427 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
429 if (sc_reg > SCR_CONTROL)
431 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
435 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
437 if (sc_reg > SCR_CONTROL)
439 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
443 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
445 struct ata_port *ap = qc->ap;
446 dma_addr_t sg_table = ap->prd_dma;
447 unsigned int cdb_len = qc->dev->cdb_len;
449 struct pdc_port_priv *pp = ap->private_data;
451 u32 *buf32 = (u32 *) buf;
452 unsigned int dev_sel, feature, nbytes;
454 /* set control bits (byte 0), zero delay seq id (byte 3),
455 * and seq id (byte 2)
457 switch (qc->tf.protocol) {
458 case ATA_PROT_ATAPI_DMA:
459 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
460 buf32[0] = cpu_to_le32(PDC_PKT_READ);
464 case ATA_PROT_ATAPI_NODATA:
465 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
471 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
472 buf32[2] = 0; /* no next-packet */
475 if (sata_scr_valid(&ap->link)) {
476 dev_sel = PDC_DEVICE_SATA;
478 dev_sel = ATA_DEVICE_OBS;
479 if (qc->dev->devno != 0)
482 buf[12] = (1 << 5) | ATA_REG_DEVICE;
484 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
485 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
487 buf[16] = (1 << 5) | ATA_REG_NSECT;
489 buf[18] = (1 << 5) | ATA_REG_LBAL;
492 /* set feature and byte counter registers */
493 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
494 feature = PDC_FEATURE_ATAPI_PIO;
495 /* set byte counter register to real transfer byte count */
500 feature = PDC_FEATURE_ATAPI_DMA;
501 /* set byte counter register to 0 */
504 buf[20] = (1 << 5) | ATA_REG_FEATURE;
506 buf[22] = (1 << 5) | ATA_REG_BYTEL;
507 buf[23] = nbytes & 0xFF;
508 buf[24] = (1 << 5) | ATA_REG_BYTEH;
509 buf[25] = (nbytes >> 8) & 0xFF;
511 /* send ATAPI packet command 0xA0 */
512 buf[26] = (1 << 5) | ATA_REG_CMD;
513 buf[27] = ATA_CMD_PACKET;
515 /* select drive and check DRQ */
516 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
519 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
520 BUG_ON(cdb_len & ~0x1E);
522 /* append the CDB as the final part */
523 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
524 memcpy(buf+31, cdb, cdb_len);
527 static void pdc_qc_prep(struct ata_queued_cmd *qc)
529 struct pdc_port_priv *pp = qc->ap->private_data;
534 switch (qc->tf.protocol) {
539 case ATA_PROT_NODATA:
540 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
541 qc->dev->devno, pp->pkt);
543 if (qc->tf.flags & ATA_TFLAG_LBA48)
544 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
546 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
548 pdc_pkt_footer(&qc->tf, pp->pkt, i);
555 case ATA_PROT_ATAPI_DMA:
558 case ATA_PROT_ATAPI_NODATA:
567 static void pdc_freeze(struct ata_port *ap)
569 void __iomem *mmio = ap->ioaddr.cmd_addr;
572 tmp = readl(mmio + PDC_CTLSTAT);
573 tmp |= PDC_IRQ_DISABLE;
574 tmp &= ~PDC_DMA_ENABLE;
575 writel(tmp, mmio + PDC_CTLSTAT);
576 readl(mmio + PDC_CTLSTAT); /* flush */
579 static void pdc_thaw(struct ata_port *ap)
581 void __iomem *mmio = ap->ioaddr.cmd_addr;
585 readl(mmio + PDC_INT_SEQMASK);
587 /* turn IRQ back on */
588 tmp = readl(mmio + PDC_CTLSTAT);
589 tmp &= ~PDC_IRQ_DISABLE;
590 writel(tmp, mmio + PDC_CTLSTAT);
591 readl(mmio + PDC_CTLSTAT); /* flush */
594 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
596 if (!(ap->pflags & ATA_PFLAG_FROZEN))
599 /* perform recovery */
600 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
604 static void pdc_pata_error_handler(struct ata_port *ap)
606 pdc_common_error_handler(ap, NULL);
609 static void pdc_sata_error_handler(struct ata_port *ap)
611 pdc_common_error_handler(ap, sata_std_hardreset);
614 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
616 struct ata_port *ap = qc->ap;
618 /* make DMA engine forget about the failed command */
619 if (qc->flags & ATA_QCFLAG_FAILED)
623 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
624 u32 port_status, u32 err_mask)
626 struct ata_eh_info *ehi = &ap->link.eh_info;
627 unsigned int ac_err_mask = 0;
629 ata_ehi_clear_desc(ehi);
630 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
631 port_status &= err_mask;
633 if (port_status & PDC_DRIVE_ERR)
634 ac_err_mask |= AC_ERR_DEV;
635 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
636 ac_err_mask |= AC_ERR_HSM;
637 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
638 ac_err_mask |= AC_ERR_ATA_BUS;
639 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
640 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
641 ac_err_mask |= AC_ERR_HOST_BUS;
643 if (sata_scr_valid(&ap->link)) {
646 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
647 ehi->serror |= serror;
650 qc->err_mask |= ac_err_mask;
657 static inline unsigned int pdc_host_intr(struct ata_port *ap,
658 struct ata_queued_cmd *qc)
660 unsigned int handled = 0;
661 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
662 u32 port_status, err_mask;
664 err_mask = PDC_ERR_MASK;
665 if (ap->flags & PDC_FLAG_GEN_II)
666 err_mask &= ~PDC1_ERR_MASK;
668 err_mask &= ~PDC2_ERR_MASK;
669 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
670 if (unlikely(port_status & err_mask)) {
671 pdc_error_intr(ap, qc, port_status, err_mask);
675 switch (qc->tf.protocol) {
677 case ATA_PROT_NODATA:
678 case ATA_PROT_ATAPI_DMA:
679 case ATA_PROT_ATAPI_NODATA:
680 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
686 ap->stats.idle_irq++;
693 static void pdc_irq_clear(struct ata_port *ap)
695 struct ata_host *host = ap->host;
696 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
698 readl(mmio + PDC_INT_SEQMASK);
701 static inline int pdc_is_sataii_tx4(unsigned long flags)
703 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
704 return (flags & mask) == mask;
707 static inline unsigned int pdc_port_no_to_ata_no(unsigned int port_no, int is_sataii_tx4)
709 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
710 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
713 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
715 struct ata_host *host = dev_instance;
719 unsigned int handled = 0;
720 void __iomem *mmio_base;
721 unsigned int hotplug_offset, ata_no;
727 if (!host || !host->iomap[PDC_MMIO_BAR]) {
728 VPRINTK("QUICK EXIT\n");
732 mmio_base = host->iomap[PDC_MMIO_BAR];
734 /* read and clear hotplug flags for all ports */
735 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
736 hotplug_offset = PDC2_SATA_PLUG_CSR;
738 hotplug_offset = PDC_SATA_PLUG_CSR;
739 hotplug_status = readl(mmio_base + hotplug_offset);
740 if (hotplug_status & 0xff)
741 writel(hotplug_status | 0xff, mmio_base + hotplug_offset);
742 hotplug_status &= 0xff; /* clear uninteresting bits */
744 /* reading should also clear interrupts */
745 mask = readl(mmio_base + PDC_INT_SEQMASK);
747 if (mask == 0xffffffff && hotplug_status == 0) {
748 VPRINTK("QUICK EXIT 2\n");
752 spin_lock(&host->lock);
754 mask &= 0xffff; /* only 16 tags possible */
755 if (mask == 0 && hotplug_status == 0) {
756 VPRINTK("QUICK EXIT 3\n");
760 writel(mask, mmio_base + PDC_INT_SEQMASK);
762 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
764 for (i = 0; i < host->n_ports; i++) {
765 VPRINTK("port %u\n", i);
768 /* check for a plug or unplug event */
769 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
770 tmp = hotplug_status & (0x11 << ata_no);
772 !(ap->flags & ATA_FLAG_DISABLED)) {
773 struct ata_eh_info *ehi = &ap->link.eh_info;
774 ata_ehi_clear_desc(ehi);
775 ata_ehi_hotplugged(ehi);
776 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
782 /* check for a packet interrupt */
783 tmp = mask & (1 << (i + 1));
785 !(ap->flags & ATA_FLAG_DISABLED)) {
786 struct ata_queued_cmd *qc;
788 qc = ata_qc_from_tag(ap, ap->link.active_tag);
789 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
790 handled += pdc_host_intr(ap, qc);
797 spin_unlock(&host->lock);
798 return IRQ_RETVAL(handled);
801 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
803 struct ata_port *ap = qc->ap;
804 struct pdc_port_priv *pp = ap->private_data;
805 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
806 unsigned int port_no = ap->port_no;
807 u8 seq = (u8) (port_no + 1);
809 VPRINTK("ENTER, ap %p\n", ap);
811 writel(0x00000001, mmio + (seq * 4));
812 readl(mmio + (seq * 4)); /* flush */
815 wmb(); /* flush PRD, pkt writes */
816 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
817 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
820 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
822 switch (qc->tf.protocol) {
823 case ATA_PROT_ATAPI_NODATA:
824 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
827 case ATA_PROT_NODATA:
828 if (qc->tf.flags & ATA_TFLAG_POLLING)
831 case ATA_PROT_ATAPI_DMA:
833 pdc_packet_start(qc);
840 return ata_qc_issue_prot(qc);
843 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
845 WARN_ON (tf->protocol == ATA_PROT_DMA ||
846 tf->protocol == ATA_PROT_ATAPI_DMA);
850 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
852 WARN_ON (tf->protocol == ATA_PROT_DMA ||
853 tf->protocol == ATA_PROT_ATAPI_DMA);
854 ata_exec_command(ap, tf);
857 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
859 u8 *scsicmd = qc->scsicmd->cmnd;
860 int pio = 1; /* atapi dma off by default */
862 /* Whitelist commands that may use DMA. */
863 switch (scsicmd[0]) {
870 case 0xad: /* READ_DVD_STRUCTURE */
871 case 0xbe: /* READ_CD */
874 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
875 if (scsicmd[0] == WRITE_10) {
877 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
878 if (lba >= 0xFFFF4FA2)
884 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
886 /* First generation chips cannot use ATAPI DMA on SATA ports */
890 static void pdc_ata_setup_port(struct ata_port *ap,
891 void __iomem *base, void __iomem *scr_addr)
893 ap->ioaddr.cmd_addr = base;
894 ap->ioaddr.data_addr = base;
895 ap->ioaddr.feature_addr =
896 ap->ioaddr.error_addr = base + 0x4;
897 ap->ioaddr.nsect_addr = base + 0x8;
898 ap->ioaddr.lbal_addr = base + 0xc;
899 ap->ioaddr.lbam_addr = base + 0x10;
900 ap->ioaddr.lbah_addr = base + 0x14;
901 ap->ioaddr.device_addr = base + 0x18;
902 ap->ioaddr.command_addr =
903 ap->ioaddr.status_addr = base + 0x1c;
904 ap->ioaddr.altstatus_addr =
905 ap->ioaddr.ctl_addr = base + 0x38;
906 ap->ioaddr.scr_addr = scr_addr;
909 static void pdc_host_init(struct ata_host *host)
911 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
912 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
917 hotplug_offset = PDC2_SATA_PLUG_CSR;
919 hotplug_offset = PDC_SATA_PLUG_CSR;
922 * Except for the hotplug stuff, this is voodoo from the
923 * Promise driver. Label this entire section
924 * "TODO: figure out why we do this"
927 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
928 tmp = readl(mmio + PDC_FLASH_CTL);
929 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
931 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
932 writel(tmp, mmio + PDC_FLASH_CTL);
934 /* clear plug/unplug flags for all ports */
935 tmp = readl(mmio + hotplug_offset);
936 writel(tmp | 0xff, mmio + hotplug_offset);
938 /* unmask plug/unplug ints */
939 tmp = readl(mmio + hotplug_offset);
940 writel(tmp & ~0xff0000, mmio + hotplug_offset);
942 /* don't initialise TBG or SLEW on 2nd generation chips */
946 /* reduce TBG clock to 133 Mhz. */
947 tmp = readl(mmio + PDC_TBG_MODE);
948 tmp &= ~0x30000; /* clear bit 17, 16*/
949 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
950 writel(tmp, mmio + PDC_TBG_MODE);
952 readl(mmio + PDC_TBG_MODE); /* flush */
955 /* adjust slew rate control register. */
956 tmp = readl(mmio + PDC_SLEW_CTL);
957 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
958 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
959 writel(tmp, mmio + PDC_SLEW_CTL);
962 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
964 static int printed_version;
965 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
966 const struct ata_port_info *ppi[PDC_MAX_PORTS];
967 struct ata_host *host;
972 if (!printed_version++)
973 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
975 /* enable and acquire resources */
976 rc = pcim_enable_device(pdev);
980 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
982 pcim_pin_device(pdev);
985 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
987 /* determine port configuration and setup host */
989 if (pi->flags & PDC_FLAG_4_PORTS)
991 for (i = 0; i < n_ports; i++)
994 if (pi->flags & PDC_FLAG_SATA_PATA) {
995 u8 tmp = readb(base + PDC_FLASH_CTL+1);
997 ppi[n_ports++] = pi + 1;
1000 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1002 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1005 host->iomap = pcim_iomap_table(pdev);
1007 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1008 for (i = 0; i < host->n_ports; i++) {
1009 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1010 pdc_ata_setup_port(host->ports[i],
1011 base + 0x200 + ata_no * 0x80,
1012 base + 0x400 + ata_no * 0x100);
1015 /* initialize adapter */
1016 pdc_host_init(host);
1018 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1021 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1025 /* start host, request IRQ and attach */
1026 pci_set_master(pdev);
1027 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1031 static int __init pdc_ata_init(void)
1033 return pci_register_driver(&pdc_ata_pci_driver);
1036 static void __exit pdc_ata_exit(void)
1038 pci_unregister_driver(&pdc_ata_pci_driver);
1041 MODULE_AUTHOR("Jeff Garzik");
1042 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1043 MODULE_LICENSE("GPL");
1044 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1045 MODULE_VERSION(DRV_VERSION);
1047 module_init(pdc_ata_init);
1048 module_exit(pdc_ata_exit);