2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * --> Errata workaround for NCQ device errors.
30 * --> More errata workarounds for PCI-X.
32 * --> Complete a full errata audit for all chipsets to identify others.
34 * --> Develop a low-power-consumption strategy, and implement it.
36 * --> [Experiment, low priority] Investigate interrupt coalescing.
37 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
38 * the overhead reduced by interrupt mitigation is quite often not
39 * worth the latency cost.
41 * --> [Experiment, Marvell value added] Is it possible to use target
42 * mode to cross-connect two Linux boxes with Marvell cards? If so,
43 * creating LibATA target mode support would be very interesting.
45 * Target mode, for those without docs, is the ability to directly
46 * connect two SATA ports.
49 #include <linux/kernel.h>
50 #include <linux/module.h>
51 #include <linux/pci.h>
52 #include <linux/init.h>
53 #include <linux/blkdev.h>
54 #include <linux/delay.h>
55 #include <linux/interrupt.h>
56 #include <linux/dmapool.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/device.h>
59 #include <linux/platform_device.h>
60 #include <linux/ata_platform.h>
61 #include <linux/mbus.h>
62 #include <linux/bitops.h>
63 #include <scsi/scsi_host.h>
64 #include <scsi/scsi_cmnd.h>
65 #include <scsi/scsi_device.h>
66 #include <linux/libata.h>
68 #define DRV_NAME "sata_mv"
69 #define DRV_VERSION "1.26"
72 /* BAR's are enumerated in terms of pci_resource_start() terms */
73 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
74 MV_IO_BAR = 2, /* offset 0x18: IO space */
75 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
77 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
78 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
81 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
82 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
83 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
84 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
85 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
86 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
88 MV_SATAHC0_REG_BASE = 0x20000,
89 MV_FLASH_CTL_OFS = 0x1046c,
90 MV_GPIO_PORT_CTL_OFS = 0x104f0,
91 MV_RESET_CFG_OFS = 0x180d8,
93 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
94 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
95 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
96 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
99 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
101 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
102 * CRPB needs alignment on a 256B boundary. Size == 256B
103 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
105 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
106 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
108 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
110 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
111 MV_PORT_HC_SHIFT = 2,
112 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
113 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
114 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
117 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
118 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
120 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
121 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
123 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
125 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | MV_FLAG_IRQ_COALESCE |
126 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
129 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
131 CRQB_FLAG_READ = (1 << 0),
133 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
134 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
135 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
136 CRQB_CMD_ADDR_SHIFT = 8,
137 CRQB_CMD_CS = (0x2 << 11),
138 CRQB_CMD_LAST = (1 << 15),
140 CRPB_FLAG_STATUS_SHIFT = 8,
141 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
142 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
144 EPRD_FLAG_END_OF_TBL = (1 << 31),
146 /* PCI interface registers */
148 PCI_COMMAND_OFS = 0xc00,
149 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
151 PCI_MAIN_CMD_STS_OFS = 0xd30,
152 STOP_PCI_MASTER = (1 << 2),
153 PCI_MASTER_EMPTY = (1 << 3),
154 GLOB_SFT_RST = (1 << 4),
156 MV_PCI_MODE_OFS = 0xd00,
157 MV_PCI_MODE_MASK = 0x30,
159 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
160 MV_PCI_DISC_TIMER = 0xd04,
161 MV_PCI_MSI_TRIGGER = 0xc38,
162 MV_PCI_SERR_MASK = 0xc28,
163 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
164 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
165 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
166 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
167 MV_PCI_ERR_COMMAND = 0x1d50,
169 PCI_IRQ_CAUSE_OFS = 0x1d58,
170 PCI_IRQ_MASK_OFS = 0x1d5c,
171 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
173 PCIE_IRQ_CAUSE_OFS = 0x1900,
174 PCIE_IRQ_MASK_OFS = 0x1910,
175 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
177 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
178 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
179 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
180 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
181 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
182 ERR_IRQ = (1 << 0), /* shift by port # */
183 DONE_IRQ = (1 << 1), /* shift by port # */
184 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
185 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
187 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
188 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
189 PORTS_0_3_COAL_DONE = (1 << 8),
190 PORTS_4_7_COAL_DONE = (1 << 17),
191 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
192 GPIO_INT = (1 << 22),
193 SELF_INT = (1 << 23),
194 TWSI_INT = (1 << 24),
195 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
196 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
197 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
199 /* SATAHC registers */
202 HC_IRQ_CAUSE_OFS = 0x14,
203 DMA_IRQ = (1 << 0), /* shift by port # */
204 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
205 DEV_IRQ = (1 << 8), /* shift by port # */
207 /* Shadow block registers */
209 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
212 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
213 SATA_ACTIVE_OFS = 0x350,
214 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
215 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
218 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
222 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
223 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
224 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
225 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
228 SATA_IFCTL_OFS = 0x344,
229 SATA_TESTCTL_OFS = 0x348,
230 SATA_IFSTAT_OFS = 0x34c,
231 VENDOR_UNIQUE_FIS_OFS = 0x35c,
234 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
235 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
238 MV5_LTMODE_OFS = 0x30,
239 MV5_PHY_CTL_OFS = 0x0C,
240 SATA_INTERFACE_CFG_OFS = 0x050,
242 MV_M2_PREAMP_MASK = 0x7e0,
246 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
247 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
248 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
249 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
250 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
251 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
252 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
254 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
255 EDMA_ERR_IRQ_MASK_OFS = 0xc,
256 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
257 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
258 EDMA_ERR_DEV = (1 << 2), /* device error */
259 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
260 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
261 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
262 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
263 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
264 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
265 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
266 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
267 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
268 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
269 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
271 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
272 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
273 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
274 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
275 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
277 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
279 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
280 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
281 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
282 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
283 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
284 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
286 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
288 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
289 EDMA_ERR_OVERRUN_5 = (1 << 5),
290 EDMA_ERR_UNDERRUN_5 = (1 << 6),
292 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
293 EDMA_ERR_LNK_CTRL_RX_1 |
294 EDMA_ERR_LNK_CTRL_RX_3 |
295 EDMA_ERR_LNK_CTRL_TX,
297 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
307 EDMA_ERR_LNK_CTRL_RX_2 |
308 EDMA_ERR_LNK_DATA_RX |
309 EDMA_ERR_LNK_DATA_TX |
310 EDMA_ERR_TRANS_PROTO,
312 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
317 EDMA_ERR_UNDERRUN_5 |
318 EDMA_ERR_SELF_DIS_5 |
324 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
325 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
327 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
328 EDMA_REQ_Q_PTR_SHIFT = 5,
330 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
331 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
332 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
333 EDMA_RSP_Q_PTR_SHIFT = 3,
335 EDMA_CMD_OFS = 0x28, /* EDMA command register */
336 EDMA_EN = (1 << 0), /* enable EDMA */
337 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
338 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
340 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
341 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
342 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
344 EDMA_IORDY_TMOUT_OFS = 0x34,
345 EDMA_ARB_CFG_OFS = 0x38,
347 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
348 EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */
350 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
351 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
352 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
353 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
355 /* Host private flags (hp_flags) */
356 MV_HP_FLAG_MSI = (1 << 0),
357 MV_HP_ERRATA_50XXB0 = (1 << 1),
358 MV_HP_ERRATA_50XXB2 = (1 << 2),
359 MV_HP_ERRATA_60X1B2 = (1 << 3),
360 MV_HP_ERRATA_60X1C0 = (1 << 4),
361 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
362 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
363 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
364 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
365 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
366 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
368 /* Port private flags (pp_flags) */
369 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
370 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
371 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
372 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
375 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
376 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
377 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
378 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
379 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
381 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
382 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
385 /* DMA boundary 0xffff is required by the s/g splitting
386 * we need on /length/ in mv_fill-sg().
388 MV_DMA_BOUNDARY = 0xffffU,
390 /* mask of register bits containing lower 32 bits
391 * of EDMA request queue DMA address
393 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
395 /* ditto, for response queue */
396 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
410 /* Command ReQuest Block: 32B */
426 /* Command ResPonse Block: 8B */
433 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
442 * We keep a local cache of a few frequently accessed port
443 * registers here, to avoid having to read them (very slow)
444 * when switching between EDMA and non-EDMA modes.
446 struct mv_cached_regs {
453 struct mv_port_priv {
454 struct mv_crqb *crqb;
456 struct mv_crpb *crpb;
458 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
459 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
461 unsigned int req_idx;
462 unsigned int resp_idx;
465 struct mv_cached_regs cached;
466 unsigned int delayed_eh_pmp_map;
469 struct mv_port_signal {
474 struct mv_host_priv {
477 struct mv_port_signal signal[8];
478 const struct mv_hw_ops *ops;
481 void __iomem *main_irq_cause_addr;
482 void __iomem *main_irq_mask_addr;
487 * These consistent DMA memory pools give us guaranteed
488 * alignment for hardware-accessed data structures,
489 * and less memory waste in accomplishing the alignment.
491 struct dma_pool *crqb_pool;
492 struct dma_pool *crpb_pool;
493 struct dma_pool *sg_tbl_pool;
497 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
499 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
500 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
502 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
504 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
505 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
508 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
509 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
510 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
511 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
512 static int mv_port_start(struct ata_port *ap);
513 static void mv_port_stop(struct ata_port *ap);
514 static int mv_qc_defer(struct ata_queued_cmd *qc);
515 static void mv_qc_prep(struct ata_queued_cmd *qc);
516 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
517 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
518 static int mv_hardreset(struct ata_link *link, unsigned int *class,
519 unsigned long deadline);
520 static void mv_eh_freeze(struct ata_port *ap);
521 static void mv_eh_thaw(struct ata_port *ap);
522 static void mv6_dev_config(struct ata_device *dev);
524 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
526 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
527 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
529 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
531 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
532 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
534 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
536 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
537 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
539 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
541 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
542 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
544 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
546 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
547 void __iomem *mmio, unsigned int n_hc);
548 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
550 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
551 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
552 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
553 unsigned int port_no);
554 static int mv_stop_edma(struct ata_port *ap);
555 static int mv_stop_edma_engine(void __iomem *port_mmio);
556 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
558 static void mv_pmp_select(struct ata_port *ap, int pmp);
559 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
560 unsigned long deadline);
561 static int mv_softreset(struct ata_link *link, unsigned int *class,
562 unsigned long deadline);
563 static void mv_pmp_error_handler(struct ata_port *ap);
564 static void mv_process_crpb_entries(struct ata_port *ap,
565 struct mv_port_priv *pp);
567 static void mv_sff_irq_clear(struct ata_port *ap);
568 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
569 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
570 static void mv_bmdma_start(struct ata_queued_cmd *qc);
571 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
572 static u8 mv_bmdma_status(struct ata_port *ap);
574 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
575 * because we have to allow room for worst case splitting of
576 * PRDs for 64K boundaries in mv_fill_sg().
578 static struct scsi_host_template mv5_sht = {
579 ATA_BASE_SHT(DRV_NAME),
580 .sg_tablesize = MV_MAX_SG_CT / 2,
581 .dma_boundary = MV_DMA_BOUNDARY,
584 static struct scsi_host_template mv6_sht = {
585 ATA_NCQ_SHT(DRV_NAME),
586 .can_queue = MV_MAX_Q_DEPTH - 1,
587 .sg_tablesize = MV_MAX_SG_CT / 2,
588 .dma_boundary = MV_DMA_BOUNDARY,
591 static struct ata_port_operations mv5_ops = {
592 .inherits = &ata_sff_port_ops,
594 .qc_defer = mv_qc_defer,
595 .qc_prep = mv_qc_prep,
596 .qc_issue = mv_qc_issue,
598 .freeze = mv_eh_freeze,
600 .hardreset = mv_hardreset,
601 .error_handler = ata_std_error_handler, /* avoid SFF EH */
602 .post_internal_cmd = ATA_OP_NULL,
604 .scr_read = mv5_scr_read,
605 .scr_write = mv5_scr_write,
607 .port_start = mv_port_start,
608 .port_stop = mv_port_stop,
611 static struct ata_port_operations mv6_ops = {
612 .inherits = &mv5_ops,
613 .dev_config = mv6_dev_config,
614 .scr_read = mv_scr_read,
615 .scr_write = mv_scr_write,
617 .pmp_hardreset = mv_pmp_hardreset,
618 .pmp_softreset = mv_softreset,
619 .softreset = mv_softreset,
620 .error_handler = mv_pmp_error_handler,
622 .sff_irq_clear = mv_sff_irq_clear,
623 .check_atapi_dma = mv_check_atapi_dma,
624 .bmdma_setup = mv_bmdma_setup,
625 .bmdma_start = mv_bmdma_start,
626 .bmdma_stop = mv_bmdma_stop,
627 .bmdma_status = mv_bmdma_status,
630 static struct ata_port_operations mv_iie_ops = {
631 .inherits = &mv6_ops,
632 .dev_config = ATA_OP_NULL,
633 .qc_prep = mv_qc_prep_iie,
636 static const struct ata_port_info mv_port_info[] = {
638 .flags = MV_GEN_I_FLAGS,
639 .pio_mask = 0x1f, /* pio0-4 */
640 .udma_mask = ATA_UDMA6,
641 .port_ops = &mv5_ops,
644 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
645 .pio_mask = 0x1f, /* pio0-4 */
646 .udma_mask = ATA_UDMA6,
647 .port_ops = &mv5_ops,
650 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
651 .pio_mask = 0x1f, /* pio0-4 */
652 .udma_mask = ATA_UDMA6,
653 .port_ops = &mv5_ops,
656 .flags = MV_GEN_II_FLAGS,
657 .pio_mask = 0x1f, /* pio0-4 */
658 .udma_mask = ATA_UDMA6,
659 .port_ops = &mv6_ops,
662 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
663 .pio_mask = 0x1f, /* pio0-4 */
664 .udma_mask = ATA_UDMA6,
665 .port_ops = &mv6_ops,
668 .flags = MV_GEN_IIE_FLAGS,
669 .pio_mask = 0x1f, /* pio0-4 */
670 .udma_mask = ATA_UDMA6,
671 .port_ops = &mv_iie_ops,
674 .flags = MV_GEN_IIE_FLAGS,
675 .pio_mask = 0x1f, /* pio0-4 */
676 .udma_mask = ATA_UDMA6,
677 .port_ops = &mv_iie_ops,
680 .flags = MV_GEN_IIE_FLAGS,
681 .pio_mask = 0x1f, /* pio0-4 */
682 .udma_mask = ATA_UDMA6,
683 .port_ops = &mv_iie_ops,
687 static const struct pci_device_id mv_pci_tbl[] = {
688 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
689 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
690 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
691 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
692 /* RocketRAID 1720/174x have different identifiers */
693 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
694 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
695 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
697 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
698 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
699 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
700 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
701 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
703 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
706 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
708 /* Marvell 7042 support */
709 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
711 /* Highpoint RocketRAID PCIe series */
712 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
713 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
715 { } /* terminate list */
718 static const struct mv_hw_ops mv5xxx_ops = {
719 .phy_errata = mv5_phy_errata,
720 .enable_leds = mv5_enable_leds,
721 .read_preamp = mv5_read_preamp,
722 .reset_hc = mv5_reset_hc,
723 .reset_flash = mv5_reset_flash,
724 .reset_bus = mv5_reset_bus,
727 static const struct mv_hw_ops mv6xxx_ops = {
728 .phy_errata = mv6_phy_errata,
729 .enable_leds = mv6_enable_leds,
730 .read_preamp = mv6_read_preamp,
731 .reset_hc = mv6_reset_hc,
732 .reset_flash = mv6_reset_flash,
733 .reset_bus = mv_reset_pci_bus,
736 static const struct mv_hw_ops mv_soc_ops = {
737 .phy_errata = mv6_phy_errata,
738 .enable_leds = mv_soc_enable_leds,
739 .read_preamp = mv_soc_read_preamp,
740 .reset_hc = mv_soc_reset_hc,
741 .reset_flash = mv_soc_reset_flash,
742 .reset_bus = mv_soc_reset_bus,
749 static inline void writelfl(unsigned long data, void __iomem *addr)
752 (void) readl(addr); /* flush to avoid PCI posted write */
755 static inline unsigned int mv_hc_from_port(unsigned int port)
757 return port >> MV_PORT_HC_SHIFT;
760 static inline unsigned int mv_hardport_from_port(unsigned int port)
762 return port & MV_PORT_MASK;
766 * Consolidate some rather tricky bit shift calculations.
767 * This is hot-path stuff, so not a function.
768 * Simple code, with two return values, so macro rather than inline.
770 * port is the sole input, in range 0..7.
771 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
772 * hardport is the other output, in range 0..3.
774 * Note that port and hardport may be the same variable in some cases.
776 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
778 shift = mv_hc_from_port(port) * HC_SHIFT; \
779 hardport = mv_hardport_from_port(port); \
780 shift += hardport * 2; \
783 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
785 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
788 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
791 return mv_hc_base(base, mv_hc_from_port(port));
794 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
796 return mv_hc_base_from_port(base, port) +
797 MV_SATAHC_ARBTR_REG_SZ +
798 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
801 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
803 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
804 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
806 return hc_mmio + ofs;
809 static inline void __iomem *mv_host_base(struct ata_host *host)
811 struct mv_host_priv *hpriv = host->private_data;
815 static inline void __iomem *mv_ap_base(struct ata_port *ap)
817 return mv_port_base(mv_host_base(ap->host), ap->port_no);
820 static inline int mv_get_hc_count(unsigned long port_flags)
822 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
826 * mv_save_cached_regs - (re-)initialize cached port registers
827 * @ap: the port whose registers we are caching
829 * Initialize the local cache of port registers,
830 * so that reading them over and over again can
831 * be avoided on the hotter paths of this driver.
832 * This saves a few microseconds each time we switch
833 * to/from EDMA mode to perform (eg.) a drive cache flush.
835 static void mv_save_cached_regs(struct ata_port *ap)
837 void __iomem *port_mmio = mv_ap_base(ap);
838 struct mv_port_priv *pp = ap->private_data;
840 pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS);
841 pp->cached.ltmode = readl(port_mmio + LTMODE_OFS);
842 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
843 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS);
847 * mv_write_cached_reg - write to a cached port register
848 * @addr: hardware address of the register
849 * @old: pointer to cached value of the register
850 * @new: new value for the register
852 * Write a new value to a cached register,
853 * but only if the value is different from before.
855 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
863 static void mv_set_edma_ptrs(void __iomem *port_mmio,
864 struct mv_host_priv *hpriv,
865 struct mv_port_priv *pp)
870 * initialize request queue
872 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
873 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
875 WARN_ON(pp->crqb_dma & 0x3ff);
876 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
877 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
878 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
879 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
882 * initialize response queue
884 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
885 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
887 WARN_ON(pp->crpb_dma & 0xff);
888 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
889 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
890 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
891 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
894 static void mv_set_main_irq_mask(struct ata_host *host,
895 u32 disable_bits, u32 enable_bits)
897 struct mv_host_priv *hpriv = host->private_data;
898 u32 old_mask, new_mask;
900 old_mask = hpriv->main_irq_mask;
901 new_mask = (old_mask & ~disable_bits) | enable_bits;
902 if (new_mask != old_mask) {
903 hpriv->main_irq_mask = new_mask;
904 writelfl(new_mask, hpriv->main_irq_mask_addr);
908 static void mv_enable_port_irqs(struct ata_port *ap,
909 unsigned int port_bits)
911 unsigned int shift, hardport, port = ap->port_no;
912 u32 disable_bits, enable_bits;
914 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
916 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
917 enable_bits = port_bits << shift;
918 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
921 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
922 void __iomem *port_mmio,
923 unsigned int port_irqs)
925 struct mv_host_priv *hpriv = ap->host->private_data;
926 int hardport = mv_hardport_from_port(ap->port_no);
927 void __iomem *hc_mmio = mv_hc_base_from_port(
928 mv_host_base(ap->host), ap->port_no);
931 /* clear EDMA event indicators, if any */
932 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
934 /* clear pending irq events */
935 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
936 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
938 /* clear FIS IRQ Cause */
939 if (IS_GEN_IIE(hpriv))
940 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
942 mv_enable_port_irqs(ap, port_irqs);
946 * mv_start_edma - Enable eDMA engine
947 * @base: port base address
948 * @pp: port private data
950 * Verify the local cache of the eDMA state is accurate with a
954 * Inherited from caller.
956 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
957 struct mv_port_priv *pp, u8 protocol)
959 int want_ncq = (protocol == ATA_PROT_NCQ);
961 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
962 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
963 if (want_ncq != using_ncq)
966 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
967 struct mv_host_priv *hpriv = ap->host->private_data;
969 mv_edma_cfg(ap, want_ncq, 1);
971 mv_set_edma_ptrs(port_mmio, hpriv, pp);
972 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
974 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
975 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
979 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
981 void __iomem *port_mmio = mv_ap_base(ap);
982 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
983 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
987 * Wait for the EDMA engine to finish transactions in progress.
988 * No idea what a good "timeout" value might be, but measurements
989 * indicate that it often requires hundreds of microseconds
990 * with two drives in-use. So we use the 15msec value above
991 * as a rough guess at what even more drives might require.
993 for (i = 0; i < timeout; ++i) {
994 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
995 if ((edma_stat & empty_idle) == empty_idle)
999 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1003 * mv_stop_edma_engine - Disable eDMA engine
1004 * @port_mmio: io base address
1007 * Inherited from caller.
1009 static int mv_stop_edma_engine(void __iomem *port_mmio)
1013 /* Disable eDMA. The disable bit auto clears. */
1014 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1016 /* Wait for the chip to confirm eDMA is off. */
1017 for (i = 10000; i > 0; i--) {
1018 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
1019 if (!(reg & EDMA_EN))
1026 static int mv_stop_edma(struct ata_port *ap)
1028 void __iomem *port_mmio = mv_ap_base(ap);
1029 struct mv_port_priv *pp = ap->private_data;
1032 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1034 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1035 mv_wait_for_edma_empty_idle(ap);
1036 if (mv_stop_edma_engine(port_mmio)) {
1037 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1040 mv_edma_cfg(ap, 0, 0);
1045 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1048 for (b = 0; b < bytes; ) {
1049 DPRINTK("%p: ", start + b);
1050 for (w = 0; b < bytes && w < 4; w++) {
1051 printk("%08x ", readl(start + b));
1059 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1064 for (b = 0; b < bytes; ) {
1065 DPRINTK("%02x: ", b);
1066 for (w = 0; b < bytes && w < 4; w++) {
1067 (void) pci_read_config_dword(pdev, b, &dw);
1068 printk("%08x ", dw);
1075 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1076 struct pci_dev *pdev)
1079 void __iomem *hc_base = mv_hc_base(mmio_base,
1080 port >> MV_PORT_HC_SHIFT);
1081 void __iomem *port_base;
1082 int start_port, num_ports, p, start_hc, num_hcs, hc;
1085 start_hc = start_port = 0;
1086 num_ports = 8; /* shld be benign for 4 port devs */
1089 start_hc = port >> MV_PORT_HC_SHIFT;
1091 num_ports = num_hcs = 1;
1093 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1094 num_ports > 1 ? num_ports - 1 : start_port);
1097 DPRINTK("PCI config space regs:\n");
1098 mv_dump_pci_cfg(pdev, 0x68);
1100 DPRINTK("PCI regs:\n");
1101 mv_dump_mem(mmio_base+0xc00, 0x3c);
1102 mv_dump_mem(mmio_base+0xd00, 0x34);
1103 mv_dump_mem(mmio_base+0xf00, 0x4);
1104 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1105 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1106 hc_base = mv_hc_base(mmio_base, hc);
1107 DPRINTK("HC regs (HC %i):\n", hc);
1108 mv_dump_mem(hc_base, 0x1c);
1110 for (p = start_port; p < start_port + num_ports; p++) {
1111 port_base = mv_port_base(mmio_base, p);
1112 DPRINTK("EDMA regs (port %i):\n", p);
1113 mv_dump_mem(port_base, 0x54);
1114 DPRINTK("SATA regs (port %i):\n", p);
1115 mv_dump_mem(port_base+0x300, 0x60);
1120 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1124 switch (sc_reg_in) {
1128 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1131 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1140 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1142 unsigned int ofs = mv_scr_offset(sc_reg_in);
1144 if (ofs != 0xffffffffU) {
1145 *val = readl(mv_ap_base(link->ap) + ofs);
1151 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1153 unsigned int ofs = mv_scr_offset(sc_reg_in);
1155 if (ofs != 0xffffffffU) {
1156 writelfl(val, mv_ap_base(link->ap) + ofs);
1162 static void mv6_dev_config(struct ata_device *adev)
1165 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1167 * Gen-II does not support NCQ over a port multiplier
1168 * (no FIS-based switching).
1170 if (adev->flags & ATA_DFLAG_NCQ) {
1171 if (sata_pmp_attached(adev->link->ap)) {
1172 adev->flags &= ~ATA_DFLAG_NCQ;
1173 ata_dev_printk(adev, KERN_INFO,
1174 "NCQ disabled for command-based switching\n");
1179 static int mv_qc_defer(struct ata_queued_cmd *qc)
1181 struct ata_link *link = qc->dev->link;
1182 struct ata_port *ap = link->ap;
1183 struct mv_port_priv *pp = ap->private_data;
1186 * Don't allow new commands if we're in a delayed EH state
1187 * for NCQ and/or FIS-based switching.
1189 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1190 return ATA_DEFER_PORT;
1192 * If the port is completely idle, then allow the new qc.
1194 if (ap->nr_active_links == 0)
1198 * The port is operating in host queuing mode (EDMA) with NCQ
1199 * enabled, allow multiple NCQ commands. EDMA also allows
1200 * queueing multiple DMA commands but libata core currently
1203 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1204 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1207 return ATA_DEFER_PORT;
1210 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1212 struct mv_port_priv *pp = ap->private_data;
1213 void __iomem *port_mmio;
1215 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1216 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1217 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1219 ltmode = *old_ltmode & ~LTMODE_BIT8;
1220 haltcond = *old_haltcond | EDMA_ERR_DEV;
1223 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1224 ltmode = *old_ltmode | LTMODE_BIT8;
1226 haltcond &= ~EDMA_ERR_DEV;
1228 fiscfg |= FISCFG_WAIT_DEV_ERR;
1230 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1233 port_mmio = mv_ap_base(ap);
1234 mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg);
1235 mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode);
1236 mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond);
1239 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1241 struct mv_host_priv *hpriv = ap->host->private_data;
1244 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1245 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1247 new = old | (1 << 22);
1249 new = old & ~(1 << 22);
1251 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1255 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1256 * @ap: Port being initialized
1258 * There are two DMA modes on these chips: basic DMA, and EDMA.
1260 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1261 * of basic DMA on the GEN_IIE versions of the chips.
1263 * This bit survives EDMA resets, and must be set for basic DMA
1264 * to function, and should be cleared when EDMA is active.
1266 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1268 struct mv_port_priv *pp = ap->private_data;
1269 u32 new, *old = &pp->cached.unknown_rsvd;
1275 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new);
1278 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1281 struct mv_port_priv *pp = ap->private_data;
1282 struct mv_host_priv *hpriv = ap->host->private_data;
1283 void __iomem *port_mmio = mv_ap_base(ap);
1285 /* set up non-NCQ EDMA configuration */
1286 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1287 pp->pp_flags &= ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN);
1289 if (IS_GEN_I(hpriv))
1290 cfg |= (1 << 8); /* enab config burst size mask */
1292 else if (IS_GEN_II(hpriv)) {
1293 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1294 mv_60x1_errata_sata25(ap, want_ncq);
1296 } else if (IS_GEN_IIE(hpriv)) {
1297 int want_fbs = sata_pmp_attached(ap);
1299 * Possible future enhancement:
1301 * The chip can use FBS with non-NCQ, if we allow it,
1302 * But first we need to have the error handling in place
1303 * for this mode (datasheet section 7.3.15.4.2.3).
1304 * So disallow non-NCQ FBS for now.
1306 want_fbs &= want_ncq;
1308 mv_config_fbs(ap, want_ncq, want_fbs);
1311 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1312 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1315 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1317 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1319 cfg |= (1 << 18); /* enab early completion */
1321 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1322 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1323 mv_bmdma_enable_iie(ap, !want_edma);
1327 cfg |= EDMA_CFG_NCQ;
1328 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1331 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1334 static void mv_port_free_dma_mem(struct ata_port *ap)
1336 struct mv_host_priv *hpriv = ap->host->private_data;
1337 struct mv_port_priv *pp = ap->private_data;
1341 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1345 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1349 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1350 * For later hardware, we have one unique sg_tbl per NCQ tag.
1352 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1353 if (pp->sg_tbl[tag]) {
1354 if (tag == 0 || !IS_GEN_I(hpriv))
1355 dma_pool_free(hpriv->sg_tbl_pool,
1357 pp->sg_tbl_dma[tag]);
1358 pp->sg_tbl[tag] = NULL;
1364 * mv_port_start - Port specific init/start routine.
1365 * @ap: ATA channel to manipulate
1367 * Allocate and point to DMA memory, init port private memory,
1371 * Inherited from caller.
1373 static int mv_port_start(struct ata_port *ap)
1375 struct device *dev = ap->host->dev;
1376 struct mv_host_priv *hpriv = ap->host->private_data;
1377 struct mv_port_priv *pp;
1380 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1383 ap->private_data = pp;
1385 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1388 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1390 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1392 goto out_port_free_dma_mem;
1393 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1395 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1396 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1397 ap->flags |= ATA_FLAG_AN;
1399 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1400 * For later hardware, we need one unique sg_tbl per NCQ tag.
1402 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1403 if (tag == 0 || !IS_GEN_I(hpriv)) {
1404 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1405 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1406 if (!pp->sg_tbl[tag])
1407 goto out_port_free_dma_mem;
1409 pp->sg_tbl[tag] = pp->sg_tbl[0];
1410 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1413 mv_save_cached_regs(ap);
1414 mv_edma_cfg(ap, 0, 0);
1417 out_port_free_dma_mem:
1418 mv_port_free_dma_mem(ap);
1423 * mv_port_stop - Port specific cleanup/stop routine.
1424 * @ap: ATA channel to manipulate
1426 * Stop DMA, cleanup port memory.
1429 * This routine uses the host lock to protect the DMA stop.
1431 static void mv_port_stop(struct ata_port *ap)
1434 mv_enable_port_irqs(ap, 0);
1435 mv_port_free_dma_mem(ap);
1439 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1440 * @qc: queued command whose SG list to source from
1442 * Populate the SG list and mark the last entry.
1445 * Inherited from caller.
1447 static void mv_fill_sg(struct ata_queued_cmd *qc)
1449 struct mv_port_priv *pp = qc->ap->private_data;
1450 struct scatterlist *sg;
1451 struct mv_sg *mv_sg, *last_sg = NULL;
1454 mv_sg = pp->sg_tbl[qc->tag];
1455 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1456 dma_addr_t addr = sg_dma_address(sg);
1457 u32 sg_len = sg_dma_len(sg);
1460 u32 offset = addr & 0xffff;
1463 if (offset + len > 0x10000)
1464 len = 0x10000 - offset;
1466 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1467 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1468 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1469 mv_sg->reserved = 0;
1479 if (likely(last_sg))
1480 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1481 mb(); /* ensure data structure is visible to the chipset */
1484 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1486 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1487 (last ? CRQB_CMD_LAST : 0);
1488 *cmdw = cpu_to_le16(tmp);
1492 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1493 * @ap: Port associated with this ATA transaction.
1495 * We need this only for ATAPI bmdma transactions,
1496 * as otherwise we experience spurious interrupts
1497 * after libata-sff handles the bmdma interrupts.
1499 static void mv_sff_irq_clear(struct ata_port *ap)
1501 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1505 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1506 * @qc: queued command to check for chipset/DMA compatibility.
1508 * The bmdma engines cannot handle speculative data sizes
1509 * (bytecount under/over flow). So only allow DMA for
1510 * data transfer commands with known data sizes.
1513 * Inherited from caller.
1515 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1517 struct scsi_cmnd *scmd = qc->scsicmd;
1520 switch (scmd->cmnd[0]) {
1528 case GPCMD_SEND_DVD_STRUCTURE:
1529 case GPCMD_SEND_CUE_SHEET:
1530 return 0; /* DMA is safe */
1533 return -EOPNOTSUPP; /* use PIO instead */
1537 * mv_bmdma_setup - Set up BMDMA transaction
1538 * @qc: queued command to prepare DMA for.
1541 * Inherited from caller.
1543 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1545 struct ata_port *ap = qc->ap;
1546 void __iomem *port_mmio = mv_ap_base(ap);
1547 struct mv_port_priv *pp = ap->private_data;
1551 /* clear all DMA cmd bits */
1552 writel(0, port_mmio + BMDMA_CMD_OFS);
1554 /* load PRD table addr. */
1555 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1556 port_mmio + BMDMA_PRD_HIGH_OFS);
1557 writelfl(pp->sg_tbl_dma[qc->tag],
1558 port_mmio + BMDMA_PRD_LOW_OFS);
1560 /* issue r/w command */
1561 ap->ops->sff_exec_command(ap, &qc->tf);
1565 * mv_bmdma_start - Start a BMDMA transaction
1566 * @qc: queued command to start DMA on.
1569 * Inherited from caller.
1571 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1573 struct ata_port *ap = qc->ap;
1574 void __iomem *port_mmio = mv_ap_base(ap);
1575 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1576 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1578 /* start host DMA transaction */
1579 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1583 * mv_bmdma_stop - Stop BMDMA transfer
1584 * @qc: queued command to stop DMA on.
1586 * Clears the ATA_DMA_START flag in the bmdma control register
1589 * Inherited from caller.
1591 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1593 struct ata_port *ap = qc->ap;
1594 void __iomem *port_mmio = mv_ap_base(ap);
1597 /* clear start/stop bit */
1598 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1599 cmd &= ~ATA_DMA_START;
1600 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1602 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1603 ata_sff_dma_pause(ap);
1607 * mv_bmdma_status - Read BMDMA status
1608 * @ap: port for which to retrieve DMA status.
1610 * Read and return equivalent of the sff BMDMA status register.
1613 * Inherited from caller.
1615 static u8 mv_bmdma_status(struct ata_port *ap)
1617 void __iomem *port_mmio = mv_ap_base(ap);
1621 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1622 * and the ATA_DMA_INTR bit doesn't exist.
1624 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1625 if (reg & ATA_DMA_ACTIVE)
1626 status = ATA_DMA_ACTIVE;
1628 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1633 * mv_qc_prep - Host specific command preparation.
1634 * @qc: queued command to prepare
1636 * This routine simply redirects to the general purpose routine
1637 * if command is not DMA. Else, it handles prep of the CRQB
1638 * (command request block), does some sanity checking, and calls
1639 * the SG load routine.
1642 * Inherited from caller.
1644 static void mv_qc_prep(struct ata_queued_cmd *qc)
1646 struct ata_port *ap = qc->ap;
1647 struct mv_port_priv *pp = ap->private_data;
1649 struct ata_taskfile *tf;
1653 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1654 (qc->tf.protocol != ATA_PROT_NCQ))
1657 /* Fill in command request block
1659 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1660 flags |= CRQB_FLAG_READ;
1661 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1662 flags |= qc->tag << CRQB_TAG_SHIFT;
1663 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1665 /* get current queue index from software */
1666 in_index = pp->req_idx;
1668 pp->crqb[in_index].sg_addr =
1669 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1670 pp->crqb[in_index].sg_addr_hi =
1671 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1672 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1674 cw = &pp->crqb[in_index].ata_cmd[0];
1677 /* Sadly, the CRQB cannot accomodate all registers--there are
1678 * only 11 bytes...so we must pick and choose required
1679 * registers based on the command. So, we drop feature and
1680 * hob_feature for [RW] DMA commands, but they are needed for
1681 * NCQ. NCQ will drop hob_nsect, which is not needed there
1682 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
1684 switch (tf->command) {
1686 case ATA_CMD_READ_EXT:
1688 case ATA_CMD_WRITE_EXT:
1689 case ATA_CMD_WRITE_FUA_EXT:
1690 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1692 case ATA_CMD_FPDMA_READ:
1693 case ATA_CMD_FPDMA_WRITE:
1694 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1695 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1698 /* The only other commands EDMA supports in non-queued and
1699 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1700 * of which are defined/used by Linux. If we get here, this
1701 * driver needs work.
1703 * FIXME: modify libata to give qc_prep a return value and
1704 * return error here.
1706 BUG_ON(tf->command);
1709 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1710 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1711 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1712 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1713 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1714 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1715 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1716 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1717 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1719 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1725 * mv_qc_prep_iie - Host specific command preparation.
1726 * @qc: queued command to prepare
1728 * This routine simply redirects to the general purpose routine
1729 * if command is not DMA. Else, it handles prep of the CRQB
1730 * (command request block), does some sanity checking, and calls
1731 * the SG load routine.
1734 * Inherited from caller.
1736 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1738 struct ata_port *ap = qc->ap;
1739 struct mv_port_priv *pp = ap->private_data;
1740 struct mv_crqb_iie *crqb;
1741 struct ata_taskfile *tf;
1745 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1746 (qc->tf.protocol != ATA_PROT_NCQ))
1749 /* Fill in Gen IIE command request block */
1750 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1751 flags |= CRQB_FLAG_READ;
1753 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1754 flags |= qc->tag << CRQB_TAG_SHIFT;
1755 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1756 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1758 /* get current queue index from software */
1759 in_index = pp->req_idx;
1761 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1762 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1763 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1764 crqb->flags = cpu_to_le32(flags);
1767 crqb->ata_cmd[0] = cpu_to_le32(
1768 (tf->command << 16) |
1771 crqb->ata_cmd[1] = cpu_to_le32(
1777 crqb->ata_cmd[2] = cpu_to_le32(
1778 (tf->hob_lbal << 0) |
1779 (tf->hob_lbam << 8) |
1780 (tf->hob_lbah << 16) |
1781 (tf->hob_feature << 24)
1783 crqb->ata_cmd[3] = cpu_to_le32(
1785 (tf->hob_nsect << 8)
1788 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1794 * mv_qc_issue - Initiate a command to the host
1795 * @qc: queued command to start
1797 * This routine simply redirects to the general purpose routine
1798 * if command is not DMA. Else, it sanity checks our local
1799 * caches of the request producer/consumer indices then enables
1800 * DMA and bumps the request producer index.
1803 * Inherited from caller.
1805 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1807 static int limit_warnings = 10;
1808 struct ata_port *ap = qc->ap;
1809 void __iomem *port_mmio = mv_ap_base(ap);
1810 struct mv_port_priv *pp = ap->private_data;
1812 unsigned int port_irqs = DONE_IRQ | ERR_IRQ;
1814 switch (qc->tf.protocol) {
1817 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
1818 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1819 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1821 /* Write the request in pointer to kick the EDMA to life */
1822 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1823 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1828 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1830 * Someday, we might implement special polling workarounds
1831 * for these, but it all seems rather unnecessary since we
1832 * normally use only DMA for commands which transfer more
1833 * than a single block of data.
1835 * Much of the time, this could just work regardless.
1836 * So for now, just log the incident, and allow the attempt.
1838 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
1840 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1841 ": attempting PIO w/multiple DRQ: "
1842 "this may fail due to h/w errata\n");
1845 case ATAPI_PROT_PIO:
1846 port_irqs = ERR_IRQ; /* leave DONE_IRQ masked for PIO */
1850 * We're about to send a non-EDMA capable command to the
1851 * port. Turn off EDMA so there won't be problems accessing
1852 * shadow block, etc registers.
1855 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
1856 mv_pmp_select(ap, qc->dev->link->pmp);
1857 return ata_sff_qc_issue(qc);
1861 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1863 struct mv_port_priv *pp = ap->private_data;
1864 struct ata_queued_cmd *qc;
1866 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1868 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1870 if (qc->tf.flags & ATA_TFLAG_POLLING)
1872 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
1878 static void mv_pmp_error_handler(struct ata_port *ap)
1880 unsigned int pmp, pmp_map;
1881 struct mv_port_priv *pp = ap->private_data;
1883 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1885 * Perform NCQ error analysis on failed PMPs
1886 * before we freeze the port entirely.
1888 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1890 pmp_map = pp->delayed_eh_pmp_map;
1891 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1892 for (pmp = 0; pmp_map != 0; pmp++) {
1893 unsigned int this_pmp = (1 << pmp);
1894 if (pmp_map & this_pmp) {
1895 struct ata_link *link = &ap->pmp_link[pmp];
1896 pmp_map &= ~this_pmp;
1897 ata_eh_analyze_ncq_error(link);
1900 ata_port_freeze(ap);
1902 sata_pmp_error_handler(ap);
1905 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1907 void __iomem *port_mmio = mv_ap_base(ap);
1909 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1912 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1914 struct ata_eh_info *ehi;
1918 * Initialize EH info for PMPs which saw device errors
1920 ehi = &ap->link.eh_info;
1921 for (pmp = 0; pmp_map != 0; pmp++) {
1922 unsigned int this_pmp = (1 << pmp);
1923 if (pmp_map & this_pmp) {
1924 struct ata_link *link = &ap->pmp_link[pmp];
1926 pmp_map &= ~this_pmp;
1927 ehi = &link->eh_info;
1928 ata_ehi_clear_desc(ehi);
1929 ata_ehi_push_desc(ehi, "dev err");
1930 ehi->err_mask |= AC_ERR_DEV;
1931 ehi->action |= ATA_EH_RESET;
1932 ata_link_abort(link);
1937 static int mv_req_q_empty(struct ata_port *ap)
1939 void __iomem *port_mmio = mv_ap_base(ap);
1940 u32 in_ptr, out_ptr;
1942 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1943 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1944 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1945 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1946 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1949 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1951 struct mv_port_priv *pp = ap->private_data;
1953 unsigned int old_map, new_map;
1956 * Device error during FBS+NCQ operation:
1958 * Set a port flag to prevent further I/O being enqueued.
1959 * Leave the EDMA running to drain outstanding commands from this port.
1960 * Perform the post-mortem/EH only when all responses are complete.
1961 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1963 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1964 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1965 pp->delayed_eh_pmp_map = 0;
1967 old_map = pp->delayed_eh_pmp_map;
1968 new_map = old_map | mv_get_err_pmp_map(ap);
1970 if (old_map != new_map) {
1971 pp->delayed_eh_pmp_map = new_map;
1972 mv_pmp_eh_prep(ap, new_map & ~old_map);
1974 failed_links = hweight16(new_map);
1976 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1977 "failed_links=%d nr_active_links=%d\n",
1978 __func__, pp->delayed_eh_pmp_map,
1979 ap->qc_active, failed_links,
1980 ap->nr_active_links);
1982 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
1983 mv_process_crpb_entries(ap, pp);
1986 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1987 return 1; /* handled */
1989 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1990 return 1; /* handled */
1993 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1996 * Possible future enhancement:
1998 * FBS+non-NCQ operation is not yet implemented.
1999 * See related notes in mv_edma_cfg().
2001 * Device error during FBS+non-NCQ operation:
2003 * We need to snapshot the shadow registers for each failed command.
2004 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2006 return 0; /* not handled */
2009 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2011 struct mv_port_priv *pp = ap->private_data;
2013 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2014 return 0; /* EDMA was not active: not handled */
2015 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2016 return 0; /* FBS was not active: not handled */
2018 if (!(edma_err_cause & EDMA_ERR_DEV))
2019 return 0; /* non DEV error: not handled */
2020 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2021 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2022 return 0; /* other problems: not handled */
2024 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2026 * EDMA should NOT have self-disabled for this case.
2027 * If it did, then something is wrong elsewhere,
2028 * and we cannot handle it here.
2030 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2031 ata_port_printk(ap, KERN_WARNING,
2032 "%s: err_cause=0x%x pp_flags=0x%x\n",
2033 __func__, edma_err_cause, pp->pp_flags);
2034 return 0; /* not handled */
2036 return mv_handle_fbs_ncq_dev_err(ap);
2039 * EDMA should have self-disabled for this case.
2040 * If it did not, then something is wrong elsewhere,
2041 * and we cannot handle it here.
2043 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2044 ata_port_printk(ap, KERN_WARNING,
2045 "%s: err_cause=0x%x pp_flags=0x%x\n",
2046 __func__, edma_err_cause, pp->pp_flags);
2047 return 0; /* not handled */
2049 return mv_handle_fbs_non_ncq_dev_err(ap);
2051 return 0; /* not handled */
2054 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2056 struct ata_eh_info *ehi = &ap->link.eh_info;
2057 char *when = "idle";
2059 ata_ehi_clear_desc(ehi);
2060 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2062 } else if (edma_was_enabled) {
2063 when = "EDMA enabled";
2065 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2066 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2069 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2070 ehi->err_mask |= AC_ERR_OTHER;
2071 ehi->action |= ATA_EH_RESET;
2072 ata_port_freeze(ap);
2076 * mv_err_intr - Handle error interrupts on the port
2077 * @ap: ATA channel to manipulate
2079 * Most cases require a full reset of the chip's state machine,
2080 * which also performs a COMRESET.
2081 * Also, if the port disabled DMA, update our cached copy to match.
2084 * Inherited from caller.
2086 static void mv_err_intr(struct ata_port *ap)
2088 void __iomem *port_mmio = mv_ap_base(ap);
2089 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2091 struct mv_port_priv *pp = ap->private_data;
2092 struct mv_host_priv *hpriv = ap->host->private_data;
2093 unsigned int action = 0, err_mask = 0;
2094 struct ata_eh_info *ehi = &ap->link.eh_info;
2095 struct ata_queued_cmd *qc;
2099 * Read and clear the SError and err_cause bits.
2100 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2101 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2103 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2104 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2106 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2107 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2108 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2109 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2111 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2113 if (edma_err_cause & EDMA_ERR_DEV) {
2115 * Device errors during FIS-based switching operation
2116 * require special handling.
2118 if (mv_handle_dev_err(ap, edma_err_cause))
2122 qc = mv_get_active_qc(ap);
2123 ata_ehi_clear_desc(ehi);
2124 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2125 edma_err_cause, pp->pp_flags);
2127 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2128 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2129 if (fis_cause & SATA_FIS_IRQ_AN) {
2130 u32 ec = edma_err_cause &
2131 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2132 sata_async_notification(ap);
2134 return; /* Just an AN; no need for the nukes */
2135 ata_ehi_push_desc(ehi, "SDB notify");
2139 * All generations share these EDMA error cause bits:
2141 if (edma_err_cause & EDMA_ERR_DEV) {
2142 err_mask |= AC_ERR_DEV;
2143 action |= ATA_EH_RESET;
2144 ata_ehi_push_desc(ehi, "dev error");
2146 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2147 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2148 EDMA_ERR_INTRL_PAR)) {
2149 err_mask |= AC_ERR_ATA_BUS;
2150 action |= ATA_EH_RESET;
2151 ata_ehi_push_desc(ehi, "parity error");
2153 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2154 ata_ehi_hotplugged(ehi);
2155 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2156 "dev disconnect" : "dev connect");
2157 action |= ATA_EH_RESET;
2161 * Gen-I has a different SELF_DIS bit,
2162 * different FREEZE bits, and no SERR bit:
2164 if (IS_GEN_I(hpriv)) {
2165 eh_freeze_mask = EDMA_EH_FREEZE_5;
2166 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2167 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2168 ata_ehi_push_desc(ehi, "EDMA self-disable");
2171 eh_freeze_mask = EDMA_EH_FREEZE;
2172 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2173 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2174 ata_ehi_push_desc(ehi, "EDMA self-disable");
2176 if (edma_err_cause & EDMA_ERR_SERR) {
2177 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2178 err_mask |= AC_ERR_ATA_BUS;
2179 action |= ATA_EH_RESET;
2184 err_mask = AC_ERR_OTHER;
2185 action |= ATA_EH_RESET;
2188 ehi->serror |= serr;
2189 ehi->action |= action;
2192 qc->err_mask |= err_mask;
2194 ehi->err_mask |= err_mask;
2196 if (err_mask == AC_ERR_DEV) {
2198 * Cannot do ata_port_freeze() here,
2199 * because it would kill PIO access,
2200 * which is needed for further diagnosis.
2204 } else if (edma_err_cause & eh_freeze_mask) {
2206 * Note to self: ata_port_freeze() calls ata_port_abort()
2208 ata_port_freeze(ap);
2215 ata_link_abort(qc->dev->link);
2221 static void mv_process_crpb_response(struct ata_port *ap,
2222 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2224 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2228 u16 edma_status = le16_to_cpu(response->flags);
2230 * edma_status from a response queue entry:
2231 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2232 * MSB is saved ATA status from command completion.
2235 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2238 * Error will be seen/handled by mv_err_intr().
2239 * So do nothing at all here.
2244 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2245 if (!ac_err_mask(ata_status))
2246 ata_qc_complete(qc);
2247 /* else: leave it for mv_err_intr() */
2249 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2254 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2256 void __iomem *port_mmio = mv_ap_base(ap);
2257 struct mv_host_priv *hpriv = ap->host->private_data;
2259 bool work_done = false;
2260 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2262 /* Get the hardware queue position index */
2263 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2264 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2266 /* Process new responses from since the last time we looked */
2267 while (in_index != pp->resp_idx) {
2269 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2271 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2273 if (IS_GEN_I(hpriv)) {
2274 /* 50xx: no NCQ, only one command active at a time */
2275 tag = ap->link.active_tag;
2277 /* Gen II/IIE: get command tag from CRPB entry */
2278 tag = le16_to_cpu(response->id) & 0x1f;
2280 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2284 /* Update the software queue position index in hardware */
2286 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2287 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2288 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2291 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2293 struct mv_port_priv *pp;
2294 int edma_was_enabled;
2296 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2297 mv_unexpected_intr(ap, 0);
2301 * Grab a snapshot of the EDMA_EN flag setting,
2302 * so that we have a consistent view for this port,
2303 * even if something we call of our routines changes it.
2305 pp = ap->private_data;
2306 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2308 * Process completed CRPB response(s) before other events.
2310 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2311 mv_process_crpb_entries(ap, pp);
2312 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2313 mv_handle_fbs_ncq_dev_err(ap);
2316 * Handle chip-reported errors, or continue on to handle PIO.
2318 if (unlikely(port_cause & ERR_IRQ)) {
2320 } else if (!edma_was_enabled) {
2321 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2323 ata_sff_host_intr(ap, qc);
2325 mv_unexpected_intr(ap, edma_was_enabled);
2330 * mv_host_intr - Handle all interrupts on the given host controller
2331 * @host: host specific structure
2332 * @main_irq_cause: Main interrupt cause register for the chip.
2335 * Inherited from caller.
2337 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2339 struct mv_host_priv *hpriv = host->private_data;
2340 void __iomem *mmio = hpriv->base, *hc_mmio;
2341 unsigned int handled = 0, port;
2343 for (port = 0; port < hpriv->n_ports; port++) {
2344 struct ata_port *ap = host->ports[port];
2345 unsigned int p, shift, hardport, port_cause;
2347 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2349 * Each hc within the host has its own hc_irq_cause register,
2350 * where the interrupting ports bits get ack'd.
2352 if (hardport == 0) { /* first port on this hc ? */
2353 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2354 u32 port_mask, ack_irqs;
2356 * Skip this entire hc if nothing pending for any ports
2359 port += MV_PORTS_PER_HC - 1;
2363 * We don't need/want to read the hc_irq_cause register,
2364 * because doing so hurts performance, and
2365 * main_irq_cause already gives us everything we need.
2367 * But we do have to *write* to the hc_irq_cause to ack
2368 * the ports that we are handling this time through.
2370 * This requires that we create a bitmap for those
2371 * ports which interrupted us, and use that bitmap
2372 * to ack (only) those ports via hc_irq_cause.
2375 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2376 if ((port + p) >= hpriv->n_ports)
2378 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2379 if (hc_cause & port_mask)
2380 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2382 hc_mmio = mv_hc_base_from_port(mmio, port);
2383 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2387 * Handle interrupts signalled for this port:
2389 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2391 mv_port_intr(ap, port_cause);
2396 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2398 struct mv_host_priv *hpriv = host->private_data;
2399 struct ata_port *ap;
2400 struct ata_queued_cmd *qc;
2401 struct ata_eh_info *ehi;
2402 unsigned int i, err_mask, printed = 0;
2405 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2407 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2410 DPRINTK("All regs @ PCI error\n");
2411 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2413 writelfl(0, mmio + hpriv->irq_cause_ofs);
2415 for (i = 0; i < host->n_ports; i++) {
2416 ap = host->ports[i];
2417 if (!ata_link_offline(&ap->link)) {
2418 ehi = &ap->link.eh_info;
2419 ata_ehi_clear_desc(ehi);
2421 ata_ehi_push_desc(ehi,
2422 "PCI err cause 0x%08x", err_cause);
2423 err_mask = AC_ERR_HOST_BUS;
2424 ehi->action = ATA_EH_RESET;
2425 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2427 qc->err_mask |= err_mask;
2429 ehi->err_mask |= err_mask;
2431 ata_port_freeze(ap);
2434 return 1; /* handled */
2438 * mv_interrupt - Main interrupt event handler
2440 * @dev_instance: private data; in this case the host structure
2442 * Read the read only register to determine if any host
2443 * controllers have pending interrupts. If so, call lower level
2444 * routine to handle. Also check for PCI errors which are only
2448 * This routine holds the host lock while processing pending
2451 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2453 struct ata_host *host = dev_instance;
2454 struct mv_host_priv *hpriv = host->private_data;
2455 unsigned int handled = 0;
2456 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2457 u32 main_irq_cause, pending_irqs;
2459 spin_lock(&host->lock);
2461 /* for MSI: block new interrupts while in here */
2463 writel(0, hpriv->main_irq_mask_addr);
2465 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2466 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2468 * Deal with cases where we either have nothing pending, or have read
2469 * a bogus register value which can indicate HW removal or PCI fault.
2471 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2472 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2473 handled = mv_pci_error(host, hpriv->base);
2475 handled = mv_host_intr(host, pending_irqs);
2478 /* for MSI: unmask; interrupt cause bits will retrigger now */
2480 writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr);
2482 spin_unlock(&host->lock);
2484 return IRQ_RETVAL(handled);
2487 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2491 switch (sc_reg_in) {
2495 ofs = sc_reg_in * sizeof(u32);
2504 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
2506 struct mv_host_priv *hpriv = link->ap->host->private_data;
2507 void __iomem *mmio = hpriv->base;
2508 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2509 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2511 if (ofs != 0xffffffffU) {
2512 *val = readl(addr + ofs);
2518 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
2520 struct mv_host_priv *hpriv = link->ap->host->private_data;
2521 void __iomem *mmio = hpriv->base;
2522 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2523 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2525 if (ofs != 0xffffffffU) {
2526 writelfl(val, addr + ofs);
2532 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2534 struct pci_dev *pdev = to_pci_dev(host->dev);
2537 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2540 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2542 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2545 mv_reset_pci_bus(host, mmio);
2548 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2550 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2553 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2556 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2559 tmp = readl(phy_mmio + MV5_PHY_MODE);
2561 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2562 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2565 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2569 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2571 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2573 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2575 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2578 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2581 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2582 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2584 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2587 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2589 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2591 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2594 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2597 tmp = readl(phy_mmio + MV5_PHY_MODE);
2599 tmp |= hpriv->signal[port].pre;
2600 tmp |= hpriv->signal[port].amps;
2601 writel(tmp, phy_mmio + MV5_PHY_MODE);
2606 #define ZERO(reg) writel(0, port_mmio + (reg))
2607 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2610 void __iomem *port_mmio = mv_port_base(mmio, port);
2612 mv_reset_channel(hpriv, mmio, port);
2614 ZERO(0x028); /* command */
2615 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2616 ZERO(0x004); /* timer */
2617 ZERO(0x008); /* irq err cause */
2618 ZERO(0x00c); /* irq err mask */
2619 ZERO(0x010); /* rq bah */
2620 ZERO(0x014); /* rq inp */
2621 ZERO(0x018); /* rq outp */
2622 ZERO(0x01c); /* respq bah */
2623 ZERO(0x024); /* respq outp */
2624 ZERO(0x020); /* respq inp */
2625 ZERO(0x02c); /* test control */
2626 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2630 #define ZERO(reg) writel(0, hc_mmio + (reg))
2631 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2634 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2642 tmp = readl(hc_mmio + 0x20);
2645 writel(tmp, hc_mmio + 0x20);
2649 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2652 unsigned int hc, port;
2654 for (hc = 0; hc < n_hc; hc++) {
2655 for (port = 0; port < MV_PORTS_PER_HC; port++)
2656 mv5_reset_hc_port(hpriv, mmio,
2657 (hc * MV_PORTS_PER_HC) + port);
2659 mv5_reset_one_hc(hpriv, mmio, hc);
2666 #define ZERO(reg) writel(0, mmio + (reg))
2667 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2669 struct mv_host_priv *hpriv = host->private_data;
2672 tmp = readl(mmio + MV_PCI_MODE_OFS);
2674 writel(tmp, mmio + MV_PCI_MODE_OFS);
2676 ZERO(MV_PCI_DISC_TIMER);
2677 ZERO(MV_PCI_MSI_TRIGGER);
2678 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2679 ZERO(MV_PCI_SERR_MASK);
2680 ZERO(hpriv->irq_cause_ofs);
2681 ZERO(hpriv->irq_mask_ofs);
2682 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2683 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2684 ZERO(MV_PCI_ERR_ATTRIBUTE);
2685 ZERO(MV_PCI_ERR_COMMAND);
2689 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2693 mv5_reset_flash(hpriv, mmio);
2695 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2697 tmp |= (1 << 5) | (1 << 6);
2698 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2702 * mv6_reset_hc - Perform the 6xxx global soft reset
2703 * @mmio: base address of the HBA
2705 * This routine only applies to 6xxx parts.
2708 * Inherited from caller.
2710 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2713 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2717 /* Following procedure defined in PCI "main command and status
2721 writel(t | STOP_PCI_MASTER, reg);
2723 for (i = 0; i < 1000; i++) {
2726 if (PCI_MASTER_EMPTY & t)
2729 if (!(PCI_MASTER_EMPTY & t)) {
2730 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2738 writel(t | GLOB_SFT_RST, reg);
2741 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2743 if (!(GLOB_SFT_RST & t)) {
2744 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2749 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2752 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2755 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2757 if (GLOB_SFT_RST & t) {
2758 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2765 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2768 void __iomem *port_mmio;
2771 tmp = readl(mmio + MV_RESET_CFG_OFS);
2772 if ((tmp & (1 << 0)) == 0) {
2773 hpriv->signal[idx].amps = 0x7 << 8;
2774 hpriv->signal[idx].pre = 0x1 << 5;
2778 port_mmio = mv_port_base(mmio, idx);
2779 tmp = readl(port_mmio + PHY_MODE2);
2781 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2782 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2785 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2787 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2790 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2793 void __iomem *port_mmio = mv_port_base(mmio, port);
2795 u32 hp_flags = hpriv->hp_flags;
2797 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2799 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2802 if (fix_phy_mode2) {
2803 m2 = readl(port_mmio + PHY_MODE2);
2806 writel(m2, port_mmio + PHY_MODE2);
2810 m2 = readl(port_mmio + PHY_MODE2);
2811 m2 &= ~((1 << 16) | (1 << 31));
2812 writel(m2, port_mmio + PHY_MODE2);
2818 * Gen-II/IIe PHY_MODE3 errata RM#2:
2819 * Achieves better receiver noise performance than the h/w default:
2821 m3 = readl(port_mmio + PHY_MODE3);
2822 m3 = (m3 & 0x1f) | (0x5555601 << 5);
2824 /* Guideline 88F5182 (GL# SATA-S11) */
2828 if (fix_phy_mode4) {
2829 u32 m4 = readl(port_mmio + PHY_MODE4);
2831 * Enforce reserved-bit restrictions on GenIIe devices only.
2832 * For earlier chipsets, force only the internal config field
2833 * (workaround for errata FEr SATA#10 part 1).
2835 if (IS_GEN_IIE(hpriv))
2836 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2838 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
2839 writel(m4, port_mmio + PHY_MODE4);
2842 * Workaround for 60x1-B2 errata SATA#13:
2843 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2844 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2846 writel(m3, port_mmio + PHY_MODE3);
2848 /* Revert values of pre-emphasis and signal amps to the saved ones */
2849 m2 = readl(port_mmio + PHY_MODE2);
2851 m2 &= ~MV_M2_PREAMP_MASK;
2852 m2 |= hpriv->signal[port].amps;
2853 m2 |= hpriv->signal[port].pre;
2856 /* according to mvSata 3.6.1, some IIE values are fixed */
2857 if (IS_GEN_IIE(hpriv)) {
2862 writel(m2, port_mmio + PHY_MODE2);
2865 /* TODO: use the generic LED interface to configure the SATA Presence */
2866 /* & Acitivy LEDs on the board */
2867 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2873 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2876 void __iomem *port_mmio;
2879 port_mmio = mv_port_base(mmio, idx);
2880 tmp = readl(port_mmio + PHY_MODE2);
2882 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2883 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2887 #define ZERO(reg) writel(0, port_mmio + (reg))
2888 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2889 void __iomem *mmio, unsigned int port)
2891 void __iomem *port_mmio = mv_port_base(mmio, port);
2893 mv_reset_channel(hpriv, mmio, port);
2895 ZERO(0x028); /* command */
2896 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2897 ZERO(0x004); /* timer */
2898 ZERO(0x008); /* irq err cause */
2899 ZERO(0x00c); /* irq err mask */
2900 ZERO(0x010); /* rq bah */
2901 ZERO(0x014); /* rq inp */
2902 ZERO(0x018); /* rq outp */
2903 ZERO(0x01c); /* respq bah */
2904 ZERO(0x024); /* respq outp */
2905 ZERO(0x020); /* respq inp */
2906 ZERO(0x02c); /* test control */
2907 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2912 #define ZERO(reg) writel(0, hc_mmio + (reg))
2913 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2916 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2926 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2927 void __iomem *mmio, unsigned int n_hc)
2931 for (port = 0; port < hpriv->n_ports; port++)
2932 mv_soc_reset_hc_port(hpriv, mmio, port);
2934 mv_soc_reset_one_hc(hpriv, mmio);
2939 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2945 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2950 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2952 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2954 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2956 ifcfg |= (1 << 7); /* enable gen2i speed */
2957 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2960 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2961 unsigned int port_no)
2963 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2966 * The datasheet warns against setting EDMA_RESET when EDMA is active
2967 * (but doesn't say what the problem might be). So we first try
2968 * to disable the EDMA engine before doing the EDMA_RESET operation.
2970 mv_stop_edma_engine(port_mmio);
2971 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2973 if (!IS_GEN_I(hpriv)) {
2974 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2975 mv_setup_ifcfg(port_mmio, 1);
2978 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2979 * link, and physical layers. It resets all SATA interface registers
2980 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2982 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2983 udelay(25); /* allow reset propagation */
2984 writelfl(0, port_mmio + EDMA_CMD_OFS);
2986 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2988 if (IS_GEN_I(hpriv))
2992 static void mv_pmp_select(struct ata_port *ap, int pmp)
2994 if (sata_pmp_supported(ap)) {
2995 void __iomem *port_mmio = mv_ap_base(ap);
2996 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2997 int old = reg & 0xf;
3000 reg = (reg & ~0xf) | pmp;
3001 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
3006 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3007 unsigned long deadline)
3009 mv_pmp_select(link->ap, sata_srst_pmp(link));
3010 return sata_std_hardreset(link, class, deadline);
3013 static int mv_softreset(struct ata_link *link, unsigned int *class,
3014 unsigned long deadline)
3016 mv_pmp_select(link->ap, sata_srst_pmp(link));
3017 return ata_sff_softreset(link, class, deadline);
3020 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3021 unsigned long deadline)
3023 struct ata_port *ap = link->ap;
3024 struct mv_host_priv *hpriv = ap->host->private_data;
3025 struct mv_port_priv *pp = ap->private_data;
3026 void __iomem *mmio = hpriv->base;
3027 int rc, attempts = 0, extra = 0;
3031 mv_reset_channel(hpriv, mmio, ap->port_no);
3032 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3034 /* Workaround for errata FEr SATA#10 (part 2) */
3036 const unsigned long *timing =
3037 sata_ehc_deb_timing(&link->eh_context);
3039 rc = sata_link_hardreset(link, timing, deadline + extra,
3041 rc = online ? -EAGAIN : rc;
3044 sata_scr_read(link, SCR_STATUS, &sstatus);
3045 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3046 /* Force 1.5gb/s link speed and try again */
3047 mv_setup_ifcfg(mv_ap_base(ap), 0);
3048 if (time_after(jiffies + HZ, deadline))
3049 extra = HZ; /* only extend it once, max */
3051 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3052 mv_save_cached_regs(ap);
3053 mv_edma_cfg(ap, 0, 0);
3058 static void mv_eh_freeze(struct ata_port *ap)
3061 mv_enable_port_irqs(ap, 0);
3064 static void mv_eh_thaw(struct ata_port *ap)
3066 struct mv_host_priv *hpriv = ap->host->private_data;
3067 unsigned int port = ap->port_no;
3068 unsigned int hardport = mv_hardport_from_port(port);
3069 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3070 void __iomem *port_mmio = mv_ap_base(ap);
3073 /* clear EDMA errors on this port */
3074 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3076 /* clear pending irq events */
3077 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3078 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
3080 mv_enable_port_irqs(ap, ERR_IRQ);
3084 * mv_port_init - Perform some early initialization on a single port.
3085 * @port: libata data structure storing shadow register addresses
3086 * @port_mmio: base address of the port
3088 * Initialize shadow register mmio addresses, clear outstanding
3089 * interrupts on the port, and unmask interrupts for the future
3090 * start of the port.
3093 * Inherited from caller.
3095 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3097 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
3100 /* PIO related setup
3102 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3104 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3105 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3106 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3107 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3108 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3109 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3111 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3112 /* special case: control/altstatus doesn't have ATA_REG_ address */
3113 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3116 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
3118 /* Clear any currently outstanding port interrupt conditions */
3119 serr_ofs = mv_scr_offset(SCR_ERROR);
3120 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3121 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3123 /* unmask all non-transient EDMA error interrupts */
3124 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
3126 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3127 readl(port_mmio + EDMA_CFG_OFS),
3128 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3129 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
3132 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3134 struct mv_host_priv *hpriv = host->private_data;
3135 void __iomem *mmio = hpriv->base;
3138 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3139 return 0; /* not PCI-X capable */
3140 reg = readl(mmio + MV_PCI_MODE_OFS);
3141 if ((reg & MV_PCI_MODE_MASK) == 0)
3142 return 0; /* conventional PCI mode */
3143 return 1; /* chip is in PCI-X mode */
3146 static int mv_pci_cut_through_okay(struct ata_host *host)
3148 struct mv_host_priv *hpriv = host->private_data;
3149 void __iomem *mmio = hpriv->base;
3152 if (!mv_in_pcix_mode(host)) {
3153 reg = readl(mmio + PCI_COMMAND_OFS);
3154 if (reg & PCI_COMMAND_MRDTRIG)
3155 return 0; /* not okay */
3157 return 1; /* okay */
3160 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3162 struct pci_dev *pdev = to_pci_dev(host->dev);
3163 struct mv_host_priv *hpriv = host->private_data;
3164 u32 hp_flags = hpriv->hp_flags;
3166 switch (board_idx) {
3168 hpriv->ops = &mv5xxx_ops;
3169 hp_flags |= MV_HP_GEN_I;
3171 switch (pdev->revision) {
3173 hp_flags |= MV_HP_ERRATA_50XXB0;
3176 hp_flags |= MV_HP_ERRATA_50XXB2;
3179 dev_printk(KERN_WARNING, &pdev->dev,
3180 "Applying 50XXB2 workarounds to unknown rev\n");
3181 hp_flags |= MV_HP_ERRATA_50XXB2;
3188 hpriv->ops = &mv5xxx_ops;
3189 hp_flags |= MV_HP_GEN_I;
3191 switch (pdev->revision) {
3193 hp_flags |= MV_HP_ERRATA_50XXB0;
3196 hp_flags |= MV_HP_ERRATA_50XXB2;
3199 dev_printk(KERN_WARNING, &pdev->dev,
3200 "Applying B2 workarounds to unknown rev\n");
3201 hp_flags |= MV_HP_ERRATA_50XXB2;
3208 hpriv->ops = &mv6xxx_ops;
3209 hp_flags |= MV_HP_GEN_II;
3211 switch (pdev->revision) {
3213 hp_flags |= MV_HP_ERRATA_60X1B2;
3216 hp_flags |= MV_HP_ERRATA_60X1C0;
3219 dev_printk(KERN_WARNING, &pdev->dev,
3220 "Applying B2 workarounds to unknown rev\n");
3221 hp_flags |= MV_HP_ERRATA_60X1B2;
3227 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3228 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3229 (pdev->device == 0x2300 || pdev->device == 0x2310))
3232 * Highpoint RocketRAID PCIe 23xx series cards:
3234 * Unconfigured drives are treated as "Legacy"
3235 * by the BIOS, and it overwrites sector 8 with
3236 * a "Lgcy" metadata block prior to Linux boot.
3238 * Configured drives (RAID or JBOD) leave sector 8
3239 * alone, but instead overwrite a high numbered
3240 * sector for the RAID metadata. This sector can
3241 * be determined exactly, by truncating the physical
3242 * drive capacity to a nice even GB value.
3244 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3246 * Warn the user, lest they think we're just buggy.
3248 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3249 " BIOS CORRUPTS DATA on all attached drives,"
3250 " regardless of if/how they are configured."
3252 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3253 " use sectors 8-9 on \"Legacy\" drives,"
3254 " and avoid the final two gigabytes on"
3255 " all RocketRAID BIOS initialized drives.\n");
3259 hpriv->ops = &mv6xxx_ops;
3260 hp_flags |= MV_HP_GEN_IIE;
3261 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3262 hp_flags |= MV_HP_CUT_THROUGH;
3264 switch (pdev->revision) {
3265 case 0x2: /* Rev.B0: the first/only public release */
3266 hp_flags |= MV_HP_ERRATA_60X1C0;
3269 dev_printk(KERN_WARNING, &pdev->dev,
3270 "Applying 60X1C0 workarounds to unknown rev\n");
3271 hp_flags |= MV_HP_ERRATA_60X1C0;
3276 hpriv->ops = &mv_soc_ops;
3277 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3278 MV_HP_ERRATA_60X1C0;
3282 dev_printk(KERN_ERR, host->dev,
3283 "BUG: invalid board index %u\n", board_idx);
3287 hpriv->hp_flags = hp_flags;
3288 if (hp_flags & MV_HP_PCIE) {
3289 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3290 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3291 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3293 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3294 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3295 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3302 * mv_init_host - Perform some early initialization of the host.
3303 * @host: ATA host to initialize
3304 * @board_idx: controller index
3306 * If possible, do an early global reset of the host. Then do
3307 * our port init and clear/unmask all/relevant host interrupts.
3310 * Inherited from caller.
3312 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3314 int rc = 0, n_hc, port, hc;
3315 struct mv_host_priv *hpriv = host->private_data;
3316 void __iomem *mmio = hpriv->base;
3318 rc = mv_chip_id(host, board_idx);
3322 if (IS_SOC(hpriv)) {
3323 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3324 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3326 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3327 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3330 /* initialize shadow irq mask with register's value */
3331 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3333 /* global interrupt mask: 0 == mask everything */
3334 mv_set_main_irq_mask(host, ~0, 0);
3336 n_hc = mv_get_hc_count(host->ports[0]->flags);
3338 for (port = 0; port < host->n_ports; port++)
3339 hpriv->ops->read_preamp(hpriv, port, mmio);
3341 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3345 hpriv->ops->reset_flash(hpriv, mmio);
3346 hpriv->ops->reset_bus(host, mmio);
3347 hpriv->ops->enable_leds(hpriv, mmio);
3349 for (port = 0; port < host->n_ports; port++) {
3350 struct ata_port *ap = host->ports[port];
3351 void __iomem *port_mmio = mv_port_base(mmio, port);
3353 mv_port_init(&ap->ioaddr, port_mmio);
3356 if (!IS_SOC(hpriv)) {
3357 unsigned int offset = port_mmio - mmio;
3358 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3359 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3364 for (hc = 0; hc < n_hc; hc++) {
3365 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3367 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3368 "(before clear)=0x%08x\n", hc,
3369 readl(hc_mmio + HC_CFG_OFS),
3370 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3372 /* Clear any currently outstanding hc interrupt conditions */
3373 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3376 /* Clear any currently outstanding host interrupt conditions */
3377 writelfl(0, mmio + hpriv->irq_cause_ofs);
3379 /* and unmask interrupt generation for host regs */
3380 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3383 * enable only global host interrupts for now.
3384 * The per-port interrupts get done later as ports are set up.
3386 mv_set_main_irq_mask(host, 0, PCI_ERR);
3391 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3393 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3395 if (!hpriv->crqb_pool)
3398 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3400 if (!hpriv->crpb_pool)
3403 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3405 if (!hpriv->sg_tbl_pool)
3411 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3412 struct mbus_dram_target_info *dram)
3416 for (i = 0; i < 4; i++) {
3417 writel(0, hpriv->base + WINDOW_CTRL(i));
3418 writel(0, hpriv->base + WINDOW_BASE(i));
3421 for (i = 0; i < dram->num_cs; i++) {
3422 struct mbus_dram_window *cs = dram->cs + i;
3424 writel(((cs->size - 1) & 0xffff0000) |
3425 (cs->mbus_attr << 8) |
3426 (dram->mbus_dram_target_id << 4) | 1,
3427 hpriv->base + WINDOW_CTRL(i));
3428 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3433 * mv_platform_probe - handle a positive probe of an soc Marvell
3435 * @pdev: platform device found
3438 * Inherited from caller.
3440 static int mv_platform_probe(struct platform_device *pdev)
3442 static int printed_version;
3443 const struct mv_sata_platform_data *mv_platform_data;
3444 const struct ata_port_info *ppi[] =
3445 { &mv_port_info[chip_soc], NULL };
3446 struct ata_host *host;
3447 struct mv_host_priv *hpriv;
3448 struct resource *res;
3451 if (!printed_version++)
3452 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3455 * Simple resource validation ..
3457 if (unlikely(pdev->num_resources != 2)) {
3458 dev_err(&pdev->dev, "invalid number of resources\n");
3463 * Get the register base first
3465 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3470 mv_platform_data = pdev->dev.platform_data;
3471 n_ports = mv_platform_data->n_ports;
3473 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3474 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3476 if (!host || !hpriv)
3478 host->private_data = hpriv;
3479 hpriv->n_ports = n_ports;
3482 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3483 res->end - res->start + 1);
3484 hpriv->base -= MV_SATAHC0_REG_BASE;
3487 * (Re-)program MBUS remapping windows if we are asked to.
3489 if (mv_platform_data->dram != NULL)
3490 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3492 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3496 /* initialize adapter */
3497 rc = mv_init_host(host, chip_soc);
3501 dev_printk(KERN_INFO, &pdev->dev,
3502 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3505 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3506 IRQF_SHARED, &mv6_sht);
3511 * mv_platform_remove - unplug a platform interface
3512 * @pdev: platform device
3514 * A platform bus SATA device has been unplugged. Perform the needed
3515 * cleanup. Also called on module unload for any active devices.
3517 static int __devexit mv_platform_remove(struct platform_device *pdev)
3519 struct device *dev = &pdev->dev;
3520 struct ata_host *host = dev_get_drvdata(dev);
3522 ata_host_detach(host);
3526 static struct platform_driver mv_platform_driver = {
3527 .probe = mv_platform_probe,
3528 .remove = __devexit_p(mv_platform_remove),
3531 .owner = THIS_MODULE,
3537 static int mv_pci_init_one(struct pci_dev *pdev,
3538 const struct pci_device_id *ent);
3541 static struct pci_driver mv_pci_driver = {
3543 .id_table = mv_pci_tbl,
3544 .probe = mv_pci_init_one,
3545 .remove = ata_pci_remove_one,
3551 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3554 /* move to PCI layer or libata core? */
3555 static int pci_go_64(struct pci_dev *pdev)
3559 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3560 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3562 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3564 dev_printk(KERN_ERR, &pdev->dev,
3565 "64-bit DMA enable failed\n");
3570 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3572 dev_printk(KERN_ERR, &pdev->dev,
3573 "32-bit DMA enable failed\n");
3576 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3578 dev_printk(KERN_ERR, &pdev->dev,
3579 "32-bit consistent DMA enable failed\n");
3588 * mv_print_info - Dump key info to kernel log for perusal.
3589 * @host: ATA host to print info about
3591 * FIXME: complete this.
3594 * Inherited from caller.
3596 static void mv_print_info(struct ata_host *host)
3598 struct pci_dev *pdev = to_pci_dev(host->dev);
3599 struct mv_host_priv *hpriv = host->private_data;
3601 const char *scc_s, *gen;
3603 /* Use this to determine the HW stepping of the chip so we know
3604 * what errata to workaround
3606 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3609 else if (scc == 0x01)
3614 if (IS_GEN_I(hpriv))
3616 else if (IS_GEN_II(hpriv))
3618 else if (IS_GEN_IIE(hpriv))
3623 dev_printk(KERN_INFO, &pdev->dev,
3624 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3625 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3626 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3630 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3631 * @pdev: PCI device found
3632 * @ent: PCI device ID entry for the matched host
3635 * Inherited from caller.
3637 static int mv_pci_init_one(struct pci_dev *pdev,
3638 const struct pci_device_id *ent)
3640 static int printed_version;
3641 unsigned int board_idx = (unsigned int)ent->driver_data;
3642 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3643 struct ata_host *host;
3644 struct mv_host_priv *hpriv;
3647 if (!printed_version++)
3648 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3651 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3653 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3654 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3655 if (!host || !hpriv)
3657 host->private_data = hpriv;
3658 hpriv->n_ports = n_ports;
3660 /* acquire resources */
3661 rc = pcim_enable_device(pdev);
3665 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3667 pcim_pin_device(pdev);
3670 host->iomap = pcim_iomap_table(pdev);
3671 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3673 rc = pci_go_64(pdev);
3677 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3681 /* initialize adapter */
3682 rc = mv_init_host(host, board_idx);
3686 /* Enable message-switched interrupts, if requested */
3687 if (msi && pci_enable_msi(pdev) == 0)
3688 hpriv->hp_flags |= MV_HP_FLAG_MSI;
3690 mv_dump_pci_cfg(pdev, 0x68);
3691 mv_print_info(host);
3693 pci_set_master(pdev);
3694 pci_try_set_mwi(pdev);
3695 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3696 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3700 static int mv_platform_probe(struct platform_device *pdev);
3701 static int __devexit mv_platform_remove(struct platform_device *pdev);
3703 static int __init mv_init(void)
3707 rc = pci_register_driver(&mv_pci_driver);
3711 rc = platform_driver_register(&mv_platform_driver);
3715 pci_unregister_driver(&mv_pci_driver);
3720 static void __exit mv_exit(void)
3723 pci_unregister_driver(&mv_pci_driver);
3725 platform_driver_unregister(&mv_platform_driver);
3728 MODULE_AUTHOR("Brett Russ");
3729 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3730 MODULE_LICENSE("GPL");
3731 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3732 MODULE_VERSION(DRV_VERSION);
3733 MODULE_ALIAS("platform:" DRV_NAME);
3736 module_param(msi, int, 0444);
3737 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3740 module_init(mv_init);
3741 module_exit(mv_exit);