2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * --> Errata workaround for NCQ device errors.
30 * --> More errata workarounds for PCI-X.
32 * --> Complete a full errata audit for all chipsets to identify others.
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
40 * --> Develop a low-power-consumption strategy, and implement it.
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <scsi/scsi_host.h>
69 #include <scsi/scsi_cmnd.h>
70 #include <scsi/scsi_device.h>
71 #include <linux/libata.h>
73 #define DRV_NAME "sata_mv"
74 #define DRV_VERSION "1.20"
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
79 MV_IO_BAR = 2, /* offset 0x18: IO space */
80 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
86 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
87 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
88 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
89 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
90 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
93 MV_SATAHC0_REG_BASE = 0x20000,
94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG_OFS = 0x180d8,
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
116 MV_PORT_HC_SHIFT = 2,
117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
124 /* SoC integrated controllers, no PCI interface */
125 MV_FLAG_SOC = (1 << 28),
127 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
128 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
129 ATA_FLAG_PIO_POLLING,
130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
132 CRQB_FLAG_READ = (1 << 0),
134 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
135 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
141 CRPB_FLAG_STATUS_SHIFT = 8,
142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
147 /* PCI interface registers */
149 PCI_COMMAND_OFS = 0xc00,
150 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
152 PCI_MAIN_CMD_STS_OFS = 0xd30,
153 STOP_PCI_MASTER = (1 << 2),
154 PCI_MASTER_EMPTY = (1 << 3),
155 GLOB_SFT_RST = (1 << 4),
157 MV_PCI_MODE_OFS = 0xd00,
158 MV_PCI_MODE_MASK = 0x30,
160 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
161 MV_PCI_DISC_TIMER = 0xd04,
162 MV_PCI_MSI_TRIGGER = 0xc38,
163 MV_PCI_SERR_MASK = 0xc28,
164 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
165 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
166 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
167 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
168 MV_PCI_ERR_COMMAND = 0x1d50,
170 PCI_IRQ_CAUSE_OFS = 0x1d58,
171 PCI_IRQ_MASK_OFS = 0x1d5c,
172 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
174 PCIE_IRQ_CAUSE_OFS = 0x1900,
175 PCIE_IRQ_MASK_OFS = 0x1910,
176 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
178 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
179 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
180 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
181 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
182 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
183 ERR_IRQ = (1 << 0), /* shift by port # */
184 DONE_IRQ = (1 << 1), /* shift by port # */
185 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
186 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
188 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
189 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
190 PORTS_0_3_COAL_DONE = (1 << 8),
191 PORTS_4_7_COAL_DONE = (1 << 17),
192 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
193 GPIO_INT = (1 << 22),
194 SELF_INT = (1 << 23),
195 TWSI_INT = (1 << 24),
196 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
197 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
198 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
199 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
200 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
201 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
203 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
205 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
207 /* SATAHC registers */
210 HC_IRQ_CAUSE_OFS = 0x14,
211 DMA_IRQ = (1 << 0), /* shift by port # */
212 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
213 DEV_IRQ = (1 << 8), /* shift by port # */
215 /* Shadow block registers */
217 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
220 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
221 SATA_ACTIVE_OFS = 0x350,
222 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
230 SATA_IFCTL_OFS = 0x344,
231 SATA_TESTCTL_OFS = 0x348,
232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
244 MV_M2_PREAMP_MASK = 0x7e0,
248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
297 EDMA_ERR_LNK_CTRL_TX,
299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
335 EDMA_RSP_Q_PTR_SHIFT = 3,
337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
359 MV_HP_ERRATA_XX42A0 = (1 << 5),
360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
366 /* Port private flags (pp_flags) */
367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
369 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
372 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
373 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
374 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
375 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
376 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
378 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
379 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
382 /* DMA boundary 0xffff is required by the s/g splitting
383 * we need on /length/ in mv_fill-sg().
385 MV_DMA_BOUNDARY = 0xffffU,
387 /* mask of register bits containing lower 32 bits
388 * of EDMA request queue DMA address
390 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
392 /* ditto, for response queue */
393 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
407 /* Command ReQuest Block: 32B */
423 /* Command ResPonse Block: 8B */
430 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
438 struct mv_port_priv {
439 struct mv_crqb *crqb;
441 struct mv_crpb *crpb;
443 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
444 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
446 unsigned int req_idx;
447 unsigned int resp_idx;
452 struct mv_port_signal {
457 struct mv_host_priv {
459 struct mv_port_signal signal[8];
460 const struct mv_hw_ops *ops;
463 void __iomem *main_irq_cause_addr;
464 void __iomem *main_irq_mask_addr;
469 * These consistent DMA memory pools give us guaranteed
470 * alignment for hardware-accessed data structures,
471 * and less memory waste in accomplishing the alignment.
473 struct dma_pool *crqb_pool;
474 struct dma_pool *crpb_pool;
475 struct dma_pool *sg_tbl_pool;
479 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
481 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
482 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
484 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
486 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
487 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
490 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
491 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
492 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
493 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
494 static int mv_port_start(struct ata_port *ap);
495 static void mv_port_stop(struct ata_port *ap);
496 static int mv_qc_defer(struct ata_queued_cmd *qc);
497 static void mv_qc_prep(struct ata_queued_cmd *qc);
498 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
499 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
500 static int mv_hardreset(struct ata_link *link, unsigned int *class,
501 unsigned long deadline);
502 static void mv_eh_freeze(struct ata_port *ap);
503 static void mv_eh_thaw(struct ata_port *ap);
504 static void mv6_dev_config(struct ata_device *dev);
506 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
508 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
509 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
511 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
513 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
514 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
516 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
518 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
519 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
521 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
523 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
524 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
526 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
528 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
529 void __iomem *mmio, unsigned int n_hc);
530 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
532 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
533 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
534 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
535 unsigned int port_no);
536 static int mv_stop_edma(struct ata_port *ap);
537 static int mv_stop_edma_engine(void __iomem *port_mmio);
538 static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
540 static void mv_pmp_select(struct ata_port *ap, int pmp);
541 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
542 unsigned long deadline);
543 static int mv_softreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
546 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
547 * because we have to allow room for worst case splitting of
548 * PRDs for 64K boundaries in mv_fill_sg().
550 static struct scsi_host_template mv5_sht = {
551 ATA_BASE_SHT(DRV_NAME),
552 .sg_tablesize = MV_MAX_SG_CT / 2,
553 .dma_boundary = MV_DMA_BOUNDARY,
556 static struct scsi_host_template mv6_sht = {
557 ATA_NCQ_SHT(DRV_NAME),
558 .can_queue = MV_MAX_Q_DEPTH - 1,
559 .sg_tablesize = MV_MAX_SG_CT / 2,
560 .dma_boundary = MV_DMA_BOUNDARY,
563 static struct ata_port_operations mv5_ops = {
564 .inherits = &ata_sff_port_ops,
566 .qc_defer = mv_qc_defer,
567 .qc_prep = mv_qc_prep,
568 .qc_issue = mv_qc_issue,
570 .freeze = mv_eh_freeze,
572 .hardreset = mv_hardreset,
573 .error_handler = ata_std_error_handler, /* avoid SFF EH */
574 .post_internal_cmd = ATA_OP_NULL,
576 .scr_read = mv5_scr_read,
577 .scr_write = mv5_scr_write,
579 .port_start = mv_port_start,
580 .port_stop = mv_port_stop,
583 static struct ata_port_operations mv6_ops = {
584 .inherits = &mv5_ops,
585 .dev_config = mv6_dev_config,
586 .scr_read = mv_scr_read,
587 .scr_write = mv_scr_write,
589 .pmp_hardreset = mv_pmp_hardreset,
590 .pmp_softreset = mv_softreset,
591 .softreset = mv_softreset,
592 .error_handler = sata_pmp_error_handler,
595 static struct ata_port_operations mv_iie_ops = {
596 .inherits = &mv6_ops,
597 .dev_config = ATA_OP_NULL,
598 .qc_prep = mv_qc_prep_iie,
601 static const struct ata_port_info mv_port_info[] = {
603 .flags = MV_COMMON_FLAGS,
604 .pio_mask = 0x1f, /* pio0-4 */
605 .udma_mask = ATA_UDMA6,
606 .port_ops = &mv5_ops,
609 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
610 .pio_mask = 0x1f, /* pio0-4 */
611 .udma_mask = ATA_UDMA6,
612 .port_ops = &mv5_ops,
615 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
616 .pio_mask = 0x1f, /* pio0-4 */
617 .udma_mask = ATA_UDMA6,
618 .port_ops = &mv5_ops,
621 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
622 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
624 .pio_mask = 0x1f, /* pio0-4 */
625 .udma_mask = ATA_UDMA6,
626 .port_ops = &mv6_ops,
629 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
630 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
631 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
632 .pio_mask = 0x1f, /* pio0-4 */
633 .udma_mask = ATA_UDMA6,
634 .port_ops = &mv6_ops,
637 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
638 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
640 .pio_mask = 0x1f, /* pio0-4 */
641 .udma_mask = ATA_UDMA6,
642 .port_ops = &mv_iie_ops,
645 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
646 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
648 .pio_mask = 0x1f, /* pio0-4 */
649 .udma_mask = ATA_UDMA6,
650 .port_ops = &mv_iie_ops,
653 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
654 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
655 ATA_FLAG_NCQ | MV_FLAG_SOC,
656 .pio_mask = 0x1f, /* pio0-4 */
657 .udma_mask = ATA_UDMA6,
658 .port_ops = &mv_iie_ops,
662 static const struct pci_device_id mv_pci_tbl[] = {
663 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
665 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
666 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
667 /* RocketRAID 1740/174x have different identifiers */
668 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
669 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
671 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
673 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
674 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
675 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
677 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
680 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
682 /* Marvell 7042 support */
683 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
685 /* Highpoint RocketRAID PCIe series */
686 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
687 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
689 { } /* terminate list */
692 static const struct mv_hw_ops mv5xxx_ops = {
693 .phy_errata = mv5_phy_errata,
694 .enable_leds = mv5_enable_leds,
695 .read_preamp = mv5_read_preamp,
696 .reset_hc = mv5_reset_hc,
697 .reset_flash = mv5_reset_flash,
698 .reset_bus = mv5_reset_bus,
701 static const struct mv_hw_ops mv6xxx_ops = {
702 .phy_errata = mv6_phy_errata,
703 .enable_leds = mv6_enable_leds,
704 .read_preamp = mv6_read_preamp,
705 .reset_hc = mv6_reset_hc,
706 .reset_flash = mv6_reset_flash,
707 .reset_bus = mv_reset_pci_bus,
710 static const struct mv_hw_ops mv_soc_ops = {
711 .phy_errata = mv6_phy_errata,
712 .enable_leds = mv_soc_enable_leds,
713 .read_preamp = mv_soc_read_preamp,
714 .reset_hc = mv_soc_reset_hc,
715 .reset_flash = mv_soc_reset_flash,
716 .reset_bus = mv_soc_reset_bus,
723 static inline void writelfl(unsigned long data, void __iomem *addr)
726 (void) readl(addr); /* flush to avoid PCI posted write */
729 static inline unsigned int mv_hc_from_port(unsigned int port)
731 return port >> MV_PORT_HC_SHIFT;
734 static inline unsigned int mv_hardport_from_port(unsigned int port)
736 return port & MV_PORT_MASK;
740 * Consolidate some rather tricky bit shift calculations.
741 * This is hot-path stuff, so not a function.
742 * Simple code, with two return values, so macro rather than inline.
744 * port is the sole input, in range 0..7.
745 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
746 * hardport is the other output, in range 0..3.
748 * Note that port and hardport may be the same variable in some cases.
750 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
752 shift = mv_hc_from_port(port) * HC_SHIFT; \
753 hardport = mv_hardport_from_port(port); \
754 shift += hardport * 2; \
757 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
759 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
762 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
765 return mv_hc_base(base, mv_hc_from_port(port));
768 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
770 return mv_hc_base_from_port(base, port) +
771 MV_SATAHC_ARBTR_REG_SZ +
772 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
775 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
777 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
778 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
780 return hc_mmio + ofs;
783 static inline void __iomem *mv_host_base(struct ata_host *host)
785 struct mv_host_priv *hpriv = host->private_data;
789 static inline void __iomem *mv_ap_base(struct ata_port *ap)
791 return mv_port_base(mv_host_base(ap->host), ap->port_no);
794 static inline int mv_get_hc_count(unsigned long port_flags)
796 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
799 static void mv_set_edma_ptrs(void __iomem *port_mmio,
800 struct mv_host_priv *hpriv,
801 struct mv_port_priv *pp)
806 * initialize request queue
808 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
809 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
811 WARN_ON(pp->crqb_dma & 0x3ff);
812 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
813 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
814 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
816 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
817 writelfl((pp->crqb_dma & 0xffffffff) | index,
818 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
820 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
823 * initialize response queue
825 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
826 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
828 WARN_ON(pp->crpb_dma & 0xff);
829 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
831 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
832 writelfl((pp->crpb_dma & 0xffffffff) | index,
833 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
835 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
837 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
838 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
842 * mv_start_dma - Enable eDMA engine
843 * @base: port base address
844 * @pp: port private data
846 * Verify the local cache of the eDMA state is accurate with a
850 * Inherited from caller.
852 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
853 struct mv_port_priv *pp, u8 protocol)
855 int want_ncq = (protocol == ATA_PROT_NCQ);
857 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
858 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
859 if (want_ncq != using_ncq)
862 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
863 struct mv_host_priv *hpriv = ap->host->private_data;
864 int hardport = mv_hardport_from_port(ap->port_no);
865 void __iomem *hc_mmio = mv_hc_base_from_port(
866 mv_host_base(ap->host), hardport);
867 u32 hc_irq_cause, ipending;
869 /* clear EDMA event indicators, if any */
870 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
872 /* clear EDMA interrupt indicator, if any */
873 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
874 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
875 if (hc_irq_cause & ipending) {
876 writelfl(hc_irq_cause & ~ipending,
877 hc_mmio + HC_IRQ_CAUSE_OFS);
880 mv_edma_cfg(ap, want_ncq);
882 /* clear FIS IRQ Cause */
883 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
885 mv_set_edma_ptrs(port_mmio, hpriv, pp);
887 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
888 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
892 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
894 void __iomem *port_mmio = mv_ap_base(ap);
895 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
896 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
900 * Wait for the EDMA engine to finish transactions in progress.
902 for (i = 0; i < timeout; ++i) {
903 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
904 if ((edma_stat & empty_idle) == empty_idle)
908 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
912 * mv_stop_edma_engine - Disable eDMA engine
913 * @port_mmio: io base address
916 * Inherited from caller.
918 static int mv_stop_edma_engine(void __iomem *port_mmio)
922 /* Disable eDMA. The disable bit auto clears. */
923 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
925 /* Wait for the chip to confirm eDMA is off. */
926 for (i = 10000; i > 0; i--) {
927 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
928 if (!(reg & EDMA_EN))
935 static int mv_stop_edma(struct ata_port *ap)
937 void __iomem *port_mmio = mv_ap_base(ap);
938 struct mv_port_priv *pp = ap->private_data;
940 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
942 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
943 mv_wait_for_edma_empty_idle(ap);
944 if (mv_stop_edma_engine(port_mmio)) {
945 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
952 static void mv_dump_mem(void __iomem *start, unsigned bytes)
955 for (b = 0; b < bytes; ) {
956 DPRINTK("%p: ", start + b);
957 for (w = 0; b < bytes && w < 4; w++) {
958 printk("%08x ", readl(start + b));
966 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
971 for (b = 0; b < bytes; ) {
972 DPRINTK("%02x: ", b);
973 for (w = 0; b < bytes && w < 4; w++) {
974 (void) pci_read_config_dword(pdev, b, &dw);
982 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
983 struct pci_dev *pdev)
986 void __iomem *hc_base = mv_hc_base(mmio_base,
987 port >> MV_PORT_HC_SHIFT);
988 void __iomem *port_base;
989 int start_port, num_ports, p, start_hc, num_hcs, hc;
992 start_hc = start_port = 0;
993 num_ports = 8; /* shld be benign for 4 port devs */
996 start_hc = port >> MV_PORT_HC_SHIFT;
998 num_ports = num_hcs = 1;
1000 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1001 num_ports > 1 ? num_ports - 1 : start_port);
1004 DPRINTK("PCI config space regs:\n");
1005 mv_dump_pci_cfg(pdev, 0x68);
1007 DPRINTK("PCI regs:\n");
1008 mv_dump_mem(mmio_base+0xc00, 0x3c);
1009 mv_dump_mem(mmio_base+0xd00, 0x34);
1010 mv_dump_mem(mmio_base+0xf00, 0x4);
1011 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1012 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1013 hc_base = mv_hc_base(mmio_base, hc);
1014 DPRINTK("HC regs (HC %i):\n", hc);
1015 mv_dump_mem(hc_base, 0x1c);
1017 for (p = start_port; p < start_port + num_ports; p++) {
1018 port_base = mv_port_base(mmio_base, p);
1019 DPRINTK("EDMA regs (port %i):\n", p);
1020 mv_dump_mem(port_base, 0x54);
1021 DPRINTK("SATA regs (port %i):\n", p);
1022 mv_dump_mem(port_base+0x300, 0x60);
1027 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1031 switch (sc_reg_in) {
1035 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1038 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1047 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1049 unsigned int ofs = mv_scr_offset(sc_reg_in);
1051 if (ofs != 0xffffffffU) {
1052 *val = readl(mv_ap_base(ap) + ofs);
1058 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1060 unsigned int ofs = mv_scr_offset(sc_reg_in);
1062 if (ofs != 0xffffffffU) {
1063 writelfl(val, mv_ap_base(ap) + ofs);
1069 static void mv6_dev_config(struct ata_device *adev)
1072 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1074 * Gen-II does not support NCQ over a port multiplier
1075 * (no FIS-based switching).
1077 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1078 * See mv_qc_prep() for more info.
1080 if (adev->flags & ATA_DFLAG_NCQ) {
1081 if (sata_pmp_attached(adev->link->ap)) {
1082 adev->flags &= ~ATA_DFLAG_NCQ;
1083 ata_dev_printk(adev, KERN_INFO,
1084 "NCQ disabled for command-based switching\n");
1085 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1086 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1087 ata_dev_printk(adev, KERN_INFO,
1088 "max_sectors limited to %u for NCQ\n",
1094 static int mv_qc_defer(struct ata_queued_cmd *qc)
1096 struct ata_link *link = qc->dev->link;
1097 struct ata_port *ap = link->ap;
1098 struct mv_port_priv *pp = ap->private_data;
1101 * If the port is completely idle, then allow the new qc.
1103 if (ap->nr_active_links == 0)
1106 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1108 * The port is operating in host queuing mode (EDMA).
1109 * It can accomodate a new qc if the qc protocol
1110 * is compatible with the current host queue mode.
1112 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1114 * The host queue (EDMA) is in NCQ mode.
1115 * If the new qc is also an NCQ command,
1116 * then allow the new qc.
1118 if (qc->tf.protocol == ATA_PROT_NCQ)
1122 * The host queue (EDMA) is in non-NCQ, DMA mode.
1123 * If the new qc is also a non-NCQ, DMA command,
1124 * then allow the new qc.
1126 if (qc->tf.protocol == ATA_PROT_DMA)
1130 return ATA_DEFER_PORT;
1133 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
1135 u32 new_fiscfg, old_fiscfg;
1136 u32 new_ltmode, old_ltmode;
1137 u32 new_haltcond, old_haltcond;
1139 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1140 old_ltmode = readl(port_mmio + LTMODE_OFS);
1141 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1143 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1144 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1145 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1148 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1149 new_ltmode = old_ltmode | LTMODE_BIT8;
1152 if (new_fiscfg != old_fiscfg)
1153 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1154 if (new_ltmode != old_ltmode)
1155 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1156 if (new_haltcond != old_haltcond)
1157 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
1160 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1162 struct mv_host_priv *hpriv = ap->host->private_data;
1165 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1166 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1168 new = old | (1 << 22);
1170 new = old & ~(1 << 22);
1172 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1175 static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1178 struct mv_port_priv *pp = ap->private_data;
1179 struct mv_host_priv *hpriv = ap->host->private_data;
1180 void __iomem *port_mmio = mv_ap_base(ap);
1182 /* set up non-NCQ EDMA configuration */
1183 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1184 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
1186 if (IS_GEN_I(hpriv))
1187 cfg |= (1 << 8); /* enab config burst size mask */
1189 else if (IS_GEN_II(hpriv)) {
1190 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1191 mv_60x1_errata_sata25(ap, want_ncq);
1193 } else if (IS_GEN_IIE(hpriv)) {
1194 int want_fbs = sata_pmp_attached(ap);
1196 * Possible future enhancement:
1198 * The chip can use FBS with non-NCQ, if we allow it,
1199 * But first we need to have the error handling in place
1200 * for this mode (datasheet section 7.3.15.4.2.3).
1201 * So disallow non-NCQ FBS for now.
1203 want_fbs &= want_ncq;
1205 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1208 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1209 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1212 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1213 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1214 if (HAS_PCI(ap->host))
1215 cfg |= (1 << 18); /* enab early completion */
1216 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1217 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1221 cfg |= EDMA_CFG_NCQ;
1222 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1224 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1226 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1229 static void mv_port_free_dma_mem(struct ata_port *ap)
1231 struct mv_host_priv *hpriv = ap->host->private_data;
1232 struct mv_port_priv *pp = ap->private_data;
1236 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1240 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1244 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1245 * For later hardware, we have one unique sg_tbl per NCQ tag.
1247 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1248 if (pp->sg_tbl[tag]) {
1249 if (tag == 0 || !IS_GEN_I(hpriv))
1250 dma_pool_free(hpriv->sg_tbl_pool,
1252 pp->sg_tbl_dma[tag]);
1253 pp->sg_tbl[tag] = NULL;
1259 * mv_port_start - Port specific init/start routine.
1260 * @ap: ATA channel to manipulate
1262 * Allocate and point to DMA memory, init port private memory,
1266 * Inherited from caller.
1268 static int mv_port_start(struct ata_port *ap)
1270 struct device *dev = ap->host->dev;
1271 struct mv_host_priv *hpriv = ap->host->private_data;
1272 struct mv_port_priv *pp;
1275 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1278 ap->private_data = pp;
1280 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1283 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1285 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1287 goto out_port_free_dma_mem;
1288 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1291 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1292 * For later hardware, we need one unique sg_tbl per NCQ tag.
1294 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1295 if (tag == 0 || !IS_GEN_I(hpriv)) {
1296 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1297 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1298 if (!pp->sg_tbl[tag])
1299 goto out_port_free_dma_mem;
1301 pp->sg_tbl[tag] = pp->sg_tbl[0];
1302 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1307 out_port_free_dma_mem:
1308 mv_port_free_dma_mem(ap);
1313 * mv_port_stop - Port specific cleanup/stop routine.
1314 * @ap: ATA channel to manipulate
1316 * Stop DMA, cleanup port memory.
1319 * This routine uses the host lock to protect the DMA stop.
1321 static void mv_port_stop(struct ata_port *ap)
1324 mv_port_free_dma_mem(ap);
1328 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1329 * @qc: queued command whose SG list to source from
1331 * Populate the SG list and mark the last entry.
1334 * Inherited from caller.
1336 static void mv_fill_sg(struct ata_queued_cmd *qc)
1338 struct mv_port_priv *pp = qc->ap->private_data;
1339 struct scatterlist *sg;
1340 struct mv_sg *mv_sg, *last_sg = NULL;
1343 mv_sg = pp->sg_tbl[qc->tag];
1344 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1345 dma_addr_t addr = sg_dma_address(sg);
1346 u32 sg_len = sg_dma_len(sg);
1349 u32 offset = addr & 0xffff;
1352 if ((offset + sg_len > 0x10000))
1353 len = 0x10000 - offset;
1355 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1356 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1357 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1367 if (likely(last_sg))
1368 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1371 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1373 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1374 (last ? CRQB_CMD_LAST : 0);
1375 *cmdw = cpu_to_le16(tmp);
1379 * mv_qc_prep - Host specific command preparation.
1380 * @qc: queued command to prepare
1382 * This routine simply redirects to the general purpose routine
1383 * if command is not DMA. Else, it handles prep of the CRQB
1384 * (command request block), does some sanity checking, and calls
1385 * the SG load routine.
1388 * Inherited from caller.
1390 static void mv_qc_prep(struct ata_queued_cmd *qc)
1392 struct ata_port *ap = qc->ap;
1393 struct mv_port_priv *pp = ap->private_data;
1395 struct ata_taskfile *tf;
1399 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1400 (qc->tf.protocol != ATA_PROT_NCQ))
1403 /* Fill in command request block
1405 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1406 flags |= CRQB_FLAG_READ;
1407 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1408 flags |= qc->tag << CRQB_TAG_SHIFT;
1409 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1411 /* get current queue index from software */
1412 in_index = pp->req_idx;
1414 pp->crqb[in_index].sg_addr =
1415 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1416 pp->crqb[in_index].sg_addr_hi =
1417 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1418 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1420 cw = &pp->crqb[in_index].ata_cmd[0];
1423 /* Sadly, the CRQB cannot accomodate all registers--there are
1424 * only 11 bytes...so we must pick and choose required
1425 * registers based on the command. So, we drop feature and
1426 * hob_feature for [RW] DMA commands, but they are needed for
1427 * NCQ. NCQ will drop hob_nsect.
1429 switch (tf->command) {
1431 case ATA_CMD_READ_EXT:
1433 case ATA_CMD_WRITE_EXT:
1434 case ATA_CMD_WRITE_FUA_EXT:
1435 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1437 case ATA_CMD_FPDMA_READ:
1438 case ATA_CMD_FPDMA_WRITE:
1439 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1440 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1443 /* The only other commands EDMA supports in non-queued and
1444 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1445 * of which are defined/used by Linux. If we get here, this
1446 * driver needs work.
1448 * FIXME: modify libata to give qc_prep a return value and
1449 * return error here.
1451 BUG_ON(tf->command);
1454 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1455 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1456 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1457 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1458 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1459 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1460 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1461 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1462 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1464 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1470 * mv_qc_prep_iie - Host specific command preparation.
1471 * @qc: queued command to prepare
1473 * This routine simply redirects to the general purpose routine
1474 * if command is not DMA. Else, it handles prep of the CRQB
1475 * (command request block), does some sanity checking, and calls
1476 * the SG load routine.
1479 * Inherited from caller.
1481 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1483 struct ata_port *ap = qc->ap;
1484 struct mv_port_priv *pp = ap->private_data;
1485 struct mv_crqb_iie *crqb;
1486 struct ata_taskfile *tf;
1490 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1491 (qc->tf.protocol != ATA_PROT_NCQ))
1494 /* Fill in Gen IIE command request block */
1495 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1496 flags |= CRQB_FLAG_READ;
1498 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1499 flags |= qc->tag << CRQB_TAG_SHIFT;
1500 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1501 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1503 /* get current queue index from software */
1504 in_index = pp->req_idx;
1506 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1507 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1508 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1509 crqb->flags = cpu_to_le32(flags);
1512 crqb->ata_cmd[0] = cpu_to_le32(
1513 (tf->command << 16) |
1516 crqb->ata_cmd[1] = cpu_to_le32(
1522 crqb->ata_cmd[2] = cpu_to_le32(
1523 (tf->hob_lbal << 0) |
1524 (tf->hob_lbam << 8) |
1525 (tf->hob_lbah << 16) |
1526 (tf->hob_feature << 24)
1528 crqb->ata_cmd[3] = cpu_to_le32(
1530 (tf->hob_nsect << 8)
1533 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1539 * mv_qc_issue - Initiate a command to the host
1540 * @qc: queued command to start
1542 * This routine simply redirects to the general purpose routine
1543 * if command is not DMA. Else, it sanity checks our local
1544 * caches of the request producer/consumer indices then enables
1545 * DMA and bumps the request producer index.
1548 * Inherited from caller.
1550 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1552 struct ata_port *ap = qc->ap;
1553 void __iomem *port_mmio = mv_ap_base(ap);
1554 struct mv_port_priv *pp = ap->private_data;
1557 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1558 (qc->tf.protocol != ATA_PROT_NCQ)) {
1560 * We're about to send a non-EDMA capable command to the
1561 * port. Turn off EDMA so there won't be problems accessing
1562 * shadow block, etc registers.
1565 mv_pmp_select(ap, qc->dev->link->pmp);
1566 return ata_sff_qc_issue(qc);
1569 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
1571 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1572 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1574 /* and write the request in pointer to kick the EDMA to life */
1575 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1576 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1581 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1583 struct mv_port_priv *pp = ap->private_data;
1584 struct ata_queued_cmd *qc;
1586 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1588 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1589 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1594 static void mv_unexpected_intr(struct ata_port *ap)
1596 struct mv_port_priv *pp = ap->private_data;
1597 struct ata_eh_info *ehi = &ap->link.eh_info;
1601 * We got a device interrupt from something that
1602 * was supposed to be using EDMA or polling.
1604 ata_ehi_clear_desc(ehi);
1605 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1606 when = " while EDMA enabled";
1608 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1609 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1610 when = " while polling";
1612 ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when);
1613 ehi->err_mask |= AC_ERR_OTHER;
1614 ehi->action |= ATA_EH_RESET;
1615 ata_port_freeze(ap);
1619 * mv_err_intr - Handle error interrupts on the port
1620 * @ap: ATA channel to manipulate
1621 * @qc: affected command (non-NCQ), or NULL
1623 * Most cases require a full reset of the chip's state machine,
1624 * which also performs a COMRESET.
1625 * Also, if the port disabled DMA, update our cached copy to match.
1628 * Inherited from caller.
1630 static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1632 void __iomem *port_mmio = mv_ap_base(ap);
1633 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1634 struct mv_port_priv *pp = ap->private_data;
1635 struct mv_host_priv *hpriv = ap->host->private_data;
1636 unsigned int action = 0, err_mask = 0;
1637 struct ata_eh_info *ehi = &ap->link.eh_info;
1639 ata_ehi_clear_desc(ehi);
1642 * Read and clear the err_cause bits. This won't actually
1643 * clear for some errors (eg. SError), but we will be doing
1644 * a hard reset in those cases regardless, which *will* clear it.
1646 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1647 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1649 ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause);
1652 * All generations share these EDMA error cause bits:
1654 if (edma_err_cause & EDMA_ERR_DEV)
1655 err_mask |= AC_ERR_DEV;
1656 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1657 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1658 EDMA_ERR_INTRL_PAR)) {
1659 err_mask |= AC_ERR_ATA_BUS;
1660 action |= ATA_EH_RESET;
1661 ata_ehi_push_desc(ehi, "parity error");
1663 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1664 ata_ehi_hotplugged(ehi);
1665 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
1666 "dev disconnect" : "dev connect");
1667 action |= ATA_EH_RESET;
1671 * Gen-I has a different SELF_DIS bit,
1672 * different FREEZE bits, and no SERR bit:
1674 if (IS_GEN_I(hpriv)) {
1675 eh_freeze_mask = EDMA_EH_FREEZE_5;
1676 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1677 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1678 ata_ehi_push_desc(ehi, "EDMA self-disable");
1681 eh_freeze_mask = EDMA_EH_FREEZE;
1682 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1683 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1684 ata_ehi_push_desc(ehi, "EDMA self-disable");
1686 if (edma_err_cause & EDMA_ERR_SERR) {
1688 * Ensure that we read our own SCR, not a pmp link SCR:
1690 ap->ops->scr_read(ap, SCR_ERROR, &serr);
1692 * Don't clear SError here; leave it for libata-eh:
1694 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1695 err_mask |= AC_ERR_ATA_BUS;
1696 action |= ATA_EH_RESET;
1701 err_mask = AC_ERR_OTHER;
1702 action |= ATA_EH_RESET;
1705 ehi->serror |= serr;
1706 ehi->action |= action;
1709 qc->err_mask |= err_mask;
1711 ehi->err_mask |= err_mask;
1713 if (edma_err_cause & eh_freeze_mask)
1714 ata_port_freeze(ap);
1719 static void mv_process_crpb_response(struct ata_port *ap,
1720 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1722 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1726 u16 edma_status = le16_to_cpu(response->flags);
1728 * edma_status from a response queue entry:
1729 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1730 * MSB is saved ATA status from command completion.
1733 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1736 * Error will be seen/handled by mv_err_intr().
1737 * So do nothing at all here.
1742 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1743 qc->err_mask |= ac_err_mask(ata_status);
1744 ata_qc_complete(qc);
1746 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1751 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
1753 void __iomem *port_mmio = mv_ap_base(ap);
1754 struct mv_host_priv *hpriv = ap->host->private_data;
1756 bool work_done = false;
1757 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
1759 /* Get the hardware queue position index */
1760 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1761 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1763 /* Process new responses from since the last time we looked */
1764 while (in_index != pp->resp_idx) {
1766 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
1768 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1770 if (IS_GEN_I(hpriv)) {
1771 /* 50xx: no NCQ, only one command active at a time */
1772 tag = ap->link.active_tag;
1774 /* Gen II/IIE: get command tag from CRPB entry */
1775 tag = le16_to_cpu(response->id) & 0x1f;
1777 mv_process_crpb_response(ap, response, tag, ncq_enabled);
1781 /* Update the software queue position index in hardware */
1783 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
1784 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
1785 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1789 * mv_host_intr - Handle all interrupts on the given host controller
1790 * @host: host specific structure
1791 * @main_irq_cause: Main interrupt cause register for the chip.
1794 * Inherited from caller.
1796 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
1798 struct mv_host_priv *hpriv = host->private_data;
1799 void __iomem *mmio = hpriv->base, *hc_mmio = NULL;
1800 u32 hc_irq_cause = 0;
1801 unsigned int handled = 0, port;
1803 for (port = 0; port < hpriv->n_ports; port++) {
1804 struct ata_port *ap = host->ports[port];
1805 struct mv_port_priv *pp;
1806 unsigned int shift, hardport, port_cause;
1808 * When we move to the second hc, flag our cached
1809 * copies of hc_mmio (and hc_irq_cause) as invalid again.
1811 if (port == MV_PORTS_PER_HC)
1814 * Do nothing if port is not interrupting or is disabled:
1816 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1817 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
1818 if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED))
1821 * Each hc within the host has its own hc_irq_cause register.
1822 * We defer reading it until we know we need it, right now:
1824 * FIXME later: we don't really need to read this register
1825 * (some logic changes required below if we go that way),
1826 * because it doesn't tell us anything new. But we do need
1827 * to write to it, outside the top of this loop,
1828 * to reset the interrupt triggers for next time.
1831 hc_mmio = mv_hc_base_from_port(mmio, port);
1832 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1833 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1837 * Process completed CRPB response(s) before other events.
1839 pp = ap->private_data;
1840 if (hc_irq_cause & (DMA_IRQ << hardport)) {
1841 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN)
1842 mv_process_crpb_entries(ap, pp);
1845 * Handle chip-reported errors, or continue on to handle PIO.
1847 if (unlikely(port_cause & ERR_IRQ)) {
1848 mv_err_intr(ap, mv_get_active_qc(ap));
1849 } else if (hc_irq_cause & (DEV_IRQ << hardport)) {
1850 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1851 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
1853 ata_sff_host_intr(ap, qc);
1857 mv_unexpected_intr(ap);
1863 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
1865 struct mv_host_priv *hpriv = host->private_data;
1866 struct ata_port *ap;
1867 struct ata_queued_cmd *qc;
1868 struct ata_eh_info *ehi;
1869 unsigned int i, err_mask, printed = 0;
1872 err_cause = readl(mmio + hpriv->irq_cause_ofs);
1874 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
1877 DPRINTK("All regs @ PCI error\n");
1878 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1880 writelfl(0, mmio + hpriv->irq_cause_ofs);
1882 for (i = 0; i < host->n_ports; i++) {
1883 ap = host->ports[i];
1884 if (!ata_link_offline(&ap->link)) {
1885 ehi = &ap->link.eh_info;
1886 ata_ehi_clear_desc(ehi);
1888 ata_ehi_push_desc(ehi,
1889 "PCI err cause 0x%08x", err_cause);
1890 err_mask = AC_ERR_HOST_BUS;
1891 ehi->action = ATA_EH_RESET;
1892 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1894 qc->err_mask |= err_mask;
1896 ehi->err_mask |= err_mask;
1898 ata_port_freeze(ap);
1901 return 1; /* handled */
1905 * mv_interrupt - Main interrupt event handler
1907 * @dev_instance: private data; in this case the host structure
1909 * Read the read only register to determine if any host
1910 * controllers have pending interrupts. If so, call lower level
1911 * routine to handle. Also check for PCI errors which are only
1915 * This routine holds the host lock while processing pending
1918 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1920 struct ata_host *host = dev_instance;
1921 struct mv_host_priv *hpriv = host->private_data;
1922 unsigned int handled = 0;
1923 u32 main_irq_cause, main_irq_mask;
1925 spin_lock(&host->lock);
1926 main_irq_cause = readl(hpriv->main_irq_cause_addr);
1927 main_irq_mask = readl(hpriv->main_irq_mask_addr);
1929 * Deal with cases where we either have nothing pending, or have read
1930 * a bogus register value which can indicate HW removal or PCI fault.
1932 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
1933 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
1934 handled = mv_pci_error(host, hpriv->base);
1936 handled = mv_host_intr(host, main_irq_cause);
1938 spin_unlock(&host->lock);
1939 return IRQ_RETVAL(handled);
1942 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1946 switch (sc_reg_in) {
1950 ofs = sc_reg_in * sizeof(u32);
1959 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1961 struct mv_host_priv *hpriv = ap->host->private_data;
1962 void __iomem *mmio = hpriv->base;
1963 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1964 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1966 if (ofs != 0xffffffffU) {
1967 *val = readl(addr + ofs);
1973 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1975 struct mv_host_priv *hpriv = ap->host->private_data;
1976 void __iomem *mmio = hpriv->base;
1977 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1978 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1980 if (ofs != 0xffffffffU) {
1981 writelfl(val, addr + ofs);
1987 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
1989 struct pci_dev *pdev = to_pci_dev(host->dev);
1992 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
1995 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1997 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2000 mv_reset_pci_bus(host, mmio);
2003 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2005 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2008 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2011 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2014 tmp = readl(phy_mmio + MV5_PHY_MODE);
2016 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2017 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2020 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2024 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2026 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2028 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2030 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2033 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2036 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2037 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2039 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2042 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2044 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2046 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2049 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2052 tmp = readl(phy_mmio + MV5_PHY_MODE);
2054 tmp |= hpriv->signal[port].pre;
2055 tmp |= hpriv->signal[port].amps;
2056 writel(tmp, phy_mmio + MV5_PHY_MODE);
2061 #define ZERO(reg) writel(0, port_mmio + (reg))
2062 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2065 void __iomem *port_mmio = mv_port_base(mmio, port);
2067 mv_reset_channel(hpriv, mmio, port);
2069 ZERO(0x028); /* command */
2070 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2071 ZERO(0x004); /* timer */
2072 ZERO(0x008); /* irq err cause */
2073 ZERO(0x00c); /* irq err mask */
2074 ZERO(0x010); /* rq bah */
2075 ZERO(0x014); /* rq inp */
2076 ZERO(0x018); /* rq outp */
2077 ZERO(0x01c); /* respq bah */
2078 ZERO(0x024); /* respq outp */
2079 ZERO(0x020); /* respq inp */
2080 ZERO(0x02c); /* test control */
2081 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2085 #define ZERO(reg) writel(0, hc_mmio + (reg))
2086 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2089 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2097 tmp = readl(hc_mmio + 0x20);
2100 writel(tmp, hc_mmio + 0x20);
2104 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2107 unsigned int hc, port;
2109 for (hc = 0; hc < n_hc; hc++) {
2110 for (port = 0; port < MV_PORTS_PER_HC; port++)
2111 mv5_reset_hc_port(hpriv, mmio,
2112 (hc * MV_PORTS_PER_HC) + port);
2114 mv5_reset_one_hc(hpriv, mmio, hc);
2121 #define ZERO(reg) writel(0, mmio + (reg))
2122 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2124 struct mv_host_priv *hpriv = host->private_data;
2127 tmp = readl(mmio + MV_PCI_MODE_OFS);
2129 writel(tmp, mmio + MV_PCI_MODE_OFS);
2131 ZERO(MV_PCI_DISC_TIMER);
2132 ZERO(MV_PCI_MSI_TRIGGER);
2133 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2134 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
2135 ZERO(MV_PCI_SERR_MASK);
2136 ZERO(hpriv->irq_cause_ofs);
2137 ZERO(hpriv->irq_mask_ofs);
2138 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2139 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2140 ZERO(MV_PCI_ERR_ATTRIBUTE);
2141 ZERO(MV_PCI_ERR_COMMAND);
2145 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2149 mv5_reset_flash(hpriv, mmio);
2151 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2153 tmp |= (1 << 5) | (1 << 6);
2154 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2158 * mv6_reset_hc - Perform the 6xxx global soft reset
2159 * @mmio: base address of the HBA
2161 * This routine only applies to 6xxx parts.
2164 * Inherited from caller.
2166 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2169 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2173 /* Following procedure defined in PCI "main command and status
2177 writel(t | STOP_PCI_MASTER, reg);
2179 for (i = 0; i < 1000; i++) {
2182 if (PCI_MASTER_EMPTY & t)
2185 if (!(PCI_MASTER_EMPTY & t)) {
2186 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2194 writel(t | GLOB_SFT_RST, reg);
2197 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2199 if (!(GLOB_SFT_RST & t)) {
2200 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2205 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2208 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2211 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2213 if (GLOB_SFT_RST & t) {
2214 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2221 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2224 void __iomem *port_mmio;
2227 tmp = readl(mmio + MV_RESET_CFG_OFS);
2228 if ((tmp & (1 << 0)) == 0) {
2229 hpriv->signal[idx].amps = 0x7 << 8;
2230 hpriv->signal[idx].pre = 0x1 << 5;
2234 port_mmio = mv_port_base(mmio, idx);
2235 tmp = readl(port_mmio + PHY_MODE2);
2237 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2238 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2241 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2243 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2246 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2249 void __iomem *port_mmio = mv_port_base(mmio, port);
2251 u32 hp_flags = hpriv->hp_flags;
2253 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2255 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2258 if (fix_phy_mode2) {
2259 m2 = readl(port_mmio + PHY_MODE2);
2262 writel(m2, port_mmio + PHY_MODE2);
2266 m2 = readl(port_mmio + PHY_MODE2);
2267 m2 &= ~((1 << 16) | (1 << 31));
2268 writel(m2, port_mmio + PHY_MODE2);
2273 /* who knows what this magic does */
2274 tmp = readl(port_mmio + PHY_MODE3);
2277 writel(tmp, port_mmio + PHY_MODE3);
2279 if (fix_phy_mode4) {
2282 m4 = readl(port_mmio + PHY_MODE4);
2284 if (hp_flags & MV_HP_ERRATA_60X1B2)
2285 tmp = readl(port_mmio + PHY_MODE3);
2287 /* workaround for errata FEr SATA#10 (part 1) */
2288 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2290 writel(m4, port_mmio + PHY_MODE4);
2292 if (hp_flags & MV_HP_ERRATA_60X1B2)
2293 writel(tmp, port_mmio + PHY_MODE3);
2296 /* Revert values of pre-emphasis and signal amps to the saved ones */
2297 m2 = readl(port_mmio + PHY_MODE2);
2299 m2 &= ~MV_M2_PREAMP_MASK;
2300 m2 |= hpriv->signal[port].amps;
2301 m2 |= hpriv->signal[port].pre;
2304 /* according to mvSata 3.6.1, some IIE values are fixed */
2305 if (IS_GEN_IIE(hpriv)) {
2310 writel(m2, port_mmio + PHY_MODE2);
2313 /* TODO: use the generic LED interface to configure the SATA Presence */
2314 /* & Acitivy LEDs on the board */
2315 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2321 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2324 void __iomem *port_mmio;
2327 port_mmio = mv_port_base(mmio, idx);
2328 tmp = readl(port_mmio + PHY_MODE2);
2330 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2331 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2335 #define ZERO(reg) writel(0, port_mmio + (reg))
2336 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2337 void __iomem *mmio, unsigned int port)
2339 void __iomem *port_mmio = mv_port_base(mmio, port);
2341 mv_reset_channel(hpriv, mmio, port);
2343 ZERO(0x028); /* command */
2344 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2345 ZERO(0x004); /* timer */
2346 ZERO(0x008); /* irq err cause */
2347 ZERO(0x00c); /* irq err mask */
2348 ZERO(0x010); /* rq bah */
2349 ZERO(0x014); /* rq inp */
2350 ZERO(0x018); /* rq outp */
2351 ZERO(0x01c); /* respq bah */
2352 ZERO(0x024); /* respq outp */
2353 ZERO(0x020); /* respq inp */
2354 ZERO(0x02c); /* test control */
2355 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2360 #define ZERO(reg) writel(0, hc_mmio + (reg))
2361 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2364 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2374 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2375 void __iomem *mmio, unsigned int n_hc)
2379 for (port = 0; port < hpriv->n_ports; port++)
2380 mv_soc_reset_hc_port(hpriv, mmio, port);
2382 mv_soc_reset_one_hc(hpriv, mmio);
2387 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2393 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2398 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2400 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2402 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2404 ifcfg |= (1 << 7); /* enable gen2i speed */
2405 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2408 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2409 unsigned int port_no)
2411 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2414 * The datasheet warns against setting EDMA_RESET when EDMA is active
2415 * (but doesn't say what the problem might be). So we first try
2416 * to disable the EDMA engine before doing the EDMA_RESET operation.
2418 mv_stop_edma_engine(port_mmio);
2419 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2421 if (!IS_GEN_I(hpriv)) {
2422 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2423 mv_setup_ifcfg(port_mmio, 1);
2426 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2427 * link, and physical layers. It resets all SATA interface registers
2428 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2430 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2431 udelay(25); /* allow reset propagation */
2432 writelfl(0, port_mmio + EDMA_CMD_OFS);
2434 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2436 if (IS_GEN_I(hpriv))
2440 static void mv_pmp_select(struct ata_port *ap, int pmp)
2442 if (sata_pmp_supported(ap)) {
2443 void __iomem *port_mmio = mv_ap_base(ap);
2444 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2445 int old = reg & 0xf;
2448 reg = (reg & ~0xf) | pmp;
2449 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2454 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2455 unsigned long deadline)
2457 mv_pmp_select(link->ap, sata_srst_pmp(link));
2458 return sata_std_hardreset(link, class, deadline);
2461 static int mv_softreset(struct ata_link *link, unsigned int *class,
2462 unsigned long deadline)
2464 mv_pmp_select(link->ap, sata_srst_pmp(link));
2465 return ata_sff_softreset(link, class, deadline);
2468 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2469 unsigned long deadline)
2471 struct ata_port *ap = link->ap;
2472 struct mv_host_priv *hpriv = ap->host->private_data;
2473 struct mv_port_priv *pp = ap->private_data;
2474 void __iomem *mmio = hpriv->base;
2475 int rc, attempts = 0, extra = 0;
2479 mv_reset_channel(hpriv, mmio, ap->port_no);
2480 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2482 /* Workaround for errata FEr SATA#10 (part 2) */
2484 const unsigned long *timing =
2485 sata_ehc_deb_timing(&link->eh_context);
2487 rc = sata_link_hardreset(link, timing, deadline + extra,
2491 sata_scr_read(link, SCR_STATUS, &sstatus);
2492 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2493 /* Force 1.5gb/s link speed and try again */
2494 mv_setup_ifcfg(mv_ap_base(ap), 0);
2495 if (time_after(jiffies + HZ, deadline))
2496 extra = HZ; /* only extend it once, max */
2498 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
2503 static void mv_eh_freeze(struct ata_port *ap)
2505 struct mv_host_priv *hpriv = ap->host->private_data;
2506 unsigned int shift, hardport, port = ap->port_no;
2509 /* FIXME: handle coalescing completion events properly */
2512 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2514 /* disable assertion of portN err, done events */
2515 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2516 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2517 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2520 static void mv_eh_thaw(struct ata_port *ap)
2522 struct mv_host_priv *hpriv = ap->host->private_data;
2523 unsigned int shift, hardport, port = ap->port_no;
2524 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2525 void __iomem *port_mmio = mv_ap_base(ap);
2526 u32 main_irq_mask, hc_irq_cause;
2528 /* FIXME: handle coalescing completion events properly */
2530 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2532 /* clear EDMA errors on this port */
2533 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2535 /* clear pending irq events */
2536 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
2537 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2538 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2540 /* enable assertion of portN err, done events */
2541 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2542 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2543 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2547 * mv_port_init - Perform some early initialization on a single port.
2548 * @port: libata data structure storing shadow register addresses
2549 * @port_mmio: base address of the port
2551 * Initialize shadow register mmio addresses, clear outstanding
2552 * interrupts on the port, and unmask interrupts for the future
2553 * start of the port.
2556 * Inherited from caller.
2558 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2560 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2563 /* PIO related setup
2565 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2567 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2568 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2569 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2570 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2571 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2572 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2574 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2575 /* special case: control/altstatus doesn't have ATA_REG_ address */
2576 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2579 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2581 /* Clear any currently outstanding port interrupt conditions */
2582 serr_ofs = mv_scr_offset(SCR_ERROR);
2583 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2584 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2586 /* unmask all non-transient EDMA error interrupts */
2587 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2589 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2590 readl(port_mmio + EDMA_CFG_OFS),
2591 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2592 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2595 static unsigned int mv_in_pcix_mode(struct ata_host *host)
2597 struct mv_host_priv *hpriv = host->private_data;
2598 void __iomem *mmio = hpriv->base;
2601 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2602 return 0; /* not PCI-X capable */
2603 reg = readl(mmio + MV_PCI_MODE_OFS);
2604 if ((reg & MV_PCI_MODE_MASK) == 0)
2605 return 0; /* conventional PCI mode */
2606 return 1; /* chip is in PCI-X mode */
2609 static int mv_pci_cut_through_okay(struct ata_host *host)
2611 struct mv_host_priv *hpriv = host->private_data;
2612 void __iomem *mmio = hpriv->base;
2615 if (!mv_in_pcix_mode(host)) {
2616 reg = readl(mmio + PCI_COMMAND_OFS);
2617 if (reg & PCI_COMMAND_MRDTRIG)
2618 return 0; /* not okay */
2620 return 1; /* okay */
2623 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2625 struct pci_dev *pdev = to_pci_dev(host->dev);
2626 struct mv_host_priv *hpriv = host->private_data;
2627 u32 hp_flags = hpriv->hp_flags;
2629 switch (board_idx) {
2631 hpriv->ops = &mv5xxx_ops;
2632 hp_flags |= MV_HP_GEN_I;
2634 switch (pdev->revision) {
2636 hp_flags |= MV_HP_ERRATA_50XXB0;
2639 hp_flags |= MV_HP_ERRATA_50XXB2;
2642 dev_printk(KERN_WARNING, &pdev->dev,
2643 "Applying 50XXB2 workarounds to unknown rev\n");
2644 hp_flags |= MV_HP_ERRATA_50XXB2;
2651 hpriv->ops = &mv5xxx_ops;
2652 hp_flags |= MV_HP_GEN_I;
2654 switch (pdev->revision) {
2656 hp_flags |= MV_HP_ERRATA_50XXB0;
2659 hp_flags |= MV_HP_ERRATA_50XXB2;
2662 dev_printk(KERN_WARNING, &pdev->dev,
2663 "Applying B2 workarounds to unknown rev\n");
2664 hp_flags |= MV_HP_ERRATA_50XXB2;
2671 hpriv->ops = &mv6xxx_ops;
2672 hp_flags |= MV_HP_GEN_II;
2674 switch (pdev->revision) {
2676 hp_flags |= MV_HP_ERRATA_60X1B2;
2679 hp_flags |= MV_HP_ERRATA_60X1C0;
2682 dev_printk(KERN_WARNING, &pdev->dev,
2683 "Applying B2 workarounds to unknown rev\n");
2684 hp_flags |= MV_HP_ERRATA_60X1B2;
2690 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
2691 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2692 (pdev->device == 0x2300 || pdev->device == 0x2310))
2695 * Highpoint RocketRAID PCIe 23xx series cards:
2697 * Unconfigured drives are treated as "Legacy"
2698 * by the BIOS, and it overwrites sector 8 with
2699 * a "Lgcy" metadata block prior to Linux boot.
2701 * Configured drives (RAID or JBOD) leave sector 8
2702 * alone, but instead overwrite a high numbered
2703 * sector for the RAID metadata. This sector can
2704 * be determined exactly, by truncating the physical
2705 * drive capacity to a nice even GB value.
2707 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2709 * Warn the user, lest they think we're just buggy.
2711 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2712 " BIOS CORRUPTS DATA on all attached drives,"
2713 " regardless of if/how they are configured."
2715 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2716 " use sectors 8-9 on \"Legacy\" drives,"
2717 " and avoid the final two gigabytes on"
2718 " all RocketRAID BIOS initialized drives.\n");
2722 hpriv->ops = &mv6xxx_ops;
2723 hp_flags |= MV_HP_GEN_IIE;
2724 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2725 hp_flags |= MV_HP_CUT_THROUGH;
2727 switch (pdev->revision) {
2729 hp_flags |= MV_HP_ERRATA_XX42A0;
2732 hp_flags |= MV_HP_ERRATA_60X1C0;
2735 dev_printk(KERN_WARNING, &pdev->dev,
2736 "Applying 60X1C0 workarounds to unknown rev\n");
2737 hp_flags |= MV_HP_ERRATA_60X1C0;
2742 hpriv->ops = &mv_soc_ops;
2743 hp_flags |= MV_HP_ERRATA_60X1C0;
2747 dev_printk(KERN_ERR, host->dev,
2748 "BUG: invalid board index %u\n", board_idx);
2752 hpriv->hp_flags = hp_flags;
2753 if (hp_flags & MV_HP_PCIE) {
2754 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
2755 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
2756 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
2758 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
2759 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
2760 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
2767 * mv_init_host - Perform some early initialization of the host.
2768 * @host: ATA host to initialize
2769 * @board_idx: controller index
2771 * If possible, do an early global reset of the host. Then do
2772 * our port init and clear/unmask all/relevant host interrupts.
2775 * Inherited from caller.
2777 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
2779 int rc = 0, n_hc, port, hc;
2780 struct mv_host_priv *hpriv = host->private_data;
2781 void __iomem *mmio = hpriv->base;
2783 rc = mv_chip_id(host, board_idx);
2787 if (HAS_PCI(host)) {
2788 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
2789 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
2791 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
2792 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
2795 /* global interrupt mask: 0 == mask everything */
2796 writel(0, hpriv->main_irq_mask_addr);
2798 n_hc = mv_get_hc_count(host->ports[0]->flags);
2800 for (port = 0; port < host->n_ports; port++)
2801 hpriv->ops->read_preamp(hpriv, port, mmio);
2803 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2807 hpriv->ops->reset_flash(hpriv, mmio);
2808 hpriv->ops->reset_bus(host, mmio);
2809 hpriv->ops->enable_leds(hpriv, mmio);
2811 for (port = 0; port < host->n_ports; port++) {
2812 struct ata_port *ap = host->ports[port];
2813 void __iomem *port_mmio = mv_port_base(mmio, port);
2815 mv_port_init(&ap->ioaddr, port_mmio);
2818 if (HAS_PCI(host)) {
2819 unsigned int offset = port_mmio - mmio;
2820 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
2821 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
2826 for (hc = 0; hc < n_hc; hc++) {
2827 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2829 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2830 "(before clear)=0x%08x\n", hc,
2831 readl(hc_mmio + HC_CFG_OFS),
2832 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2834 /* Clear any currently outstanding hc interrupt conditions */
2835 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2838 if (HAS_PCI(host)) {
2839 /* Clear any currently outstanding host interrupt conditions */
2840 writelfl(0, mmio + hpriv->irq_cause_ofs);
2842 /* and unmask interrupt generation for host regs */
2843 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
2844 if (IS_GEN_I(hpriv))
2845 writelfl(~HC_MAIN_MASKED_IRQS_5,
2846 hpriv->main_irq_mask_addr);
2848 writelfl(~HC_MAIN_MASKED_IRQS,
2849 hpriv->main_irq_mask_addr);
2851 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2852 "PCI int cause/mask=0x%08x/0x%08x\n",
2853 readl(hpriv->main_irq_cause_addr),
2854 readl(hpriv->main_irq_mask_addr),
2855 readl(mmio + hpriv->irq_cause_ofs),
2856 readl(mmio + hpriv->irq_mask_ofs));
2858 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
2859 hpriv->main_irq_mask_addr);
2860 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
2861 readl(hpriv->main_irq_cause_addr),
2862 readl(hpriv->main_irq_mask_addr));
2868 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
2870 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
2872 if (!hpriv->crqb_pool)
2875 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
2877 if (!hpriv->crpb_pool)
2880 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
2882 if (!hpriv->sg_tbl_pool)
2888 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
2889 struct mbus_dram_target_info *dram)
2893 for (i = 0; i < 4; i++) {
2894 writel(0, hpriv->base + WINDOW_CTRL(i));
2895 writel(0, hpriv->base + WINDOW_BASE(i));
2898 for (i = 0; i < dram->num_cs; i++) {
2899 struct mbus_dram_window *cs = dram->cs + i;
2901 writel(((cs->size - 1) & 0xffff0000) |
2902 (cs->mbus_attr << 8) |
2903 (dram->mbus_dram_target_id << 4) | 1,
2904 hpriv->base + WINDOW_CTRL(i));
2905 writel(cs->base, hpriv->base + WINDOW_BASE(i));
2910 * mv_platform_probe - handle a positive probe of an soc Marvell
2912 * @pdev: platform device found
2915 * Inherited from caller.
2917 static int mv_platform_probe(struct platform_device *pdev)
2919 static int printed_version;
2920 const struct mv_sata_platform_data *mv_platform_data;
2921 const struct ata_port_info *ppi[] =
2922 { &mv_port_info[chip_soc], NULL };
2923 struct ata_host *host;
2924 struct mv_host_priv *hpriv;
2925 struct resource *res;
2928 if (!printed_version++)
2929 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2932 * Simple resource validation ..
2934 if (unlikely(pdev->num_resources != 2)) {
2935 dev_err(&pdev->dev, "invalid number of resources\n");
2940 * Get the register base first
2942 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2947 mv_platform_data = pdev->dev.platform_data;
2948 n_ports = mv_platform_data->n_ports;
2950 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2951 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2953 if (!host || !hpriv)
2955 host->private_data = hpriv;
2956 hpriv->n_ports = n_ports;
2959 hpriv->base = devm_ioremap(&pdev->dev, res->start,
2960 res->end - res->start + 1);
2961 hpriv->base -= MV_SATAHC0_REG_BASE;
2964 * (Re-)program MBUS remapping windows if we are asked to.
2966 if (mv_platform_data->dram != NULL)
2967 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
2969 rc = mv_create_dma_pools(hpriv, &pdev->dev);
2973 /* initialize adapter */
2974 rc = mv_init_host(host, chip_soc);
2978 dev_printk(KERN_INFO, &pdev->dev,
2979 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
2982 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
2983 IRQF_SHARED, &mv6_sht);
2988 * mv_platform_remove - unplug a platform interface
2989 * @pdev: platform device
2991 * A platform bus SATA device has been unplugged. Perform the needed
2992 * cleanup. Also called on module unload for any active devices.
2994 static int __devexit mv_platform_remove(struct platform_device *pdev)
2996 struct device *dev = &pdev->dev;
2997 struct ata_host *host = dev_get_drvdata(dev);
2999 ata_host_detach(host);
3003 static struct platform_driver mv_platform_driver = {
3004 .probe = mv_platform_probe,
3005 .remove = __devexit_p(mv_platform_remove),
3008 .owner = THIS_MODULE,
3014 static int mv_pci_init_one(struct pci_dev *pdev,
3015 const struct pci_device_id *ent);
3018 static struct pci_driver mv_pci_driver = {
3020 .id_table = mv_pci_tbl,
3021 .probe = mv_pci_init_one,
3022 .remove = ata_pci_remove_one,
3028 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3031 /* move to PCI layer or libata core? */
3032 static int pci_go_64(struct pci_dev *pdev)
3036 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3037 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3039 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3041 dev_printk(KERN_ERR, &pdev->dev,
3042 "64-bit DMA enable failed\n");
3047 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3049 dev_printk(KERN_ERR, &pdev->dev,
3050 "32-bit DMA enable failed\n");
3053 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3055 dev_printk(KERN_ERR, &pdev->dev,
3056 "32-bit consistent DMA enable failed\n");
3065 * mv_print_info - Dump key info to kernel log for perusal.
3066 * @host: ATA host to print info about
3068 * FIXME: complete this.
3071 * Inherited from caller.
3073 static void mv_print_info(struct ata_host *host)
3075 struct pci_dev *pdev = to_pci_dev(host->dev);
3076 struct mv_host_priv *hpriv = host->private_data;
3078 const char *scc_s, *gen;
3080 /* Use this to determine the HW stepping of the chip so we know
3081 * what errata to workaround
3083 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3086 else if (scc == 0x01)
3091 if (IS_GEN_I(hpriv))
3093 else if (IS_GEN_II(hpriv))
3095 else if (IS_GEN_IIE(hpriv))
3100 dev_printk(KERN_INFO, &pdev->dev,
3101 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3102 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3103 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3107 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3108 * @pdev: PCI device found
3109 * @ent: PCI device ID entry for the matched host
3112 * Inherited from caller.
3114 static int mv_pci_init_one(struct pci_dev *pdev,
3115 const struct pci_device_id *ent)
3117 static int printed_version;
3118 unsigned int board_idx = (unsigned int)ent->driver_data;
3119 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3120 struct ata_host *host;
3121 struct mv_host_priv *hpriv;
3124 if (!printed_version++)
3125 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3128 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3130 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3131 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3132 if (!host || !hpriv)
3134 host->private_data = hpriv;
3135 hpriv->n_ports = n_ports;
3137 /* acquire resources */
3138 rc = pcim_enable_device(pdev);
3142 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3144 pcim_pin_device(pdev);
3147 host->iomap = pcim_iomap_table(pdev);
3148 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3150 rc = pci_go_64(pdev);
3154 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3158 /* initialize adapter */
3159 rc = mv_init_host(host, board_idx);
3163 /* Enable interrupts */
3164 if (msi && pci_enable_msi(pdev))
3167 mv_dump_pci_cfg(pdev, 0x68);
3168 mv_print_info(host);
3170 pci_set_master(pdev);
3171 pci_try_set_mwi(pdev);
3172 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3173 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3177 static int mv_platform_probe(struct platform_device *pdev);
3178 static int __devexit mv_platform_remove(struct platform_device *pdev);
3180 static int __init mv_init(void)
3184 rc = pci_register_driver(&mv_pci_driver);
3188 rc = platform_driver_register(&mv_platform_driver);
3192 pci_unregister_driver(&mv_pci_driver);
3197 static void __exit mv_exit(void)
3200 pci_unregister_driver(&mv_pci_driver);
3202 platform_driver_unregister(&mv_platform_driver);
3205 MODULE_AUTHOR("Brett Russ");
3206 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3207 MODULE_LICENSE("GPL");
3208 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3209 MODULE_VERSION(DRV_VERSION);
3210 MODULE_ALIAS("platform:" DRV_NAME);
3213 module_param(msi, int, 0444);
3214 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3217 module_init(mv_init);
3218 module_exit(mv_exit);