2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * --> More errata workarounds for PCI-X.
33 * --> Complete a full errata audit for all chipsets to identify others.
35 * --> Develop a low-power-consumption strategy, and implement it.
37 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
39 * --> [Experiment, Marvell value added] Is it possible to use target
40 * mode to cross-connect two Linux boxes with Marvell cards? If so,
41 * creating LibATA target mode support would be very interesting.
43 * Target mode, for those without docs, is the ability to directly
44 * connect two SATA ports.
47 #include <linux/kernel.h>
48 #include <linux/module.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51 #include <linux/blkdev.h>
52 #include <linux/delay.h>
53 #include <linux/interrupt.h>
54 #include <linux/dmapool.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/device.h>
57 #include <linux/platform_device.h>
58 #include <linux/ata_platform.h>
59 #include <linux/mbus.h>
60 #include <linux/bitops.h>
61 #include <scsi/scsi_host.h>
62 #include <scsi/scsi_cmnd.h>
63 #include <scsi/scsi_device.h>
64 #include <linux/libata.h>
66 #define DRV_NAME "sata_mv"
67 #define DRV_VERSION "1.27"
75 module_param(msi, int, S_IRUGO);
76 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
79 static int irq_coalescing_io_count;
80 module_param(irq_coalescing_io_count, int, S_IRUGO);
81 MODULE_PARM_DESC(irq_coalescing_io_count,
82 "IRQ coalescing I/O count threshold (0..255)");
84 static int irq_coalescing_usecs;
85 module_param(irq_coalescing_usecs, int, S_IRUGO);
86 MODULE_PARM_DESC(irq_coalescing_usecs,
87 "IRQ coalescing time threshold in usecs");
90 /* BAR's are enumerated in terms of pci_resource_start() terms */
91 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
92 MV_IO_BAR = 2, /* offset 0x18: IO space */
93 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
95 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
96 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
98 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
99 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
100 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
101 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
106 * Per-chip ("all ports") interrupt coalescing feature.
107 * This is only for GEN_II / GEN_IIE hardware.
109 * Coalescing defers the interrupt until either the IO_THRESHOLD
110 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
112 MV_COAL_REG_BASE = 0x18000,
113 MV_IRQ_COAL_CAUSE = (MV_COAL_REG_BASE + 0x08),
114 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
116 MV_IRQ_COAL_IO_THRESHOLD = (MV_COAL_REG_BASE + 0xcc),
117 MV_IRQ_COAL_TIME_THRESHOLD = (MV_COAL_REG_BASE + 0xd0),
120 * Registers for the (unused here) transaction coalescing feature:
122 MV_TRAN_COAL_CAUSE_LO = (MV_COAL_REG_BASE + 0x88),
123 MV_TRAN_COAL_CAUSE_HI = (MV_COAL_REG_BASE + 0x8c),
125 MV_SATAHC0_REG_BASE = 0x20000,
126 MV_FLASH_CTL_OFS = 0x1046c,
127 MV_GPIO_PORT_CTL_OFS = 0x104f0,
128 MV_RESET_CFG_OFS = 0x180d8,
130 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
131 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
132 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
133 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
136 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
138 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
139 * CRPB needs alignment on a 256B boundary. Size == 256B
140 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
142 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
143 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
145 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
147 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
148 MV_PORT_HC_SHIFT = 2,
149 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
150 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
151 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
154 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
156 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
157 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
159 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
161 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
162 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
164 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
166 CRQB_FLAG_READ = (1 << 0),
168 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
169 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
170 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
171 CRQB_CMD_ADDR_SHIFT = 8,
172 CRQB_CMD_CS = (0x2 << 11),
173 CRQB_CMD_LAST = (1 << 15),
175 CRPB_FLAG_STATUS_SHIFT = 8,
176 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
177 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
179 EPRD_FLAG_END_OF_TBL = (1 << 31),
181 /* PCI interface registers */
183 PCI_COMMAND_OFS = 0xc00,
184 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
186 PCI_MAIN_CMD_STS_OFS = 0xd30,
187 STOP_PCI_MASTER = (1 << 2),
188 PCI_MASTER_EMPTY = (1 << 3),
189 GLOB_SFT_RST = (1 << 4),
191 MV_PCI_MODE_OFS = 0xd00,
192 MV_PCI_MODE_MASK = 0x30,
194 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
195 MV_PCI_DISC_TIMER = 0xd04,
196 MV_PCI_MSI_TRIGGER = 0xc38,
197 MV_PCI_SERR_MASK = 0xc28,
198 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
199 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
200 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
201 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
202 MV_PCI_ERR_COMMAND = 0x1d50,
204 PCI_IRQ_CAUSE_OFS = 0x1d58,
205 PCI_IRQ_MASK_OFS = 0x1d5c,
206 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
208 PCIE_IRQ_CAUSE_OFS = 0x1900,
209 PCIE_IRQ_MASK_OFS = 0x1910,
210 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
212 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
213 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
214 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
215 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
216 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
217 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
218 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
219 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
220 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
221 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
222 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
224 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
225 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
226 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
227 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
228 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
229 GPIO_INT = (1 << 22),
230 SELF_INT = (1 << 23),
231 TWSI_INT = (1 << 24),
232 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
233 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
234 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
236 /* SATAHC registers */
239 HC_IRQ_CAUSE_OFS = 0x14,
240 DMA_IRQ = (1 << 0), /* shift by port # */
241 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
242 DEV_IRQ = (1 << 8), /* shift by port # */
245 * Per-HC (Host-Controller) interrupt coalescing feature.
246 * This is present on all chip generations.
248 * Coalescing defers the interrupt until either the IO_THRESHOLD
249 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
251 HC_IRQ_COAL_IO_THRESHOLD_OFS = 0x000c,
252 HC_IRQ_COAL_TIME_THRESHOLD_OFS = 0x0010,
254 SOC_LED_CTRL_OFS = 0x2c,
255 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
256 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
257 /* with dev activity LED */
259 /* Shadow block registers */
261 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
264 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
265 SATA_ACTIVE_OFS = 0x350,
266 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
267 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
270 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
274 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
275 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
276 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
277 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
280 SATA_IFCTL_OFS = 0x344,
281 SATA_TESTCTL_OFS = 0x348,
282 SATA_IFSTAT_OFS = 0x34c,
283 VENDOR_UNIQUE_FIS_OFS = 0x35c,
286 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
287 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
290 MV5_LTMODE_OFS = 0x30,
291 MV5_PHY_CTL_OFS = 0x0C,
292 SATA_INTERFACE_CFG_OFS = 0x050,
294 MV_M2_PREAMP_MASK = 0x7e0,
298 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
299 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
300 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
301 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
302 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
303 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
304 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
306 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
307 EDMA_ERR_IRQ_MASK_OFS = 0xc,
308 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
309 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
310 EDMA_ERR_DEV = (1 << 2), /* device error */
311 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
312 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
313 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
314 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
315 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
316 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
317 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
318 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
319 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
320 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
321 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
323 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
324 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
325 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
326 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
327 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
329 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
331 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
332 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
333 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
334 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
335 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
336 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
338 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
340 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
341 EDMA_ERR_OVERRUN_5 = (1 << 5),
342 EDMA_ERR_UNDERRUN_5 = (1 << 6),
344 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
345 EDMA_ERR_LNK_CTRL_RX_1 |
346 EDMA_ERR_LNK_CTRL_RX_3 |
347 EDMA_ERR_LNK_CTRL_TX,
349 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
359 EDMA_ERR_LNK_CTRL_RX_2 |
360 EDMA_ERR_LNK_DATA_RX |
361 EDMA_ERR_LNK_DATA_TX |
362 EDMA_ERR_TRANS_PROTO,
364 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
369 EDMA_ERR_UNDERRUN_5 |
370 EDMA_ERR_SELF_DIS_5 |
376 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
377 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
379 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
380 EDMA_REQ_Q_PTR_SHIFT = 5,
382 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
383 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
384 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
385 EDMA_RSP_Q_PTR_SHIFT = 3,
387 EDMA_CMD_OFS = 0x28, /* EDMA command register */
388 EDMA_EN = (1 << 0), /* enable EDMA */
389 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
390 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
392 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
393 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
394 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
396 EDMA_IORDY_TMOUT_OFS = 0x34,
397 EDMA_ARB_CFG_OFS = 0x38,
399 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
400 EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */
402 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
403 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
404 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
405 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
407 /* Host private flags (hp_flags) */
408 MV_HP_FLAG_MSI = (1 << 0),
409 MV_HP_ERRATA_50XXB0 = (1 << 1),
410 MV_HP_ERRATA_50XXB2 = (1 << 2),
411 MV_HP_ERRATA_60X1B2 = (1 << 3),
412 MV_HP_ERRATA_60X1C0 = (1 << 4),
413 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
414 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
415 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
416 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
417 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
418 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
419 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
421 /* Port private flags (pp_flags) */
422 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
423 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
424 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
425 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
426 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
429 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
430 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
431 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
432 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
433 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
435 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
436 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
439 /* DMA boundary 0xffff is required by the s/g splitting
440 * we need on /length/ in mv_fill-sg().
442 MV_DMA_BOUNDARY = 0xffffU,
444 /* mask of register bits containing lower 32 bits
445 * of EDMA request queue DMA address
447 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
449 /* ditto, for response queue */
450 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
464 /* Command ReQuest Block: 32B */
480 /* Command ResPonse Block: 8B */
487 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
496 * We keep a local cache of a few frequently accessed port
497 * registers here, to avoid having to read them (very slow)
498 * when switching between EDMA and non-EDMA modes.
500 struct mv_cached_regs {
507 struct mv_port_priv {
508 struct mv_crqb *crqb;
510 struct mv_crpb *crpb;
512 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
513 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
515 unsigned int req_idx;
516 unsigned int resp_idx;
519 struct mv_cached_regs cached;
520 unsigned int delayed_eh_pmp_map;
523 struct mv_port_signal {
528 struct mv_host_priv {
531 struct mv_port_signal signal[8];
532 const struct mv_hw_ops *ops;
535 void __iomem *main_irq_cause_addr;
536 void __iomem *main_irq_mask_addr;
541 * These consistent DMA memory pools give us guaranteed
542 * alignment for hardware-accessed data structures,
543 * and less memory waste in accomplishing the alignment.
545 struct dma_pool *crqb_pool;
546 struct dma_pool *crpb_pool;
547 struct dma_pool *sg_tbl_pool;
551 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
553 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
554 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
556 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
558 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
559 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
562 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
563 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
564 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
565 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
566 static int mv_port_start(struct ata_port *ap);
567 static void mv_port_stop(struct ata_port *ap);
568 static int mv_qc_defer(struct ata_queued_cmd *qc);
569 static void mv_qc_prep(struct ata_queued_cmd *qc);
570 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
571 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
572 static int mv_hardreset(struct ata_link *link, unsigned int *class,
573 unsigned long deadline);
574 static void mv_eh_freeze(struct ata_port *ap);
575 static void mv_eh_thaw(struct ata_port *ap);
576 static void mv6_dev_config(struct ata_device *dev);
578 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
580 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
581 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
583 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
585 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
586 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
588 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
590 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
591 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
593 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
595 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
596 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
598 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
600 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
601 void __iomem *mmio, unsigned int n_hc);
602 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
604 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
605 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
606 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
607 unsigned int port_no);
608 static int mv_stop_edma(struct ata_port *ap);
609 static int mv_stop_edma_engine(void __iomem *port_mmio);
610 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
612 static void mv_pmp_select(struct ata_port *ap, int pmp);
613 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
614 unsigned long deadline);
615 static int mv_softreset(struct ata_link *link, unsigned int *class,
616 unsigned long deadline);
617 static void mv_pmp_error_handler(struct ata_port *ap);
618 static void mv_process_crpb_entries(struct ata_port *ap,
619 struct mv_port_priv *pp);
621 static void mv_sff_irq_clear(struct ata_port *ap);
622 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
623 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
624 static void mv_bmdma_start(struct ata_queued_cmd *qc);
625 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
626 static u8 mv_bmdma_status(struct ata_port *ap);
627 static u8 mv_sff_check_status(struct ata_port *ap);
629 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
630 * because we have to allow room for worst case splitting of
631 * PRDs for 64K boundaries in mv_fill_sg().
633 static struct scsi_host_template mv5_sht = {
634 ATA_BASE_SHT(DRV_NAME),
635 .sg_tablesize = MV_MAX_SG_CT / 2,
636 .dma_boundary = MV_DMA_BOUNDARY,
639 static struct scsi_host_template mv6_sht = {
640 ATA_NCQ_SHT(DRV_NAME),
641 .can_queue = MV_MAX_Q_DEPTH - 1,
642 .sg_tablesize = MV_MAX_SG_CT / 2,
643 .dma_boundary = MV_DMA_BOUNDARY,
646 static struct ata_port_operations mv5_ops = {
647 .inherits = &ata_sff_port_ops,
649 .lost_interrupt = ATA_OP_NULL,
651 .qc_defer = mv_qc_defer,
652 .qc_prep = mv_qc_prep,
653 .qc_issue = mv_qc_issue,
655 .freeze = mv_eh_freeze,
657 .hardreset = mv_hardreset,
658 .error_handler = ata_std_error_handler, /* avoid SFF EH */
659 .post_internal_cmd = ATA_OP_NULL,
661 .scr_read = mv5_scr_read,
662 .scr_write = mv5_scr_write,
664 .port_start = mv_port_start,
665 .port_stop = mv_port_stop,
668 static struct ata_port_operations mv6_ops = {
669 .inherits = &mv5_ops,
670 .dev_config = mv6_dev_config,
671 .scr_read = mv_scr_read,
672 .scr_write = mv_scr_write,
674 .pmp_hardreset = mv_pmp_hardreset,
675 .pmp_softreset = mv_softreset,
676 .softreset = mv_softreset,
677 .error_handler = mv_pmp_error_handler,
679 .sff_check_status = mv_sff_check_status,
680 .sff_irq_clear = mv_sff_irq_clear,
681 .check_atapi_dma = mv_check_atapi_dma,
682 .bmdma_setup = mv_bmdma_setup,
683 .bmdma_start = mv_bmdma_start,
684 .bmdma_stop = mv_bmdma_stop,
685 .bmdma_status = mv_bmdma_status,
688 static struct ata_port_operations mv_iie_ops = {
689 .inherits = &mv6_ops,
690 .dev_config = ATA_OP_NULL,
691 .qc_prep = mv_qc_prep_iie,
694 static const struct ata_port_info mv_port_info[] = {
696 .flags = MV_GEN_I_FLAGS,
697 .pio_mask = ATA_PIO4,
698 .udma_mask = ATA_UDMA6,
699 .port_ops = &mv5_ops,
702 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
703 .pio_mask = ATA_PIO4,
704 .udma_mask = ATA_UDMA6,
705 .port_ops = &mv5_ops,
708 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
709 .pio_mask = ATA_PIO4,
710 .udma_mask = ATA_UDMA6,
711 .port_ops = &mv5_ops,
714 .flags = MV_GEN_II_FLAGS,
715 .pio_mask = ATA_PIO4,
716 .udma_mask = ATA_UDMA6,
717 .port_ops = &mv6_ops,
720 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
721 .pio_mask = ATA_PIO4,
722 .udma_mask = ATA_UDMA6,
723 .port_ops = &mv6_ops,
726 .flags = MV_GEN_IIE_FLAGS,
727 .pio_mask = ATA_PIO4,
728 .udma_mask = ATA_UDMA6,
729 .port_ops = &mv_iie_ops,
732 .flags = MV_GEN_IIE_FLAGS,
733 .pio_mask = ATA_PIO4,
734 .udma_mask = ATA_UDMA6,
735 .port_ops = &mv_iie_ops,
738 .flags = MV_GEN_IIE_FLAGS,
739 .pio_mask = ATA_PIO4,
740 .udma_mask = ATA_UDMA6,
741 .port_ops = &mv_iie_ops,
745 static const struct pci_device_id mv_pci_tbl[] = {
746 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
747 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
748 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
749 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
750 /* RocketRAID 1720/174x have different identifiers */
751 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
752 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
753 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
755 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
756 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
757 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
758 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
759 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
761 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
764 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
766 /* Marvell 7042 support */
767 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
769 /* Highpoint RocketRAID PCIe series */
770 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
771 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
773 { } /* terminate list */
776 static const struct mv_hw_ops mv5xxx_ops = {
777 .phy_errata = mv5_phy_errata,
778 .enable_leds = mv5_enable_leds,
779 .read_preamp = mv5_read_preamp,
780 .reset_hc = mv5_reset_hc,
781 .reset_flash = mv5_reset_flash,
782 .reset_bus = mv5_reset_bus,
785 static const struct mv_hw_ops mv6xxx_ops = {
786 .phy_errata = mv6_phy_errata,
787 .enable_leds = mv6_enable_leds,
788 .read_preamp = mv6_read_preamp,
789 .reset_hc = mv6_reset_hc,
790 .reset_flash = mv6_reset_flash,
791 .reset_bus = mv_reset_pci_bus,
794 static const struct mv_hw_ops mv_soc_ops = {
795 .phy_errata = mv6_phy_errata,
796 .enable_leds = mv_soc_enable_leds,
797 .read_preamp = mv_soc_read_preamp,
798 .reset_hc = mv_soc_reset_hc,
799 .reset_flash = mv_soc_reset_flash,
800 .reset_bus = mv_soc_reset_bus,
807 static inline void writelfl(unsigned long data, void __iomem *addr)
810 (void) readl(addr); /* flush to avoid PCI posted write */
813 static inline unsigned int mv_hc_from_port(unsigned int port)
815 return port >> MV_PORT_HC_SHIFT;
818 static inline unsigned int mv_hardport_from_port(unsigned int port)
820 return port & MV_PORT_MASK;
824 * Consolidate some rather tricky bit shift calculations.
825 * This is hot-path stuff, so not a function.
826 * Simple code, with two return values, so macro rather than inline.
828 * port is the sole input, in range 0..7.
829 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
830 * hardport is the other output, in range 0..3.
832 * Note that port and hardport may be the same variable in some cases.
834 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
836 shift = mv_hc_from_port(port) * HC_SHIFT; \
837 hardport = mv_hardport_from_port(port); \
838 shift += hardport * 2; \
841 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
843 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
846 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
849 return mv_hc_base(base, mv_hc_from_port(port));
852 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
854 return mv_hc_base_from_port(base, port) +
855 MV_SATAHC_ARBTR_REG_SZ +
856 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
859 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
861 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
862 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
864 return hc_mmio + ofs;
867 static inline void __iomem *mv_host_base(struct ata_host *host)
869 struct mv_host_priv *hpriv = host->private_data;
873 static inline void __iomem *mv_ap_base(struct ata_port *ap)
875 return mv_port_base(mv_host_base(ap->host), ap->port_no);
878 static inline int mv_get_hc_count(unsigned long port_flags)
880 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
884 * mv_save_cached_regs - (re-)initialize cached port registers
885 * @ap: the port whose registers we are caching
887 * Initialize the local cache of port registers,
888 * so that reading them over and over again can
889 * be avoided on the hotter paths of this driver.
890 * This saves a few microseconds each time we switch
891 * to/from EDMA mode to perform (eg.) a drive cache flush.
893 static void mv_save_cached_regs(struct ata_port *ap)
895 void __iomem *port_mmio = mv_ap_base(ap);
896 struct mv_port_priv *pp = ap->private_data;
898 pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS);
899 pp->cached.ltmode = readl(port_mmio + LTMODE_OFS);
900 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
901 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS);
905 * mv_write_cached_reg - write to a cached port register
906 * @addr: hardware address of the register
907 * @old: pointer to cached value of the register
908 * @new: new value for the register
910 * Write a new value to a cached register,
911 * but only if the value is different from before.
913 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
921 static void mv_set_edma_ptrs(void __iomem *port_mmio,
922 struct mv_host_priv *hpriv,
923 struct mv_port_priv *pp)
928 * initialize request queue
930 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
931 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
933 WARN_ON(pp->crqb_dma & 0x3ff);
934 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
935 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
936 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
937 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
940 * initialize response queue
942 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
943 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
945 WARN_ON(pp->crpb_dma & 0xff);
946 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
947 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
948 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
949 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
952 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
955 * When writing to the main_irq_mask in hardware,
956 * we must ensure exclusivity between the interrupt coalescing bits
957 * and the corresponding individual port DONE_IRQ bits.
959 * Note that this register is really an "IRQ enable" register,
960 * not an "IRQ mask" register as Marvell's naming might suggest.
962 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
963 mask &= ~DONE_IRQ_0_3;
964 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
965 mask &= ~DONE_IRQ_4_7;
966 writelfl(mask, hpriv->main_irq_mask_addr);
969 static void mv_set_main_irq_mask(struct ata_host *host,
970 u32 disable_bits, u32 enable_bits)
972 struct mv_host_priv *hpriv = host->private_data;
973 u32 old_mask, new_mask;
975 old_mask = hpriv->main_irq_mask;
976 new_mask = (old_mask & ~disable_bits) | enable_bits;
977 if (new_mask != old_mask) {
978 hpriv->main_irq_mask = new_mask;
979 mv_write_main_irq_mask(new_mask, hpriv);
983 static void mv_enable_port_irqs(struct ata_port *ap,
984 unsigned int port_bits)
986 unsigned int shift, hardport, port = ap->port_no;
987 u32 disable_bits, enable_bits;
989 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
991 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
992 enable_bits = port_bits << shift;
993 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
996 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
997 void __iomem *port_mmio,
998 unsigned int port_irqs)
1000 struct mv_host_priv *hpriv = ap->host->private_data;
1001 int hardport = mv_hardport_from_port(ap->port_no);
1002 void __iomem *hc_mmio = mv_hc_base_from_port(
1003 mv_host_base(ap->host), ap->port_no);
1006 /* clear EDMA event indicators, if any */
1007 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1009 /* clear pending irq events */
1010 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1011 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1013 /* clear FIS IRQ Cause */
1014 if (IS_GEN_IIE(hpriv))
1015 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1017 mv_enable_port_irqs(ap, port_irqs);
1020 static void mv_set_irq_coalescing(struct ata_host *host,
1021 unsigned int count, unsigned int usecs)
1023 struct mv_host_priv *hpriv = host->private_data;
1024 void __iomem *mmio = hpriv->base, *hc_mmio;
1025 u32 coal_enable = 0;
1026 unsigned long flags;
1027 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1028 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1029 ALL_PORTS_COAL_DONE;
1031 /* Disable IRQ coalescing if either threshold is zero */
1032 if (!usecs || !count) {
1035 /* Respect maximum limits of the hardware */
1036 clks = usecs * COAL_CLOCKS_PER_USEC;
1037 if (clks > MAX_COAL_TIME_THRESHOLD)
1038 clks = MAX_COAL_TIME_THRESHOLD;
1039 if (count > MAX_COAL_IO_COUNT)
1040 count = MAX_COAL_IO_COUNT;
1043 spin_lock_irqsave(&host->lock, flags);
1044 mv_set_main_irq_mask(host, coal_disable, 0);
1046 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1048 * GEN_II/GEN_IIE with dual host controllers:
1049 * one set of global thresholds for the entire chip.
1051 writel(clks, mmio + MV_IRQ_COAL_TIME_THRESHOLD);
1052 writel(count, mmio + MV_IRQ_COAL_IO_THRESHOLD);
1053 /* clear leftover coal IRQ bit */
1054 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
1056 coal_enable = ALL_PORTS_COAL_DONE;
1057 clks = count = 0; /* force clearing of regular regs below */
1061 * All chips: independent thresholds for each HC on the chip.
1063 hc_mmio = mv_hc_base_from_port(mmio, 0);
1064 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1065 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
1066 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1068 coal_enable |= PORTS_0_3_COAL_DONE;
1070 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1071 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1072 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
1073 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1075 coal_enable |= PORTS_4_7_COAL_DONE;
1078 mv_set_main_irq_mask(host, 0, coal_enable);
1079 spin_unlock_irqrestore(&host->lock, flags);
1083 * mv_start_edma - Enable eDMA engine
1084 * @base: port base address
1085 * @pp: port private data
1087 * Verify the local cache of the eDMA state is accurate with a
1091 * Inherited from caller.
1093 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1094 struct mv_port_priv *pp, u8 protocol)
1096 int want_ncq = (protocol == ATA_PROT_NCQ);
1098 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1099 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1100 if (want_ncq != using_ncq)
1103 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1104 struct mv_host_priv *hpriv = ap->host->private_data;
1106 mv_edma_cfg(ap, want_ncq, 1);
1108 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1109 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1111 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
1112 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1116 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1118 void __iomem *port_mmio = mv_ap_base(ap);
1119 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1120 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1124 * Wait for the EDMA engine to finish transactions in progress.
1125 * No idea what a good "timeout" value might be, but measurements
1126 * indicate that it often requires hundreds of microseconds
1127 * with two drives in-use. So we use the 15msec value above
1128 * as a rough guess at what even more drives might require.
1130 for (i = 0; i < timeout; ++i) {
1131 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
1132 if ((edma_stat & empty_idle) == empty_idle)
1136 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1140 * mv_stop_edma_engine - Disable eDMA engine
1141 * @port_mmio: io base address
1144 * Inherited from caller.
1146 static int mv_stop_edma_engine(void __iomem *port_mmio)
1150 /* Disable eDMA. The disable bit auto clears. */
1151 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1153 /* Wait for the chip to confirm eDMA is off. */
1154 for (i = 10000; i > 0; i--) {
1155 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
1156 if (!(reg & EDMA_EN))
1163 static int mv_stop_edma(struct ata_port *ap)
1165 void __iomem *port_mmio = mv_ap_base(ap);
1166 struct mv_port_priv *pp = ap->private_data;
1169 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1171 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1172 mv_wait_for_edma_empty_idle(ap);
1173 if (mv_stop_edma_engine(port_mmio)) {
1174 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1177 mv_edma_cfg(ap, 0, 0);
1182 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1185 for (b = 0; b < bytes; ) {
1186 DPRINTK("%p: ", start + b);
1187 for (w = 0; b < bytes && w < 4; w++) {
1188 printk("%08x ", readl(start + b));
1196 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1201 for (b = 0; b < bytes; ) {
1202 DPRINTK("%02x: ", b);
1203 for (w = 0; b < bytes && w < 4; w++) {
1204 (void) pci_read_config_dword(pdev, b, &dw);
1205 printk("%08x ", dw);
1212 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1213 struct pci_dev *pdev)
1216 void __iomem *hc_base = mv_hc_base(mmio_base,
1217 port >> MV_PORT_HC_SHIFT);
1218 void __iomem *port_base;
1219 int start_port, num_ports, p, start_hc, num_hcs, hc;
1222 start_hc = start_port = 0;
1223 num_ports = 8; /* shld be benign for 4 port devs */
1226 start_hc = port >> MV_PORT_HC_SHIFT;
1228 num_ports = num_hcs = 1;
1230 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1231 num_ports > 1 ? num_ports - 1 : start_port);
1234 DPRINTK("PCI config space regs:\n");
1235 mv_dump_pci_cfg(pdev, 0x68);
1237 DPRINTK("PCI regs:\n");
1238 mv_dump_mem(mmio_base+0xc00, 0x3c);
1239 mv_dump_mem(mmio_base+0xd00, 0x34);
1240 mv_dump_mem(mmio_base+0xf00, 0x4);
1241 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1242 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1243 hc_base = mv_hc_base(mmio_base, hc);
1244 DPRINTK("HC regs (HC %i):\n", hc);
1245 mv_dump_mem(hc_base, 0x1c);
1247 for (p = start_port; p < start_port + num_ports; p++) {
1248 port_base = mv_port_base(mmio_base, p);
1249 DPRINTK("EDMA regs (port %i):\n", p);
1250 mv_dump_mem(port_base, 0x54);
1251 DPRINTK("SATA regs (port %i):\n", p);
1252 mv_dump_mem(port_base+0x300, 0x60);
1257 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1261 switch (sc_reg_in) {
1265 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1268 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1277 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1279 unsigned int ofs = mv_scr_offset(sc_reg_in);
1281 if (ofs != 0xffffffffU) {
1282 *val = readl(mv_ap_base(link->ap) + ofs);
1288 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1290 unsigned int ofs = mv_scr_offset(sc_reg_in);
1292 if (ofs != 0xffffffffU) {
1293 writelfl(val, mv_ap_base(link->ap) + ofs);
1299 static void mv6_dev_config(struct ata_device *adev)
1302 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1304 * Gen-II does not support NCQ over a port multiplier
1305 * (no FIS-based switching).
1307 if (adev->flags & ATA_DFLAG_NCQ) {
1308 if (sata_pmp_attached(adev->link->ap)) {
1309 adev->flags &= ~ATA_DFLAG_NCQ;
1310 ata_dev_printk(adev, KERN_INFO,
1311 "NCQ disabled for command-based switching\n");
1316 static int mv_qc_defer(struct ata_queued_cmd *qc)
1318 struct ata_link *link = qc->dev->link;
1319 struct ata_port *ap = link->ap;
1320 struct mv_port_priv *pp = ap->private_data;
1323 * Don't allow new commands if we're in a delayed EH state
1324 * for NCQ and/or FIS-based switching.
1326 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1327 return ATA_DEFER_PORT;
1329 * If the port is completely idle, then allow the new qc.
1331 if (ap->nr_active_links == 0)
1335 * The port is operating in host queuing mode (EDMA) with NCQ
1336 * enabled, allow multiple NCQ commands. EDMA also allows
1337 * queueing multiple DMA commands but libata core currently
1340 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1341 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1344 return ATA_DEFER_PORT;
1347 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1349 struct mv_port_priv *pp = ap->private_data;
1350 void __iomem *port_mmio;
1352 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1353 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1354 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1356 ltmode = *old_ltmode & ~LTMODE_BIT8;
1357 haltcond = *old_haltcond | EDMA_ERR_DEV;
1360 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1361 ltmode = *old_ltmode | LTMODE_BIT8;
1363 haltcond &= ~EDMA_ERR_DEV;
1365 fiscfg |= FISCFG_WAIT_DEV_ERR;
1367 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1370 port_mmio = mv_ap_base(ap);
1371 mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg);
1372 mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode);
1373 mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond);
1376 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1378 struct mv_host_priv *hpriv = ap->host->private_data;
1381 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1382 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1384 new = old | (1 << 22);
1386 new = old & ~(1 << 22);
1388 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1392 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1393 * @ap: Port being initialized
1395 * There are two DMA modes on these chips: basic DMA, and EDMA.
1397 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1398 * of basic DMA on the GEN_IIE versions of the chips.
1400 * This bit survives EDMA resets, and must be set for basic DMA
1401 * to function, and should be cleared when EDMA is active.
1403 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1405 struct mv_port_priv *pp = ap->private_data;
1406 u32 new, *old = &pp->cached.unknown_rsvd;
1412 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new);
1416 * SOC chips have an issue whereby the HDD LEDs don't always blink
1417 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1418 * of the SOC takes care of it, generating a steady blink rate when
1419 * any drive on the chip is active.
1421 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1422 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1424 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1425 * LED operation works then, and provides better (more accurate) feedback.
1427 * Note that this code assumes that an SOC never has more than one HC onboard.
1429 static void mv_soc_led_blink_enable(struct ata_port *ap)
1431 struct ata_host *host = ap->host;
1432 struct mv_host_priv *hpriv = host->private_data;
1433 void __iomem *hc_mmio;
1436 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1438 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1439 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1440 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1441 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1444 static void mv_soc_led_blink_disable(struct ata_port *ap)
1446 struct ata_host *host = ap->host;
1447 struct mv_host_priv *hpriv = host->private_data;
1448 void __iomem *hc_mmio;
1452 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1455 /* disable led-blink only if no ports are using NCQ */
1456 for (port = 0; port < hpriv->n_ports; port++) {
1457 struct ata_port *this_ap = host->ports[port];
1458 struct mv_port_priv *pp = this_ap->private_data;
1460 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1464 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1465 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1466 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1467 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1470 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1473 struct mv_port_priv *pp = ap->private_data;
1474 struct mv_host_priv *hpriv = ap->host->private_data;
1475 void __iomem *port_mmio = mv_ap_base(ap);
1477 /* set up non-NCQ EDMA configuration */
1478 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1480 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1482 if (IS_GEN_I(hpriv))
1483 cfg |= (1 << 8); /* enab config burst size mask */
1485 else if (IS_GEN_II(hpriv)) {
1486 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1487 mv_60x1_errata_sata25(ap, want_ncq);
1489 } else if (IS_GEN_IIE(hpriv)) {
1490 int want_fbs = sata_pmp_attached(ap);
1492 * Possible future enhancement:
1494 * The chip can use FBS with non-NCQ, if we allow it,
1495 * But first we need to have the error handling in place
1496 * for this mode (datasheet section 7.3.15.4.2.3).
1497 * So disallow non-NCQ FBS for now.
1499 want_fbs &= want_ncq;
1501 mv_config_fbs(ap, want_ncq, want_fbs);
1504 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1505 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1508 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1510 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1512 cfg |= (1 << 18); /* enab early completion */
1514 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1515 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1516 mv_bmdma_enable_iie(ap, !want_edma);
1518 if (IS_SOC(hpriv)) {
1520 mv_soc_led_blink_enable(ap);
1522 mv_soc_led_blink_disable(ap);
1527 cfg |= EDMA_CFG_NCQ;
1528 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1531 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1534 static void mv_port_free_dma_mem(struct ata_port *ap)
1536 struct mv_host_priv *hpriv = ap->host->private_data;
1537 struct mv_port_priv *pp = ap->private_data;
1541 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1545 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1549 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1550 * For later hardware, we have one unique sg_tbl per NCQ tag.
1552 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1553 if (pp->sg_tbl[tag]) {
1554 if (tag == 0 || !IS_GEN_I(hpriv))
1555 dma_pool_free(hpriv->sg_tbl_pool,
1557 pp->sg_tbl_dma[tag]);
1558 pp->sg_tbl[tag] = NULL;
1564 * mv_port_start - Port specific init/start routine.
1565 * @ap: ATA channel to manipulate
1567 * Allocate and point to DMA memory, init port private memory,
1571 * Inherited from caller.
1573 static int mv_port_start(struct ata_port *ap)
1575 struct device *dev = ap->host->dev;
1576 struct mv_host_priv *hpriv = ap->host->private_data;
1577 struct mv_port_priv *pp;
1578 unsigned long flags;
1581 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1584 ap->private_data = pp;
1586 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1589 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1591 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1593 goto out_port_free_dma_mem;
1594 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1596 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1597 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1598 ap->flags |= ATA_FLAG_AN;
1600 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1601 * For later hardware, we need one unique sg_tbl per NCQ tag.
1603 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1604 if (tag == 0 || !IS_GEN_I(hpriv)) {
1605 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1606 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1607 if (!pp->sg_tbl[tag])
1608 goto out_port_free_dma_mem;
1610 pp->sg_tbl[tag] = pp->sg_tbl[0];
1611 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1615 spin_lock_irqsave(ap->lock, flags);
1616 mv_save_cached_regs(ap);
1617 mv_edma_cfg(ap, 0, 0);
1618 spin_unlock_irqrestore(ap->lock, flags);
1622 out_port_free_dma_mem:
1623 mv_port_free_dma_mem(ap);
1628 * mv_port_stop - Port specific cleanup/stop routine.
1629 * @ap: ATA channel to manipulate
1631 * Stop DMA, cleanup port memory.
1634 * This routine uses the host lock to protect the DMA stop.
1636 static void mv_port_stop(struct ata_port *ap)
1638 unsigned long flags;
1640 spin_lock_irqsave(ap->lock, flags);
1642 mv_enable_port_irqs(ap, 0);
1643 spin_unlock_irqrestore(ap->lock, flags);
1644 mv_port_free_dma_mem(ap);
1648 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1649 * @qc: queued command whose SG list to source from
1651 * Populate the SG list and mark the last entry.
1654 * Inherited from caller.
1656 static void mv_fill_sg(struct ata_queued_cmd *qc)
1658 struct mv_port_priv *pp = qc->ap->private_data;
1659 struct scatterlist *sg;
1660 struct mv_sg *mv_sg, *last_sg = NULL;
1663 mv_sg = pp->sg_tbl[qc->tag];
1664 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1665 dma_addr_t addr = sg_dma_address(sg);
1666 u32 sg_len = sg_dma_len(sg);
1669 u32 offset = addr & 0xffff;
1672 if (offset + len > 0x10000)
1673 len = 0x10000 - offset;
1675 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1676 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1677 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1678 mv_sg->reserved = 0;
1688 if (likely(last_sg))
1689 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1690 mb(); /* ensure data structure is visible to the chipset */
1693 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1695 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1696 (last ? CRQB_CMD_LAST : 0);
1697 *cmdw = cpu_to_le16(tmp);
1701 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1702 * @ap: Port associated with this ATA transaction.
1704 * We need this only for ATAPI bmdma transactions,
1705 * as otherwise we experience spurious interrupts
1706 * after libata-sff handles the bmdma interrupts.
1708 static void mv_sff_irq_clear(struct ata_port *ap)
1710 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1714 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1715 * @qc: queued command to check for chipset/DMA compatibility.
1717 * The bmdma engines cannot handle speculative data sizes
1718 * (bytecount under/over flow). So only allow DMA for
1719 * data transfer commands with known data sizes.
1722 * Inherited from caller.
1724 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1726 struct scsi_cmnd *scmd = qc->scsicmd;
1729 switch (scmd->cmnd[0]) {
1737 case GPCMD_SEND_DVD_STRUCTURE:
1738 case GPCMD_SEND_CUE_SHEET:
1739 return 0; /* DMA is safe */
1742 return -EOPNOTSUPP; /* use PIO instead */
1746 * mv_bmdma_setup - Set up BMDMA transaction
1747 * @qc: queued command to prepare DMA for.
1750 * Inherited from caller.
1752 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1754 struct ata_port *ap = qc->ap;
1755 void __iomem *port_mmio = mv_ap_base(ap);
1756 struct mv_port_priv *pp = ap->private_data;
1760 /* clear all DMA cmd bits */
1761 writel(0, port_mmio + BMDMA_CMD_OFS);
1763 /* load PRD table addr. */
1764 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1765 port_mmio + BMDMA_PRD_HIGH_OFS);
1766 writelfl(pp->sg_tbl_dma[qc->tag],
1767 port_mmio + BMDMA_PRD_LOW_OFS);
1769 /* issue r/w command */
1770 ap->ops->sff_exec_command(ap, &qc->tf);
1774 * mv_bmdma_start - Start a BMDMA transaction
1775 * @qc: queued command to start DMA on.
1778 * Inherited from caller.
1780 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1782 struct ata_port *ap = qc->ap;
1783 void __iomem *port_mmio = mv_ap_base(ap);
1784 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1785 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1787 /* start host DMA transaction */
1788 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1792 * mv_bmdma_stop - Stop BMDMA transfer
1793 * @qc: queued command to stop DMA on.
1795 * Clears the ATA_DMA_START flag in the bmdma control register
1798 * Inherited from caller.
1800 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1802 struct ata_port *ap = qc->ap;
1803 void __iomem *port_mmio = mv_ap_base(ap);
1806 /* clear start/stop bit */
1807 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1808 cmd &= ~ATA_DMA_START;
1809 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1811 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1812 ata_sff_dma_pause(ap);
1816 * mv_bmdma_status - Read BMDMA status
1817 * @ap: port for which to retrieve DMA status.
1819 * Read and return equivalent of the sff BMDMA status register.
1822 * Inherited from caller.
1824 static u8 mv_bmdma_status(struct ata_port *ap)
1826 void __iomem *port_mmio = mv_ap_base(ap);
1830 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1831 * and the ATA_DMA_INTR bit doesn't exist.
1833 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1834 if (reg & ATA_DMA_ACTIVE)
1835 status = ATA_DMA_ACTIVE;
1837 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1842 * mv_qc_prep - Host specific command preparation.
1843 * @qc: queued command to prepare
1845 * This routine simply redirects to the general purpose routine
1846 * if command is not DMA. Else, it handles prep of the CRQB
1847 * (command request block), does some sanity checking, and calls
1848 * the SG load routine.
1851 * Inherited from caller.
1853 static void mv_qc_prep(struct ata_queued_cmd *qc)
1855 struct ata_port *ap = qc->ap;
1856 struct mv_port_priv *pp = ap->private_data;
1858 struct ata_taskfile *tf;
1862 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1863 (qc->tf.protocol != ATA_PROT_NCQ))
1866 /* Fill in command request block
1868 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1869 flags |= CRQB_FLAG_READ;
1870 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1871 flags |= qc->tag << CRQB_TAG_SHIFT;
1872 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1874 /* get current queue index from software */
1875 in_index = pp->req_idx;
1877 pp->crqb[in_index].sg_addr =
1878 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1879 pp->crqb[in_index].sg_addr_hi =
1880 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1881 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1883 cw = &pp->crqb[in_index].ata_cmd[0];
1886 /* Sadly, the CRQB cannot accomodate all registers--there are
1887 * only 11 bytes...so we must pick and choose required
1888 * registers based on the command. So, we drop feature and
1889 * hob_feature for [RW] DMA commands, but they are needed for
1890 * NCQ. NCQ will drop hob_nsect, which is not needed there
1891 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
1893 switch (tf->command) {
1895 case ATA_CMD_READ_EXT:
1897 case ATA_CMD_WRITE_EXT:
1898 case ATA_CMD_WRITE_FUA_EXT:
1899 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1901 case ATA_CMD_FPDMA_READ:
1902 case ATA_CMD_FPDMA_WRITE:
1903 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1904 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1907 /* The only other commands EDMA supports in non-queued and
1908 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1909 * of which are defined/used by Linux. If we get here, this
1910 * driver needs work.
1912 * FIXME: modify libata to give qc_prep a return value and
1913 * return error here.
1915 BUG_ON(tf->command);
1918 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1919 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1920 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1921 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1922 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1923 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1924 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1925 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1926 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1928 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1934 * mv_qc_prep_iie - Host specific command preparation.
1935 * @qc: queued command to prepare
1937 * This routine simply redirects to the general purpose routine
1938 * if command is not DMA. Else, it handles prep of the CRQB
1939 * (command request block), does some sanity checking, and calls
1940 * the SG load routine.
1943 * Inherited from caller.
1945 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1947 struct ata_port *ap = qc->ap;
1948 struct mv_port_priv *pp = ap->private_data;
1949 struct mv_crqb_iie *crqb;
1950 struct ata_taskfile *tf;
1954 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1955 (qc->tf.protocol != ATA_PROT_NCQ))
1958 /* Fill in Gen IIE command request block */
1959 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1960 flags |= CRQB_FLAG_READ;
1962 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1963 flags |= qc->tag << CRQB_TAG_SHIFT;
1964 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1965 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1967 /* get current queue index from software */
1968 in_index = pp->req_idx;
1970 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1971 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1972 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1973 crqb->flags = cpu_to_le32(flags);
1976 crqb->ata_cmd[0] = cpu_to_le32(
1977 (tf->command << 16) |
1980 crqb->ata_cmd[1] = cpu_to_le32(
1986 crqb->ata_cmd[2] = cpu_to_le32(
1987 (tf->hob_lbal << 0) |
1988 (tf->hob_lbam << 8) |
1989 (tf->hob_lbah << 16) |
1990 (tf->hob_feature << 24)
1992 crqb->ata_cmd[3] = cpu_to_le32(
1994 (tf->hob_nsect << 8)
1997 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2003 * mv_sff_check_status - fetch device status, if valid
2004 * @ap: ATA port to fetch status from
2006 * When using command issue via mv_qc_issue_fis(),
2007 * the initial ATA_BUSY state does not show up in the
2008 * ATA status (shadow) register. This can confuse libata!
2010 * So we have a hook here to fake ATA_BUSY for that situation,
2011 * until the first time a BUSY, DRQ, or ERR bit is seen.
2013 * The rest of the time, it simply returns the ATA status register.
2015 static u8 mv_sff_check_status(struct ata_port *ap)
2017 u8 stat = ioread8(ap->ioaddr.status_addr);
2018 struct mv_port_priv *pp = ap->private_data;
2020 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2021 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2022 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2030 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2031 * @fis: fis to be sent
2032 * @nwords: number of 32-bit words in the fis
2034 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2036 void __iomem *port_mmio = mv_ap_base(ap);
2037 u32 ifctl, old_ifctl, ifstat;
2038 int i, timeout = 200, final_word = nwords - 1;
2040 /* Initiate FIS transmission mode */
2041 old_ifctl = readl(port_mmio + SATA_IFCTL_OFS);
2042 ifctl = 0x100 | (old_ifctl & 0xf);
2043 writelfl(ifctl, port_mmio + SATA_IFCTL_OFS);
2045 /* Send all words of the FIS except for the final word */
2046 for (i = 0; i < final_word; ++i)
2047 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2049 /* Flag end-of-transmission, and then send the final word */
2050 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL_OFS);
2051 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2054 * Wait for FIS transmission to complete.
2055 * This typically takes just a single iteration.
2058 ifstat = readl(port_mmio + SATA_IFSTAT_OFS);
2059 } while (!(ifstat & 0x1000) && --timeout);
2061 /* Restore original port configuration */
2062 writelfl(old_ifctl, port_mmio + SATA_IFCTL_OFS);
2064 /* See if it worked */
2065 if ((ifstat & 0x3000) != 0x1000) {
2066 ata_port_printk(ap, KERN_WARNING,
2067 "%s transmission error, ifstat=%08x\n",
2069 return AC_ERR_OTHER;
2075 * mv_qc_issue_fis - Issue a command directly as a FIS
2076 * @qc: queued command to start
2078 * Note that the ATA shadow registers are not updated
2079 * after command issue, so the device will appear "READY"
2080 * if polled, even while it is BUSY processing the command.
2082 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2084 * Note: we don't get updated shadow regs on *completion*
2085 * of non-data commands. So avoid sending them via this function,
2086 * as they will appear to have completed immediately.
2088 * GEN_IIE has special registers that we could get the result tf from,
2089 * but earlier chipsets do not. For now, we ignore those registers.
2091 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2093 struct ata_port *ap = qc->ap;
2094 struct mv_port_priv *pp = ap->private_data;
2095 struct ata_link *link = qc->dev->link;
2099 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2100 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
2104 switch (qc->tf.protocol) {
2105 case ATAPI_PROT_PIO:
2106 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2108 case ATAPI_PROT_NODATA:
2109 ap->hsm_task_state = HSM_ST_FIRST;
2112 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2113 if (qc->tf.flags & ATA_TFLAG_WRITE)
2114 ap->hsm_task_state = HSM_ST_FIRST;
2116 ap->hsm_task_state = HSM_ST;
2119 ap->hsm_task_state = HSM_ST_LAST;
2123 if (qc->tf.flags & ATA_TFLAG_POLLING)
2124 ata_pio_queue_task(ap, qc, 0);
2129 * mv_qc_issue - Initiate a command to the host
2130 * @qc: queued command to start
2132 * This routine simply redirects to the general purpose routine
2133 * if command is not DMA. Else, it sanity checks our local
2134 * caches of the request producer/consumer indices then enables
2135 * DMA and bumps the request producer index.
2138 * Inherited from caller.
2140 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2142 static int limit_warnings = 10;
2143 struct ata_port *ap = qc->ap;
2144 void __iomem *port_mmio = mv_ap_base(ap);
2145 struct mv_port_priv *pp = ap->private_data;
2147 unsigned int port_irqs;
2149 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2151 switch (qc->tf.protocol) {
2154 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2155 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2156 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2158 /* Write the request in pointer to kick the EDMA to life */
2159 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2160 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
2165 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2167 * Someday, we might implement special polling workarounds
2168 * for these, but it all seems rather unnecessary since we
2169 * normally use only DMA for commands which transfer more
2170 * than a single block of data.
2172 * Much of the time, this could just work regardless.
2173 * So for now, just log the incident, and allow the attempt.
2175 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2177 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2178 ": attempting PIO w/multiple DRQ: "
2179 "this may fail due to h/w errata\n");
2182 case ATA_PROT_NODATA:
2183 case ATAPI_PROT_PIO:
2184 case ATAPI_PROT_NODATA:
2185 if (ap->flags & ATA_FLAG_PIO_POLLING)
2186 qc->tf.flags |= ATA_TFLAG_POLLING;
2190 if (qc->tf.flags & ATA_TFLAG_POLLING)
2191 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2193 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2196 * We're about to send a non-EDMA capable command to the
2197 * port. Turn off EDMA so there won't be problems accessing
2198 * shadow block, etc registers.
2201 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2202 mv_pmp_select(ap, qc->dev->link->pmp);
2204 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2205 struct mv_host_priv *hpriv = ap->host->private_data;
2207 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2209 * After any NCQ error, the READ_LOG_EXT command
2210 * from libata-eh *must* use mv_qc_issue_fis().
2211 * Otherwise it might fail, due to chip errata.
2213 * Rather than special-case it, we'll just *always*
2214 * use this method here for READ_LOG_EXT, making for
2217 if (IS_GEN_II(hpriv))
2218 return mv_qc_issue_fis(qc);
2220 return ata_sff_qc_issue(qc);
2223 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2225 struct mv_port_priv *pp = ap->private_data;
2226 struct ata_queued_cmd *qc;
2228 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2230 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2232 if (qc->tf.flags & ATA_TFLAG_POLLING)
2234 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2240 static void mv_pmp_error_handler(struct ata_port *ap)
2242 unsigned int pmp, pmp_map;
2243 struct mv_port_priv *pp = ap->private_data;
2245 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2247 * Perform NCQ error analysis on failed PMPs
2248 * before we freeze the port entirely.
2250 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2252 pmp_map = pp->delayed_eh_pmp_map;
2253 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2254 for (pmp = 0; pmp_map != 0; pmp++) {
2255 unsigned int this_pmp = (1 << pmp);
2256 if (pmp_map & this_pmp) {
2257 struct ata_link *link = &ap->pmp_link[pmp];
2258 pmp_map &= ~this_pmp;
2259 ata_eh_analyze_ncq_error(link);
2262 ata_port_freeze(ap);
2264 sata_pmp_error_handler(ap);
2267 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2269 void __iomem *port_mmio = mv_ap_base(ap);
2271 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
2274 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2276 struct ata_eh_info *ehi;
2280 * Initialize EH info for PMPs which saw device errors
2282 ehi = &ap->link.eh_info;
2283 for (pmp = 0; pmp_map != 0; pmp++) {
2284 unsigned int this_pmp = (1 << pmp);
2285 if (pmp_map & this_pmp) {
2286 struct ata_link *link = &ap->pmp_link[pmp];
2288 pmp_map &= ~this_pmp;
2289 ehi = &link->eh_info;
2290 ata_ehi_clear_desc(ehi);
2291 ata_ehi_push_desc(ehi, "dev err");
2292 ehi->err_mask |= AC_ERR_DEV;
2293 ehi->action |= ATA_EH_RESET;
2294 ata_link_abort(link);
2299 static int mv_req_q_empty(struct ata_port *ap)
2301 void __iomem *port_mmio = mv_ap_base(ap);
2302 u32 in_ptr, out_ptr;
2304 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
2305 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2306 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
2307 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2308 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2311 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2313 struct mv_port_priv *pp = ap->private_data;
2315 unsigned int old_map, new_map;
2318 * Device error during FBS+NCQ operation:
2320 * Set a port flag to prevent further I/O being enqueued.
2321 * Leave the EDMA running to drain outstanding commands from this port.
2322 * Perform the post-mortem/EH only when all responses are complete.
2323 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2325 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2326 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2327 pp->delayed_eh_pmp_map = 0;
2329 old_map = pp->delayed_eh_pmp_map;
2330 new_map = old_map | mv_get_err_pmp_map(ap);
2332 if (old_map != new_map) {
2333 pp->delayed_eh_pmp_map = new_map;
2334 mv_pmp_eh_prep(ap, new_map & ~old_map);
2336 failed_links = hweight16(new_map);
2338 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2339 "failed_links=%d nr_active_links=%d\n",
2340 __func__, pp->delayed_eh_pmp_map,
2341 ap->qc_active, failed_links,
2342 ap->nr_active_links);
2344 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2345 mv_process_crpb_entries(ap, pp);
2348 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2349 return 1; /* handled */
2351 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2352 return 1; /* handled */
2355 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2358 * Possible future enhancement:
2360 * FBS+non-NCQ operation is not yet implemented.
2361 * See related notes in mv_edma_cfg().
2363 * Device error during FBS+non-NCQ operation:
2365 * We need to snapshot the shadow registers for each failed command.
2366 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2368 return 0; /* not handled */
2371 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2373 struct mv_port_priv *pp = ap->private_data;
2375 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2376 return 0; /* EDMA was not active: not handled */
2377 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2378 return 0; /* FBS was not active: not handled */
2380 if (!(edma_err_cause & EDMA_ERR_DEV))
2381 return 0; /* non DEV error: not handled */
2382 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2383 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2384 return 0; /* other problems: not handled */
2386 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2388 * EDMA should NOT have self-disabled for this case.
2389 * If it did, then something is wrong elsewhere,
2390 * and we cannot handle it here.
2392 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2393 ata_port_printk(ap, KERN_WARNING,
2394 "%s: err_cause=0x%x pp_flags=0x%x\n",
2395 __func__, edma_err_cause, pp->pp_flags);
2396 return 0; /* not handled */
2398 return mv_handle_fbs_ncq_dev_err(ap);
2401 * EDMA should have self-disabled for this case.
2402 * If it did not, then something is wrong elsewhere,
2403 * and we cannot handle it here.
2405 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2406 ata_port_printk(ap, KERN_WARNING,
2407 "%s: err_cause=0x%x pp_flags=0x%x\n",
2408 __func__, edma_err_cause, pp->pp_flags);
2409 return 0; /* not handled */
2411 return mv_handle_fbs_non_ncq_dev_err(ap);
2413 return 0; /* not handled */
2416 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2418 struct ata_eh_info *ehi = &ap->link.eh_info;
2419 char *when = "idle";
2421 ata_ehi_clear_desc(ehi);
2422 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2424 } else if (edma_was_enabled) {
2425 when = "EDMA enabled";
2427 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2428 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2431 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2432 ehi->err_mask |= AC_ERR_OTHER;
2433 ehi->action |= ATA_EH_RESET;
2434 ata_port_freeze(ap);
2438 * mv_err_intr - Handle error interrupts on the port
2439 * @ap: ATA channel to manipulate
2441 * Most cases require a full reset of the chip's state machine,
2442 * which also performs a COMRESET.
2443 * Also, if the port disabled DMA, update our cached copy to match.
2446 * Inherited from caller.
2448 static void mv_err_intr(struct ata_port *ap)
2450 void __iomem *port_mmio = mv_ap_base(ap);
2451 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2453 struct mv_port_priv *pp = ap->private_data;
2454 struct mv_host_priv *hpriv = ap->host->private_data;
2455 unsigned int action = 0, err_mask = 0;
2456 struct ata_eh_info *ehi = &ap->link.eh_info;
2457 struct ata_queued_cmd *qc;
2461 * Read and clear the SError and err_cause bits.
2462 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2463 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2465 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2466 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2468 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2469 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2470 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2471 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2473 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2475 if (edma_err_cause & EDMA_ERR_DEV) {
2477 * Device errors during FIS-based switching operation
2478 * require special handling.
2480 if (mv_handle_dev_err(ap, edma_err_cause))
2484 qc = mv_get_active_qc(ap);
2485 ata_ehi_clear_desc(ehi);
2486 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2487 edma_err_cause, pp->pp_flags);
2489 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2490 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2491 if (fis_cause & SATA_FIS_IRQ_AN) {
2492 u32 ec = edma_err_cause &
2493 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2494 sata_async_notification(ap);
2496 return; /* Just an AN; no need for the nukes */
2497 ata_ehi_push_desc(ehi, "SDB notify");
2501 * All generations share these EDMA error cause bits:
2503 if (edma_err_cause & EDMA_ERR_DEV) {
2504 err_mask |= AC_ERR_DEV;
2505 action |= ATA_EH_RESET;
2506 ata_ehi_push_desc(ehi, "dev error");
2508 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2509 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2510 EDMA_ERR_INTRL_PAR)) {
2511 err_mask |= AC_ERR_ATA_BUS;
2512 action |= ATA_EH_RESET;
2513 ata_ehi_push_desc(ehi, "parity error");
2515 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2516 ata_ehi_hotplugged(ehi);
2517 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2518 "dev disconnect" : "dev connect");
2519 action |= ATA_EH_RESET;
2523 * Gen-I has a different SELF_DIS bit,
2524 * different FREEZE bits, and no SERR bit:
2526 if (IS_GEN_I(hpriv)) {
2527 eh_freeze_mask = EDMA_EH_FREEZE_5;
2528 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2529 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2530 ata_ehi_push_desc(ehi, "EDMA self-disable");
2533 eh_freeze_mask = EDMA_EH_FREEZE;
2534 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2535 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2536 ata_ehi_push_desc(ehi, "EDMA self-disable");
2538 if (edma_err_cause & EDMA_ERR_SERR) {
2539 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2540 err_mask |= AC_ERR_ATA_BUS;
2541 action |= ATA_EH_RESET;
2546 err_mask = AC_ERR_OTHER;
2547 action |= ATA_EH_RESET;
2550 ehi->serror |= serr;
2551 ehi->action |= action;
2554 qc->err_mask |= err_mask;
2556 ehi->err_mask |= err_mask;
2558 if (err_mask == AC_ERR_DEV) {
2560 * Cannot do ata_port_freeze() here,
2561 * because it would kill PIO access,
2562 * which is needed for further diagnosis.
2566 } else if (edma_err_cause & eh_freeze_mask) {
2568 * Note to self: ata_port_freeze() calls ata_port_abort()
2570 ata_port_freeze(ap);
2577 ata_link_abort(qc->dev->link);
2583 static void mv_process_crpb_response(struct ata_port *ap,
2584 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2586 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2590 u16 edma_status = le16_to_cpu(response->flags);
2592 * edma_status from a response queue entry:
2593 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2594 * MSB is saved ATA status from command completion.
2597 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2600 * Error will be seen/handled by mv_err_intr().
2601 * So do nothing at all here.
2606 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2607 if (!ac_err_mask(ata_status))
2608 ata_qc_complete(qc);
2609 /* else: leave it for mv_err_intr() */
2611 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2616 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2618 void __iomem *port_mmio = mv_ap_base(ap);
2619 struct mv_host_priv *hpriv = ap->host->private_data;
2621 bool work_done = false;
2622 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2624 /* Get the hardware queue position index */
2625 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2626 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2628 /* Process new responses from since the last time we looked */
2629 while (in_index != pp->resp_idx) {
2631 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2633 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2635 if (IS_GEN_I(hpriv)) {
2636 /* 50xx: no NCQ, only one command active at a time */
2637 tag = ap->link.active_tag;
2639 /* Gen II/IIE: get command tag from CRPB entry */
2640 tag = le16_to_cpu(response->id) & 0x1f;
2642 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2646 /* Update the software queue position index in hardware */
2648 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2649 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2650 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2653 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2655 struct mv_port_priv *pp;
2656 int edma_was_enabled;
2658 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2659 mv_unexpected_intr(ap, 0);
2663 * Grab a snapshot of the EDMA_EN flag setting,
2664 * so that we have a consistent view for this port,
2665 * even if something we call of our routines changes it.
2667 pp = ap->private_data;
2668 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2670 * Process completed CRPB response(s) before other events.
2672 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2673 mv_process_crpb_entries(ap, pp);
2674 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2675 mv_handle_fbs_ncq_dev_err(ap);
2678 * Handle chip-reported errors, or continue on to handle PIO.
2680 if (unlikely(port_cause & ERR_IRQ)) {
2682 } else if (!edma_was_enabled) {
2683 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2685 ata_sff_host_intr(ap, qc);
2687 mv_unexpected_intr(ap, edma_was_enabled);
2692 * mv_host_intr - Handle all interrupts on the given host controller
2693 * @host: host specific structure
2694 * @main_irq_cause: Main interrupt cause register for the chip.
2697 * Inherited from caller.
2699 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2701 struct mv_host_priv *hpriv = host->private_data;
2702 void __iomem *mmio = hpriv->base, *hc_mmio;
2703 unsigned int handled = 0, port;
2705 /* If asserted, clear the "all ports" IRQ coalescing bit */
2706 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2707 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
2709 for (port = 0; port < hpriv->n_ports; port++) {
2710 struct ata_port *ap = host->ports[port];
2711 unsigned int p, shift, hardport, port_cause;
2713 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2715 * Each hc within the host has its own hc_irq_cause register,
2716 * where the interrupting ports bits get ack'd.
2718 if (hardport == 0) { /* first port on this hc ? */
2719 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2720 u32 port_mask, ack_irqs;
2722 * Skip this entire hc if nothing pending for any ports
2725 port += MV_PORTS_PER_HC - 1;
2729 * We don't need/want to read the hc_irq_cause register,
2730 * because doing so hurts performance, and
2731 * main_irq_cause already gives us everything we need.
2733 * But we do have to *write* to the hc_irq_cause to ack
2734 * the ports that we are handling this time through.
2736 * This requires that we create a bitmap for those
2737 * ports which interrupted us, and use that bitmap
2738 * to ack (only) those ports via hc_irq_cause.
2741 if (hc_cause & PORTS_0_3_COAL_DONE)
2742 ack_irqs = HC_COAL_IRQ;
2743 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2744 if ((port + p) >= hpriv->n_ports)
2746 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2747 if (hc_cause & port_mask)
2748 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2750 hc_mmio = mv_hc_base_from_port(mmio, port);
2751 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2755 * Handle interrupts signalled for this port:
2757 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2759 mv_port_intr(ap, port_cause);
2764 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2766 struct mv_host_priv *hpriv = host->private_data;
2767 struct ata_port *ap;
2768 struct ata_queued_cmd *qc;
2769 struct ata_eh_info *ehi;
2770 unsigned int i, err_mask, printed = 0;
2773 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2775 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2778 DPRINTK("All regs @ PCI error\n");
2779 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2781 writelfl(0, mmio + hpriv->irq_cause_ofs);
2783 for (i = 0; i < host->n_ports; i++) {
2784 ap = host->ports[i];
2785 if (!ata_link_offline(&ap->link)) {
2786 ehi = &ap->link.eh_info;
2787 ata_ehi_clear_desc(ehi);
2789 ata_ehi_push_desc(ehi,
2790 "PCI err cause 0x%08x", err_cause);
2791 err_mask = AC_ERR_HOST_BUS;
2792 ehi->action = ATA_EH_RESET;
2793 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2795 qc->err_mask |= err_mask;
2797 ehi->err_mask |= err_mask;
2799 ata_port_freeze(ap);
2802 return 1; /* handled */
2806 * mv_interrupt - Main interrupt event handler
2808 * @dev_instance: private data; in this case the host structure
2810 * Read the read only register to determine if any host
2811 * controllers have pending interrupts. If so, call lower level
2812 * routine to handle. Also check for PCI errors which are only
2816 * This routine holds the host lock while processing pending
2819 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2821 struct ata_host *host = dev_instance;
2822 struct mv_host_priv *hpriv = host->private_data;
2823 unsigned int handled = 0;
2824 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2825 u32 main_irq_cause, pending_irqs;
2827 spin_lock(&host->lock);
2829 /* for MSI: block new interrupts while in here */
2831 mv_write_main_irq_mask(0, hpriv);
2833 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2834 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2836 * Deal with cases where we either have nothing pending, or have read
2837 * a bogus register value which can indicate HW removal or PCI fault.
2839 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2840 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2841 handled = mv_pci_error(host, hpriv->base);
2843 handled = mv_host_intr(host, pending_irqs);
2846 /* for MSI: unmask; interrupt cause bits will retrigger now */
2848 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2850 spin_unlock(&host->lock);
2852 return IRQ_RETVAL(handled);
2855 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2859 switch (sc_reg_in) {
2863 ofs = sc_reg_in * sizeof(u32);
2872 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
2874 struct mv_host_priv *hpriv = link->ap->host->private_data;
2875 void __iomem *mmio = hpriv->base;
2876 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2877 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2879 if (ofs != 0xffffffffU) {
2880 *val = readl(addr + ofs);
2886 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
2888 struct mv_host_priv *hpriv = link->ap->host->private_data;
2889 void __iomem *mmio = hpriv->base;
2890 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2891 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2893 if (ofs != 0xffffffffU) {
2894 writelfl(val, addr + ofs);
2900 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2902 struct pci_dev *pdev = to_pci_dev(host->dev);
2905 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2908 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2910 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2913 mv_reset_pci_bus(host, mmio);
2916 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2918 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2921 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2924 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2927 tmp = readl(phy_mmio + MV5_PHY_MODE);
2929 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2930 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2933 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2937 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2939 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2941 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2943 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2946 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2949 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2950 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2952 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2955 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2957 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2959 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2962 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2965 tmp = readl(phy_mmio + MV5_PHY_MODE);
2967 tmp |= hpriv->signal[port].pre;
2968 tmp |= hpriv->signal[port].amps;
2969 writel(tmp, phy_mmio + MV5_PHY_MODE);
2974 #define ZERO(reg) writel(0, port_mmio + (reg))
2975 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2978 void __iomem *port_mmio = mv_port_base(mmio, port);
2980 mv_reset_channel(hpriv, mmio, port);
2982 ZERO(0x028); /* command */
2983 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2984 ZERO(0x004); /* timer */
2985 ZERO(0x008); /* irq err cause */
2986 ZERO(0x00c); /* irq err mask */
2987 ZERO(0x010); /* rq bah */
2988 ZERO(0x014); /* rq inp */
2989 ZERO(0x018); /* rq outp */
2990 ZERO(0x01c); /* respq bah */
2991 ZERO(0x024); /* respq outp */
2992 ZERO(0x020); /* respq inp */
2993 ZERO(0x02c); /* test control */
2994 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2998 #define ZERO(reg) writel(0, hc_mmio + (reg))
2999 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3002 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3010 tmp = readl(hc_mmio + 0x20);
3013 writel(tmp, hc_mmio + 0x20);
3017 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3020 unsigned int hc, port;
3022 for (hc = 0; hc < n_hc; hc++) {
3023 for (port = 0; port < MV_PORTS_PER_HC; port++)
3024 mv5_reset_hc_port(hpriv, mmio,
3025 (hc * MV_PORTS_PER_HC) + port);
3027 mv5_reset_one_hc(hpriv, mmio, hc);
3034 #define ZERO(reg) writel(0, mmio + (reg))
3035 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3037 struct mv_host_priv *hpriv = host->private_data;
3040 tmp = readl(mmio + MV_PCI_MODE_OFS);
3042 writel(tmp, mmio + MV_PCI_MODE_OFS);
3044 ZERO(MV_PCI_DISC_TIMER);
3045 ZERO(MV_PCI_MSI_TRIGGER);
3046 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
3047 ZERO(MV_PCI_SERR_MASK);
3048 ZERO(hpriv->irq_cause_ofs);
3049 ZERO(hpriv->irq_mask_ofs);
3050 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3051 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3052 ZERO(MV_PCI_ERR_ATTRIBUTE);
3053 ZERO(MV_PCI_ERR_COMMAND);
3057 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3061 mv5_reset_flash(hpriv, mmio);
3063 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
3065 tmp |= (1 << 5) | (1 << 6);
3066 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
3070 * mv6_reset_hc - Perform the 6xxx global soft reset
3071 * @mmio: base address of the HBA
3073 * This routine only applies to 6xxx parts.
3076 * Inherited from caller.
3078 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3081 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
3085 /* Following procedure defined in PCI "main command and status
3089 writel(t | STOP_PCI_MASTER, reg);
3091 for (i = 0; i < 1000; i++) {
3094 if (PCI_MASTER_EMPTY & t)
3097 if (!(PCI_MASTER_EMPTY & t)) {
3098 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3106 writel(t | GLOB_SFT_RST, reg);
3109 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3111 if (!(GLOB_SFT_RST & t)) {
3112 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3117 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3120 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3123 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3125 if (GLOB_SFT_RST & t) {
3126 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3133 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3136 void __iomem *port_mmio;
3139 tmp = readl(mmio + MV_RESET_CFG_OFS);
3140 if ((tmp & (1 << 0)) == 0) {
3141 hpriv->signal[idx].amps = 0x7 << 8;
3142 hpriv->signal[idx].pre = 0x1 << 5;
3146 port_mmio = mv_port_base(mmio, idx);
3147 tmp = readl(port_mmio + PHY_MODE2);
3149 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3150 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3153 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3155 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
3158 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3161 void __iomem *port_mmio = mv_port_base(mmio, port);
3163 u32 hp_flags = hpriv->hp_flags;
3165 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3167 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3170 if (fix_phy_mode2) {
3171 m2 = readl(port_mmio + PHY_MODE2);
3174 writel(m2, port_mmio + PHY_MODE2);
3178 m2 = readl(port_mmio + PHY_MODE2);
3179 m2 &= ~((1 << 16) | (1 << 31));
3180 writel(m2, port_mmio + PHY_MODE2);
3186 * Gen-II/IIe PHY_MODE3 errata RM#2:
3187 * Achieves better receiver noise performance than the h/w default:
3189 m3 = readl(port_mmio + PHY_MODE3);
3190 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3192 /* Guideline 88F5182 (GL# SATA-S11) */
3196 if (fix_phy_mode4) {
3197 u32 m4 = readl(port_mmio + PHY_MODE4);
3199 * Enforce reserved-bit restrictions on GenIIe devices only.
3200 * For earlier chipsets, force only the internal config field
3201 * (workaround for errata FEr SATA#10 part 1).
3203 if (IS_GEN_IIE(hpriv))
3204 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3206 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3207 writel(m4, port_mmio + PHY_MODE4);
3210 * Workaround for 60x1-B2 errata SATA#13:
3211 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3212 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3214 writel(m3, port_mmio + PHY_MODE3);
3216 /* Revert values of pre-emphasis and signal amps to the saved ones */
3217 m2 = readl(port_mmio + PHY_MODE2);
3219 m2 &= ~MV_M2_PREAMP_MASK;
3220 m2 |= hpriv->signal[port].amps;
3221 m2 |= hpriv->signal[port].pre;
3224 /* according to mvSata 3.6.1, some IIE values are fixed */
3225 if (IS_GEN_IIE(hpriv)) {
3230 writel(m2, port_mmio + PHY_MODE2);
3233 /* TODO: use the generic LED interface to configure the SATA Presence */
3234 /* & Acitivy LEDs on the board */
3235 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3241 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3244 void __iomem *port_mmio;
3247 port_mmio = mv_port_base(mmio, idx);
3248 tmp = readl(port_mmio + PHY_MODE2);
3250 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3251 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3255 #define ZERO(reg) writel(0, port_mmio + (reg))
3256 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3257 void __iomem *mmio, unsigned int port)
3259 void __iomem *port_mmio = mv_port_base(mmio, port);
3261 mv_reset_channel(hpriv, mmio, port);
3263 ZERO(0x028); /* command */
3264 writel(0x101f, port_mmio + EDMA_CFG_OFS);
3265 ZERO(0x004); /* timer */
3266 ZERO(0x008); /* irq err cause */
3267 ZERO(0x00c); /* irq err mask */
3268 ZERO(0x010); /* rq bah */
3269 ZERO(0x014); /* rq inp */
3270 ZERO(0x018); /* rq outp */
3271 ZERO(0x01c); /* respq bah */
3272 ZERO(0x024); /* respq outp */
3273 ZERO(0x020); /* respq inp */
3274 ZERO(0x02c); /* test control */
3275 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
3280 #define ZERO(reg) writel(0, hc_mmio + (reg))
3281 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3284 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3294 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3295 void __iomem *mmio, unsigned int n_hc)
3299 for (port = 0; port < hpriv->n_ports; port++)
3300 mv_soc_reset_hc_port(hpriv, mmio, port);
3302 mv_soc_reset_one_hc(hpriv, mmio);
3307 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3313 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3318 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3320 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
3322 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3324 ifcfg |= (1 << 7); /* enable gen2i speed */
3325 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
3328 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3329 unsigned int port_no)
3331 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3334 * The datasheet warns against setting EDMA_RESET when EDMA is active
3335 * (but doesn't say what the problem might be). So we first try
3336 * to disable the EDMA engine before doing the EDMA_RESET operation.
3338 mv_stop_edma_engine(port_mmio);
3339 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
3341 if (!IS_GEN_I(hpriv)) {
3342 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3343 mv_setup_ifcfg(port_mmio, 1);
3346 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3347 * link, and physical layers. It resets all SATA interface registers
3348 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
3350 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
3351 udelay(25); /* allow reset propagation */
3352 writelfl(0, port_mmio + EDMA_CMD_OFS);
3354 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3356 if (IS_GEN_I(hpriv))
3360 static void mv_pmp_select(struct ata_port *ap, int pmp)
3362 if (sata_pmp_supported(ap)) {
3363 void __iomem *port_mmio = mv_ap_base(ap);
3364 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
3365 int old = reg & 0xf;
3368 reg = (reg & ~0xf) | pmp;
3369 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
3374 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3375 unsigned long deadline)
3377 mv_pmp_select(link->ap, sata_srst_pmp(link));
3378 return sata_std_hardreset(link, class, deadline);
3381 static int mv_softreset(struct ata_link *link, unsigned int *class,
3382 unsigned long deadline)
3384 mv_pmp_select(link->ap, sata_srst_pmp(link));
3385 return ata_sff_softreset(link, class, deadline);
3388 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3389 unsigned long deadline)
3391 struct ata_port *ap = link->ap;
3392 struct mv_host_priv *hpriv = ap->host->private_data;
3393 struct mv_port_priv *pp = ap->private_data;
3394 void __iomem *mmio = hpriv->base;
3395 int rc, attempts = 0, extra = 0;
3399 mv_reset_channel(hpriv, mmio, ap->port_no);
3400 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3402 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3404 /* Workaround for errata FEr SATA#10 (part 2) */
3406 const unsigned long *timing =
3407 sata_ehc_deb_timing(&link->eh_context);
3409 rc = sata_link_hardreset(link, timing, deadline + extra,
3411 rc = online ? -EAGAIN : rc;
3414 sata_scr_read(link, SCR_STATUS, &sstatus);
3415 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3416 /* Force 1.5gb/s link speed and try again */
3417 mv_setup_ifcfg(mv_ap_base(ap), 0);
3418 if (time_after(jiffies + HZ, deadline))
3419 extra = HZ; /* only extend it once, max */
3421 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3422 mv_save_cached_regs(ap);
3423 mv_edma_cfg(ap, 0, 0);
3428 static void mv_eh_freeze(struct ata_port *ap)
3431 mv_enable_port_irqs(ap, 0);
3434 static void mv_eh_thaw(struct ata_port *ap)
3436 struct mv_host_priv *hpriv = ap->host->private_data;
3437 unsigned int port = ap->port_no;
3438 unsigned int hardport = mv_hardport_from_port(port);
3439 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3440 void __iomem *port_mmio = mv_ap_base(ap);
3443 /* clear EDMA errors on this port */
3444 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3446 /* clear pending irq events */
3447 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3448 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
3450 mv_enable_port_irqs(ap, ERR_IRQ);
3454 * mv_port_init - Perform some early initialization on a single port.
3455 * @port: libata data structure storing shadow register addresses
3456 * @port_mmio: base address of the port
3458 * Initialize shadow register mmio addresses, clear outstanding
3459 * interrupts on the port, and unmask interrupts for the future
3460 * start of the port.
3463 * Inherited from caller.
3465 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3467 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
3470 /* PIO related setup
3472 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3474 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3475 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3476 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3477 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3478 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3479 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3481 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3482 /* special case: control/altstatus doesn't have ATA_REG_ address */
3483 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3486 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
3488 /* Clear any currently outstanding port interrupt conditions */
3489 serr_ofs = mv_scr_offset(SCR_ERROR);
3490 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3491 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3493 /* unmask all non-transient EDMA error interrupts */
3494 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
3496 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3497 readl(port_mmio + EDMA_CFG_OFS),
3498 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3499 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
3502 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3504 struct mv_host_priv *hpriv = host->private_data;
3505 void __iomem *mmio = hpriv->base;
3508 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3509 return 0; /* not PCI-X capable */
3510 reg = readl(mmio + MV_PCI_MODE_OFS);
3511 if ((reg & MV_PCI_MODE_MASK) == 0)
3512 return 0; /* conventional PCI mode */
3513 return 1; /* chip is in PCI-X mode */
3516 static int mv_pci_cut_through_okay(struct ata_host *host)
3518 struct mv_host_priv *hpriv = host->private_data;
3519 void __iomem *mmio = hpriv->base;
3522 if (!mv_in_pcix_mode(host)) {
3523 reg = readl(mmio + PCI_COMMAND_OFS);
3524 if (reg & PCI_COMMAND_MRDTRIG)
3525 return 0; /* not okay */
3527 return 1; /* okay */
3530 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3532 struct pci_dev *pdev = to_pci_dev(host->dev);
3533 struct mv_host_priv *hpriv = host->private_data;
3534 u32 hp_flags = hpriv->hp_flags;
3536 switch (board_idx) {
3538 hpriv->ops = &mv5xxx_ops;
3539 hp_flags |= MV_HP_GEN_I;
3541 switch (pdev->revision) {
3543 hp_flags |= MV_HP_ERRATA_50XXB0;
3546 hp_flags |= MV_HP_ERRATA_50XXB2;
3549 dev_printk(KERN_WARNING, &pdev->dev,
3550 "Applying 50XXB2 workarounds to unknown rev\n");
3551 hp_flags |= MV_HP_ERRATA_50XXB2;
3558 hpriv->ops = &mv5xxx_ops;
3559 hp_flags |= MV_HP_GEN_I;
3561 switch (pdev->revision) {
3563 hp_flags |= MV_HP_ERRATA_50XXB0;
3566 hp_flags |= MV_HP_ERRATA_50XXB2;
3569 dev_printk(KERN_WARNING, &pdev->dev,
3570 "Applying B2 workarounds to unknown rev\n");
3571 hp_flags |= MV_HP_ERRATA_50XXB2;
3578 hpriv->ops = &mv6xxx_ops;
3579 hp_flags |= MV_HP_GEN_II;
3581 switch (pdev->revision) {
3583 hp_flags |= MV_HP_ERRATA_60X1B2;
3586 hp_flags |= MV_HP_ERRATA_60X1C0;
3589 dev_printk(KERN_WARNING, &pdev->dev,
3590 "Applying B2 workarounds to unknown rev\n");
3591 hp_flags |= MV_HP_ERRATA_60X1B2;
3597 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3598 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3599 (pdev->device == 0x2300 || pdev->device == 0x2310))
3602 * Highpoint RocketRAID PCIe 23xx series cards:
3604 * Unconfigured drives are treated as "Legacy"
3605 * by the BIOS, and it overwrites sector 8 with
3606 * a "Lgcy" metadata block prior to Linux boot.
3608 * Configured drives (RAID or JBOD) leave sector 8
3609 * alone, but instead overwrite a high numbered
3610 * sector for the RAID metadata. This sector can
3611 * be determined exactly, by truncating the physical
3612 * drive capacity to a nice even GB value.
3614 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3616 * Warn the user, lest they think we're just buggy.
3618 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3619 " BIOS CORRUPTS DATA on all attached drives,"
3620 " regardless of if/how they are configured."
3622 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3623 " use sectors 8-9 on \"Legacy\" drives,"
3624 " and avoid the final two gigabytes on"
3625 " all RocketRAID BIOS initialized drives.\n");
3629 hpriv->ops = &mv6xxx_ops;
3630 hp_flags |= MV_HP_GEN_IIE;
3631 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3632 hp_flags |= MV_HP_CUT_THROUGH;
3634 switch (pdev->revision) {
3635 case 0x2: /* Rev.B0: the first/only public release */
3636 hp_flags |= MV_HP_ERRATA_60X1C0;
3639 dev_printk(KERN_WARNING, &pdev->dev,
3640 "Applying 60X1C0 workarounds to unknown rev\n");
3641 hp_flags |= MV_HP_ERRATA_60X1C0;
3646 hpriv->ops = &mv_soc_ops;
3647 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3648 MV_HP_ERRATA_60X1C0;
3652 dev_printk(KERN_ERR, host->dev,
3653 "BUG: invalid board index %u\n", board_idx);
3657 hpriv->hp_flags = hp_flags;
3658 if (hp_flags & MV_HP_PCIE) {
3659 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3660 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3661 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3663 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3664 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3665 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3672 * mv_init_host - Perform some early initialization of the host.
3673 * @host: ATA host to initialize
3674 * @board_idx: controller index
3676 * If possible, do an early global reset of the host. Then do
3677 * our port init and clear/unmask all/relevant host interrupts.
3680 * Inherited from caller.
3682 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3684 int rc = 0, n_hc, port, hc;
3685 struct mv_host_priv *hpriv = host->private_data;
3686 void __iomem *mmio = hpriv->base;
3688 rc = mv_chip_id(host, board_idx);
3692 if (IS_SOC(hpriv)) {
3693 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3694 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3696 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3697 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3700 /* initialize shadow irq mask with register's value */
3701 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3703 /* global interrupt mask: 0 == mask everything */
3704 mv_set_main_irq_mask(host, ~0, 0);
3706 n_hc = mv_get_hc_count(host->ports[0]->flags);
3708 for (port = 0; port < host->n_ports; port++)
3709 hpriv->ops->read_preamp(hpriv, port, mmio);
3711 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3715 hpriv->ops->reset_flash(hpriv, mmio);
3716 hpriv->ops->reset_bus(host, mmio);
3717 hpriv->ops->enable_leds(hpriv, mmio);
3719 for (port = 0; port < host->n_ports; port++) {
3720 struct ata_port *ap = host->ports[port];
3721 void __iomem *port_mmio = mv_port_base(mmio, port);
3723 mv_port_init(&ap->ioaddr, port_mmio);
3726 if (!IS_SOC(hpriv)) {
3727 unsigned int offset = port_mmio - mmio;
3728 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3729 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3734 for (hc = 0; hc < n_hc; hc++) {
3735 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3737 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3738 "(before clear)=0x%08x\n", hc,
3739 readl(hc_mmio + HC_CFG_OFS),
3740 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3742 /* Clear any currently outstanding hc interrupt conditions */
3743 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3746 if (!IS_SOC(hpriv)) {
3747 /* Clear any currently outstanding host interrupt conditions */
3748 writelfl(0, mmio + hpriv->irq_cause_ofs);
3750 /* and unmask interrupt generation for host regs */
3751 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3755 * enable only global host interrupts for now.
3756 * The per-port interrupts get done later as ports are set up.
3758 mv_set_main_irq_mask(host, 0, PCI_ERR);
3759 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3760 irq_coalescing_usecs);
3765 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3767 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3769 if (!hpriv->crqb_pool)
3772 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3774 if (!hpriv->crpb_pool)
3777 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3779 if (!hpriv->sg_tbl_pool)
3785 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3786 struct mbus_dram_target_info *dram)
3790 for (i = 0; i < 4; i++) {
3791 writel(0, hpriv->base + WINDOW_CTRL(i));
3792 writel(0, hpriv->base + WINDOW_BASE(i));
3795 for (i = 0; i < dram->num_cs; i++) {
3796 struct mbus_dram_window *cs = dram->cs + i;
3798 writel(((cs->size - 1) & 0xffff0000) |
3799 (cs->mbus_attr << 8) |
3800 (dram->mbus_dram_target_id << 4) | 1,
3801 hpriv->base + WINDOW_CTRL(i));
3802 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3807 * mv_platform_probe - handle a positive probe of an soc Marvell
3809 * @pdev: platform device found
3812 * Inherited from caller.
3814 static int mv_platform_probe(struct platform_device *pdev)
3816 static int printed_version;
3817 const struct mv_sata_platform_data *mv_platform_data;
3818 const struct ata_port_info *ppi[] =
3819 { &mv_port_info[chip_soc], NULL };
3820 struct ata_host *host;
3821 struct mv_host_priv *hpriv;
3822 struct resource *res;
3825 if (!printed_version++)
3826 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3829 * Simple resource validation ..
3831 if (unlikely(pdev->num_resources != 2)) {
3832 dev_err(&pdev->dev, "invalid number of resources\n");
3837 * Get the register base first
3839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3844 mv_platform_data = pdev->dev.platform_data;
3845 n_ports = mv_platform_data->n_ports;
3847 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3848 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3850 if (!host || !hpriv)
3852 host->private_data = hpriv;
3853 hpriv->n_ports = n_ports;
3856 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3857 res->end - res->start + 1);
3858 hpriv->base -= MV_SATAHC0_REG_BASE;
3861 * (Re-)program MBUS remapping windows if we are asked to.
3863 if (mv_platform_data->dram != NULL)
3864 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3866 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3870 /* initialize adapter */
3871 rc = mv_init_host(host, chip_soc);
3875 dev_printk(KERN_INFO, &pdev->dev,
3876 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3879 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3880 IRQF_SHARED, &mv6_sht);
3885 * mv_platform_remove - unplug a platform interface
3886 * @pdev: platform device
3888 * A platform bus SATA device has been unplugged. Perform the needed
3889 * cleanup. Also called on module unload for any active devices.
3891 static int __devexit mv_platform_remove(struct platform_device *pdev)
3893 struct device *dev = &pdev->dev;
3894 struct ata_host *host = dev_get_drvdata(dev);
3896 ata_host_detach(host);
3900 static struct platform_driver mv_platform_driver = {
3901 .probe = mv_platform_probe,
3902 .remove = __devexit_p(mv_platform_remove),
3905 .owner = THIS_MODULE,
3911 static int mv_pci_init_one(struct pci_dev *pdev,
3912 const struct pci_device_id *ent);
3915 static struct pci_driver mv_pci_driver = {
3917 .id_table = mv_pci_tbl,
3918 .probe = mv_pci_init_one,
3919 .remove = ata_pci_remove_one,
3922 /* move to PCI layer or libata core? */
3923 static int pci_go_64(struct pci_dev *pdev)
3927 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3928 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3930 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3932 dev_printk(KERN_ERR, &pdev->dev,
3933 "64-bit DMA enable failed\n");
3938 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3940 dev_printk(KERN_ERR, &pdev->dev,
3941 "32-bit DMA enable failed\n");
3944 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3946 dev_printk(KERN_ERR, &pdev->dev,
3947 "32-bit consistent DMA enable failed\n");
3956 * mv_print_info - Dump key info to kernel log for perusal.
3957 * @host: ATA host to print info about
3959 * FIXME: complete this.
3962 * Inherited from caller.
3964 static void mv_print_info(struct ata_host *host)
3966 struct pci_dev *pdev = to_pci_dev(host->dev);
3967 struct mv_host_priv *hpriv = host->private_data;
3969 const char *scc_s, *gen;
3971 /* Use this to determine the HW stepping of the chip so we know
3972 * what errata to workaround
3974 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3977 else if (scc == 0x01)
3982 if (IS_GEN_I(hpriv))
3984 else if (IS_GEN_II(hpriv))
3986 else if (IS_GEN_IIE(hpriv))
3991 dev_printk(KERN_INFO, &pdev->dev,
3992 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3993 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3994 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3998 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3999 * @pdev: PCI device found
4000 * @ent: PCI device ID entry for the matched host
4003 * Inherited from caller.
4005 static int mv_pci_init_one(struct pci_dev *pdev,
4006 const struct pci_device_id *ent)
4008 static int printed_version;
4009 unsigned int board_idx = (unsigned int)ent->driver_data;
4010 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4011 struct ata_host *host;
4012 struct mv_host_priv *hpriv;
4015 if (!printed_version++)
4016 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4019 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4021 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4022 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4023 if (!host || !hpriv)
4025 host->private_data = hpriv;
4026 hpriv->n_ports = n_ports;
4028 /* acquire resources */
4029 rc = pcim_enable_device(pdev);
4033 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4035 pcim_pin_device(pdev);
4038 host->iomap = pcim_iomap_table(pdev);
4039 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4041 rc = pci_go_64(pdev);
4045 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4049 /* initialize adapter */
4050 rc = mv_init_host(host, board_idx);
4054 /* Enable message-switched interrupts, if requested */
4055 if (msi && pci_enable_msi(pdev) == 0)
4056 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4058 mv_dump_pci_cfg(pdev, 0x68);
4059 mv_print_info(host);
4061 pci_set_master(pdev);
4062 pci_try_set_mwi(pdev);
4063 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4064 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4068 static int mv_platform_probe(struct platform_device *pdev);
4069 static int __devexit mv_platform_remove(struct platform_device *pdev);
4071 static int __init mv_init(void)
4075 rc = pci_register_driver(&mv_pci_driver);
4079 rc = platform_driver_register(&mv_platform_driver);
4083 pci_unregister_driver(&mv_pci_driver);
4088 static void __exit mv_exit(void)
4091 pci_unregister_driver(&mv_pci_driver);
4093 platform_driver_unregister(&mv_platform_driver);
4096 MODULE_AUTHOR("Brett Russ");
4097 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4098 MODULE_LICENSE("GPL");
4099 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4100 MODULE_VERSION(DRV_VERSION);
4101 MODULE_ALIAS("platform:" DRV_NAME);
4103 module_init(mv_init);
4104 module_exit(mv_exit);