2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
7 * This file is released under GPL v2.
9 * This controller is eccentric and easily locks up if something isn't
10 * right. Documentation is available at initio's website but it only
11 * documents registers (not programming model).
15 * - ATAPI read works but burning doesn't. This thing is really
16 * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
17 * ATAPI DMA WRITE should be programmed. If you've got a clue, be
19 * - Both STR and STD work.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27 #include <linux/blkdev.h>
28 #include <scsi/scsi_device.h>
30 #define DRV_NAME "sata_inic162x"
31 #define DRV_VERSION "0.3"
45 /* registers for ATA TF operation */
52 PORT_PRD_XFERLEN = 0x10,
60 HCTL_IRQOFF = (1 << 8), /* global IRQ off */
61 HCTL_PWRDWN = (1 << 13), /* power down PHYs */
62 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
63 HCTL_RPGSEL = (1 << 15), /* register page select */
65 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
68 /* HOST_IRQ_(STAT|MASK) bits */
69 HIRQ_PORT0 = (1 << 0),
70 HIRQ_PORT1 = (1 << 1),
71 HIRQ_SOFT = (1 << 14),
72 HIRQ_GLOBAL = (1 << 15), /* STAT only */
74 /* PORT_IRQ_(STAT|MASK) bits */
75 PIRQ_OFFLINE = (1 << 0), /* device unplugged */
76 PIRQ_ONLINE = (1 << 1), /* device plugged */
77 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
78 PIRQ_FATAL = (1 << 3), /* fatal error */
79 PIRQ_ATA = (1 << 4), /* ATA interrupt */
80 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
81 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
83 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
85 PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA,
86 PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE,
87 PIRQ_MASK_FREEZE = 0xff,
89 /* PORT_PRD_CTL bits */
90 PRD_CTL_START = (1 << 0),
91 PRD_CTL_WR = (1 << 3),
92 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
94 /* PORT_IDMA_CTL bits */
95 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
96 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
97 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
98 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
101 struct inic_host_priv {
105 struct inic_port_priv {
111 static struct scsi_host_template inic_sht = {
112 ATA_BMDMA_SHT(DRV_NAME),
115 static const int scr_map[] = {
121 static void __iomem *inic_port_base(struct ata_port *ap)
123 return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE;
126 static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask)
128 void __iomem *port_base = inic_port_base(ap);
129 struct inic_port_priv *pp = ap->private_data;
131 writeb(mask, port_base + PORT_IRQ_MASK);
132 pp->cached_pirq_mask = mask;
135 static void inic_set_pirq_mask(struct ata_port *ap, u8 mask)
137 struct inic_port_priv *pp = ap->private_data;
139 if (pp->cached_pirq_mask != mask)
140 __inic_set_pirq_mask(ap, mask);
143 static void inic_reset_port(void __iomem *port_base)
145 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
148 ctl = readw(idma_ctl);
149 ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO);
151 /* mask IRQ and assert reset */
152 writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl);
153 readw(idma_ctl); /* flush */
155 /* give it some time */
159 writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl);
162 writeb(0xff, port_base + PORT_IRQ_STAT);
164 /* reenable ATA IRQ, turn off IDMA mode */
165 writew(ctl, idma_ctl);
168 static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
170 void __iomem *scr_addr = ap->ioaddr.scr_addr;
173 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
176 addr = scr_addr + scr_map[sc_reg] * 4;
177 *val = readl(scr_addr + scr_map[sc_reg] * 4);
179 /* this controller has stuck DIAG.N, ignore it */
180 if (sc_reg == SCR_ERROR)
181 *val &= ~SERR_PHYRDY_CHG;
185 static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
187 void __iomem *scr_addr = ap->ioaddr.scr_addr;
190 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
193 addr = scr_addr + scr_map[sc_reg] * 4;
194 writel(val, scr_addr + scr_map[sc_reg] * 4);
199 * In TF mode, inic162x is very similar to SFF device. TF registers
200 * function the same. DMA engine behaves similary using the same PRD
201 * format as BMDMA but different command register, interrupt and event
202 * notification methods are used. The following inic_bmdma_*()
203 * functions do the impedance matching.
205 static void inic_bmdma_setup(struct ata_queued_cmd *qc)
207 struct ata_port *ap = qc->ap;
208 struct inic_port_priv *pp = ap->private_data;
209 void __iomem *port_base = inic_port_base(ap);
210 int rw = qc->tf.flags & ATA_TFLAG_WRITE;
212 /* make sure device sees PRD table writes */
215 /* load transfer length */
216 writel(qc->nbytes, port_base + PORT_PRD_XFERLEN);
218 /* turn on DMA and specify data direction */
219 pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN;
221 pp->cached_prdctl |= PRD_CTL_WR;
222 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
224 /* issue r/w command */
225 ap->ops->sff_exec_command(ap, &qc->tf);
228 static void inic_bmdma_start(struct ata_queued_cmd *qc)
230 struct ata_port *ap = qc->ap;
231 struct inic_port_priv *pp = ap->private_data;
232 void __iomem *port_base = inic_port_base(ap);
234 /* start host DMA transaction */
235 pp->cached_prdctl |= PRD_CTL_START;
236 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
239 static void inic_bmdma_stop(struct ata_queued_cmd *qc)
241 struct ata_port *ap = qc->ap;
242 struct inic_port_priv *pp = ap->private_data;
243 void __iomem *port_base = inic_port_base(ap);
245 /* stop DMA engine */
246 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
249 static u8 inic_bmdma_status(struct ata_port *ap)
251 /* event is already verified by the interrupt handler */
255 static void inic_host_intr(struct ata_port *ap)
257 void __iomem *port_base = inic_port_base(ap);
258 struct ata_eh_info *ehi = &ap->link.eh_info;
261 /* fetch and clear irq */
262 irq_stat = readb(port_base + PORT_IRQ_STAT);
263 writeb(irq_stat, port_base + PORT_IRQ_STAT);
265 if (likely(!(irq_stat & PIRQ_ERR))) {
266 struct ata_queued_cmd *qc =
267 ata_qc_from_tag(ap, ap->link.active_tag);
269 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
270 ap->ops->sff_check_status(ap); /* clear ATA interrupt */
274 if (likely(ata_sff_host_intr(ap, qc)))
277 ap->ops->sff_check_status(ap); /* clear ATA interrupt */
278 ata_port_printk(ap, KERN_WARNING, "unhandled "
279 "interrupt, irq_stat=%x\n", irq_stat);
284 ata_ehi_push_desc(ehi, "irq_stat=0x%x", irq_stat);
286 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
287 ata_ehi_hotplugged(ehi);
293 static irqreturn_t inic_interrupt(int irq, void *dev_instance)
295 struct ata_host *host = dev_instance;
296 void __iomem *mmio_base = host->iomap[MMIO_BAR];
300 host_irq_stat = readw(mmio_base + HOST_IRQ_STAT);
302 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
305 spin_lock(&host->lock);
307 for (i = 0; i < NR_PORTS; i++) {
308 struct ata_port *ap = host->ports[i];
310 if (!(host_irq_stat & (HIRQ_PORT0 << i)))
313 if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
318 dev_printk(KERN_ERR, host->dev, "interrupt "
319 "from disabled port %d (0x%x)\n",
324 spin_unlock(&host->lock);
327 return IRQ_RETVAL(handled);
330 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
332 struct ata_port *ap = qc->ap;
334 /* ATA IRQ doesn't wait for DMA transfer completion and vice
335 * versa. Mask IRQ selectively to detect command completion.
336 * Without it, ATA DMA read command can cause data corruption.
338 * Something similar might be needed for ATAPI writes. I
339 * tried a lot of combinations but couldn't find the solution.
341 if (qc->tf.protocol == ATA_PROT_DMA &&
342 !(qc->tf.flags & ATA_TFLAG_WRITE))
343 inic_set_pirq_mask(ap, PIRQ_MASK_DMA_READ);
345 inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
347 /* Issuing a command to yet uninitialized port locks up the
348 * controller. Most of the time, this happens for the first
349 * command after reset which are ATA and ATAPI IDENTIFYs.
350 * Fast fail if stat is 0x7f or 0xff for those commands.
352 if (unlikely(qc->tf.command == ATA_CMD_ID_ATA ||
353 qc->tf.command == ATA_CMD_ID_ATAPI)) {
354 u8 stat = ap->ops->sff_check_status(ap);
355 if (stat == 0x7f || stat == 0xff)
359 return ata_sff_qc_issue(qc);
362 static void inic_freeze(struct ata_port *ap)
364 void __iomem *port_base = inic_port_base(ap);
366 __inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE);
368 ap->ops->sff_check_status(ap);
369 writeb(0xff, port_base + PORT_IRQ_STAT);
371 readb(port_base + PORT_IRQ_STAT); /* flush */
374 static void inic_thaw(struct ata_port *ap)
376 void __iomem *port_base = inic_port_base(ap);
378 ap->ops->sff_check_status(ap);
379 writeb(0xff, port_base + PORT_IRQ_STAT);
381 __inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
383 readb(port_base + PORT_IRQ_STAT); /* flush */
387 * SRST and SControl hardreset don't give valid signature on this
388 * controller. Only controller specific hardreset mechanism works.
390 static int inic_hardreset(struct ata_link *link, unsigned int *class,
391 unsigned long deadline)
393 struct ata_port *ap = link->ap;
394 void __iomem *port_base = inic_port_base(ap);
395 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
396 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
400 /* hammer it into sane state */
401 inic_reset_port(port_base);
403 val = readw(idma_ctl);
404 writew(val | IDMA_CTL_RST_ATA, idma_ctl);
405 readw(idma_ctl); /* flush */
407 writew(val & ~IDMA_CTL_RST_ATA, idma_ctl);
409 rc = sata_link_resume(link, timing, deadline);
411 ata_link_printk(link, KERN_WARNING, "failed to resume "
412 "link after reset (errno=%d)\n", rc);
416 *class = ATA_DEV_NONE;
417 if (ata_link_online(link)) {
418 struct ata_taskfile tf;
420 /* wait for link to become ready */
421 rc = ata_sff_wait_after_reset(link, 1, deadline);
422 /* link occupied, -ENODEV too is an error */
424 ata_link_printk(link, KERN_WARNING, "device not ready "
425 "after hardreset (errno=%d)\n", rc);
429 ata_sff_tf_read(ap, &tf);
430 *class = ata_dev_classify(&tf);
431 if (*class == ATA_DEV_UNKNOWN)
432 *class = ATA_DEV_NONE;
438 static void inic_error_handler(struct ata_port *ap)
440 void __iomem *port_base = inic_port_base(ap);
441 struct inic_port_priv *pp = ap->private_data;
444 /* reset PIO HSM and stop DMA engine */
445 inic_reset_port(port_base);
447 spin_lock_irqsave(ap->lock, flags);
448 ap->hsm_task_state = HSM_ST_IDLE;
449 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
450 spin_unlock_irqrestore(ap->lock, flags);
452 /* PIO and DMA engines have been stopped, perform recovery */
453 ata_std_error_handler(ap);
456 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
458 /* make DMA engine forget about the failed command */
459 if (qc->flags & ATA_QCFLAG_FAILED)
460 inic_reset_port(inic_port_base(qc->ap));
463 static void inic_dev_config(struct ata_device *dev)
465 /* inic can only handle upto LBA28 max sectors */
466 if (dev->max_sectors > ATA_MAX_SECTORS)
467 dev->max_sectors = ATA_MAX_SECTORS;
469 if (dev->n_sectors >= 1 << 28) {
470 ata_dev_printk(dev, KERN_ERR,
471 "ERROR: This driver doesn't support LBA48 yet and may cause\n"
472 " data corruption on such devices. Disabling.\n");
473 ata_dev_disable(dev);
477 static void init_port(struct ata_port *ap)
479 void __iomem *port_base = inic_port_base(ap);
481 /* Setup PRD address */
482 writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
485 static int inic_port_resume(struct ata_port *ap)
491 static int inic_port_start(struct ata_port *ap)
493 void __iomem *port_base = inic_port_base(ap);
494 struct inic_port_priv *pp;
498 /* alloc and initialize private data */
499 pp = devm_kzalloc(ap->host->dev, sizeof(*pp), GFP_KERNEL);
502 ap->private_data = pp;
504 /* default PRD_CTL value, DMAEN, WR and START off */
505 tmp = readb(port_base + PORT_PRD_CTL);
506 tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START);
507 pp->dfl_prdctl = tmp;
509 /* Alloc resources */
510 rc = ata_port_start(ap);
521 static struct ata_port_operations inic_port_ops = {
522 .inherits = &ata_sff_port_ops,
524 .bmdma_setup = inic_bmdma_setup,
525 .bmdma_start = inic_bmdma_start,
526 .bmdma_stop = inic_bmdma_stop,
527 .bmdma_status = inic_bmdma_status,
528 .qc_issue = inic_qc_issue,
530 .freeze = inic_freeze,
532 .softreset = ATA_OP_NULL, /* softreset is broken */
533 .hardreset = inic_hardreset,
534 .error_handler = inic_error_handler,
535 .post_internal_cmd = inic_post_internal_cmd,
536 .dev_config = inic_dev_config,
538 .scr_read = inic_scr_read,
539 .scr_write = inic_scr_write,
541 .port_resume = inic_port_resume,
542 .port_start = inic_port_start,
545 static struct ata_port_info inic_port_info = {
546 /* For some reason, ATAPI_PROT_PIO is broken on this
547 * controller, and no, PIO_POLLING does't fix it. It somehow
548 * manages to report the wrong ireason and ignoring ireason
549 * results in machine lock up. Tell libata to always prefer
552 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
553 .pio_mask = 0x1f, /* pio0-4 */
554 .mwdma_mask = 0x07, /* mwdma0-2 */
555 .udma_mask = ATA_UDMA6,
556 .port_ops = &inic_port_ops
559 static int init_controller(void __iomem *mmio_base, u16 hctl)
564 hctl &= ~HCTL_KNOWN_BITS;
566 /* Soft reset whole controller. Spec says reset duration is 3
567 * PCI clocks, be generous and give it 10ms.
569 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
570 readw(mmio_base + HOST_CTL); /* flush */
572 for (i = 0; i < 10; i++) {
574 val = readw(mmio_base + HOST_CTL);
575 if (!(val & HCTL_SOFTRST))
579 if (val & HCTL_SOFTRST)
582 /* mask all interrupts and reset ports */
583 for (i = 0; i < NR_PORTS; i++) {
584 void __iomem *port_base = mmio_base + i * PORT_SIZE;
586 writeb(0xff, port_base + PORT_IRQ_MASK);
587 inic_reset_port(port_base);
590 /* port IRQ is masked now, unmask global IRQ */
591 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
592 val = readw(mmio_base + HOST_IRQ_MASK);
593 val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
594 writew(val, mmio_base + HOST_IRQ_MASK);
600 static int inic_pci_device_resume(struct pci_dev *pdev)
602 struct ata_host *host = dev_get_drvdata(&pdev->dev);
603 struct inic_host_priv *hpriv = host->private_data;
604 void __iomem *mmio_base = host->iomap[MMIO_BAR];
607 rc = ata_pci_device_do_resume(pdev);
611 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
612 rc = init_controller(mmio_base, hpriv->cached_hctl);
617 ata_host_resume(host);
623 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
625 static int printed_version;
626 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
627 struct ata_host *host;
628 struct inic_host_priv *hpriv;
629 void __iomem * const *iomap;
632 if (!printed_version++)
633 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
636 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
637 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
641 host->private_data = hpriv;
643 /* acquire resources and fill host */
644 rc = pcim_enable_device(pdev);
648 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
651 host->iomap = iomap = pcim_iomap_table(pdev);
653 for (i = 0; i < NR_PORTS; i++) {
654 struct ata_port *ap = host->ports[i];
655 struct ata_ioports *port = &ap->ioaddr;
656 unsigned int offset = i * PORT_SIZE;
658 port->cmd_addr = iomap[2 * i];
659 port->altstatus_addr =
660 port->ctl_addr = (void __iomem *)
661 ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS);
662 port->scr_addr = iomap[MMIO_BAR] + offset + PORT_SCR;
664 ata_sff_std_ports(port);
666 ata_port_pbar_desc(ap, MMIO_BAR, -1, "mmio");
667 ata_port_pbar_desc(ap, MMIO_BAR, offset, "port");
668 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
669 (unsigned long long)pci_resource_start(pdev, 2 * i),
670 (unsigned long long)pci_resource_start(pdev, (2 * i + 1)) |
674 hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL);
676 /* Set dma_mask. This devices doesn't support 64bit addressing. */
677 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
679 dev_printk(KERN_ERR, &pdev->dev,
680 "32-bit DMA enable failed\n");
684 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
686 dev_printk(KERN_ERR, &pdev->dev,
687 "32-bit consistent DMA enable failed\n");
692 * This controller is braindamaged. dma_boundary is 0xffff
693 * like others but it will lock up the whole machine HARD if
694 * 65536 byte PRD entry is fed. Reduce maximum segment size.
696 rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
698 dev_printk(KERN_ERR, &pdev->dev,
699 "failed to set the maximum segment size.\n");
703 rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl);
705 dev_printk(KERN_ERR, &pdev->dev,
706 "failed to initialize controller\n");
710 pci_set_master(pdev);
711 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
715 static const struct pci_device_id inic_pci_tbl[] = {
716 { PCI_VDEVICE(INIT, 0x1622), },
720 static struct pci_driver inic_pci_driver = {
722 .id_table = inic_pci_tbl,
724 .suspend = ata_pci_device_suspend,
725 .resume = inic_pci_device_resume,
727 .probe = inic_init_one,
728 .remove = ata_pci_remove_one,
731 static int __init inic_init(void)
733 return pci_register_driver(&inic_pci_driver);
736 static void __exit inic_exit(void)
738 pci_unregister_driver(&inic_pci_driver);
741 MODULE_AUTHOR("Tejun Heo");
742 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
743 MODULE_LICENSE("GPL v2");
744 MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
745 MODULE_VERSION(DRV_VERSION);
747 module_init(inic_init);
748 module_exit(inic_exit);