2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 * An ATA driver for the legacy ATA ports.
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
29 * Unsupported but docs exist:
30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
32 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
33 * on PC class systems. There are three hybrid devices that are exceptions
34 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
35 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
37 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
38 * opti82c465mv/promise 20230c/20630/winbond83759A
40 * Use the autospeed and pio_mask options with:
41 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
42 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
43 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
44 * Winbond W83759A, Promise PDC20230-B
46 * For now use autospeed and pio_mask as above with the W83759A. This may
51 #include <linux/kernel.h>
52 #include <linux/module.h>
53 #include <linux/pci.h>
54 #include <linux/init.h>
55 #include <linux/blkdev.h>
56 #include <linux/delay.h>
57 #include <scsi/scsi_host.h>
58 #include <linux/ata.h>
59 #include <linux/libata.h>
60 #include <linux/platform_device.h>
62 #define DRV_NAME "pata_legacy"
63 #define DRV_VERSION "0.6.5"
68 module_param(all, int, 0444);
69 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
76 struct platform_device *platform_dev;
90 QDI6580DP = 9, /* Dual channel mode is different */
102 enum controller type;
103 unsigned long private;
106 struct legacy_controller {
108 struct ata_port_operations *ops;
109 unsigned int pio_mask;
111 int (*setup)(struct platform_device *, struct legacy_probe *probe,
112 struct legacy_data *data);
115 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
117 static struct legacy_probe probe_list[NR_HOST];
118 static struct legacy_data legacy_data[NR_HOST];
119 static struct ata_host *legacy_host[NR_HOST];
120 static int nr_legacy_host;
123 static int probe_all; /* Set to check all ISA port ranges */
124 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
125 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
126 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
127 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
128 static int qdi; /* Set to probe QDI controllers */
129 static int winbond; /* Set to probe Winbond controllers,
130 give I/O port if non standard */
131 static int autospeed; /* Chip present which snoops speed changes */
132 static int pio_mask = 0x1F; /* PIO range for autospeed devices */
133 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
136 * legacy_probe_add - Add interface to probe list
137 * @port: Controller port
139 * @type: Controller type
140 * @private: Controller specific info
142 * Add an entry into the probe list for ATA controllers. This is used
143 * to add the default ISA slots and then to build up the table
144 * further according to other ISA/VLB/Weird device scans
146 * An I/O port list is used to keep ordering stable and sane, as we
147 * don't have any good way to talk about ordering otherwise
150 static int legacy_probe_add(unsigned long port, unsigned int irq,
151 enum controller type, unsigned long private)
153 struct legacy_probe *lp = &probe_list[0];
155 struct legacy_probe *free = NULL;
157 for (i = 0; i < NR_HOST; i++) {
158 if (lp->port == 0 && free == NULL)
160 /* Matching port, or the correct slot for ordering */
161 if (lp->port == port || legacy_port[i] == port) {
168 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
171 /* Fill in the entry for later probing */
175 free->private = private;
181 * legacy_set_mode - mode setting
183 * @unused: Device that failed when error is returned
185 * Use a non standard set_mode function. We don't want to be tuned.
187 * The BIOS configured everything. Our job is not to fiddle. Just use
188 * whatever PIO the hardware is using and leave it at that. When we
189 * get some kind of nice user driven API for control then we can
190 * expand on this as per hdparm in the base kernel.
193 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
195 struct ata_device *dev;
197 ata_link_for_each_dev(dev, link) {
198 if (ata_dev_enabled(dev)) {
199 ata_dev_printk(dev, KERN_INFO,
200 "configured for PIO\n");
201 dev->pio_mode = XFER_PIO_0;
202 dev->xfer_mode = XFER_PIO_0;
203 dev->xfer_shift = ATA_SHIFT_PIO;
204 dev->flags |= ATA_DFLAG_PIO;
210 static struct scsi_host_template legacy_sht = {
211 ATA_PIO_SHT(DRV_NAME),
215 * These ops are used if the user indicates the hardware
216 * snoops the commands to decide on the mode and handles the
217 * mode selection "magically" itself. Several legacy controllers
218 * do this. The mode range can be set if it is not 0x1F by setting
222 static struct ata_port_operations simple_port_ops = {
223 .tf_load = ata_tf_load,
224 .tf_read = ata_tf_read,
225 .check_status = ata_check_status,
226 .exec_command = ata_exec_command,
227 .dev_select = ata_std_dev_select,
229 .freeze = ata_bmdma_freeze,
230 .thaw = ata_bmdma_thaw,
231 .error_handler = ata_bmdma_error_handler,
232 .post_internal_cmd = ata_bmdma_post_internal_cmd,
233 .cable_detect = ata_cable_40wire,
235 .qc_prep = ata_qc_prep,
236 .qc_issue = ata_qc_issue_prot,
238 .data_xfer = ata_data_xfer_noirq,
240 .irq_handler = ata_interrupt,
241 .irq_clear = ata_noop_irq_clear,
242 .irq_on = ata_irq_on,
244 .port_start = ata_sff_port_start,
247 static struct ata_port_operations legacy_port_ops = {
248 .set_mode = legacy_set_mode,
250 .tf_load = ata_tf_load,
251 .tf_read = ata_tf_read,
252 .check_status = ata_check_status,
253 .exec_command = ata_exec_command,
254 .dev_select = ata_std_dev_select,
255 .cable_detect = ata_cable_40wire,
257 .freeze = ata_bmdma_freeze,
258 .thaw = ata_bmdma_thaw,
259 .error_handler = ata_bmdma_error_handler,
260 .post_internal_cmd = ata_bmdma_post_internal_cmd,
262 .qc_prep = ata_qc_prep,
263 .qc_issue = ata_qc_issue_prot,
265 .data_xfer = ata_data_xfer_noirq,
267 .irq_handler = ata_interrupt,
268 .irq_clear = ata_noop_irq_clear,
269 .irq_on = ata_irq_on,
271 .port_start = ata_sff_port_start,
275 * Promise 20230C and 20620 support
277 * This controller supports PIO0 to PIO2. We set PIO timings
278 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
279 * support is weird being DMA to controller and PIO'd to the host
283 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
286 int pio = adev->pio_mode - XFER_PIO_0;
290 /* Safe as UP only. Force I/Os to occur together */
292 local_irq_save(flags);
294 /* Unlock the control interface */
297 outb(inb(0x1F2) | 0x80, 0x1F2);
304 while ((inb(0x1F2) & 0x80) && --tries);
306 local_irq_restore(flags);
308 outb(inb(0x1F4) & 0x07, 0x1F4);
311 rt &= 0x07 << (3 * adev->devno);
313 rt |= (1 + 3 * pio) << (3 * adev->devno);
316 outb(inb(0x1F2) | 0x01, 0x1F2);
322 static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
323 unsigned char *buf, unsigned int buflen, int rw)
325 if (ata_id_has_dword_io(dev->id)) {
326 struct ata_port *ap = dev->link->ap;
327 int slop = buflen & 3;
330 local_irq_save(flags);
332 /* Perform the 32bit I/O synchronization sequence */
333 ioread8(ap->ioaddr.nsect_addr);
334 ioread8(ap->ioaddr.nsect_addr);
335 ioread8(ap->ioaddr.nsect_addr);
339 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
341 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
343 if (unlikely(slop)) {
346 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
347 memcpy(buf + buflen - slop, &pad, slop);
349 memcpy(&pad, buf + buflen - slop, slop);
350 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
354 local_irq_restore(flags);
356 buflen = ata_data_xfer_noirq(dev, buf, buflen, rw);
361 static struct ata_port_operations pdc20230_port_ops = {
362 .set_piomode = pdc20230_set_piomode,
364 .tf_load = ata_tf_load,
365 .tf_read = ata_tf_read,
366 .check_status = ata_check_status,
367 .exec_command = ata_exec_command,
368 .dev_select = ata_std_dev_select,
370 .freeze = ata_bmdma_freeze,
371 .thaw = ata_bmdma_thaw,
372 .error_handler = ata_bmdma_error_handler,
373 .post_internal_cmd = ata_bmdma_post_internal_cmd,
374 .cable_detect = ata_cable_40wire,
376 .qc_prep = ata_qc_prep,
377 .qc_issue = ata_qc_issue_prot,
379 .data_xfer = pdc_data_xfer_vlb,
381 .irq_handler = ata_interrupt,
382 .irq_clear = ata_noop_irq_clear,
383 .irq_on = ata_irq_on,
385 .port_start = ata_sff_port_start,
389 * Holtek 6560A support
391 * This controller supports PIO0 to PIO2 (no IORDY even though higher
392 * timings can be loaded).
395 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
400 /* Get the timing data in cycles. For now play safe at 50Mhz */
401 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
403 active = FIT(t.active, 2, 15);
404 recover = FIT(t.recover, 4, 15);
411 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
412 ioread8(ap->ioaddr.status_addr);
415 static struct ata_port_operations ht6560a_port_ops = {
416 .set_piomode = ht6560a_set_piomode,
418 .tf_load = ata_tf_load,
419 .tf_read = ata_tf_read,
420 .check_status = ata_check_status,
421 .exec_command = ata_exec_command,
422 .dev_select = ata_std_dev_select,
424 .freeze = ata_bmdma_freeze,
425 .thaw = ata_bmdma_thaw,
426 .error_handler = ata_bmdma_error_handler,
427 .post_internal_cmd = ata_bmdma_post_internal_cmd,
428 .cable_detect = ata_cable_40wire,
430 .qc_prep = ata_qc_prep,
431 .qc_issue = ata_qc_issue_prot,
433 .data_xfer = ata_data_xfer, /* Check vlb/noirq */
435 .irq_handler = ata_interrupt,
436 .irq_clear = ata_noop_irq_clear,
437 .irq_on = ata_irq_on,
439 .port_start = ata_sff_port_start,
443 * Holtek 6560B support
445 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
446 * setting unless we see an ATAPI device in which case we force it off.
448 * FIXME: need to implement 2nd channel support.
451 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
456 /* Get the timing data in cycles. For now play safe at 50Mhz */
457 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
459 active = FIT(t.active, 2, 15);
460 recover = FIT(t.recover, 2, 16);
468 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
470 if (adev->class != ATA_DEV_ATA) {
471 u8 rconf = inb(0x3E6);
477 ioread8(ap->ioaddr.status_addr);
480 static struct ata_port_operations ht6560b_port_ops = {
481 .set_piomode = ht6560b_set_piomode,
483 .tf_load = ata_tf_load,
484 .tf_read = ata_tf_read,
485 .check_status = ata_check_status,
486 .exec_command = ata_exec_command,
487 .dev_select = ata_std_dev_select,
489 .freeze = ata_bmdma_freeze,
490 .thaw = ata_bmdma_thaw,
491 .error_handler = ata_bmdma_error_handler,
492 .post_internal_cmd = ata_bmdma_post_internal_cmd,
493 .cable_detect = ata_cable_40wire,
495 .qc_prep = ata_qc_prep,
496 .qc_issue = ata_qc_issue_prot,
498 .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */
500 .irq_handler = ata_interrupt,
501 .irq_clear = ata_noop_irq_clear,
502 .irq_on = ata_irq_on,
504 .port_start = ata_sff_port_start,
508 * Opti core chipset helpers
512 * opti_syscfg - read OPTI chipset configuration
513 * @reg: Configuration register to read
515 * Returns the value of an OPTI system board configuration register.
518 static u8 opti_syscfg(u8 reg)
523 /* Uniprocessor chipset and must force cycles adjancent */
524 local_irq_save(flags);
527 local_irq_restore(flags);
534 * This controller supports PIO0 to PIO3.
537 static void opti82c611a_set_piomode(struct ata_port *ap,
538 struct ata_device *adev)
540 u8 active, recover, setup;
542 struct ata_device *pair = ata_dev_pair(adev);
544 int khz[4] = { 50000, 40000, 33000, 25000 };
547 /* Enter configuration mode */
548 ioread16(ap->ioaddr.error_addr);
549 ioread16(ap->ioaddr.error_addr);
550 iowrite8(3, ap->ioaddr.nsect_addr);
552 /* Read VLB clock strapping */
553 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
555 /* Get the timing data in cycles */
556 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
558 /* Setup timing is shared */
560 struct ata_timing tp;
561 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
563 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
566 active = FIT(t.active, 2, 17) - 2;
567 recover = FIT(t.recover, 1, 16) - 1;
568 setup = FIT(t.setup, 1, 4) - 1;
570 /* Select the right timing bank for write timing */
571 rc = ioread8(ap->ioaddr.lbal_addr);
573 rc |= (adev->devno << 7);
574 iowrite8(rc, ap->ioaddr.lbal_addr);
576 /* Write the timings */
577 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
579 /* Select the right bank for read timings, also
580 load the shared timings for address */
581 rc = ioread8(ap->ioaddr.device_addr);
583 rc |= adev->devno; /* Index select */
584 rc |= (setup << 4) | 0x04;
585 iowrite8(rc, ap->ioaddr.device_addr);
587 /* Load the read timings */
588 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
590 /* Ensure the timing register mode is right */
591 rc = ioread8(ap->ioaddr.lbal_addr);
594 iowrite8(rc, ap->ioaddr.lbal_addr);
596 /* Exit command mode */
597 iowrite8(0x83, ap->ioaddr.nsect_addr);
601 static struct ata_port_operations opti82c611a_port_ops = {
602 .set_piomode = opti82c611a_set_piomode,
604 .tf_load = ata_tf_load,
605 .tf_read = ata_tf_read,
606 .check_status = ata_check_status,
607 .exec_command = ata_exec_command,
608 .dev_select = ata_std_dev_select,
610 .freeze = ata_bmdma_freeze,
611 .thaw = ata_bmdma_thaw,
612 .error_handler = ata_bmdma_error_handler,
613 .post_internal_cmd = ata_bmdma_post_internal_cmd,
614 .cable_detect = ata_cable_40wire,
616 .qc_prep = ata_qc_prep,
617 .qc_issue = ata_qc_issue_prot,
619 .data_xfer = ata_data_xfer,
621 .irq_handler = ata_interrupt,
622 .irq_clear = ata_noop_irq_clear,
623 .irq_on = ata_irq_on,
625 .port_start = ata_sff_port_start,
631 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
632 * version is dual channel but doesn't have a lot of unique registers.
635 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
637 u8 active, recover, setup;
639 struct ata_device *pair = ata_dev_pair(adev);
641 int khz[4] = { 50000, 40000, 33000, 25000 };
646 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
648 /* Enter configuration mode */
649 ioread16(ap->ioaddr.error_addr);
650 ioread16(ap->ioaddr.error_addr);
651 iowrite8(3, ap->ioaddr.nsect_addr);
653 /* Read VLB clock strapping */
654 clock = 1000000000 / khz[sysclk];
656 /* Get the timing data in cycles */
657 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
659 /* Setup timing is shared */
661 struct ata_timing tp;
662 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
664 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
667 active = FIT(t.active, 2, 17) - 2;
668 recover = FIT(t.recover, 1, 16) - 1;
669 setup = FIT(t.setup, 1, 4) - 1;
671 /* Select the right timing bank for write timing */
672 rc = ioread8(ap->ioaddr.lbal_addr);
674 rc |= (adev->devno << 7);
675 iowrite8(rc, ap->ioaddr.lbal_addr);
677 /* Write the timings */
678 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
680 /* Select the right bank for read timings, also
681 load the shared timings for address */
682 rc = ioread8(ap->ioaddr.device_addr);
684 rc |= adev->devno; /* Index select */
685 rc |= (setup << 4) | 0x04;
686 iowrite8(rc, ap->ioaddr.device_addr);
688 /* Load the read timings */
689 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
691 /* Ensure the timing register mode is right */
692 rc = ioread8(ap->ioaddr.lbal_addr);
695 iowrite8(rc, ap->ioaddr.lbal_addr);
697 /* Exit command mode */
698 iowrite8(0x83, ap->ioaddr.nsect_addr);
700 /* We need to know this for quad device on the MVB */
701 ap->host->private_data = ap;
705 * opt82c465mv_qc_issue_prot - command issue
706 * @qc: command pending
708 * Called when the libata layer is about to issue a command. We wrap
709 * this interface so that we can load the correct ATA timings. The
710 * MVB has a single set of timing registers and these are shared
711 * across channels. As there are two registers we really ought to
712 * track the last two used values as a sort of register window. For
713 * now we just reload on a channel switch. On the single channel
714 * setup this condition never fires so we do nothing extra.
716 * FIXME: dual channel needs ->serialize support
719 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
721 struct ata_port *ap = qc->ap;
722 struct ata_device *adev = qc->dev;
724 /* If timings are set and for the wrong channel (2nd test is
725 due to a libata shortcoming and will eventually go I hope) */
726 if (ap->host->private_data != ap->host
727 && ap->host->private_data != NULL)
728 opti82c46x_set_piomode(ap, adev);
730 return ata_qc_issue_prot(qc);
733 static struct ata_port_operations opti82c46x_port_ops = {
734 .set_piomode = opti82c46x_set_piomode,
736 .tf_load = ata_tf_load,
737 .tf_read = ata_tf_read,
738 .check_status = ata_check_status,
739 .exec_command = ata_exec_command,
740 .dev_select = ata_std_dev_select,
742 .freeze = ata_bmdma_freeze,
743 .thaw = ata_bmdma_thaw,
744 .error_handler = ata_bmdma_error_handler,
745 .post_internal_cmd = ata_bmdma_post_internal_cmd,
746 .cable_detect = ata_cable_40wire,
748 .qc_prep = ata_qc_prep,
749 .qc_issue = opti82c46x_qc_issue_prot,
751 .data_xfer = ata_data_xfer,
753 .irq_handler = ata_interrupt,
754 .irq_clear = ata_noop_irq_clear,
755 .irq_on = ata_irq_on,
757 .port_start = ata_sff_port_start,
760 static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
763 struct legacy_data *ld_qdi = ap->host->private_data;
764 int active, recovery;
767 /* Get the timing data in cycles */
768 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
771 active = 8 - FIT(t.active, 1, 8);
772 recovery = 18 - FIT(t.recover, 3, 18);
774 active = 9 - FIT(t.active, 2, 9);
775 recovery = 15 - FIT(t.recover, 0, 15);
777 timing = (recovery << 4) | active | 0x08;
779 ld_qdi->clock[adev->devno] = timing;
781 outb(timing, ld_qdi->timing);
785 * qdi6580dp_set_piomode - PIO setup for dual channel
788 * @irq: interrupt line
790 * In dual channel mode the 6580 has one clock per channel and we have
791 * to software clockswitch in qc_issue_prot.
794 static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev)
797 struct legacy_data *ld_qdi = ap->host->private_data;
798 int active, recovery;
801 /* Get the timing data in cycles */
802 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
805 active = 8 - FIT(t.active, 1, 8);
806 recovery = 18 - FIT(t.recover, 3, 18);
808 active = 9 - FIT(t.active, 2, 9);
809 recovery = 15 - FIT(t.recover, 0, 15);
811 timing = (recovery << 4) | active | 0x08;
813 ld_qdi->clock[adev->devno] = timing;
815 outb(timing, ld_qdi->timing + 2 * ap->port_no);
817 if (adev->class != ATA_DEV_ATA)
818 outb(0x5F, ld_qdi->timing + 3);
822 * qdi6580_set_piomode - PIO setup for single channel
826 * In single channel mode the 6580 has one clock per device and we can
827 * avoid the requirement to clock switch. We also have to load the timing
828 * into the right clock according to whether we are master or slave.
831 static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
834 struct legacy_data *ld_qdi = ap->host->private_data;
835 int active, recovery;
838 /* Get the timing data in cycles */
839 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
842 active = 8 - FIT(t.active, 1, 8);
843 recovery = 18 - FIT(t.recover, 3, 18);
845 active = 9 - FIT(t.active, 2, 9);
846 recovery = 15 - FIT(t.recover, 0, 15);
848 timing = (recovery << 4) | active | 0x08;
849 ld_qdi->clock[adev->devno] = timing;
850 outb(timing, ld_qdi->timing + 2 * adev->devno);
852 if (adev->class != ATA_DEV_ATA)
853 outb(0x5F, ld_qdi->timing + 3);
857 * qdi_qc_issue_prot - command issue
858 * @qc: command pending
860 * Called when the libata layer is about to issue a command. We wrap
861 * this interface so that we can load the correct ATA timings.
864 static unsigned int qdi_qc_issue_prot(struct ata_queued_cmd *qc)
866 struct ata_port *ap = qc->ap;
867 struct ata_device *adev = qc->dev;
868 struct legacy_data *ld_qdi = ap->host->private_data;
870 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
871 if (adev->pio_mode) {
872 ld_qdi->last = ld_qdi->clock[adev->devno];
873 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
877 return ata_qc_issue_prot(qc);
880 static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,
881 unsigned int buflen, int rw)
883 struct ata_port *ap = adev->link->ap;
884 int slop = buflen & 3;
886 if (ata_id_has_dword_io(adev->id)) {
888 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
890 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
892 if (unlikely(slop)) {
895 memcpy(&pad, buf + buflen - slop, slop);
896 pad = le32_to_cpu(pad);
897 iowrite32(pad, ap->ioaddr.data_addr);
899 pad = ioread32(ap->ioaddr.data_addr);
900 pad = cpu_to_le32(pad);
901 memcpy(buf + buflen - slop, &pad, slop);
904 return (buflen + 3) & ~3;
906 return ata_data_xfer(adev, buf, buflen, rw);
909 static int qdi_port(struct platform_device *dev,
910 struct legacy_probe *lp, struct legacy_data *ld)
912 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
914 ld->timing = lp->private;
918 static struct ata_port_operations qdi6500_port_ops = {
919 .set_piomode = qdi6500_set_piomode,
921 .tf_load = ata_tf_load,
922 .tf_read = ata_tf_read,
923 .check_status = ata_check_status,
924 .exec_command = ata_exec_command,
925 .dev_select = ata_std_dev_select,
927 .freeze = ata_bmdma_freeze,
928 .thaw = ata_bmdma_thaw,
929 .error_handler = ata_bmdma_error_handler,
930 .post_internal_cmd = ata_bmdma_post_internal_cmd,
931 .cable_detect = ata_cable_40wire,
933 .qc_prep = ata_qc_prep,
934 .qc_issue = qdi_qc_issue_prot,
936 .data_xfer = vlb32_data_xfer,
938 .irq_handler = ata_interrupt,
939 .irq_clear = ata_noop_irq_clear,
940 .irq_on = ata_irq_on,
942 .port_start = ata_sff_port_start,
945 static struct ata_port_operations qdi6580_port_ops = {
946 .set_piomode = qdi6580_set_piomode,
948 .tf_load = ata_tf_load,
949 .tf_read = ata_tf_read,
950 .check_status = ata_check_status,
951 .exec_command = ata_exec_command,
952 .dev_select = ata_std_dev_select,
954 .freeze = ata_bmdma_freeze,
955 .thaw = ata_bmdma_thaw,
956 .error_handler = ata_bmdma_error_handler,
957 .post_internal_cmd = ata_bmdma_post_internal_cmd,
958 .cable_detect = ata_cable_40wire,
960 .qc_prep = ata_qc_prep,
961 .qc_issue = ata_qc_issue_prot,
963 .data_xfer = vlb32_data_xfer,
965 .irq_handler = ata_interrupt,
966 .irq_clear = ata_noop_irq_clear,
967 .irq_on = ata_irq_on,
969 .port_start = ata_sff_port_start,
972 static struct ata_port_operations qdi6580dp_port_ops = {
973 .set_piomode = qdi6580dp_set_piomode,
975 .tf_load = ata_tf_load,
976 .tf_read = ata_tf_read,
977 .check_status = ata_check_status,
978 .exec_command = ata_exec_command,
979 .dev_select = ata_std_dev_select,
981 .freeze = ata_bmdma_freeze,
982 .thaw = ata_bmdma_thaw,
983 .error_handler = ata_bmdma_error_handler,
984 .post_internal_cmd = ata_bmdma_post_internal_cmd,
985 .cable_detect = ata_cable_40wire,
987 .qc_prep = ata_qc_prep,
988 .qc_issue = qdi_qc_issue_prot,
990 .data_xfer = vlb32_data_xfer,
992 .irq_handler = ata_interrupt,
993 .irq_clear = ata_noop_irq_clear,
994 .irq_on = ata_irq_on,
996 .port_start = ata_sff_port_start,
999 static DEFINE_SPINLOCK(winbond_lock);
1001 static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
1003 unsigned long flags;
1004 spin_lock_irqsave(&winbond_lock, flags);
1005 outb(reg, port + 0x01);
1006 outb(val, port + 0x02);
1007 spin_unlock_irqrestore(&winbond_lock, flags);
1010 static u8 winbond_readcfg(unsigned long port, u8 reg)
1014 unsigned long flags;
1015 spin_lock_irqsave(&winbond_lock, flags);
1016 outb(reg, port + 0x01);
1017 val = inb(port + 0x02);
1018 spin_unlock_irqrestore(&winbond_lock, flags);
1023 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
1025 struct ata_timing t;
1026 struct legacy_data *ld_winbond = ap->host->private_data;
1027 int active, recovery;
1029 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
1031 reg = winbond_readcfg(ld_winbond->timing, 0x81);
1033 /* Get the timing data in cycles */
1034 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
1035 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
1037 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
1039 active = (FIT(t.active, 3, 17) - 1) & 0x0F;
1040 recovery = (FIT(t.recover, 1, 15) + 1) & 0x0F;
1041 timing = (active << 4) | recovery;
1042 winbond_writecfg(ld_winbond->timing, timing, reg);
1044 /* Load the setup timing */
1047 if (adev->class != ATA_DEV_ATA)
1048 reg |= 0x08; /* FIFO off */
1049 if (!ata_pio_need_iordy(adev))
1050 reg |= 0x02; /* IORDY off */
1051 reg |= (FIT(t.setup, 0, 3) << 6);
1052 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
1055 static int winbond_port(struct platform_device *dev,
1056 struct legacy_probe *lp, struct legacy_data *ld)
1058 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
1060 ld->timing = lp->private;
1064 static struct ata_port_operations winbond_port_ops = {
1065 .set_piomode = winbond_set_piomode,
1067 .tf_load = ata_tf_load,
1068 .tf_read = ata_tf_read,
1069 .check_status = ata_check_status,
1070 .exec_command = ata_exec_command,
1071 .dev_select = ata_std_dev_select,
1073 .freeze = ata_bmdma_freeze,
1074 .thaw = ata_bmdma_thaw,
1075 .error_handler = ata_bmdma_error_handler,
1076 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1077 .cable_detect = ata_cable_40wire,
1079 .qc_prep = ata_qc_prep,
1080 .qc_issue = ata_qc_issue_prot,
1082 .data_xfer = vlb32_data_xfer,
1084 .irq_clear = ata_noop_irq_clear,
1085 .irq_on = ata_irq_on,
1087 .port_start = ata_sff_port_start,
1090 static struct legacy_controller controllers[] = {
1091 {"BIOS", &legacy_port_ops, 0x1F,
1092 ATA_FLAG_NO_IORDY, NULL },
1093 {"Snooping", &simple_port_ops, 0x1F,
1095 {"PDC20230", &pdc20230_port_ops, 0x7,
1096 ATA_FLAG_NO_IORDY, NULL },
1097 {"HT6560A", &ht6560a_port_ops, 0x07,
1098 ATA_FLAG_NO_IORDY, NULL },
1099 {"HT6560B", &ht6560b_port_ops, 0x1F,
1100 ATA_FLAG_NO_IORDY, NULL },
1101 {"OPTI82C611A", &opti82c611a_port_ops, 0x0F,
1103 {"OPTI82C46X", &opti82c46x_port_ops, 0x0F,
1105 {"QDI6500", &qdi6500_port_ops, 0x07,
1106 ATA_FLAG_NO_IORDY, qdi_port },
1107 {"QDI6580", &qdi6580_port_ops, 0x1F,
1109 {"QDI6580DP", &qdi6580dp_port_ops, 0x1F,
1111 {"W83759A", &winbond_port_ops, 0x1F,
1116 * probe_chip_type - Discover controller
1117 * @probe: Probe entry to check
1119 * Probe an ATA port and identify the type of controller. We don't
1120 * check if the controller appears to be driveless at this point.
1123 static __init int probe_chip_type(struct legacy_probe *probe)
1125 int mask = 1 << probe->slot;
1127 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
1128 u8 reg = winbond_readcfg(winbond, 0x81);
1129 reg |= 0x80; /* jumpered mode off */
1130 winbond_writecfg(winbond, 0x81, reg);
1131 reg = winbond_readcfg(winbond, 0x83);
1132 reg |= 0xF0; /* local control */
1133 winbond_writecfg(winbond, 0x83, reg);
1134 reg = winbond_readcfg(winbond, 0x85);
1135 reg |= 0xF0; /* programmable timing */
1136 winbond_writecfg(winbond, 0x85, reg);
1138 reg = winbond_readcfg(winbond, 0x81);
1143 if (probe->port == 0x1F0) {
1144 unsigned long flags;
1145 local_irq_save(flags);
1147 outb(inb(0x1F2) | 0x80, 0x1F2);
1155 if ((inb(0x1F2) & 0x80) == 0) {
1156 /* PDC20230c or 20630 ? */
1157 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
1161 local_irq_restore(flags);
1167 if (inb(0x1F2) == 0x00)
1168 printk(KERN_INFO "PDC20230-B VLB ATA "
1169 "controller detected.\n");
1170 local_irq_restore(flags);
1173 local_irq_restore(flags);
1180 if (opti82c611a & mask)
1182 if (opti82c46x & mask)
1184 if (autospeed & mask)
1191 * legacy_init_one - attach a legacy interface
1194 * Register an ISA bus IDE interface. Such interfaces are PIO and we
1195 * assume do not support IRQ sharing.
1198 static __init int legacy_init_one(struct legacy_probe *probe)
1200 struct legacy_controller *controller = &controllers[probe->type];
1201 int pio_modes = controller->pio_mask;
1202 unsigned long io = probe->port;
1203 u32 mask = (1 << probe->slot);
1204 struct ata_port_operations *ops = controller->ops;
1205 struct legacy_data *ld = &legacy_data[probe->slot];
1206 struct ata_host *host = NULL;
1207 struct ata_port *ap;
1208 struct platform_device *pdev;
1209 struct ata_device *dev;
1210 void __iomem *io_addr, *ctrl_addr;
1211 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
1214 iordy |= controller->flags;
1216 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
1218 return PTR_ERR(pdev);
1221 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
1222 devm_request_region(&pdev->dev, io + 0x0206, 1,
1223 "pata_legacy") == NULL)
1227 io_addr = devm_ioport_map(&pdev->dev, io, 8);
1228 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
1229 if (!io_addr || !ctrl_addr)
1231 if (controller->setup)
1232 if (controller->setup(pdev, probe, ld) < 0)
1234 host = ata_host_alloc(&pdev->dev, 1);
1237 ap = host->ports[0];
1240 ap->pio_mask = pio_modes;
1241 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
1242 ap->ioaddr.cmd_addr = io_addr;
1243 ap->ioaddr.altstatus_addr = ctrl_addr;
1244 ap->ioaddr.ctl_addr = ctrl_addr;
1245 ata_std_ports(&ap->ioaddr);
1246 ap->host->private_data = ld;
1248 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
1250 ret = ata_host_activate(host, probe->irq, ata_interrupt, 0,
1254 ld->platform_dev = pdev;
1256 /* Nothing found means we drop the port as its probably not there */
1259 ata_link_for_each_dev(dev, &ap->link) {
1260 if (!ata_dev_absent(dev)) {
1261 legacy_host[probe->slot] = host;
1262 ld->platform_dev = pdev;
1267 platform_device_unregister(pdev);
1272 * legacy_check_special_cases - ATA special cases
1273 * @p: PCI device to check
1274 * @master: set this if we find an ATA master
1275 * @master: set this if we find an ATA secondary
1277 * A small number of vendors implemented early PCI ATA interfaces
1278 * on bridge logic without the ATA interface being PCI visible.
1279 * Where we have a matching PCI driver we must skip the relevant
1280 * device here. If we don't know about it then the legacy driver
1281 * is the right driver anyway.
1284 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1287 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1288 if (p->vendor == 0x1078 && p->device == 0x0000) {
1289 *primary = *secondary = 1;
1292 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1293 if (p->vendor == 0x1078 && p->device == 0x0002) {
1294 *primary = *secondary = 1;
1297 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1298 if (p->vendor == 0x8086 && p->device == 0x1234) {
1300 pci_read_config_word(p, 0x6C, &r);
1302 /* ATA port enabled */
1312 static __init void probe_opti_vlb(void)
1314 /* If an OPTI 82C46X is present find out where the channels are */
1315 static const char *optis[4] = {
1320 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1322 opti82c46x = 3; /* Assume master and slave first */
1323 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1326 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1327 ctrl = opti_syscfg(0xAC);
1328 /* Check enabled and this port is the 465MV port. On the
1329 MVB we may have two channels */
1332 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1333 legacy_probe_add(0x170, 15, OPTI46X, 0);
1336 legacy_probe_add(0x170, 15, OPTI46X, 0);
1338 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1340 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1343 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1345 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1346 /* Check card type */
1347 if ((r & 0xF0) == 0xC0) {
1348 /* QD6500: single channel */
1352 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1355 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1356 /* QD6580: dual channel */
1357 if (!request_region(port + 2 , 2, "pata_qdi")) {
1358 release_region(port, 2);
1361 res = inb(port + 3);
1362 /* Single channel mode ? */
1364 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1366 else { /* Dual channel mode */
1367 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1368 /* port + 0x02, r & 0x04 */
1369 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1371 release_region(port + 2, 2);
1375 static __init void probe_qdi_vlb(void)
1377 unsigned long flags;
1378 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1382 * Check each possible QD65xx base address
1385 for (i = 0; i < 2; i++) {
1386 unsigned long port = qd_port[i];
1390 if (request_region(port, 2, "pata_qdi")) {
1391 /* Check for a card */
1392 local_irq_save(flags);
1393 /* I have no h/w that needs this delay but it
1394 is present in the historic code */
1403 local_irq_restore(flags);
1407 release_region(port, 2);
1410 /* Passes the presence test */
1413 /* Check port agrees with port set */
1414 if ((r & 2) >> 1 == i)
1415 qdi65_identify_port(r, res, port);
1416 release_region(port, 2);
1422 * legacy_init - attach legacy interfaces
1424 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1425 * Right now we do not scan the ide0 and ide1 address but should do so
1426 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1427 * If you fix that note there are special cases to consider like VLB
1428 * drivers and CS5510/20.
1431 static __init int legacy_init(void)
1437 int pci_present = 0;
1438 struct legacy_probe *pl = &probe_list[0];
1441 struct pci_dev *p = NULL;
1443 for_each_pci_dev(p) {
1445 /* Check for any overlap of the system ATA mappings. Native
1446 mode controllers stuck on these addresses or some devices
1447 in 'raid' mode won't be found by the storage class test */
1448 for (r = 0; r < 6; r++) {
1449 if (pci_resource_start(p, r) == 0x1f0)
1451 if (pci_resource_start(p, r) == 0x170)
1454 /* Check for special cases */
1455 legacy_check_special_cases(p, &primary, &secondary);
1457 /* If PCI bus is present then don't probe for tertiary
1463 winbond = 0x130; /* Default port, alt is 1B0 */
1465 if (primary == 0 || all)
1466 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1467 if (secondary == 0 || all)
1468 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1470 if (probe_all || !pci_present) {
1471 /* ISA/VLB extra ports */
1472 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1473 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1474 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1475 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1483 for (i = 0; i < NR_HOST; i++, pl++) {
1486 if (pl->type == UNKNOWN)
1487 pl->type = probe_chip_type(pl);
1489 if (legacy_init_one(pl) == 0)
1497 static __exit void legacy_exit(void)
1501 for (i = 0; i < nr_legacy_host; i++) {
1502 struct legacy_data *ld = &legacy_data[i];
1503 ata_host_detach(legacy_host[i]);
1504 platform_device_unregister(ld->platform_dev);
1508 MODULE_AUTHOR("Alan Cox");
1509 MODULE_DESCRIPTION("low-level driver for legacy ATA");
1510 MODULE_LICENSE("GPL");
1511 MODULE_VERSION(DRV_VERSION);
1513 module_param(probe_all, int, 0);
1514 module_param(autospeed, int, 0);
1515 module_param(ht6560a, int, 0);
1516 module_param(ht6560b, int, 0);
1517 module_param(opti82c611a, int, 0);
1518 module_param(opti82c46x, int, 0);
1519 module_param(qdi, int, 0);
1520 module_param(pio_mask, int, 0);
1521 module_param(iordy_mask, int, 0);
1523 module_init(legacy_init);
1524 module_exit(legacy_exit);