1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/init.h>
4 #include <linux/blkdev.h>
5 #include <scsi/scsi_host.h>
7 #include <linux/libata.h>
10 #include <asm/ecard.h>
12 #define DRV_NAME "pata_icside"
14 #define ICS_IDENT_OFFSET 0x2280
16 #define ICS_ARCIN_V5_INTRSTAT 0x0000
17 #define ICS_ARCIN_V5_INTROFFSET 0x0004
19 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
20 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
21 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
22 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
25 unsigned int dataoffset;
26 unsigned int ctrloffset;
27 unsigned int stepping;
30 static const struct portinfo pata_icside_portinfo_v5 = {
36 static const struct portinfo pata_icside_portinfo_v6_1 = {
42 static const struct portinfo pata_icside_portinfo_v6_2 = {
48 #define PATA_ICSIDE_MAX_SG 128
50 struct pata_icside_state {
51 void __iomem *irq_port;
52 void __iomem *ioc_base;
58 unsigned int speed[ATA_MAX_DEVICES];
60 struct scatterlist sg[PATA_ICSIDE_MAX_SG];
63 struct pata_icside_info {
64 struct pata_icside_state *state;
65 struct expansion_card *ec;
67 void __iomem *irqaddr;
69 const expansioncard_ops_t *irqops;
70 unsigned int mwdma_mask;
71 unsigned int nr_ports;
72 const struct portinfo *port[2];
73 unsigned long raw_base;
74 unsigned long raw_ioc_base;
77 #define ICS_TYPE_A3IN 0
78 #define ICS_TYPE_A3USER 1
80 #define ICS_TYPE_V5 15
81 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
83 /* ---------------- Version 5 PCB Support Functions --------------------- */
84 /* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
85 * Purpose : enable interrupts from card
87 static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
89 struct pata_icside_state *state = ec->irq_data;
91 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
94 /* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
95 * Purpose : disable interrupts from card
97 static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
99 struct pata_icside_state *state = ec->irq_data;
101 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
104 static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
105 .irqenable = pata_icside_irqenable_arcin_v5,
106 .irqdisable = pata_icside_irqdisable_arcin_v5,
110 /* ---------------- Version 6 PCB Support Functions --------------------- */
111 /* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
112 * Purpose : enable interrupts from card
114 static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
116 struct pata_icside_state *state = ec->irq_data;
117 void __iomem *base = state->irq_port;
119 if (!state->port[0].disabled)
120 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
121 if (!state->port[1].disabled)
122 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
125 /* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
126 * Purpose : disable interrupts from card
128 static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
130 struct pata_icside_state *state = ec->irq_data;
132 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
133 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
136 /* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
137 * Purpose : detect an active interrupt from card
139 static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
141 struct pata_icside_state *state = ec->irq_data;
143 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
144 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
147 static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
148 .irqenable = pata_icside_irqenable_arcin_v6,
149 .irqdisable = pata_icside_irqdisable_arcin_v6,
150 .irqpending = pata_icside_irqpending_arcin_v6,
157 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
158 * There is only one DMA controller per card, which means that only
159 * one drive can be accessed at one time. NOTE! We do not enforce that
160 * here, but we rely on the main IDE driver spotting that both
161 * interfaces use the same IRQ, which should guarantee this.
165 * Configure the IOMD to give the appropriate timings for the transfer
166 * mode being requested. We take the advice of the ATA standards, and
167 * calculate the cycle time based on the transfer mode, and the EIDE
168 * MW DMA specs that the drive provides in the IDENTIFY command.
170 * We have the following IOMD DMA modes to choose from:
172 * Type Active Recovery Cycle
173 * A 250 (250) 312 (550) 562 (800)
174 * B 187 (200) 250 (550) 437 (750)
175 * C 125 (125) 125 (375) 250 (500)
176 * D 62 (50) 125 (375) 187 (425)
178 * (figures in brackets are actual measured timings on DIOR/DIOW)
180 * However, we also need to take care of the read/write active and
184 * Mode Active -- Recovery -- Cycle IOMD type
185 * MW0 215 50 215 480 A
189 static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
191 struct pata_icside_state *state = ap->host->private_data;
197 * DMA is based on a 16MHz clock
199 if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
203 * Choose the IOMD cycle timing which ensure that the interface
204 * satisfies the measured active, recovery and cycle times.
206 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
207 iomd_type = 'D', cycle = 187;
208 else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
209 iomd_type = 'C', cycle = 250;
210 else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
211 iomd_type = 'B', cycle = 437;
213 iomd_type = 'A', cycle = 562;
215 ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n",
216 t.active, t.recover, t.cycle, iomd_type);
218 state->port[ap->port_no].speed[adev->devno] = cycle;
221 static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
223 struct ata_port *ap = qc->ap;
224 struct pata_icside_state *state = ap->host->private_data;
225 struct scatterlist *sg, *rsg = state->sg;
226 unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
230 * We are simplex; BUG if we try to fiddle with DMA
233 BUG_ON(dma_channel_active(state->dma));
236 * Copy ATAs scattered sg list into a contiguous array of sg
238 for_each_sg(qc->sg, sg, qc->n_elem, si) {
239 memcpy(rsg, sg, sizeof(*sg));
244 * Route the DMA signals to the correct interface
246 writeb(state->port[ap->port_no].port_sel, state->ioc_base);
248 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
249 set_dma_sg(state->dma, state->sg, rsg - state->sg);
250 set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
252 /* issue r/w command */
253 ap->ops->exec_command(ap, &qc->tf);
256 static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
258 struct ata_port *ap = qc->ap;
259 struct pata_icside_state *state = ap->host->private_data;
261 BUG_ON(dma_channel_active(state->dma));
262 enable_dma(state->dma);
265 static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
267 struct ata_port *ap = qc->ap;
268 struct pata_icside_state *state = ap->host->private_data;
270 disable_dma(state->dma);
272 /* see ata_bmdma_stop */
276 static u8 pata_icside_bmdma_status(struct ata_port *ap)
278 struct pata_icside_state *state = ap->host->private_data;
279 void __iomem *irq_port;
281 irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
282 ICS_ARCIN_V6_INTRSTAT_1);
284 return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
287 static int icside_dma_init(struct pata_icside_info *info)
289 struct pata_icside_state *state = info->state;
290 struct expansion_card *ec = info->ec;
293 for (i = 0; i < ATA_MAX_DEVICES; i++) {
294 state->port[0].speed[i] = 480;
295 state->port[1].speed[i] = 480;
298 if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
299 state->dma = ec->dma;
300 info->mwdma_mask = 0x07; /* MW0..2 */
307 static struct scsi_host_template pata_icside_sht = {
308 .module = THIS_MODULE,
310 .ioctl = ata_scsi_ioctl,
311 .queuecommand = ata_scsi_queuecmd,
312 .can_queue = ATA_DEF_QUEUE,
313 .this_id = ATA_SHT_THIS_ID,
314 .sg_tablesize = PATA_ICSIDE_MAX_SG,
315 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
316 .emulated = ATA_SHT_EMULATED,
317 .use_clustering = ATA_SHT_USE_CLUSTERING,
318 .proc_name = DRV_NAME,
319 .dma_boundary = ~0, /* no dma boundaries */
320 .slave_configure = ata_scsi_slave_config,
321 .slave_destroy = ata_scsi_slave_destroy,
322 .bios_param = ata_std_bios_param,
325 static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
327 struct ata_port *ap = link->ap;
328 struct pata_icside_state *state = ap->host->private_data;
330 if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE)
331 return ata_std_postreset(link, classes);
333 state->port[ap->port_no].disabled = 1;
335 if (state->type == ICS_TYPE_V6) {
337 * Disable interrupts from this port, otherwise we
338 * receive spurious interrupts from the floating
341 void __iomem *irq_port = state->irq_port +
342 (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
347 static void pata_icside_error_handler(struct ata_port *ap)
349 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
350 pata_icside_postreset);
353 static struct ata_port_operations pata_icside_port_ops = {
354 .set_dmamode = pata_icside_set_dmamode,
356 .tf_load = ata_tf_load,
357 .tf_read = ata_tf_read,
358 .exec_command = ata_exec_command,
359 .check_status = ata_check_status,
360 .dev_select = ata_std_dev_select,
362 .cable_detect = ata_cable_40wire,
364 .bmdma_setup = pata_icside_bmdma_setup,
365 .bmdma_start = pata_icside_bmdma_start,
367 .data_xfer = ata_data_xfer_noirq,
369 /* no need to build any PRD tables for DMA */
370 .qc_prep = ata_noop_qc_prep,
371 .qc_issue = ata_qc_issue_prot,
373 .freeze = ata_bmdma_freeze,
374 .thaw = ata_bmdma_thaw,
375 .error_handler = pata_icside_error_handler,
376 .post_internal_cmd = pata_icside_bmdma_stop,
378 .irq_clear = ata_noop_irq_clear,
379 .irq_on = ata_irq_on,
381 .bmdma_stop = pata_icside_bmdma_stop,
382 .bmdma_status = pata_icside_bmdma_status,
385 static void __devinit
386 pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base,
387 struct pata_icside_info *info,
388 const struct portinfo *port)
390 struct ata_ioports *ioaddr = &ap->ioaddr;
391 void __iomem *cmd = base + port->dataoffset;
393 ioaddr->cmd_addr = cmd;
394 ioaddr->data_addr = cmd + (ATA_REG_DATA << port->stepping);
395 ioaddr->error_addr = cmd + (ATA_REG_ERR << port->stepping);
396 ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << port->stepping);
397 ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << port->stepping);
398 ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping);
399 ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << port->stepping);
400 ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << port->stepping);
401 ioaddr->device_addr = cmd + (ATA_REG_DEVICE << port->stepping);
402 ioaddr->status_addr = cmd + (ATA_REG_STATUS << port->stepping);
403 ioaddr->command_addr = cmd + (ATA_REG_CMD << port->stepping);
405 ioaddr->ctl_addr = base + port->ctrloffset;
406 ioaddr->altstatus_addr = ioaddr->ctl_addr;
408 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
409 info->raw_base + port->dataoffset,
410 info->raw_base + port->ctrloffset);
412 if (info->raw_ioc_base)
413 ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
416 static int __devinit pata_icside_register_v5(struct pata_icside_info *info)
418 struct pata_icside_state *state = info->state;
421 base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
425 state->irq_port = base;
428 info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
430 info->irqops = &pata_icside_ops_arcin_v5;
432 info->port[0] = &pata_icside_portinfo_v5;
434 info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);
439 static int __devinit pata_icside_register_v6(struct pata_icside_info *info)
441 struct pata_icside_state *state = info->state;
442 struct expansion_card *ec = info->ec;
443 void __iomem *ioc_base, *easi_base;
444 unsigned int sel = 0;
446 ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
450 easi_base = ioc_base;
452 if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
453 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
458 * Enable access to the EASI region.
463 writeb(sel, ioc_base);
465 state->irq_port = easi_base;
466 state->ioc_base = ioc_base;
467 state->port[0].port_sel = sel;
468 state->port[1].port_sel = sel | 1;
470 info->base = easi_base;
471 info->irqops = &pata_icside_ops_arcin_v6;
473 info->port[0] = &pata_icside_portinfo_v6_1;
474 info->port[1] = &pata_icside_portinfo_v6_2;
476 info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
477 info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);
479 return icside_dma_init(info);
482 static int __devinit pata_icside_add_ports(struct pata_icside_info *info)
484 struct expansion_card *ec = info->ec;
485 struct ata_host *host;
489 ec->irqaddr = info->irqaddr;
490 ec->irqmask = info->irqmask;
493 ecard_setirq(ec, info->irqops, info->state);
496 * Be on the safe side - disable interrupts
498 ec->ops->irqdisable(ec, ec->irq);
500 host = ata_host_alloc(&ec->dev, info->nr_ports);
504 host->private_data = info->state;
505 host->flags = ATA_HOST_SIMPLEX;
507 for (i = 0; i < info->nr_ports; i++) {
508 struct ata_port *ap = host->ports[i];
511 ap->mwdma_mask = info->mwdma_mask;
512 ap->flags |= ATA_FLAG_SLAVE_POSS;
513 ap->ops = &pata_icside_port_ops;
515 pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
518 return ata_host_activate(host, ec->irq, ata_interrupt, 0,
523 pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id)
525 struct pata_icside_state *state;
526 struct pata_icside_info info;
530 ret = ecard_request_resources(ec);
534 state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
540 state->type = ICS_TYPE_NOTYPE;
543 idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
547 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
548 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
549 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
550 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
551 ecardm_iounmap(ec, idmem);
556 memset(&info, 0, sizeof(info));
560 switch (state->type) {
562 dev_warn(&ec->dev, "A3IN unsupported\n");
566 case ICS_TYPE_A3USER:
567 dev_warn(&ec->dev, "A3USER unsupported\n");
572 ret = pata_icside_register_v5(&info);
576 ret = pata_icside_register_v6(&info);
580 dev_warn(&ec->dev, "unknown interface type\n");
586 ret = pata_icside_add_ports(&info);
592 ecard_release_resources(ec);
597 static void pata_icside_shutdown(struct expansion_card *ec)
599 struct ata_host *host = ecard_get_drvdata(ec);
603 * Disable interrupts from this card. We need to do
604 * this before disabling EASI since we may be accessing
605 * this register via that region.
607 local_irq_save(flags);
608 ec->ops->irqdisable(ec, ec->irq);
609 local_irq_restore(flags);
612 * Reset the ROM pointer so that we can read the ROM
613 * after a soft reboot. This also disables access to
614 * the IDE taskfile via the EASI region.
617 struct pata_icside_state *state = host->private_data;
619 writeb(0, state->ioc_base);
623 static void __devexit pata_icside_remove(struct expansion_card *ec)
625 struct ata_host *host = ecard_get_drvdata(ec);
626 struct pata_icside_state *state = host->private_data;
628 ata_host_detach(host);
630 pata_icside_shutdown(ec);
633 * don't NULL out the drvdata - devres/libata wants it
634 * to free the ata_host structure.
636 if (state->dma != NO_DMA)
637 free_dma(state->dma);
639 ecard_release_resources(ec);
642 static const struct ecard_id pata_icside_ids[] = {
643 { MANU_ICS, PROD_ICS_IDE },
644 { MANU_ICS2, PROD_ICS2_IDE },
648 static struct ecard_driver pata_icside_driver = {
649 .probe = pata_icside_probe,
650 .remove = __devexit_p(pata_icside_remove),
651 .shutdown = pata_icside_shutdown,
652 .id_table = pata_icside_ids,
658 static int __init pata_icside_init(void)
660 return ecard_register_driver(&pata_icside_driver);
663 static void __exit pata_icside_exit(void)
665 ecard_remove_driver(&pata_icside_driver);
668 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
669 MODULE_LICENSE("GPL");
670 MODULE_DESCRIPTION("ICS PATA driver");
672 module_init(pata_icside_init);
673 module_exit(pata_icside_exit);