2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
14 * Look into engine reset on timeout errors. Should not be required.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
26 #define DRV_NAME "pata_hpt37x"
27 #define DRV_VERSION "0.6.12"
37 struct hpt_clock const *clocks[4];
40 /* key for bus clock timings
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
63 static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
72 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
76 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
83 static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
92 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
96 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
103 static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
124 static const struct hpt_chip hpt370 = {
135 static const struct hpt_chip hpt370a = {
146 static const struct hpt_chip hpt372 = {
157 static const struct hpt_chip hpt302 = {
168 static const struct hpt_chip hpt371 = {
179 static const struct hpt_chip hpt372a = {
190 static const struct hpt_chip hpt374 = {
202 * hpt37x_find_mode - reset the hpt37x bus
204 * @speed: transfer mode
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
210 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
212 struct hpt_clock *clocks = ap->host->private_data;
214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
220 return 0xffffffffU; /* silence compiler warning */
223 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
241 static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
252 static const char *bad_ata100_5[] = {
272 * hpt370_filter - mode selection filter
275 * Block UDMA on devices that cause trouble with this controller.
278 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
280 if (adev->class == ATA_DEV_ATA) {
281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
284 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
286 return ata_bmdma_mode_filter(adev, mask);
290 * hpt370a_filter - mode selection filter
293 * Block UDMA on devices that cause trouble with this controller.
296 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
298 if (adev->class == ATA_DEV_ATA) {
299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
300 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
302 return ata_bmdma_mode_filter(adev, mask);
306 * hpt37x_cable_detect - Detect the cable type
307 * @ap: ATA port to detect on
309 * Return the cable type attached to this port
312 static int hpt37x_cable_detect(struct ata_port *ap)
314 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
317 pci_read_config_byte(pdev, 0x5B, &scr2);
318 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
319 /* Cable register now active */
320 pci_read_config_byte(pdev, 0x5A, &ata66);
322 pci_write_config_byte(pdev, 0x5B, scr2);
324 if (ata66 & (2 >> ap->port_no))
325 return ATA_CBL_PATA40;
327 return ATA_CBL_PATA80;
331 * hpt374_fn1_cable_detect - Detect the cable type
332 * @ap: ATA port to detect on
334 * Return the cable type attached to this port
337 static int hpt374_fn1_cable_detect(struct ata_port *ap)
339 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
340 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
344 /* Do the extra channel work */
345 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
346 /* Set bit 15 of 0x52 to enable TCBLID as input */
347 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
348 pci_read_config_byte(pdev, 0x5A, &ata66);
349 /* Reset TCBLID/FCBLID to output */
350 pci_write_config_word(pdev, mcrbase + 2, mcr3);
352 if (ata66 & (2 >> ap->port_no))
353 return ATA_CBL_PATA40;
355 return ATA_CBL_PATA80;
359 * hpt37x_pre_reset - reset the hpt37x bus
360 * @link: ATA link to reset
361 * @deadline: deadline jiffies for the operation
363 * Perform the initial reset handling for the 370/372 and 374 func 0
366 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
368 struct ata_port *ap = link->ap;
369 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
370 static const struct pci_bits hpt37x_enable_bits[] = {
371 { 0x50, 1, 0x04, 0x04 },
372 { 0x54, 1, 0x04, 0x04 }
374 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
377 /* Reset the state machine */
378 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
381 return ata_sff_prereset(link, deadline);
384 static int hpt374_fn1_pre_reset(struct ata_link *link, unsigned long deadline)
386 static const struct pci_bits hpt37x_enable_bits[] = {
387 { 0x50, 1, 0x04, 0x04 },
388 { 0x54, 1, 0x04, 0x04 }
390 struct ata_port *ap = link->ap;
391 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
393 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
396 /* Reset the state machine */
397 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
400 return ata_sff_prereset(link, deadline);
404 * hpt370_set_piomode - PIO setup
406 * @adev: device on the interface
408 * Perform PIO mode setup.
411 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
413 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
419 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
420 addr2 = 0x51 + 4 * ap->port_no;
422 /* Fast interrupt prediction disable, hold off interrupt disable */
423 pci_read_config_byte(pdev, addr2, &fast);
426 pci_write_config_byte(pdev, addr2, fast);
428 pci_read_config_dword(pdev, addr1, ®);
429 mode = hpt37x_find_mode(ap, adev->pio_mode);
430 mode &= ~0x8000000; /* No FIFO in PIO */
431 mode &= ~0x30070000; /* Leave config bits alone */
432 reg &= 0x30070000; /* Strip timing bits */
433 pci_write_config_dword(pdev, addr1, reg | mode);
437 * hpt370_set_dmamode - DMA timing setup
439 * @adev: Device being configured
441 * Set up the channel for MWDMA or UDMA modes. Much the same as with
442 * PIO, load the mode number and then set MWDMA or UDMA flag.
445 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
447 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
453 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
454 addr2 = 0x51 + 4 * ap->port_no;
456 /* Fast interrupt prediction disable, hold off interrupt disable */
457 pci_read_config_byte(pdev, addr2, &fast);
460 pci_write_config_byte(pdev, addr2, fast);
462 pci_read_config_dword(pdev, addr1, ®);
463 mode = hpt37x_find_mode(ap, adev->dma_mode);
464 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
465 mode &= ~0xC0000000; /* Leave config bits alone */
466 reg &= 0xC0000000; /* Strip timing bits */
467 pci_write_config_dword(pdev, addr1, reg | mode);
471 * hpt370_bmdma_end - DMA engine stop
474 * Work around the HPT370 DMA engine.
477 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
479 struct ata_port *ap = qc->ap;
480 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
481 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
483 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
485 if (dma_stat & 0x01) {
487 dma_stat = ioread8(bmdma + 2);
489 if (dma_stat & 0x01) {
490 /* Clear the engine */
491 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
494 dma_cmd = ioread8(bmdma );
495 iowrite8(dma_cmd & 0xFE, bmdma);
497 dma_stat = ioread8(bmdma + 2);
498 iowrite8(dma_stat | 0x06 , bmdma + 2);
499 /* Clear the engine */
500 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
507 * hpt372_set_piomode - PIO setup
509 * @adev: device on the interface
511 * Perform PIO mode setup.
514 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
516 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
522 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
523 addr2 = 0x51 + 4 * ap->port_no;
525 /* Fast interrupt prediction disable, hold off interrupt disable */
526 pci_read_config_byte(pdev, addr2, &fast);
528 pci_write_config_byte(pdev, addr2, fast);
530 pci_read_config_dword(pdev, addr1, ®);
531 mode = hpt37x_find_mode(ap, adev->pio_mode);
533 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
534 mode &= ~0x80000000; /* No FIFO in PIO */
535 mode &= ~0x30070000; /* Leave config bits alone */
536 reg &= 0x30070000; /* Strip timing bits */
537 pci_write_config_dword(pdev, addr1, reg | mode);
541 * hpt372_set_dmamode - DMA timing setup
543 * @adev: Device being configured
545 * Set up the channel for MWDMA or UDMA modes. Much the same as with
546 * PIO, load the mode number and then set MWDMA or UDMA flag.
549 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
551 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
557 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
558 addr2 = 0x51 + 4 * ap->port_no;
560 /* Fast interrupt prediction disable, hold off interrupt disable */
561 pci_read_config_byte(pdev, addr2, &fast);
563 pci_write_config_byte(pdev, addr2, fast);
565 pci_read_config_dword(pdev, addr1, ®);
566 mode = hpt37x_find_mode(ap, adev->dma_mode);
567 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
568 mode &= ~0xC0000000; /* Leave config bits alone */
569 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
570 reg &= 0xC0000000; /* Strip timing bits */
571 pci_write_config_dword(pdev, addr1, reg | mode);
575 * hpt37x_bmdma_end - DMA engine stop
578 * Clean up after the HPT372 and later DMA engine
581 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
583 struct ata_port *ap = qc->ap;
584 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
585 int mscreg = 0x50 + 4 * ap->port_no;
586 u8 bwsr_stat, msc_stat;
588 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
589 pci_read_config_byte(pdev, mscreg, &msc_stat);
590 if (bwsr_stat & (1 << ap->port_no))
591 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
596 static struct scsi_host_template hpt37x_sht = {
597 ATA_BMDMA_SHT(DRV_NAME),
601 * Configuration for HPT370
604 static struct ata_port_operations hpt370_port_ops = {
605 .inherits = &ata_bmdma_port_ops,
607 .bmdma_stop = hpt370_bmdma_stop,
609 .mode_filter = hpt370_filter,
610 .cable_detect = hpt37x_cable_detect,
611 .set_piomode = hpt370_set_piomode,
612 .set_dmamode = hpt370_set_dmamode,
613 .prereset = hpt37x_pre_reset,
617 * Configuration for HPT370A. Close to 370 but less filters
620 static struct ata_port_operations hpt370a_port_ops = {
621 .inherits = &hpt370_port_ops,
622 .mode_filter = hpt370a_filter,
626 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
627 * and DMA mode setting functionality.
630 static struct ata_port_operations hpt372_port_ops = {
631 .inherits = &ata_bmdma_port_ops,
633 .bmdma_stop = hpt37x_bmdma_stop,
635 .cable_detect = hpt37x_cable_detect,
636 .set_piomode = hpt372_set_piomode,
637 .set_dmamode = hpt372_set_dmamode,
638 .prereset = hpt37x_pre_reset,
642 * Configuration for HPT374. Mode setting works like 372 and friends
643 * but we have a different cable detection procedure for function 1.
646 static struct ata_port_operations hpt374_fn1_port_ops = {
647 .inherits = &hpt372_port_ops,
648 .cable_detect = hpt374_fn1_cable_detect,
649 .prereset = hpt374_fn1_pre_reset,
653 * hpt37x_clock_slot - Turn timing to PC clock entry
654 * @freq: Reported frequency timing
657 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
661 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
663 unsigned int f = (base * freq) / 192; /* Mhz */
665 return 0; /* 33Mhz slot */
667 return 1; /* 40Mhz slot */
669 return 2; /* 50Mhz slot */
670 return 3; /* 60Mhz slot */
674 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
677 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
681 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
687 for(tries = 0; tries < 0x5000; tries++) {
689 pci_read_config_byte(dev, 0x5b, ®5b);
691 /* See if it stays set */
692 for(tries = 0; tries < 0x1000; tries ++) {
693 pci_read_config_byte(dev, 0x5b, ®5b);
695 if ((reg5b & 0x80) == 0)
698 /* Turn off tuning, we have the DPLL set */
699 pci_read_config_dword(dev, 0x5c, ®5c);
700 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
704 /* Never went stable */
708 static u32 hpt374_read_freq(struct pci_dev *pdev)
711 unsigned long io_base = pci_resource_start(pdev, 4);
712 if (PCI_FUNC(pdev->devfn) & 1) {
713 struct pci_dev *pdev_0;
715 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
716 /* Someone hot plugged the controller on us ? */
719 io_base = pci_resource_start(pdev_0, 4);
720 freq = inl(io_base + 0x90);
723 freq = inl(io_base + 0x90);
728 * hpt37x_init_one - Initialise an HPT37X/302
730 * @id: Entry in match table
732 * Initialise an HPT37x device. There are some interesting complications
733 * here. Firstly the chip may report 366 and be one of several variants.
734 * Secondly all the timings depend on the clock for the chip which we must
737 * This is the known chip mappings. It may be missing a couple of later
740 * Chip version PCI Rev Notes
741 * HPT366 4 (HPT366) 0 Other driver
742 * HPT366 4 (HPT366) 1 Other driver
743 * HPT368 4 (HPT366) 2 Other driver
744 * HPT370 4 (HPT366) 3 UDMA100
745 * HPT370A 4 (HPT366) 4 UDMA100
746 * HPT372 4 (HPT366) 5 UDMA133 (1)
747 * HPT372N 4 (HPT366) 6 Other driver
748 * HPT372A 5 (HPT372) 1 UDMA133 (1)
749 * HPT372N 5 (HPT372) 2 Other driver
750 * HPT302 6 (HPT302) 1 UDMA133
751 * HPT302N 6 (HPT302) 2 Other driver
752 * HPT371 7 (HPT371) * UDMA133
753 * HPT374 8 (HPT374) * UDMA133 4 channel
754 * HPT372N 9 (HPT372N) * Other driver
756 * (1) UDMA133 support depends on the bus clock
759 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
761 /* HPT370 - UDMA100 */
762 static const struct ata_port_info info_hpt370 = {
763 .flags = ATA_FLAG_SLAVE_POSS,
764 .pio_mask = ATA_PIO4,
765 .mwdma_mask = ATA_MWDMA2,
766 .udma_mask = ATA_UDMA5,
767 .port_ops = &hpt370_port_ops
769 /* HPT370A - UDMA100 */
770 static const struct ata_port_info info_hpt370a = {
771 .flags = ATA_FLAG_SLAVE_POSS,
772 .pio_mask = ATA_PIO4,
773 .mwdma_mask = ATA_MWDMA2,
774 .udma_mask = ATA_UDMA5,
775 .port_ops = &hpt370a_port_ops
777 /* HPT370 - UDMA100 */
778 static const struct ata_port_info info_hpt370_33 = {
779 .flags = ATA_FLAG_SLAVE_POSS,
780 .pio_mask = ATA_PIO4,
781 .mwdma_mask = ATA_MWDMA2,
782 .udma_mask = ATA_UDMA5,
783 .port_ops = &hpt370_port_ops
785 /* HPT370A - UDMA100 */
786 static const struct ata_port_info info_hpt370a_33 = {
787 .flags = ATA_FLAG_SLAVE_POSS,
788 .pio_mask = ATA_PIO4,
789 .mwdma_mask = ATA_MWDMA2,
790 .udma_mask = ATA_UDMA5,
791 .port_ops = &hpt370a_port_ops
793 /* HPT371, 372 and friends - UDMA133 */
794 static const struct ata_port_info info_hpt372 = {
795 .flags = ATA_FLAG_SLAVE_POSS,
796 .pio_mask = ATA_PIO4,
797 .mwdma_mask = ATA_MWDMA2,
798 .udma_mask = ATA_UDMA6,
799 .port_ops = &hpt372_port_ops
801 /* HPT374 - UDMA100, function 1 uses different prereset method */
802 static const struct ata_port_info info_hpt374_fn0 = {
803 .flags = ATA_FLAG_SLAVE_POSS,
804 .pio_mask = ATA_PIO4,
805 .mwdma_mask = ATA_MWDMA2,
806 .udma_mask = ATA_UDMA5,
807 .port_ops = &hpt372_port_ops
809 static const struct ata_port_info info_hpt374_fn1 = {
810 .flags = ATA_FLAG_SLAVE_POSS,
811 .pio_mask = ATA_PIO4,
812 .mwdma_mask = ATA_MWDMA2,
813 .udma_mask = ATA_UDMA5,
814 .port_ops = &hpt374_fn1_port_ops
817 static const int MHz[4] = { 33, 40, 50, 66 };
818 void *private_data = NULL;
819 const struct ata_port_info *ppi[] = { NULL, NULL };
827 unsigned long iobase = pci_resource_start(dev, 4);
829 const struct hpt_chip *chip_table;
833 rc = pcim_enable_device(dev);
837 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
840 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
841 /* May be a later chip in disguise. Check */
842 /* Older chips are in the HPT366 driver. Ignore them */
845 /* N series chips have their own driver. Ignore */
851 ppi[0] = &info_hpt370;
852 chip_table = &hpt370;
856 ppi[0] = &info_hpt370a;
857 chip_table = &hpt370a;
861 ppi[0] = &info_hpt372;
862 chip_table = &hpt372;
865 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
869 switch(dev->device) {
870 case PCI_DEVICE_ID_TTI_HPT372:
871 /* 372N if rev >= 2*/
874 ppi[0] = &info_hpt372;
875 chip_table = &hpt372a;
877 case PCI_DEVICE_ID_TTI_HPT302:
878 /* 302N if rev > 1 */
881 ppi[0] = &info_hpt372;
883 chip_table = &hpt302;
885 case PCI_DEVICE_ID_TTI_HPT371:
888 ppi[0] = &info_hpt372;
889 chip_table = &hpt371;
890 /* Single channel device, master is not present
891 but the BIOS (or us for non x86) must mark it
893 pci_read_config_byte(dev, 0x50, &mcr1);
895 pci_write_config_byte(dev, 0x50, mcr1);
897 case PCI_DEVICE_ID_TTI_HPT374:
898 chip_table = &hpt374;
899 if (!(PCI_FUNC(dev->devfn) & 1))
900 *ppi = &info_hpt374_fn0;
902 *ppi = &info_hpt374_fn1;
905 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
909 /* Ok so this is a chip we support */
911 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
912 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
913 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
914 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
916 pci_read_config_byte(dev, 0x5A, &irqmask);
918 pci_write_config_byte(dev, 0x5a, irqmask);
921 * default to pci clock. make sure MA15/16 are set to output
922 * to prevent drives having problems with 40-pin cables. Needed
923 * for some drives such as IBM-DTLA which will not enter ready
924 * state on reset when PDIAG is a input.
927 pci_write_config_byte(dev, 0x5b, 0x23);
930 * HighPoint does this for HPT372A.
931 * NOTE: This register is only writeable via I/O space.
933 if (chip_table == &hpt372a)
934 outb(0x0e, iobase + 0x9c);
936 /* Some devices do not let this value be accessed via PCI space
937 according to the old driver. In addition we must use the value
938 from FN 0 on the HPT374 */
940 if (chip_table == &hpt374) {
941 freq = hpt374_read_freq(dev);
945 freq = inl(iobase + 0x90);
947 if ((freq >> 12) != 0xABCDE) {
952 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
954 /* This is the process the HPT371 BIOS is reported to use */
955 for(i = 0; i < 128; i++) {
956 pci_read_config_byte(dev, 0x78, &sr);
965 * Turn the frequency check into a band and then find a timing
969 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
970 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
972 * We need to try PLL mode instead
974 * For non UDMA133 capable devices we should
975 * use a 50MHz DPLL by choice
977 unsigned int f_low, f_high;
981 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
983 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
988 /* Select the DPLL clock. */
989 pci_write_config_byte(dev, 0x5b, 0x21);
990 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
992 for(adjust = 0; adjust < 8; adjust++) {
993 if (hpt37x_calibrate_dpll(dev))
995 /* See if it'll settle at a fractionally different clock */
997 f_low -= adjust >> 1;
999 f_high += adjust >> 1;
1000 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
1003 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
1007 private_data = (void *)hpt37x_timings_66;
1009 private_data = (void *)hpt37x_timings_50;
1011 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
1012 MHz[clock_slot], MHz[dpll]);
1014 private_data = (void *)chip_table->clocks[clock_slot];
1016 * Perform a final fixup. Note that we will have used the
1017 * DPLL on the HPT372 which means we don't have to worry
1018 * about lack of UDMA133 support on lower clocks
1021 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1022 ppi[0] = &info_hpt370_33;
1023 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1024 ppi[0] = &info_hpt370a_33;
1025 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
1026 chip_table->name, MHz[clock_slot]);
1029 /* Now kick off ATA set up */
1030 return ata_pci_sff_init_one(dev, ppi, &hpt37x_sht, private_data);
1033 static const struct pci_device_id hpt37x[] = {
1034 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1035 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1036 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1037 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1038 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1043 static struct pci_driver hpt37x_pci_driver = {
1046 .probe = hpt37x_init_one,
1047 .remove = ata_pci_remove_one
1050 static int __init hpt37x_init(void)
1052 return pci_register_driver(&hpt37x_pci_driver);
1055 static void __exit hpt37x_exit(void)
1057 pci_unregister_driver(&hpt37x_pci_driver);
1060 MODULE_AUTHOR("Alan Cox");
1061 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1062 MODULE_LICENSE("GPL");
1063 MODULE_DEVICE_TABLE(pci, hpt37x);
1064 MODULE_VERSION(DRV_VERSION);
1066 module_init(hpt37x_init);
1067 module_exit(hpt37x_exit);