2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
15 * Look into engine reset on timeout errors. Should not be
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/blkdev.h>
25 #include <linux/delay.h>
26 #include <scsi/scsi_host.h>
27 #include <linux/libata.h>
29 #define DRV_NAME "pata_hpt366"
30 #define DRV_VERSION "0.6.2"
37 /* key for bus clock timings
39 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 * DMA. cycles = value + 1
41 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 * DMA. cycles = value + 1
43 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
45 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
47 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 * during task file register access.
49 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
51 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
55 * 30 PIO_MST enable. if set, the chip is in bus master mode during
60 static const struct hpt_clock hpt366_40[] = {
61 { XFER_UDMA_4, 0x900fd943 },
62 { XFER_UDMA_3, 0x900ad943 },
63 { XFER_UDMA_2, 0x900bd943 },
64 { XFER_UDMA_1, 0x9008d943 },
65 { XFER_UDMA_0, 0x9008d943 },
67 { XFER_MW_DMA_2, 0xa008d943 },
68 { XFER_MW_DMA_1, 0xa010d955 },
69 { XFER_MW_DMA_0, 0xa010d9fc },
71 { XFER_PIO_4, 0xc008d963 },
72 { XFER_PIO_3, 0xc010d974 },
73 { XFER_PIO_2, 0xc010d997 },
74 { XFER_PIO_1, 0xc010d9c7 },
75 { XFER_PIO_0, 0xc018d9d9 },
79 static const struct hpt_clock hpt366_33[] = {
80 { XFER_UDMA_4, 0x90c9a731 },
81 { XFER_UDMA_3, 0x90cfa731 },
82 { XFER_UDMA_2, 0x90caa731 },
83 { XFER_UDMA_1, 0x90cba731 },
84 { XFER_UDMA_0, 0x90c8a731 },
86 { XFER_MW_DMA_2, 0xa0c8a731 },
87 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
88 { XFER_MW_DMA_0, 0xa0c8a797 },
90 { XFER_PIO_4, 0xc0c8a731 },
91 { XFER_PIO_3, 0xc0c8a742 },
92 { XFER_PIO_2, 0xc0d0a753 },
93 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
94 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
98 static const struct hpt_clock hpt366_25[] = {
99 { XFER_UDMA_4, 0x90c98521 },
100 { XFER_UDMA_3, 0x90cf8521 },
101 { XFER_UDMA_2, 0x90cf8521 },
102 { XFER_UDMA_1, 0x90cb8521 },
103 { XFER_UDMA_0, 0x90cb8521 },
105 { XFER_MW_DMA_2, 0xa0ca8521 },
106 { XFER_MW_DMA_1, 0xa0ca8532 },
107 { XFER_MW_DMA_0, 0xa0ca8575 },
109 { XFER_PIO_4, 0xc0ca8521 },
110 { XFER_PIO_3, 0xc0ca8532 },
111 { XFER_PIO_2, 0xc0ca8542 },
112 { XFER_PIO_1, 0xc0d08572 },
113 { XFER_PIO_0, 0xc0d08585 },
117 static const char *bad_ata33[] = {
118 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
122 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
128 static const char *bad_ata66_4[] = {
147 static const char *bad_ata66_3[] = {
152 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
154 unsigned char model_num[ATA_ID_PROD_LEN + 1];
157 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
159 while (list[i] != NULL) {
160 if (!strcmp(list[i], model_num)) {
161 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
171 * hpt366_filter - mode selection filter
174 * Block UDMA on devices that cause trouble with this controller.
177 static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
179 if (adev->class == ATA_DEV_ATA) {
180 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
181 mask &= ~ATA_MASK_UDMA;
182 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
183 mask &= ~(0xF8 << ATA_SHIFT_UDMA);
184 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
185 mask &= ~(0xF0 << ATA_SHIFT_UDMA);
187 return ata_bmdma_mode_filter(adev, mask);
191 * hpt36x_find_mode - reset the hpt36x bus
193 * @speed: transfer mode
195 * Return the 32bit register programming information for this channel
196 * that matches the speed provided.
199 static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
201 struct hpt_clock *clocks = ap->host->private_data;
203 while(clocks->xfer_speed) {
204 if (clocks->xfer_speed == speed)
205 return clocks->timing;
209 return 0xffffffffU; /* silence compiler warning */
212 static int hpt36x_cable_detect(struct ata_port *ap)
214 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
218 * Each channel of pata_hpt366 occupies separate PCI function
219 * as the primary channel and bit1 indicates the cable type.
221 pci_read_config_byte(pdev, 0x5A, &ata66);
223 return ATA_CBL_PATA40;
224 return ATA_CBL_PATA80;
228 * hpt366_set_piomode - PIO setup
230 * @adev: device on the interface
232 * Perform PIO mode setup.
235 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
237 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
243 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
244 addr2 = 0x51 + 4 * ap->port_no;
246 /* Fast interrupt prediction disable, hold off interrupt disable */
247 pci_read_config_byte(pdev, addr2, &fast);
250 pci_write_config_byte(pdev, addr2, fast);
253 pci_read_config_dword(pdev, addr1, ®);
254 mode = hpt36x_find_mode(ap, adev->pio_mode);
255 mode &= ~0x8000000; /* No FIFO in PIO */
256 mode &= ~0x30070000; /* Leave config bits alone */
257 reg &= 0x30070000; /* Strip timing bits */
258 pci_write_config_dword(pdev, addr1, reg | mode);
262 * hpt366_set_dmamode - DMA timing setup
264 * @adev: Device being configured
266 * Set up the channel for MWDMA or UDMA modes. Much the same as with
267 * PIO, load the mode number and then set MWDMA or UDMA flag.
270 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
272 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
278 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
279 addr2 = 0x51 + 4 * ap->port_no;
281 /* Fast interrupt prediction disable, hold off interrupt disable */
282 pci_read_config_byte(pdev, addr2, &fast);
285 pci_write_config_byte(pdev, addr2, fast);
288 pci_read_config_dword(pdev, addr1, ®);
289 mode = hpt36x_find_mode(ap, adev->dma_mode);
290 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
291 mode &= ~0xC0000000; /* Leave config bits alone */
292 reg &= 0xC0000000; /* Strip timing bits */
293 pci_write_config_dword(pdev, addr1, reg | mode);
296 static struct scsi_host_template hpt36x_sht = {
297 ATA_BMDMA_SHT(DRV_NAME),
301 * Configuration for HPT366/68
304 static struct ata_port_operations hpt366_port_ops = {
305 .inherits = &ata_bmdma_port_ops,
306 .cable_detect = hpt36x_cable_detect,
307 .mode_filter = hpt366_filter,
308 .set_piomode = hpt366_set_piomode,
309 .set_dmamode = hpt366_set_dmamode,
313 * hpt36x_init_chipset - common chip setup
316 * Perform the chip setup work that must be done at both init and
320 static void hpt36x_init_chipset(struct pci_dev *dev)
323 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
324 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
325 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
326 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
328 pci_read_config_byte(dev, 0x51, &drive_fast);
329 if (drive_fast & 0x80)
330 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
334 * hpt36x_init_one - Initialise an HPT366/368
336 * @id: Entry in match table
338 * Initialise an HPT36x device. There are some interesting complications
339 * here. Firstly the chip may report 366 and be one of several variants.
340 * Secondly all the timings depend on the clock for the chip which we must
343 * This is the known chip mappings. It may be missing a couple of later
346 * Chip version PCI Rev Notes
347 * HPT366 4 (HPT366) 0 UDMA66
348 * HPT366 4 (HPT366) 1 UDMA66
349 * HPT368 4 (HPT366) 2 UDMA66
350 * HPT37x/30x 4 (HPT366) 3+ Other driver
354 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
356 static const struct ata_port_info info_hpt366 = {
357 .flags = ATA_FLAG_SLAVE_POSS,
360 .udma_mask = ATA_UDMA4,
361 .port_ops = &hpt366_port_ops
363 const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
370 rc = pcim_enable_device(dev);
374 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
377 /* May be a later chip in disguise. Check */
378 /* Newer chips are not in the HPT36x driver. Ignore them */
382 hpt36x_init_chipset(dev);
384 pci_read_config_dword(dev, 0x40, ®1);
386 /* PCI clocking determines the ATA timing values to use */
387 /* info_hpt366 is safe against re-entry so we can scribble on it */
388 switch((reg1 & 0x700) >> 8) {
399 /* Now kick off ATA set up */
400 return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
404 static int hpt36x_reinit_one(struct pci_dev *dev)
406 struct ata_host *host = dev_get_drvdata(&dev->dev);
409 rc = ata_pci_device_do_resume(dev);
412 hpt36x_init_chipset(dev);
413 ata_host_resume(host);
418 static const struct pci_device_id hpt36x[] = {
419 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
423 static struct pci_driver hpt36x_pci_driver = {
426 .probe = hpt36x_init_one,
427 .remove = ata_pci_remove_one,
429 .suspend = ata_pci_device_suspend,
430 .resume = hpt36x_reinit_one,
434 static int __init hpt36x_init(void)
436 return pci_register_driver(&hpt36x_pci_driver);
439 static void __exit hpt36x_exit(void)
441 pci_unregister_driver(&hpt36x_pci_driver);
444 MODULE_AUTHOR("Alan Cox");
445 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
446 MODULE_LICENSE("GPL");
447 MODULE_DEVICE_TABLE(pci, hpt36x);
448 MODULE_VERSION(DRV_VERSION);
450 module_init(hpt36x_init);
451 module_exit(hpt36x_exit);