2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
11 * Variable system clock when/if it makes sense
12 * Power management on ports
15 * Documentation publically available.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
27 #define DRV_NAME "pata_amd"
28 #define DRV_VERSION "0.3.9"
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
44 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
55 const int amd_clock = 33333; /* KHz. */
58 T = 1000000000 / amd_clock;
59 UT = T / min_t(int, max_t(int, clock, 1), 2);
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
67 /* This may be over conservative */
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
80 * Now do the setup work
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
122 * amd_pre_reset - perform reset handling
124 * @deadline: deadline jiffies for the operation
126 * Reset sequence checking enable bits to see which ports are
130 static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
132 static const struct pci_bits amd_enable_bits[] = {
133 { 0x40, 1, 0x02, 0x02 },
134 { 0x40, 1, 0x01, 0x01 }
137 struct ata_port *ap = link->ap;
138 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
140 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
143 return ata_std_prereset(link, deadline);
146 static void amd_error_handler(struct ata_port *ap)
148 return ata_bmdma_drive_eh(ap, amd_pre_reset,
149 ata_std_softreset, NULL,
153 static int amd_cable_detect(struct ata_port *ap)
155 static const u32 bitmask[2] = {0x03, 0x0C};
156 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
159 pci_read_config_byte(pdev, 0x42, &ata66);
160 if (ata66 & bitmask[ap->port_no])
161 return ATA_CBL_PATA80;
162 return ATA_CBL_PATA40;
166 * amd33_set_piomode - set initial PIO mode data
170 * Program the AMD registers for PIO mode.
173 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
175 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
178 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
180 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
183 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
185 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
188 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
190 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
194 * amd33_set_dmamode - set initial DMA mode data
198 * Program the MWDMA/UDMA modes for the AMD and Nvidia
202 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
204 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
207 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
209 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
212 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
214 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
217 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
219 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
224 * nv_probe_init - cable detection
227 * Perform cable detection. The BIOS stores this in PCI config
231 static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
233 static const struct pci_bits nv_enable_bits[] = {
234 { 0x50, 1, 0x02, 0x02 },
235 { 0x50, 1, 0x01, 0x01 }
238 struct ata_port *ap = link->ap;
239 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
241 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
244 return ata_std_prereset(link, deadline);
247 static void nv_error_handler(struct ata_port *ap)
249 ata_bmdma_drive_eh(ap, nv_pre_reset,
250 ata_std_softreset, NULL,
254 static int nv_cable_detect(struct ata_port *ap)
256 static const u8 bitmask[2] = {0x03, 0x0C};
257 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
262 pci_read_config_byte(pdev, 0x52, &ata66);
263 if (ata66 & bitmask[ap->port_no])
264 cbl = ATA_CBL_PATA80;
266 cbl = ATA_CBL_PATA40;
268 /* We now have to double check because the Nvidia boxes BIOS
269 doesn't always set the cable bits but does set mode bits */
270 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
271 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
272 cbl = ATA_CBL_PATA80;
277 * nv100_set_piomode - set initial PIO mode data
281 * Program the AMD registers for PIO mode.
284 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
286 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
289 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
291 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
295 * nv100_set_dmamode - set initial DMA mode data
299 * Program the MWDMA/UDMA modes for the AMD and Nvidia
303 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
305 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
308 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
310 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
313 static struct scsi_host_template amd_sht = {
314 .module = THIS_MODULE,
316 .ioctl = ata_scsi_ioctl,
317 .queuecommand = ata_scsi_queuecmd,
318 .can_queue = ATA_DEF_QUEUE,
319 .this_id = ATA_SHT_THIS_ID,
320 .sg_tablesize = LIBATA_MAX_PRD,
321 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
322 .emulated = ATA_SHT_EMULATED,
323 .use_clustering = ATA_SHT_USE_CLUSTERING,
324 .proc_name = DRV_NAME,
325 .dma_boundary = ATA_DMA_BOUNDARY,
326 .slave_configure = ata_scsi_slave_config,
327 .slave_destroy = ata_scsi_slave_destroy,
328 .bios_param = ata_std_bios_param,
331 static struct ata_port_operations amd33_port_ops = {
332 .port_disable = ata_port_disable,
333 .set_piomode = amd33_set_piomode,
334 .set_dmamode = amd33_set_dmamode,
335 .mode_filter = ata_pci_default_filter,
336 .tf_load = ata_tf_load,
337 .tf_read = ata_tf_read,
338 .check_status = ata_check_status,
339 .exec_command = ata_exec_command,
340 .dev_select = ata_std_dev_select,
342 .freeze = ata_bmdma_freeze,
343 .thaw = ata_bmdma_thaw,
344 .error_handler = amd_error_handler,
345 .post_internal_cmd = ata_bmdma_post_internal_cmd,
346 .cable_detect = ata_cable_40wire,
348 .bmdma_setup = ata_bmdma_setup,
349 .bmdma_start = ata_bmdma_start,
350 .bmdma_stop = ata_bmdma_stop,
351 .bmdma_status = ata_bmdma_status,
353 .qc_prep = ata_qc_prep,
354 .qc_issue = ata_qc_issue_prot,
356 .data_xfer = ata_data_xfer,
358 .irq_handler = ata_interrupt,
359 .irq_clear = ata_bmdma_irq_clear,
360 .irq_on = ata_irq_on,
361 .irq_ack = ata_irq_ack,
363 .port_start = ata_port_start,
366 static struct ata_port_operations amd66_port_ops = {
367 .port_disable = ata_port_disable,
368 .set_piomode = amd66_set_piomode,
369 .set_dmamode = amd66_set_dmamode,
370 .mode_filter = ata_pci_default_filter,
371 .tf_load = ata_tf_load,
372 .tf_read = ata_tf_read,
373 .check_status = ata_check_status,
374 .exec_command = ata_exec_command,
375 .dev_select = ata_std_dev_select,
377 .freeze = ata_bmdma_freeze,
378 .thaw = ata_bmdma_thaw,
379 .error_handler = amd_error_handler,
380 .post_internal_cmd = ata_bmdma_post_internal_cmd,
381 .cable_detect = ata_cable_unknown,
383 .bmdma_setup = ata_bmdma_setup,
384 .bmdma_start = ata_bmdma_start,
385 .bmdma_stop = ata_bmdma_stop,
386 .bmdma_status = ata_bmdma_status,
388 .qc_prep = ata_qc_prep,
389 .qc_issue = ata_qc_issue_prot,
391 .data_xfer = ata_data_xfer,
393 .irq_handler = ata_interrupt,
394 .irq_clear = ata_bmdma_irq_clear,
395 .irq_on = ata_irq_on,
396 .irq_ack = ata_irq_ack,
398 .port_start = ata_port_start,
401 static struct ata_port_operations amd100_port_ops = {
402 .port_disable = ata_port_disable,
403 .set_piomode = amd100_set_piomode,
404 .set_dmamode = amd100_set_dmamode,
405 .mode_filter = ata_pci_default_filter,
406 .tf_load = ata_tf_load,
407 .tf_read = ata_tf_read,
408 .check_status = ata_check_status,
409 .exec_command = ata_exec_command,
410 .dev_select = ata_std_dev_select,
412 .freeze = ata_bmdma_freeze,
413 .thaw = ata_bmdma_thaw,
414 .error_handler = amd_error_handler,
415 .post_internal_cmd = ata_bmdma_post_internal_cmd,
416 .cable_detect = ata_cable_unknown,
418 .bmdma_setup = ata_bmdma_setup,
419 .bmdma_start = ata_bmdma_start,
420 .bmdma_stop = ata_bmdma_stop,
421 .bmdma_status = ata_bmdma_status,
423 .qc_prep = ata_qc_prep,
424 .qc_issue = ata_qc_issue_prot,
426 .data_xfer = ata_data_xfer,
428 .irq_handler = ata_interrupt,
429 .irq_clear = ata_bmdma_irq_clear,
430 .irq_on = ata_irq_on,
431 .irq_ack = ata_irq_ack,
433 .port_start = ata_port_start,
436 static struct ata_port_operations amd133_port_ops = {
437 .port_disable = ata_port_disable,
438 .set_piomode = amd133_set_piomode,
439 .set_dmamode = amd133_set_dmamode,
440 .mode_filter = ata_pci_default_filter,
441 .tf_load = ata_tf_load,
442 .tf_read = ata_tf_read,
443 .check_status = ata_check_status,
444 .exec_command = ata_exec_command,
445 .dev_select = ata_std_dev_select,
447 .freeze = ata_bmdma_freeze,
448 .thaw = ata_bmdma_thaw,
449 .error_handler = amd_error_handler,
450 .post_internal_cmd = ata_bmdma_post_internal_cmd,
451 .cable_detect = amd_cable_detect,
453 .bmdma_setup = ata_bmdma_setup,
454 .bmdma_start = ata_bmdma_start,
455 .bmdma_stop = ata_bmdma_stop,
456 .bmdma_status = ata_bmdma_status,
458 .qc_prep = ata_qc_prep,
459 .qc_issue = ata_qc_issue_prot,
461 .data_xfer = ata_data_xfer,
463 .irq_handler = ata_interrupt,
464 .irq_clear = ata_bmdma_irq_clear,
465 .irq_on = ata_irq_on,
466 .irq_ack = ata_irq_ack,
468 .port_start = ata_port_start,
471 static struct ata_port_operations nv100_port_ops = {
472 .port_disable = ata_port_disable,
473 .set_piomode = nv100_set_piomode,
474 .set_dmamode = nv100_set_dmamode,
475 .mode_filter = ata_pci_default_filter,
476 .tf_load = ata_tf_load,
477 .tf_read = ata_tf_read,
478 .check_status = ata_check_status,
479 .exec_command = ata_exec_command,
480 .dev_select = ata_std_dev_select,
482 .freeze = ata_bmdma_freeze,
483 .thaw = ata_bmdma_thaw,
484 .error_handler = nv_error_handler,
485 .post_internal_cmd = ata_bmdma_post_internal_cmd,
486 .cable_detect = nv_cable_detect,
488 .bmdma_setup = ata_bmdma_setup,
489 .bmdma_start = ata_bmdma_start,
490 .bmdma_stop = ata_bmdma_stop,
491 .bmdma_status = ata_bmdma_status,
493 .qc_prep = ata_qc_prep,
494 .qc_issue = ata_qc_issue_prot,
496 .data_xfer = ata_data_xfer,
498 .irq_handler = ata_interrupt,
499 .irq_clear = ata_bmdma_irq_clear,
500 .irq_on = ata_irq_on,
501 .irq_ack = ata_irq_ack,
503 .port_start = ata_port_start,
506 static struct ata_port_operations nv133_port_ops = {
507 .port_disable = ata_port_disable,
508 .set_piomode = nv133_set_piomode,
509 .set_dmamode = nv133_set_dmamode,
510 .mode_filter = ata_pci_default_filter,
511 .tf_load = ata_tf_load,
512 .tf_read = ata_tf_read,
513 .check_status = ata_check_status,
514 .exec_command = ata_exec_command,
515 .dev_select = ata_std_dev_select,
517 .freeze = ata_bmdma_freeze,
518 .thaw = ata_bmdma_thaw,
519 .error_handler = nv_error_handler,
520 .post_internal_cmd = ata_bmdma_post_internal_cmd,
521 .cable_detect = nv_cable_detect,
523 .bmdma_setup = ata_bmdma_setup,
524 .bmdma_start = ata_bmdma_start,
525 .bmdma_stop = ata_bmdma_stop,
526 .bmdma_status = ata_bmdma_status,
528 .qc_prep = ata_qc_prep,
529 .qc_issue = ata_qc_issue_prot,
531 .data_xfer = ata_data_xfer,
533 .irq_handler = ata_interrupt,
534 .irq_clear = ata_bmdma_irq_clear,
535 .irq_on = ata_irq_on,
536 .irq_ack = ata_irq_ack,
538 .port_start = ata_port_start,
541 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
543 static const struct ata_port_info info[10] = {
546 .flags = ATA_FLAG_SLAVE_POSS,
548 .mwdma_mask = 0x07, /* No SWDMA */
549 .udma_mask = 0x07, /* UDMA 33 */
550 .port_ops = &amd33_port_ops
552 { /* 1: Early AMD7409 - no swdma */
554 .flags = ATA_FLAG_SLAVE_POSS,
557 .udma_mask = ATA_UDMA4, /* UDMA 66 */
558 .port_ops = &amd66_port_ops
560 { /* 2: AMD 7409, no swdma errata */
562 .flags = ATA_FLAG_SLAVE_POSS,
565 .udma_mask = ATA_UDMA4, /* UDMA 66 */
566 .port_ops = &amd66_port_ops
570 .flags = ATA_FLAG_SLAVE_POSS,
573 .udma_mask = ATA_UDMA5, /* UDMA 100 */
574 .port_ops = &amd100_port_ops
578 .flags = ATA_FLAG_SLAVE_POSS,
581 .udma_mask = ATA_UDMA5, /* UDMA 100 */
582 .port_ops = &amd100_port_ops
586 .flags = ATA_FLAG_SLAVE_POSS,
589 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
590 .port_ops = &amd133_port_ops
592 { /* 6: AMD 8111 UDMA 100 (Serenade) */
594 .flags = ATA_FLAG_SLAVE_POSS,
597 .udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */
598 .port_ops = &amd133_port_ops
600 { /* 7: Nvidia Nforce */
602 .flags = ATA_FLAG_SLAVE_POSS,
605 .udma_mask = ATA_UDMA5, /* UDMA 100 */
606 .port_ops = &nv100_port_ops
608 { /* 8: Nvidia Nforce2 and later */
610 .flags = ATA_FLAG_SLAVE_POSS,
613 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
614 .port_ops = &nv133_port_ops
616 { /* 9: AMD CS5536 (Geode companion) */
618 .flags = ATA_FLAG_SLAVE_POSS,
621 .udma_mask = ATA_UDMA5, /* UDMA 100 */
622 .port_ops = &amd100_port_ops
625 const struct ata_port_info *ppi[] = { NULL, NULL };
626 static int printed_version;
627 int type = id->driver_data;
630 if (!printed_version++)
631 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
633 pci_read_config_byte(pdev, 0x41, &fifo);
635 /* Check for AMD7409 without swdma errata and if found adjust type */
636 if (type == 1 && pdev->revision > 0x7)
639 /* Check for AMD7411 */
642 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
644 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
647 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
648 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
649 type = 6; /* UDMA 100 only */
652 ata_pci_clear_simplex(pdev);
655 ppi[0] = &info[type];
656 return ata_pci_init_one(pdev, ppi);
660 static int amd_reinit_one(struct pci_dev *pdev)
662 if (pdev->vendor == PCI_VENDOR_ID_AMD) {
664 pci_read_config_byte(pdev, 0x41, &fifo);
665 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
667 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
669 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
670 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
671 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
672 ata_pci_clear_simplex(pdev);
674 return ata_pci_device_resume(pdev);
678 static const struct pci_device_id amd[] = {
679 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
680 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
681 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
682 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
683 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
684 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
685 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
686 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
687 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
688 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
689 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
690 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
691 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
692 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
693 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
694 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
695 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
696 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
697 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
698 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
703 static struct pci_driver amd_pci_driver = {
706 .probe = amd_init_one,
707 .remove = ata_pci_remove_one,
709 .suspend = ata_pci_device_suspend,
710 .resume = amd_reinit_one,
714 static int __init amd_init(void)
716 return pci_register_driver(&amd_pci_driver);
719 static void __exit amd_exit(void)
721 pci_unregister_driver(&amd_pci_driver);
724 MODULE_AUTHOR("Alan Cox");
725 MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
726 MODULE_LICENSE("GPL");
727 MODULE_DEVICE_TABLE(pci, amd);
728 MODULE_VERSION(DRV_VERSION);
730 module_init(amd_init);
731 module_exit(amd_exit);