2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/libata.h>
42 * ata_irq_on - Enable interrupts on a port.
43 * @ap: Port on which interrupts are enabled.
45 * Enable interrupts on a legacy IDE device using MMIO or PIO,
46 * wait for idle, clear any pending interrupts.
49 * Inherited from caller.
51 u8 ata_irq_on(struct ata_port *ap)
53 struct ata_ioports *ioaddr = &ap->ioaddr;
57 ap->last_ctl = ap->ctl;
60 iowrite8(ap->ctl, ioaddr->ctl_addr);
61 tmp = ata_wait_idle(ap);
63 ap->ops->irq_clear(ap);
69 * ata_tf_load - send taskfile registers to host controller
70 * @ap: Port to which output is sent
71 * @tf: ATA taskfile register set
73 * Outputs ATA taskfile to standard ATA host controller.
76 * Inherited from caller.
79 void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
81 struct ata_ioports *ioaddr = &ap->ioaddr;
82 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
84 if (tf->ctl != ap->last_ctl) {
86 iowrite8(tf->ctl, ioaddr->ctl_addr);
87 ap->last_ctl = tf->ctl;
91 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
92 WARN_ON(!ioaddr->ctl_addr);
93 iowrite8(tf->hob_feature, ioaddr->feature_addr);
94 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
95 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
96 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
97 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
98 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
107 iowrite8(tf->feature, ioaddr->feature_addr);
108 iowrite8(tf->nsect, ioaddr->nsect_addr);
109 iowrite8(tf->lbal, ioaddr->lbal_addr);
110 iowrite8(tf->lbam, ioaddr->lbam_addr);
111 iowrite8(tf->lbah, ioaddr->lbah_addr);
112 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
120 if (tf->flags & ATA_TFLAG_DEVICE) {
121 iowrite8(tf->device, ioaddr->device_addr);
122 VPRINTK("device 0x%X\n", tf->device);
129 * ata_exec_command - issue ATA command to host controller
130 * @ap: port to which command is being issued
131 * @tf: ATA taskfile register set
133 * Issues ATA command, with proper synchronization with interrupt
134 * handler / other threads.
137 * spin_lock_irqsave(host lock)
139 void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
141 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
143 iowrite8(tf->command, ap->ioaddr.command_addr);
148 * ata_tf_read - input device's ATA taskfile shadow registers
149 * @ap: Port from which input is read
150 * @tf: ATA taskfile register set for storing input
152 * Reads ATA taskfile registers for currently-selected device
153 * into @tf. Assumes the device has a fully SFF compliant task file
154 * layout and behaviour. If you device does not (eg has a different
155 * status method) then you will need to provide a replacement tf_read
158 * Inherited from caller.
160 void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
162 struct ata_ioports *ioaddr = &ap->ioaddr;
164 tf->command = ata_check_status(ap);
165 tf->feature = ioread8(ioaddr->error_addr);
166 tf->nsect = ioread8(ioaddr->nsect_addr);
167 tf->lbal = ioread8(ioaddr->lbal_addr);
168 tf->lbam = ioread8(ioaddr->lbam_addr);
169 tf->lbah = ioread8(ioaddr->lbah_addr);
170 tf->device = ioread8(ioaddr->device_addr);
172 if (tf->flags & ATA_TFLAG_LBA48) {
173 if (likely(ioaddr->ctl_addr)) {
174 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
175 tf->hob_feature = ioread8(ioaddr->error_addr);
176 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
177 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
178 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
179 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
180 iowrite8(tf->ctl, ioaddr->ctl_addr);
181 ap->last_ctl = tf->ctl;
188 * ata_check_status - Read device status reg & clear interrupt
189 * @ap: port where the device is
191 * Reads ATA taskfile status register for currently-selected device
192 * and return its value. This also clears pending interrupts
196 * Inherited from caller.
198 u8 ata_check_status(struct ata_port *ap)
200 return ioread8(ap->ioaddr.status_addr);
204 * ata_altstatus - Read device alternate status reg
205 * @ap: port where the device is
207 * Reads ATA taskfile alternate status register for
208 * currently-selected device and return its value.
210 * Note: may NOT be used as the check_altstatus() entry in
211 * ata_port_operations.
214 * Inherited from caller.
216 u8 ata_altstatus(struct ata_port *ap)
218 if (ap->ops->check_altstatus)
219 return ap->ops->check_altstatus(ap);
221 return ioread8(ap->ioaddr.altstatus_addr);
225 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
226 * @qc: Info associated with this ATA transaction.
229 * spin_lock_irqsave(host lock)
231 void ata_bmdma_setup(struct ata_queued_cmd *qc)
233 struct ata_port *ap = qc->ap;
234 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
237 /* load PRD table addr. */
238 mb(); /* make sure PRD table writes are visible to controller */
239 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
241 /* specify data direction, triple-check start bit is clear */
242 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
243 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
245 dmactl |= ATA_DMA_WR;
246 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
248 /* issue r/w command */
249 ap->ops->exec_command(ap, &qc->tf);
253 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
254 * @qc: Info associated with this ATA transaction.
257 * spin_lock_irqsave(host lock)
259 void ata_bmdma_start(struct ata_queued_cmd *qc)
261 struct ata_port *ap = qc->ap;
264 /* start host DMA transaction */
265 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
266 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
268 /* Strictly, one may wish to issue an ioread8() here, to
269 * flush the mmio write. However, control also passes
270 * to the hardware at this point, and it will interrupt
271 * us when we are to resume control. So, in effect,
272 * we don't care when the mmio write flushes.
273 * Further, a read of the DMA status register _immediately_
274 * following the write may not be what certain flaky hardware
275 * is expected, so I think it is best to not add a readb()
276 * without first all the MMIO ATA cards/mobos.
277 * Or maybe I'm just being paranoid.
279 * FIXME: The posting of this write means I/O starts are
280 * unneccessarily delayed for MMIO
285 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
286 * @ap: Port associated with this ATA transaction.
288 * Clear interrupt and error flags in DMA status register.
290 * May be used as the irq_clear() entry in ata_port_operations.
293 * spin_lock_irqsave(host lock)
295 void ata_bmdma_irq_clear(struct ata_port *ap)
297 void __iomem *mmio = ap->ioaddr.bmdma_addr;
302 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
306 * ata_noop_irq_clear - Noop placeholder for irq_clear
307 * @ap: Port associated with this ATA transaction.
309 void ata_noop_irq_clear(struct ata_port *ap)
314 * ata_bmdma_status - Read PCI IDE BMDMA status
315 * @ap: Port associated with this ATA transaction.
317 * Read and return BMDMA status register.
319 * May be used as the bmdma_status() entry in ata_port_operations.
322 * spin_lock_irqsave(host lock)
324 u8 ata_bmdma_status(struct ata_port *ap)
326 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
330 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
331 * @qc: Command we are ending DMA for
333 * Clears the ATA_DMA_START flag in the dma control register
335 * May be used as the bmdma_stop() entry in ata_port_operations.
338 * spin_lock_irqsave(host lock)
340 void ata_bmdma_stop(struct ata_queued_cmd *qc)
342 struct ata_port *ap = qc->ap;
343 void __iomem *mmio = ap->ioaddr.bmdma_addr;
345 /* clear start/stop bit */
346 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
349 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
350 ata_altstatus(ap); /* dummy read */
354 * ata_bmdma_freeze - Freeze BMDMA controller port
355 * @ap: port to freeze
357 * Freeze BMDMA controller port.
360 * Inherited from caller.
362 void ata_bmdma_freeze(struct ata_port *ap)
364 struct ata_ioports *ioaddr = &ap->ioaddr;
367 ap->last_ctl = ap->ctl;
369 if (ioaddr->ctl_addr)
370 iowrite8(ap->ctl, ioaddr->ctl_addr);
372 /* Under certain circumstances, some controllers raise IRQ on
373 * ATA_NIEN manipulation. Also, many controllers fail to mask
374 * previously pending IRQ on ATA_NIEN assertion. Clear it.
378 ap->ops->irq_clear(ap);
382 * ata_bmdma_thaw - Thaw BMDMA controller port
385 * Thaw BMDMA controller port.
388 * Inherited from caller.
390 void ata_bmdma_thaw(struct ata_port *ap)
392 /* clear & re-enable interrupts */
394 ap->ops->irq_clear(ap);
399 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
400 * @ap: port to handle error for
402 * Stock error handler for BMDMA controller. It can handle both
403 * PATA and SATA controllers. Many controllers should be able to
404 * use this EH as-is or with some added handling before and
408 * Kernel thread context (may sleep)
410 void ata_bmdma_error_handler(struct ata_port *ap)
412 ata_reset_fn_t softreset = ap->ops->softreset;
413 ata_reset_fn_t hardreset = ap->ops->hardreset;
414 struct ata_queued_cmd *qc;
418 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
419 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
422 /* reset PIO HSM and stop DMA engine */
423 spin_lock_irqsave(ap->lock, flags);
425 ap->hsm_task_state = HSM_ST_IDLE;
427 if (qc && (qc->tf.protocol == ATA_PROT_DMA ||
428 qc->tf.protocol == ATAPI_PROT_DMA)) {
431 host_stat = ap->ops->bmdma_status(ap);
433 /* BMDMA controllers indicate host bus error by
434 * setting DMA_ERR bit and timing out. As it wasn't
435 * really a timeout event, adjust error mask and
436 * cancel frozen state.
438 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
439 qc->err_mask = AC_ERR_HOST_BUS;
443 ap->ops->bmdma_stop(qc);
448 ap->ops->irq_clear(ap);
450 spin_unlock_irqrestore(ap->lock, flags);
453 ata_eh_thaw_port(ap);
455 /* PIO and DMA engines have been stopped, perform recovery */
457 /* ata_std_softreset and sata_std_hardreset are inherited to
458 * all SFF drivers from ata_sff_port_ops. Ignore softreset if
459 * ctl isn't accessible. Ignore hardreset if SCR access isn't
462 if (softreset == ata_std_softreset && !ap->ioaddr.ctl_addr)
464 if (hardreset == sata_std_hardreset && !sata_scr_valid(&ap->link))
467 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
472 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for
474 * @qc: internal command to clean up
477 * Kernel thread context (may sleep)
479 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
481 if (qc->ap->ioaddr.bmdma_addr)
486 * ata_sff_port_start - Set port up for dma.
487 * @ap: Port to initialize
489 * Called just after data structures for each port are
490 * initialized. Allocates space for PRD table if the device
491 * is DMA capable SFF.
493 * May be used as the port_start() entry in ata_port_operations.
496 * Inherited from caller.
499 int ata_sff_port_start(struct ata_port *ap)
501 if (ap->ioaddr.bmdma_addr)
502 return ata_port_start(ap);
508 static int ata_resources_present(struct pci_dev *pdev, int port)
512 /* Check the PCI resources for this channel are enabled */
514 for (i = 0; i < 2; i ++) {
515 if (pci_resource_start(pdev, port + i) == 0 ||
516 pci_resource_len(pdev, port + i) == 0)
523 * ata_pci_init_bmdma - acquire PCI BMDMA resources and init ATA host
524 * @host: target ATA host
526 * Acquire PCI BMDMA resources and initialize @host accordingly.
529 * Inherited from calling layer (may sleep).
532 * 0 on success, -errno otherwise.
534 int ata_pci_init_bmdma(struct ata_host *host)
536 struct device *gdev = host->dev;
537 struct pci_dev *pdev = to_pci_dev(gdev);
540 /* No BAR4 allocation: No DMA */
541 if (pci_resource_start(pdev, 4) == 0)
544 /* TODO: If we get no DMA mask we should fall back to PIO */
545 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
548 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
552 /* request and iomap DMA region */
553 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
555 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
558 host->iomap = pcim_iomap_table(pdev);
560 for (i = 0; i < 2; i++) {
561 struct ata_port *ap = host->ports[i];
562 void __iomem *bmdma = host->iomap[4] + 8 * i;
564 if (ata_port_is_dummy(ap))
567 ap->ioaddr.bmdma_addr = bmdma;
568 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
569 (ioread8(bmdma + 2) & 0x80))
570 host->flags |= ATA_HOST_SIMPLEX;
572 ata_port_desc(ap, "bmdma 0x%llx",
573 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
580 * ata_pci_init_sff_host - acquire native PCI ATA resources and init host
581 * @host: target ATA host
583 * Acquire native PCI ATA resources for @host and initialize the
584 * first two ports of @host accordingly. Ports marked dummy are
585 * skipped and allocation failure makes the port dummy.
587 * Note that native PCI resources are valid even for legacy hosts
588 * as we fix up pdev resources array early in boot, so this
589 * function can be used for both native and legacy SFF hosts.
592 * Inherited from calling layer (may sleep).
595 * 0 if at least one port is initialized, -ENODEV if no port is
598 int ata_pci_init_sff_host(struct ata_host *host)
600 struct device *gdev = host->dev;
601 struct pci_dev *pdev = to_pci_dev(gdev);
602 unsigned int mask = 0;
605 /* request, iomap BARs and init port addresses accordingly */
606 for (i = 0; i < 2; i++) {
607 struct ata_port *ap = host->ports[i];
609 void __iomem * const *iomap;
611 if (ata_port_is_dummy(ap))
614 /* Discard disabled ports. Some controllers show
615 * their unused channels this way. Disabled ports are
618 if (!ata_resources_present(pdev, i)) {
619 ap->ops = &ata_dummy_port_ops;
623 rc = pcim_iomap_regions(pdev, 0x3 << base,
624 dev_driver_string(gdev));
626 dev_printk(KERN_WARNING, gdev,
627 "failed to request/iomap BARs for port %d "
628 "(errno=%d)\n", i, rc);
630 pcim_pin_device(pdev);
631 ap->ops = &ata_dummy_port_ops;
634 host->iomap = iomap = pcim_iomap_table(pdev);
636 ap->ioaddr.cmd_addr = iomap[base];
637 ap->ioaddr.altstatus_addr =
638 ap->ioaddr.ctl_addr = (void __iomem *)
639 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
640 ata_std_ports(&ap->ioaddr);
642 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
643 (unsigned long long)pci_resource_start(pdev, base),
644 (unsigned long long)pci_resource_start(pdev, base + 1));
650 dev_printk(KERN_ERR, gdev, "no available native port\n");
658 * ata_pci_prepare_sff_host - helper to prepare native PCI ATA host
659 * @pdev: target PCI device
660 * @ppi: array of port_info, must be enough for two ports
661 * @r_host: out argument for the initialized ATA host
663 * Helper to allocate ATA host for @pdev, acquire all native PCI
664 * resources and initialize it accordingly in one go.
667 * Inherited from calling layer (may sleep).
670 * 0 on success, -errno otherwise.
672 int ata_pci_prepare_sff_host(struct pci_dev *pdev,
673 const struct ata_port_info * const * ppi,
674 struct ata_host **r_host)
676 struct ata_host *host;
679 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
682 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
684 dev_printk(KERN_ERR, &pdev->dev,
685 "failed to allocate ATA host\n");
690 rc = ata_pci_init_sff_host(host);
694 /* init DMA related stuff */
695 rc = ata_pci_init_bmdma(host);
699 devres_remove_group(&pdev->dev, NULL);
704 /* This is necessary because PCI and iomap resources are
705 * merged and releasing the top group won't release the
706 * acquired resources if some of those have been acquired
707 * before entering this function.
709 pcim_iounmap_regions(pdev, 0xf);
711 devres_release_group(&pdev->dev, NULL);
716 * ata_pci_activate_sff_host - start SFF host, request IRQ and register it
717 * @host: target SFF ATA host
718 * @irq_handler: irq_handler used when requesting IRQ(s)
719 * @sht: scsi_host_template to use when registering the host
721 * This is the counterpart of ata_host_activate() for SFF ATA
722 * hosts. This separate helper is necessary because SFF hosts
723 * use two separate interrupts in legacy mode.
726 * Inherited from calling layer (may sleep).
729 * 0 on success, -errno otherwise.
731 int ata_pci_activate_sff_host(struct ata_host *host,
732 irq_handler_t irq_handler,
733 struct scsi_host_template *sht)
735 struct device *dev = host->dev;
736 struct pci_dev *pdev = to_pci_dev(dev);
737 const char *drv_name = dev_driver_string(host->dev);
738 int legacy_mode = 0, rc;
740 rc = ata_host_start(host);
744 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
747 /* TODO: What if one channel is in native mode ... */
748 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
749 mask = (1 << 2) | (1 << 0);
750 if ((tmp8 & mask) != mask)
752 #if defined(CONFIG_NO_ATA_LEGACY)
753 /* Some platforms with PCI limits cannot address compat
754 port space. In that case we punt if their firmware has
755 left a device in compatibility mode */
757 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
763 if (!devres_open_group(dev, NULL, GFP_KERNEL))
766 if (!legacy_mode && pdev->irq) {
767 rc = devm_request_irq(dev, pdev->irq, irq_handler,
768 IRQF_SHARED, drv_name, host);
772 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
773 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
774 } else if (legacy_mode) {
775 if (!ata_port_is_dummy(host->ports[0])) {
776 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
777 irq_handler, IRQF_SHARED,
782 ata_port_desc(host->ports[0], "irq %d",
783 ATA_PRIMARY_IRQ(pdev));
786 if (!ata_port_is_dummy(host->ports[1])) {
787 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
788 irq_handler, IRQF_SHARED,
793 ata_port_desc(host->ports[1], "irq %d",
794 ATA_SECONDARY_IRQ(pdev));
798 rc = ata_host_register(host, sht);
801 devres_remove_group(dev, NULL);
803 devres_release_group(dev, NULL);
809 * ata_pci_init_one - Initialize/register PCI IDE host controller
810 * @pdev: Controller to be initialized
811 * @ppi: array of port_info, must be enough for two ports
812 * @sht: scsi_host_template to use when registering the host
813 * @host_priv: host private_data
815 * This is a helper function which can be called from a driver's
816 * xxx_init_one() probe function if the hardware uses traditional
817 * IDE taskfile registers.
819 * This function calls pci_enable_device(), reserves its register
820 * regions, sets the dma mask, enables bus master mode, and calls
824 * Nobody makes a single channel controller that appears solely as
825 * the secondary legacy port on PCI.
828 * Inherited from PCI layer (may sleep).
831 * Zero on success, negative on errno-based value on error.
833 int ata_pci_init_one(struct pci_dev *pdev,
834 const struct ata_port_info * const * ppi,
835 struct scsi_host_template *sht, void *host_priv)
837 struct device *dev = &pdev->dev;
838 const struct ata_port_info *pi = NULL;
839 struct ata_host *host = NULL;
844 /* look up the first valid port_info */
845 for (i = 0; i < 2 && ppi[i]; i++) {
846 if (ppi[i]->port_ops != &ata_dummy_port_ops) {
853 dev_printk(KERN_ERR, &pdev->dev,
854 "no valid port_info specified\n");
858 if (!devres_open_group(dev, NULL, GFP_KERNEL))
861 rc = pcim_enable_device(pdev);
865 /* prepare and activate SFF host */
866 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
869 host->private_data = host_priv;
871 pci_set_master(pdev);
872 rc = ata_pci_activate_sff_host(host, ata_interrupt, sht);
875 devres_remove_group(&pdev->dev, NULL);
877 devres_release_group(&pdev->dev, NULL);
883 * ata_pci_clear_simplex - attempt to kick device out of simplex
886 * Some PCI ATA devices report simplex mode but in fact can be told to
887 * enter non simplex mode. This implements the necessary logic to
888 * perform the task on such devices. Calling it on other devices will
889 * have -undefined- behaviour.
892 int ata_pci_clear_simplex(struct pci_dev *pdev)
894 unsigned long bmdma = pci_resource_start(pdev, 4);
900 simplex = inb(bmdma + 0x02);
901 outb(simplex & 0x60, bmdma + 0x02);
902 simplex = inb(bmdma + 0x02);
908 unsigned long ata_pci_default_filter(struct ata_device *adev, unsigned long xfer_mask)
910 /* Filter out DMA modes if the device has been configured by
911 the BIOS as PIO only */
913 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
914 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
918 #endif /* CONFIG_PCI */